Device for processing serial data streams
Through the half-rate DFE architecture and cross-coupled equalization path and quadrature phase clock signal control, the signal distortion and inter-symbol interference problems under channel bandwidth limitation are solved, and efficient data flow equalization and performance improvement are achieved.
Patent Information
- Application Number
- CN202110502921.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2015-10-06
- Filing Date
- 2016-06-06
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2036-06-06
AI Technical Summary
When processing high-bandwidth serial data streams, due to channel bandwidth limitations, signal distortion and inter-symbol interference are caused. It is difficult for conventional judgment feedback equalizers (DFEs) to achieve effective equalization at high data rates, and the circuit complexity and High power consumption.
The half-rate DFE architecture is adopted and the cross-coupled equalization path. Through multiple feedback paths and quadrature phase clock signals, the circuit system and energy consumption are reduced, the feedback time specifications are relaxed, and the high-speed data stream is equalized.
Achieving equalization of higher speed data streams on a given semiconductor process reduces circuit system and power consumption, improves performance, and allows for more flexible feedback data combinations, reducing implementation complexity.
Smart Images
Figure CN113395223B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application 201680032517.6 (PCT / US2016 / 036023), whose international application date is June 6, 2016 and whose national phase entry date is December 4, 2017 and whose name is “Device for processing serial data stream”. Technical Field
[0002] The present invention relates to an apparatus for processing a serial data stream. Background Art
[0003] As technology advances and the processing power of digital computing devices increases, higher bandwidth networks are needed to interconnect computing devices and facilitate the use of increased computing power. However, increasing network data rates can be problematic due to limited channel bandwidth. The bandwidth of an electrical channel (e.g., a transmission line) can be reduced by physical effects such as skin effect, dielectric losses, and reflections due to impedance discontinuities.
[0004] Limited channel bandwidth may cause a transmission pulse to spread across more than one unit interval. Therefore, the received signal may suffer from inter-symbol interference. Equalization functions can be added to the input and / or output circuits of the network to compensate for signal distortion caused by the limited channel.
[0005] The decision feedback equalizer (DFE) is a nonlinear equalizer that is well suited for equalizing high-loss channels. Unlike a linear equalizer, a DFE is able to smooth the channel response and reduce signal distortion without amplifying noise or crosstalk, which is an important advantage when equalizing high-loss channels.
[0006] In the DFE, previously received bits are weighted, fed back, and added to the received input signal. If the magnitude and polarity of the weights applied to the previously received bits are properly adjusted to match the channel characteristics, the intersymbol interference from the previous bits in the data stream will be cancelled and the bits can be detected as having a low bit error rate. Summary of the invention
[0007] In the described example of a decision feedback equalizer (DFE) and a serializer, the DFE circuit includes a first equalization path and a second equalization path. Each of the first equalization path and the second equalization path includes a summing node, a first synchronous latch, a second synchronous latch, a feedback latch, and a feedback shift register. The first synchronous latch is configured to latch data received from the summing node. The second synchronous latch is configured to latch data received from the first synchronous latch. The feedback latch is coupled to the output of the first synchronous latch and is configured to latch data received from the first synchronous latch. The feedback shift register is coupled to the output of the second synchronous latch and one of the feedback latches. The feedback shift register includes a plurality of sequentially coupled shift latches. The first shift latch of the shift latch is configured to latch data received from one of the second synchronous latch and the feedback latch, and provide the data to the summing node. The second shift latch of the shift latch is configured to latch data received from the first of the shift latches. In the first equalization path, the feedback latch and the second shift latch of the shift latches are configured to provide data to a summing node of the second equalization path. In the second equalization path, the feedback latch and the second shift latch of the shift latches are configured to provide data to a summing node of the first equalization path.
[0008] In another embodiment, a system includes a DFE. The DFE includes a first summing node, a first synchronous latch, a second synchronous latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronous latch is configured to receive data from the first summing node. The second synchronous latch is configured to receive data from the first synchronous latch. The first feedback latch is configured to receive data from the first synchronous latch. The first feedback shift register is coupled to an output of one of the second synchronous latch and the first feedback latch. The first feedback shift register includes a plurality of sequentially coupled shift latches. A first shift latch in the shift latches is configured to latch data received from one of the second synchronous latch and the first feedback latch, and provide the data to the first summing node. A first alternative shift latch in the shift latches is configured to provide feedback data to the first summing node. The first summing node is configured to equalize the symbol by combining data provided by the first feedback latch and the first replacement shift latch of the shift latches with the symbol received from the data input of the DFE.
[0009] In a further embodiment, the system includes a serializer. The serializer includes multiple layers of serialization units. Each successive layer in the layer includes fewer serialization units than the previous layer. Each serialization unit includes a first latch, a second latch and a multiplexer. The multiplexer is coupled to the output of the first latch and the second latch. The first latch is controlled by a first clock. The second latch is controlled by a second clock. The first clock and the second clock are in an orthogonal phase relationship. The multiplexer is configured to selectively route the output of the first latch and the second latch to the output of the serialization unit based on the second clock. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 A schematic diagram showing a decision feedback equalizer (DFE) according to an example embodiment is shown.
[0011] Figure 2 Shown for Figure 1 A diagram of the DFE timing signal.
[0012] Figure 3 A schematic diagram of a DFE is shown according to an example embodiment.
[0013] Figure 4 A block diagram of a serializer / deserializer (SERDES) is shown according to an example embodiment.
[0014] Figure 5 A schematic diagram illustrating a serializer according to an example embodiment is shown.
[0015] Figure 6 A schematic diagram showing a two-layer serializer and a serializer unit according to an example embodiment.
[0016] Figure 7 A diagram illustrating timing signals in a two-layer serializer according to an example embodiment. DETAILED DESCRIPTION
[0017] If a first device couples to a second device, that connection may be through a direct electrical connection or through an indirect electrical connection via other devices and connections. Additionally, if X is based on Y, then X may be based on Y and any number of other factors.
[0018] Serializer / deserializer (SERDES) circuits are used in a variety of applications that require converting data between serial and parallel formats. SERDES circuits used to process high-speed serial data streams may include equalization circuitry such as a decision feedback equalizer (DFE) to mitigate the effects of intersymbol interference.
[0019] In a conventional full-rate decision feedback equalizer (DFE), proper operation requires the feedback loop delay to be less than one unit interval (a unit interval is a symbol interval or symbol duration), which makes implementation increasingly difficult as data rates increase. Conventional half-rate DFE architectures may be subject to the same sampling feedback delay requirements as full-rate architectures. More complex half-rate DFE architectures include sample-and-hold circuitry that relaxes the feedback delay requirements, but implementing appropriate sample-and-hold circuitry can be difficult and expensive.
[0020] The DFE circuit disclosed herein employs a half-rate architecture and cross-coupled equalization paths. Each equalization path includes a feedback shift register that provides feedback data for use in the equalization path. Some embodiments include relaxed feedback timing requirements that allow equalization of higher rate data streams than is possible with conventional DFE architectures. Alternatively, the DFE architecture disclosed herein allows the use of semiconductor processes to implement a DFE for equalizing high rate data streams that may not be suitable for implementing conventional DFEs to balance these data streams.
[0021] The SERDES circuit also includes a serializer to convert data from a parallel format to a bit stream. A serializer that requires less circuitry than a conventional high-speed serializer is disclosed herein. Compared to a conventional serializer with the same performance, the serializer of the present disclosure can be implemented with much less (e.g., 40% less) circuitry and energy consumption. An embodiment of the serializer disclosed herein avoids the use of flip-flops in favor of latches controlled via quadrature phase clock signals. In addition to reducing circuit area and power consumption, the use of quadrature phase clock signals can allow for improved performance due to reduced clock loading relative to conventional serializers.
[0022] Figure 1 A schematic diagram of a DFE circuit 100 is shown according to an example embodiment. The DFE circuit 100 allows for relaxed feedback time specifications relative to conventional DFE implementations. Thus, the DFE circuit 100 is a half-rate implementation that allows for equalization of higher speed data streams on a given semiconductor process than conventional full-rate implementations while requiring less circuitry than conventional half-rate DFE implementations.
[0023] The DFE circuit 100 includes parallel equalization paths 110 and 150 having multiple feedback paths in each equalization path. Alternate symbols of a data stream received at an input of the DFE circuit 100 are processed in each equalization path 110, 150. A multiplexer 148 selects output data from the equalization paths 110 and 150 to form an output data stream of equalized data. The multiplexer 148 serializes the half-rate data streams generated by the equalization paths 110 and 150 to produce a full-rate data stream.
[0024] Equalization path 110 includes summing node 112, synchronization latches 114 and 116, feedback latch 118, and feedback shift register 120. Feedback shift register 120 includes shift latches 122, 124, 126, and 128. Equalization path 150 includes summing node 152 and synchronization latches 154 and 156, feedback latch 158, and feedback shift register 160. Feedback shift register 160 includes shift latches 162, 164, 166, and 168. Each of summing nodes 112 and 152 receives data from an input of DFE circuit 100 and includes circuitry for summing the input data with feedback data.
[0025] In the equalization path 110, the synchronization latch 114 receives the summed data from the summing node 112 as input and provides the output data as input to the synchronization latch 116 and the feedback latch 118. The feedback latch 118 provides the output data as input to the feedback shift register 120. The data received by the feedback shift register 120 from the feedback latch 118 is latched in the shift latch 122 and shifted through the successive shift latches 124, 126 and 128. The output data of the feedback latch 118, the shift latch 124 and the shift latch 128 are weighted in the corresponding gain stages 130, 132 and 134 and provided to the summing node 152 of the equalization path 150. The output data of the shift latches 122 and 126 are weighted in the corresponding gain stages 136 and 138 and provided to the summing node 112 of the equalization path 110.
[0026] Similarly, in the equalization path 150, the synchronization latch 154 receives the summed data from the summing node 152 as input and provides output data for input to the synchronization latch 156 and the feedback latch 158. The feedback latch 158 provides the output data as input to the feedback shift register 160. The data received by the feedback shift register 160 from the feedback latch 158 is latched in the shift latch 162 and shifted through the successive shift latches 164, 166 and 168. The output data of the feedback latch 158, the shift latch 164 and the shift latch 168 are weighted in the corresponding gain stages 170, 172 and 174 and provided to the summing node 112 of the equalization path 110. The output data of the shift latches 162 and 166 are weighted in the corresponding gain stages 176 and 178 and provided to the summing node 152 of the equalization path 150.
[0027] The outputs of the synchronous latches 116 and 156 are provided to a multiplexer 148 or equivalent selection circuitry, which selects / routes the outputs of the latches 116 , 156 to the output of the DFE circuit 100 .
[0028] Gain stages 130-138 and 170-178 scale the outputs of latches 118-128 and 158-168 for combining with data input to circuit 100. The polarity of the feedback signal provided from each of gain stages 130-138 and 170-178 may be changed at the gain stage, at summing nodes 112 and 152, or elsewhere in DFE circuit 100.
[0029] Although DFE circuit 100 has been illustrated as including feedback shift registers 120, 160 having four shift latches, some embodiments of DFE feedback shift registers may include more or fewer shift latches with associated gain stages. In some embodiments, feedback registers 118 and 158 may be included in feedback shift registers 120 and 160, respectively.
[0030] Figure 2 1 shows control signals applied to DFE circuit 100. The period of clocks I and Q is twice the unit interval of the data input to circuit 100. Clock I is aligned to transition at or approximately the center of each unit interval. Clock Q is a quadrature phase (i.e., delayed 90 degrees) version of clock I. Thus, the transitions of clock Q are aligned at or approximately the edges of the unit interval of the data input to circuit 100. Thus, latches controlled by clock Q pass data during even-numbered unit intervals and latch data during odd-numbered unit intervals, while latches controlled by an inverted version of clock Q pass data during odd-numbered unit intervals and latch data during even-numbered unit intervals.
[0031] In the equalization path 110, the clock I causes the latch 114 to transparently pass the data received from the summing node 112 in the initial half of each even-numbered unit interval and latch the data through the middle of the subsequent odd-numbered unit interval. The clock Q causes the latch 118 to transparently pass the data received from the latch 114 throughout the even-numbered unit interval and latch the received data throughout the odd-numbered unit interval. Thus, the latch 118 captures the data latched by the latch 114 and aligns the feedback data through the next unit interval for combination with the input data in the summing node 152.
[0032] Latch 116 is clocked by an inverted version of clock I. Thus, latch 116 is transparent when latch 114 is latched, and latch 116 stores the output of latch 114 for an additional unit interval after latch 114 becomes transparent. Latch 122 is clocked by an inverted version of clock Q to latch, hold, and align the data provided from latch 118 with the subsequent even-numbered unit interval. Thus, latch 122 aligns the feedback data for combining with the input data in summing node 112. Thus, in equalization path 110, to equalize data in a given unit interval (e.g., unit interval 2), feedback from the immediately preceding unit interval (e.g., unit interval 1) is provided from another equalization path 150, while feedback from the unit interval two ahead of the given unit interval (unit interval 0) is provided from equalization path 110. Shift latches 124 and 128 are also clocked by clock Q and latch data for provision to summing node 152. Shift latch 126 is clocked by an inverted version of clock Q and latches data for provision to summing node 112.
[0033] With clock I applied to latch 156, clock Q applied to latches 162 and 166, the inverse of clock I applied to latch 154, and the inverse of clock Q applied to latches 158, 164, and 168, equalization path 150 operates similarly to equalization path 110 with respect to odd unit intervals. Thus, DFE circuit 100 provides reduced implementation complexity relative to full-rate DFE and conventional half-rate DFE. DFE circuit 100 advantageously increases the time available for feedback of previously received symbol data. For example, at an input rate of 25 gigabits, DFE 100 allows 40 picoseconds for feedback, rather than the 20 picoseconds provided in conventional DFE implementations. Thus, DFE 100 provides equalization at a rate equal to that provided by a full-rate architecture, but allows implementation using a less complex and less expensive semiconductor process. Conversely, DFE 100 is used to equalize at a higher rate than that allowed by a conventional full-rate DFE in a given semiconductor process. Furthermore, the DFE circuit 100 uses a simple 50% duty cycle clock, which is easier to generate and propagate in high-speed circuit systems than an asymmetric clock. In addition, compared to conventional DFEs, in the DFE circuit 100, feedback data need not be provided precisely at unit interval boundaries (i.e., symbol zero crossings); instead, feedback data may be advantageously provided at any time within a margin constraint prior to the unit interval during which the feedback data will be combined with the input data.
[0034] DFE circuit 100 may be modified in various ways. Figure 3A schematic diagram of a DFE circuit 300 similar to DFE circuit 100 is shown. DFE circuit 200 includes parallel equalization paths 310 and 350. In some embodiments of circuit 300, an additional synchronous latch 140 is coupled to the output of synchronous latch 116. Synchronous latch 140 (not synchronous latch 116 in DFE circuit 100) is connected to multiplexer 148 and provides equalized output data to multiplexer 148. In some embodiments, feedback shift register 120 is coupled to synchronous latch 116 (not feedback latch 118 as in DFE circuit 100) and receives input data from synchronous latch 116.
[0035] Similarly, in some embodiments of circuit 300, an additional synchronous latch 180 is coupled to the output of synchronous latch 156. Synchronous latch 180 is coupled to multiplexer 148 and provides the equalized output data to multiplexer 148. In some embodiments, feedback shift register 160 is coupled to synchronous latch 156 instead of feedback latch 158 and receives input data from synchronous latch 156.
[0036] Figure 4 A block diagram of a SERDES 400 according to various embodiments is shown. The SERDES 400 includes a serial-to-parallel conversion path 412 and a parallel-to-serial conversion path 414. The serial-to-parallel conversion path 412 includes a DFE circuit 404, which may be the DFE circuit 100 or the DFE circuit 300, a clock / data recovery (CDR) circuit 406, and a serial-to-parallel converter 408. The DFE 404 equalizes the serial input data to mitigate inter-symbol interference. The CDR circuit 406 extracts clock and data signals from the equalized serial data stream generated by the DFE 404. The serial-to-parallel converter 408 groups the data bits recovered by the CDR circuit 406 in parallel words. The serial-to-parallel conversion path 412 may include various other components and subsystems that are omitted for clarity. For example, the serial-to-parallel conversion path 412 may include additional equalization circuitry, receiver circuitry, and / or clock generation circuitry.
[0037] The parallel-to-serial conversion path 414 includes a serializer 402 and a driver 410. The serializer 402 receives parallel data words (each word includes multiple data bits present simultaneously) and converts the parallel data words into a serial bit stream. The driver 410 conditions the serial bit stream generated by the serializer 410 for transmission to other circuit systems.
[0038] In addition to SERDES 400 , DFE circuit 404 and / or serializer 402 may also be used in other applications, circuits, or systems that receive and / or generate serial data streams.
[0039] Figure 5 A schematic diagram of a serializer 500 according to an example embodiment is shown. The serializer 500 can be applied in a SERDES 400 as a serializer 402. The serializer 500 includes a plurality of serialization layers 502, 504, 506 arranged in a tree structure, wherein an output serial bit stream is generated at the root of the tree. The three serialization layers 502, 504, 506 are arranged to serialize eight bits of parallel data presented at the input of the serialization layer 502. Other embodiments of the serializer 500 may include different numbers of layers to serialize different numbers of parallel data bits. Each of the serialization layers 502-506 includes one or more serialization units 508. Each serialization unit 508 serializes two simultaneously presented bits / bit streams.
[0040] Figure 6 A schematic diagram of layers 504 and 506 of serializer 500 is shown, and additional details of serializer units 508 are shown. Each serializer unit 508 includes a latch 602, a latch 604, and a multiplexer 606. Latch 602 and latch 604 each receive a bit to be serialized as input. Multiplexer 606 further selects the output of each of latch 602 and latch 604 to serialize the latch output.
[0041] Referring to the serialization unit 508 that generates the output serial bit stream of the serializer 500, the latch 604 is controlled by Iclk and the latch 602 is controlled by Qclk. Qclk is a quadrature phase version of Iclk (i.e., Qclk is delayed by 90° than Iclk). The multiplexer 606 is controlled by the clock Iclk applied to the latch 604 in the serializer unit 508.
[0042] Since the rate of data to be serialized by cell 508 doubles in each subsequent layer of serializer 500, the rate of the clocks applied to latches 602 and latches 604 and multiplexers 606 in a given layer is twice the rate of the clocks applied in subsequent layers. Thus, the versions of Iclk and Qclk applied in serialization layer 504 are half the frequency of the versions of Iclk and Qclk applied in serialization layer 506. Similarly, the versions of Iclk and Qclk applied in serialization layer 502 are half the frequency of the versions of Iclk and Qclk applied in serialization layer 504. Thus, viewing the layers of serializer 500 from the output of serializer 500, each further layer applies a clock having a frequency that is half the frequency of the clocks applied in adjacent layers closer to the output of serializer 500.
[0043] Additionally, with each subsequent layer of serializer 500, the phase of the clocks applied to latches 602 and 604 and multiplexer 606 is changed. In layer 506, a quadrature phase clock is applied to latch 602, and an in-phase clock is applied to latch 604 and multiplexer 606. Clocking is changed in layer 504 such that an in-phase clock is applied to latch 602, and a quadrature phase clock is applied to latch 604 and multiplexer 606.
[0044] Figure 7 A schematic diagram illustrating timing signals in the serializer unit 508 according to an example embodiment. Figure 7 The timing of FIG. 6 is for the operation of the serializer unit 508 of the layers 504 and 506 of the serializer 500. In the layer 504, the data bits are presented to the serializer unit 508 at the rate of the clock Iclk. The clock Iclk (DIV_2ICLK) switches at about the transition time of the data bit. The clock signal Qclk (DIV_2QCLK) is offset 90° from Iclk. The multiplexer 606 is controlled by Qclk. Therefore, the data output of the serializer 508 in the layer 504 is synchronized with Qclk, and each output bit is presented at half of the Qclk period.
[0045] Data labeled "INPUT EVEN STREAM" is presented to latch 602, and data labeled "INPUT ODD STREAM" is presented to latch 604. When Iclk is low, latch 602 is transparent, and latch 602 latches the input data when Iclk is high. When Qclk is low, multiplexer 606 selects the output of latch 602. Therefore, if Figure 7 As shown, multiplexer 606 selects the output of latch 602 for output during the center portion of each unit interval. Latch 604 is transparent when Qclk is low, and latch 604 latches input data when Qclk is high. Therefore, latch 604 delays the "INPUT ODD STREAM" by 1 / 4 of the Iclk period, and multiplexer 606 selects the output of latch 604 during the high portion of Qclk.
[0046] In the subsequent serializer layer (i.e., layer 506), the Qclk applied is phase aligned with and twice the frequency of the Qclk applied in the previous layer (i.e., layer 504). The input data received in layer 506 transitions at approximately the high to low transition time of Qclk. The Iclk applied in layer 506 is phase aligned with and twice the frequency of the Iclk applied in the previous layer (i.e., layer 504). Iclk is also inverted relative to the Iclk applied in layer 504. Therefore, the timing relationship of Iclk and Qclk is the same as the previous layer, but Iclk is inverted so that Iclk is delayed 90° relative to Qclk. Qclk is applied to multiplexer 606 and latch 602, and the inverted Iclk is applied to latch 604. Thus, as described above, the clocks applied to latches 602 and 604 and multiplexer 606 are switched relative to layer 504, and in layer 506, the "DELAYED ODD STREAM" is delayed by 1 / 4 cycle via the inverted Iclk. Figure 7 As shown, the output of layer 506 is synchronized with the inverted Iclk.
[0047] Thus, in each subsequent layer of serializer 500, the clock applied to the multiplexers of the previous layer is applied to the latch(s) 502 of the subsequent layer at twice the frequency, and the inverse of the clock applied to the latch(s) 502 of the previous layer is applied to the latch(s) 504 and multiplexers 506 of the subsequent layer at twice the frequency. The use of quadrature phase clocks in the above configuration allows serializer 500 to generate a serial bit stream using significantly less circuitry than conventional serializers while potentially increasing the output bit rate.
[0048] Modifications may be made in the embodiments described, and other embodiments are possible within the scope of the claims.
Claims
1. A serial interface circuit, include: Data input terminal; A first path coupled to the data input terminal, comprising: a first summing node coupled to the data input terminal; a first synchronous latch coupled to the first summing node, the first synchronous latch being driven based on a first clock signal; a first feedback latch coupled to the first synchronous latch, the first feedback latch being driven based on a second clock signal that is a quadrature phase-shifted version of the first clock signal; and a first feedback shift register coupled between the first feedback latch and the first summing node, the first feedback shift register comprising a first shift latch driven based on a third clock signal, the third clock signal being an inverted version of the second clock signal; A second path coupled to the data input terminal, comprising: a second summing node coupled to the data input terminal; a second synchronous latch coupled to the second summing node, the second synchronous latch being driven based on a fourth clock signal, the fourth clock signal being an inverted version of the first clock signal; a second feedback latch coupled to the second synchronization latch, the second feedback latch being driven based on the third clock signal; and a second feedback shift register coupled between the second feedback latch and the second summing node, the second feedback shift register comprising a second shift latch driven based on the second clock signal; and A multiplexer having a first input terminal coupled to the first synchronous latch, a second input terminal coupled to the second synchronous latch, and a select input configured to receive the first clock signal.
2. The serial interface circuit of claim 1 further comprising a first gain stage coupled between the first feedback latch and the second summing node, and a second gain stage coupled between the second feedback latch and the first summing node.
3. The serial interface circuit of claim 1 , wherein the first path includes a third gain stage coupled between the first shift latch and the first summing node, and the second path includes a fourth gain stage coupled between the second shift latch and the second summing node.
4. The serial interface circuit according to claim 1, wherein the first feedback shift register comprises a first group of shift latches coupled in series, and adjacent shift latches in the first group of shift latches are clocked by the third clock signal and the second clock signal, respectively. 5 . The serial interface circuit of claim 4 , wherein more than one output terminal of the first set of shift latches are alternately coupled to the first summing node and the second summing node through corresponding gain stages.
6. The serial interface circuit according to claim 1, wherein the second feedback shift register comprises a second group of shift latches coupled in series, and adjacent shift latches in the second group of shift latches are clocked by the second clock signal and the third clock signal, respectively. 7 . The serial interface circuit of claim 6 , wherein more than one output terminal of the second set of shift latches is alternately coupled to the second summing node and the first summing node through corresponding gain stages.
8. The serial interface circuit according to claim 1, wherein the first path comprises a first group of synchronous latches sequentially coupled between the first summing node and the first input terminal of the multiplexer, and adjacent synchronous latches in the first group of synchronous latches are driven by the first clock signal and the fourth clock signal, respectively.
9. The serial interface circuit of claim 1 , wherein the second path comprises a second group of synchronous latches sequentially coupled between the second summing node and the second input terminal of the multiplexer, and adjacent synchronous latches in the second group of synchronous latches are clocked by the fourth clock signal and the first clock signal, respectively.
10. A data processing system, include: The decision feedback equalizer, or DFE, consists of: Data input terminal; A first path coupled to the data input terminal, comprising: a first summing node coupled to the data input terminal; a first synchronous latch coupled to the first summing node, the first synchronous latch being driven based on a first clock signal; a first feedback latch coupled to the first synchronous latch, the first feedback latch being driven based on a second clock signal that is a quadrature phase-shifted version of the first clock signal; and a first feedback shift register coupled between the first feedback latch and the first summing node, the first feedback shift register comprising a first shift latch driven based on a third clock signal, the third clock signal being an inverted version of the second clock signal; A second path coupled to the data input terminal, comprising: a second summing node coupled to the data input terminal; a second synchronous latch coupled to the second summing node, the second synchronous latch being driven based on a fourth clock signal, the fourth clock signal being an inverted version of the first clock signal; a second feedback latch coupled to the second synchronization latch, the second feedback latch being driven based on the third clock signal; and a second feedback shift register coupled between the second feedback latch and the second summing node, the second feedback shift register comprising a second shift latch driven based on the second clock signal; and A multiplexer having a first input terminal coupled to the first synchronous latch, a second input terminal coupled to the second synchronous latch, and a select input configured to receive the first clock signal.
11. The system of claim 10, further comprising a first gain stage coupled between the first feedback latch and the second summing node, and a second gain stage coupled between the second feedback latch and the first summing node.
12. The system of claim 10, wherein the first path includes a third gain stage coupled between the first shift latch and the first summing node, and the second path includes a fourth gain stage coupled between the second shift latch and the second summing node.
13. The system of claim 10, wherein the first feedback shift register comprises a first group of shift latches coupled in series, and adjacent shift latches in the first group of shift latches are clocked by the third clock signal and the second clock signal, respectively.
14. The system of claim 13, wherein more than one output terminal of the first set of shift latches are alternately coupled to the first summing node and the second summing node through respective gain stages.
15. The system of claim 10, wherein the second feedback shift register comprises a second group of shift latches coupled in series, and adjacent shift latches in the second group of shift latches are clocked by the second clock signal and the third clock signal, respectively.
16. The system of claim 15, wherein more than one output terminal of the second set of shift latches is alternately coupled to the second summing node and the first summing node through respective gain stages.
17. The system of claim 10, wherein the first path comprises a first group of synchronous latches sequentially coupled between the first summing node and the first input terminal of the multiplexer, and adjacent synchronous latches in the first group of synchronous latches are driven by the first clock signal and the fourth clock signal, respectively.
18. The system of claim 10, wherein the second path comprises a second group of synchronous latches sequentially coupled between the second summing node and the second input terminal of the multiplexer, and adjacent synchronous latches in the second group of synchronous latches are clocked by the fourth clock signal and the first clock signal, respectively.