EUV photomask and method for manufacturing the same

Abstract

The present disclosure relates to EUV photomasks and methods for manufacturing the same. In a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photoresist layer is patterned, the hard mask layer is patterned by using the patterned photoresist layer, the absorber layer is patterned by using the patterned hard mask layer, and additional elements are introduced into the patterned absorber layer to form a converted absorber layer.

Description

Technical Field

[0001] The present disclosure relates to EUV photomasks and methods of manufacturing the same. Background Art

[0002] Photolithography is one of the key operations in the semiconductor manufacturing process. Photolithography technology includes ultraviolet lithography, deep ultraviolet lithography and extreme ultraviolet lithography (EUVL). Photomask is an important component in photolithography. It is crucial to manufacture EUV photomasks with high contrast including high reflectivity parts and high absorption parts. Summary of the invention

[0003] According to one aspect of the present disclosure, a reflective mask is provided, comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer comprises a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic %, or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

[0004] According to another aspect of the present disclosure, a method for manufacturing a reflective mask is provided, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer; and removing the first hard mask layer, wherein the second hard mask layer and the absorber layer comprise a Cr-based compound, and the first hard mask layer and the intermediate layer comprise a Ta-based compound.

[0005] According to another aspect of the present disclosure, a method for manufacturing a reflective mask is provided, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the oxide layer and the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer; and patterning the intermediate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various structures are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E An EUV photomask blank according to an embodiment of the present disclosure is shown.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically shown.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically shown.

[0010] Figure 4 A cross-sectional view of an EUV photomask according to an embodiment of the present disclosure is shown.

[0011] Figure 5A , Figure 5B and Figure 5C A cross-sectional view of a multilayer structure of an absorber layer according to another embodiment of the present disclosure is shown.

[0012] Figure 6A cross-sectional view of an EUV photomask according to an embodiment of the present disclosure is shown.

[0013] Figure 7 A flow chart of manufacturing a mask blank for an EUV photomask according to an embodiment of the present disclosure is shown.

[0014] Fig. 8A A flow chart of a method for manufacturing a semiconductor device is shown, and Figure 8B , Figure 8C , Fig.8D and Fig. 8E Sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0015] It should be understood that the following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or required characteristics of the device. In addition, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. For simplicity and clarity, various features may be arbitrarily drawn in different proportions.

[0016] In addition, spatially relative terms may be used herein, for example, "below", "below", "below", "above", "upper", etc., to easily describe the relationship of an element or structure shown in the figure relative to another (some) element or feature. In addition to the orientation shown in the figure, spatially relative terms are also intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used here can also be interpreted accordingly. In addition, the term "consisting of..." can mean "including" or "consisting of..." In the present disclosure, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and unless otherwise specified, does not refer to an element from A, an element from B, and an element from C.

[0017] Embodiments of the present disclosure provide a method for manufacturing an EUV photomask. More specifically, the present disclosure provides a technique for preventing or suppressing damage to a back conductive layer of an EUV photomask.

[0018] EUV lithography (EUVL) uses scanners that use light in the extreme ultraviolet (EUV) region with a wavelength of about 1 nm to about 100 nm (e.g., 13.5 nm). The mask is a key component of the EUVL system. Since optical materials are not transparent to EUV radiation, the EUV photomask is a reflective mask. The circuit pattern is formed in an absorber layer disposed above the reflective structure. The absorber has a low EUV reflectivity, e.g., less than 3-5%.

[0019] The present disclosure provides an EUV reflective photomask having a low reflective (high absorption) absorber structure.

[0020] Figure 1A and Figure 1B An EUV reflective photomask blank according to an embodiment of the present disclosure is shown. Figure 1A is a plan view (seen from the top), Figure 1B It is a cross-sectional view along the X direction.

[0021] In some embodiments, an EUV photomask having a circuit pattern is formed from an EUV photomask blank 5. The EUV photomask blank 5 includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, a protective layer 22, an absorber layer 25, a first hard mask layer 30, and a second hard mask layer 32. Figure 1B As shown, a back conductive layer 45 is formed on the back side of the substrate 10. In some embodiments, Figure 1B As shown, an oxide layer 27 is formed on the top surface of the absorber layer 25. In other embodiments, as Figure 1D As shown, no oxide layer is formed on the top surface of the absorber layer 25 .

[0022] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, such as fused silica glass or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light of a portion of visible light wavelengths, a portion of infrared wavelengths (near infrared) near the visible spectrum, and a portion of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths close to extreme ultraviolet wavelengths. In some embodiments, the size of the substrate 10 is 152 mm×152 mm and the thickness is approximately 20 mm. In other embodiments, the size of the substrate 10 is less than 152 mm×152 mm and is equal to or greater than 148 mm×148 mm. The shape of the substrate 10 is square or rectangular.

[0023] In some embodiments, the width of the functional layers (multilayer Mo / Si stack 15, cap layer 20, protection layer 22, absorber layer 25, first hard mask layer 30 and second hard mask layer 32) above the substrate is less than the width of the substrate 10. In some embodiments, the size of the functional layer is in the range from about 138 mm×138 mm to 142 mm×142 mm. In some embodiments, the shape of the functional layer is square or rectangular in a plan view.

[0024] In other embodiments, the protective layer 22, the absorber layer 25, the first hard mask layer 30 and the second hard mask layer 32 have smaller dimensions than the substrate 10, the multilayer Mo / Si stack 15, and the cap layer 20, ranging from about 138 mm×138 mm to 142 mm×142 mm, as shown in FIG. Figure 1C When each functional layer is formed by, for example, sputtering, a smaller size of one or more functional layers can be formed by using a frame-shaped cover having an opening ranging from about 138 mm×138 mm to 142 mm×142 mm. In other embodiments, all layers above the substrate 10 have the same size as the substrate 10.

[0025] In some embodiments, the Mo / Si multilayer stack 15 includes about 30 layers of silicon and molybdenum alternating layers to about 60 layers of silicon and molybdenum alternating layers. In certain embodiments, about 40 to about 50 layers of silicon and molybdenum alternating layers are formed. In some embodiments, for a wavelength of interest, such as 13.5nm, the reflectivity is higher than about 70%. In some embodiments, the silicon layer and the molybdenum layer are formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable method of forming a film. Each layer of silicon and molybdenum is about 2nm to about 10nm thick. In some embodiments, the silicon layer and the molybdenum layer have about the same thickness. In other embodiments, the silicon layer and the molybdenum layer have different thicknesses. In some embodiments, the thickness of each silicon layer is about 4nm, and the thickness of each molybdenum layer is about 3nm.

[0026] In other embodiments, the multilayer stack 15 includes alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100, but any number of layers is allowed as long as sufficient reflectivity is maintained for imaging the target substrate. In some embodiments, the reflectivity is greater than about 70% for wavelengths of interest, such as 13.5 nm. In some embodiments, the multilayer stack 15 includes about 30 to about 60 alternating layers of Mo and Be. In other embodiments of the present disclosure, the multilayer stack 15 includes about 40 to about 50 alternating layers of Mo and Be.

[0027] In some embodiments, the cap layer 20 is disposed on the Mo / Si multilayer stack 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the cap layer 20 is formed of ruthenium, a ruthenium alloy (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN), or a ruthenium-based oxide (e.g., RuO2, RuNbO, RiVO, or RuON) with a thickness in the range of about 2 nm to about 10 nm. In some embodiments, the thickness of the cap layer 20 is in the range of from about 2 nm to about 5 nm. In some embodiments, the thickness of the cap layer 20 is 3.5 nm ± 10%. In some embodiments, the cap layer 20 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable method of forming a film. In other embodiments, a Si layer is used as the cap layer 20.

[0028] In some embodiments, a protective (intermediate) layer 22 is formed between the cap layer 20 and the absorber layer 25. In some embodiments, the protective layer 22 is used to protect the cap layer 20. In some embodiments, the protective layer 22 includes: a Ta-based material, such as TaB, TaO, TaBO, or TaBN; silicon; a silicon-based compound (e.g., silicon oxide, SiN, SiON, or MoSi); ruthenium; or a ruthenium-based compound (Ru or RuB). In some embodiments, the thickness of the protective layer 22 is about 2 nm to about 20 nm. In some embodiments, the protective layer 22 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method. In some embodiments, the protective layer 22 is used as an etch stop layer during the patterning operation of the absorber layer.

[0029] In other embodiments, the intermediate layer 22 is a photocatalytic layer that can catalyze hydrocarbon residues formed on the photomask into CO2 and / or H2O using EUV radiation. Thus, in-situ self-cleaning of the mask surface is performed. In some embodiments, in an EUV scanner system, oxygen and hydrogen are injected into the EUV chamber to maintain the chamber pressure (e.g., at about 2 Pa). The chamber background gas can be a source of oxygen. In addition to the photocatalytic function, the photocatalytic layer is also designed to have sufficient durability and resistance to various chemicals and various chemical processes (e.g., cleaning and etching). Ozone water used to manufacture EUV reflective masks in subsequent processes may damage the cap layer 20 made of Ru and produce a significant decrease in EUV reflectivity. In addition, after Ru oxidation, Ru oxide is easily etched away by etchants such as C12 or CF4 gas. In some embodiments, the photocatalytic layer includes one or more of the following: titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), or cadmium sulfide (CdS). In some embodiments, the thickness of the photocatalytic layer 22 is in a range from about 2 nm to about 10 nm, and in other embodiments, in a range from about 3 nm to about 7 nm. When the thickness is too thin, the photocatalytic layer may not function adequately as an etch stop layer. When the thickness is too large, the photocatalytic layer may absorb EUV radiation.

[0030] The absorber layer 25 is disposed on the intermediate (protective) layer 22. In an embodiment of the present disclosure, the absorber layer 25 includes a Cr-based material, for example, Cr, CrN, CrON, and / or CrCON. In some embodiments, in the case of CrON or CrCON, the nitrogen content is in the range of from about 10 atomic % to about 30 atomic %. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrN, CrON, and / or CrCON.

[0031] In certain embodiments, a CrN layer is used as the absorber layer 25. In some embodiments, when a CrN layer is used, the nitrogen content is in the range of about 16 atomic % to about 40 atomic %. When the nitrogen content is in the range of about 16 atomic % to about 30 atomic %, the CrN absorber layer includes a Cr phase and a Cr2N phase. When the nitrogen content is in the range of about 30 atomic % to about 33 atomic %, the CrN absorber layer is substantially composed of a Cr2N phase (e.g., greater than 95 vol %). When the nitrogen content is in the range of about 33 atomic % to about 40 atomic %, the CrN absorber layer includes a Cr2N phase and a CrN phase. The phases can be observed by electron energy loss spectroscopy (EELS), transmission electron microscopy (TEM), and / or X-ray diffraction (XRD) analysis. In some embodiments, the two phases form a solid solution.

[0032] In some embodiments, the nitrogen concentration in the absorber layer 25 is not uniform. In some embodiments, the nitrogen concentration in the middle or center of the absorber layer 25 is higher than the nitrogen concentration at the surface area of ​​the absorber layer 25. In some embodiments, the CrN absorber layer includes one or more impurities other than Cr and N, which are less than about 5 atomic%. In some embodiments, the absorber layer 25 also includes one or more elements of Co, Te, Hf and / or Ni.

[0033] In some embodiments, the thickness of the absorber layer 25 ranges from about 20 nm to about 50 nm, and in other embodiments, from about 35 nm to about 46 nm.

[0034] In some embodiments, an anti-reflection layer (not shown) is optionally disposed on the absorber layer 25. In some embodiments, the anti-reflection layer is formed of silicon oxide and has a thickness of about 2 nm to about 10 nm. In other embodiments, a TaBO layer having a thickness ranging from about 12 nm to about 18 nm is used as the anti-reflection layer. In some embodiments, the thickness of the anti-reflection layer is about 3 nm to 6 nm. In some embodiments, the anti-reflection layer is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.

[0035] In some embodiments, oxide layer 27 includes one or more of Cr2O3 or CrO2. In some embodiments, oxide layer 27 is formed during the manufacturing operation of the mask blank. In some embodiments, the thickness of oxide layer 27 is in a range from about 1 nm to about 3 nm. In some embodiments, as Figure 1D As shown, no oxide layer is formed.

[0036] In some embodiments, the first hard mask layer 30 is disposed on the oxide layer 27. In some embodiments, the first hard mask layer 30 is formed on the anti-reflective layer. In some embodiments, the first hard mask layer 30 is made of a Ta-based material, for example, TaB, TaO, TaBO, or TaBN. In other embodiments, the first hard mask layer 30 is made of silicon, a silicon-based compound (for example, silicon oxide, SiN, SiON, or MoSi), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the first hard mask layer 30 is made of the same or similar material as the protective layer 22. In some embodiments, the thickness of the first hard mask layer 30 is from about 2 nm to about 20 nm. In some embodiments, the first hard mask layer 30 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0037] In some embodiments, the second hard mask layer 32 is disposed on the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is made of one or more of GaN, CrON, CrCON, silicon oxide, SiCO, and / or yttrium oxide. In some embodiments, the thickness of the second hard mask layer 32 is about 2 nm to about 20 nm. In some embodiments, the second hard mask layer 32 is less than or greater than the thickness of the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0038] In some embodiments, the second hard mask layer 32 is made of a material having a higher etching rate for plasma including chlorine and oxygen than the material of the first hard mask layer 30. In some embodiments, the first hard mask layer 30 is made of a material having a higher etching rate for plasma including fluorine than the material of the second hard mask layer 32.

[0039] In some embodiments, one or more functional layers (multilayer Mo / Si stack 15, cap layer 20, protection layer 22, absorber layer 25, oxide layer 27, first hard mask layer 30, and second hard mask layer 32) above the substrate have a polycrystalline structure (e.g., a nano-crystalline structure) or an amorphous structure.

[0040] In some embodiments, the back conductive layer 45 is disposed on a second main surface of the substrate 10, which is opposite to the first main surface of the substrate 10 on which the Mo / Si multilayer stack 15 is formed. In some embodiments, the back conductive layer 45 is formed of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4 and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous. In other embodiments, the back conductive layer 45 is formed of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or less than 20Ω / □. In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or greater than 0.1Ω / □. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or less than 0.25nm. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or greater than 0.05nm. In addition, in some embodiments, the flatness of the back conductive layer 45 (within the EUV photomask) is equal to or less than 50nm. In some embodiments, the flatness of the back conductive layer 45 is greater than 1nm. In some embodiments, the thickness of the back conductive layer 45 is in the range from about 50nm to about 400nm. In other embodiments, the back conductive layer 45 has a thickness of about 50nm to about 100nm. In certain embodiments, the thickness is in the range from about 65nm to about 75nm. In some embodiments, the back conductive layer 45 is formed by atmospheric chemical vapor deposition (CVD), low pressure CVD, plasma enhanced CVD, laser enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation and sputtering) or any other suitable method of forming a film. In some embodiments, in the case of CVD, the source gas includes TaCl5 and BCl3.

[0041] In some embodiments, Figure 1E As shown, a substrate protection layer 12 is formed between the substrate 10 and the multilayer stack 15. In some embodiments, the substrate protection layer 12 is formed of Ru or a Ru compound, for example, RuO, RuNb, RuNbO, RuZr, and RuZrO. In some embodiments, the substrate protection layer 12 is formed of the same or different material as the cap layer 20. In some embodiments, the thickness of the substrate protection layer 12 is in a range from about 2 nm to about 10 nm.

[0042] Figure 2A-2F and Figure 3A-3E The method for manufacturing an EUV photomask for extreme ultraviolet lithography (EUVL) is schematically shown. It should be understood that in Figure 2A-Figure 3EAdditional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0043] In the manufacture of the EUV photomask, a first photoresist layer 35 is formed on the second hard mask layer 32 of the EUV photomask blank. Figure 2A As shown, the first photoresist layer 35 is then selectively exposed to actinic radiation EB, as shown in FIG. Figure 2B In some embodiments, before forming the first photoresist layer 35, the EUV photomask blank is inspected. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35, as shown in FIG. Figure 2C As shown. In some embodiments, the actinic radiation EB is an electron beam or an ion beam. In some embodiments, the pattern 40 corresponds to the pattern of semiconductor device features that an EUV photomask will be used to form in a subsequent operation. In some embodiments, the thickness of the first photoresist layer 35 on the second hard mask layer 32 is in the range from about 500 nm to about 1000 nm.

[0044] Next, the pattern 40 in the first photoresist layer 35 is extended into the second hard mask layer 32, thereby forming a pattern 41 in the second hard mask layer 32, exposing portions of the first hard mask layer 30, such as Figure 2D As shown. In some embodiments, a pattern 41 extending into the second hard mask layer 32 is formed by etching using a suitable wet or dry etchant that is selective to the first hard mask layer 30. In some embodiments, a plasma dry etching operation using a chlorine-containing gas (e.g., Cl2, HCl, BCl, and CCl4) and an oxygen-containing gas (e.g., O2) is used to pattern the second hard mask layer 32. In some embodiments, the material of the first hard mask layer 30 is selected to have a higher etch resistance (lower etch rate) relative to a plasma dry etching operation using chlorine and oxygen, and the etching is substantially stopped at the first hard mask layer 30. After forming the pattern 41 in the second hard mask layer 32, the first photoresist layer 35 is removed using a photoresist stripper to expose the upper surface of the second hard mask layer 32, as shown. Figure 2E shown.

[0045] Next, the pattern 41 in the second hard mask layer 32 is extended into the first hard mask layer 30, exposing portions of the oxide layer 27, such as Figure 2FAs shown. In some embodiments, a pattern 41 extending into the first hard mask layer 30 is formed by etching using a suitable wet or dry etchant that is selective to the oxide layer 27. In some embodiments, a plasma dry etching operation using a fluorine-containing gas (e.g., fluorocarbons (CF4, CHF3, etc.) and SF6) is used to pattern the first hard mask layer 30. In some embodiments, the material of the oxide layer 27 is selected to have a higher etching resistance (lower etching rate) relative to the plasma dry etching operation using fluorine, and the etching is substantially stopped at the oxide layer 27.

[0046] Then, the pattern 41 in the first hard mask layer 30 and the second hard mask layer 32 is extended into the absorber layer 25, thereby forming a pattern 42 in the absorber layer 25, exposing portions of the intermediate layer 22, such as Figure 3A As shown. The oxide layer 27 and the absorber layer 25 are etched by using a suitable wet or dry etchant that is selective to the first hard mask layer 30 and / or the intermediate layer 22. In some embodiments, a plasma dry etching operation using a chlorine-containing gas (e.g., Cl2, HCl, BCl, and CCl4) and an oxygen-containing gas (e.g., O2) is used to pattern the oxide layer 27 and the absorber layer 25. In some embodiments, the material of the intermediate layer 22 is selected to have a higher etching resistance (lower etching rate) relative to a plasma dry etching operation using chlorine and oxygen, and the etching is substantially stopped at the intermediate layer 22. In some embodiments, as Figure 3A As shown, the second hard mask layer 32 is removed during etching of the oxide layer 27 and the absorber layer 25. Specifically, when the second hard mask layer 32 is made of a Cr-based material (e.g., CrON or CrCON), the second hard mask layer 32 is removed during etching of the oxide layer 27 and the absorber layer 25. If the second hard mask layer 32 remains after etching the oxide layer 27 and the absorber layer 25, an additional removal operation of the second hard mask layer 32 is performed by using a suitable wet or dry etching process in some embodiments.

[0047] Then, the first hard mask layer 30 and the portion of the intermediate layer 22 located at the bottom of the pattern opening are removed together, as shown in FIG. Figure 3BAs shown. In some embodiments, etching is wet etching and / or dry etching. In some embodiments, a plasma dry etching operation using a fluorine-containing gas (e.g., fluorocarbons (CF4, CHF3, etc.) and SF6) is used to remove the first hard mask layer 30 and the intermediate layer 22. Specifically, when the first hard mask layer 30 is made of the same or similar material as the intermediate layer 22, the first hard mask layer 32 is removed together with the intermediate layer 22. In some embodiments, the material of the cap layer 20 is selected to have a higher etching resistance (lower etching rate) relative to a plasma dry etching operation using fluorine, and etching is substantially stopped at the cap layer 20.

[0048] like Figure 3C As shown, a second photoresist layer 50 is formed on the oxide layer 27, filling the pattern 42 in the oxide layer 27. The second photoresist layer 50 is selectively exposed to actinic radiation, such as an electron beam, an ion beam, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as shown in FIG. Figure 3C As shown. Pattern 55 corresponds to a black edge around the circuit pattern. The black edge is a frame-shaped area created by removing all the multiple layers on the EUV photomask in the area around the circuit pattern area. The frame-shaped area is created to prevent exposure of adjacent fields when the EUV photomask is printed on the wafer. In some embodiments, the width of the black edge is in the range from about 1 mm to about 5 mm.

[0049] Next, the pattern 55 in the second photoresist layer 50 is extended into the oxide layer 27, the absorber layer 25, the optional intermediate layer 22, the cap layer 20, and the Mo / Si multilayer 15, thereby forming a pattern 57 in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo / Si multilayer 15 (see Figure 3E ), exposing multiple portions of the substrate 10, such as Figure 3D In some embodiments, the pattern 57 is formed by etching using one or more suitable wet or dry etchants that are selective to each layer being etched. In some embodiments, plasma dry etching is used.

[0050] Then, the second photoresist layer 50 is removed by a suitable photoresist stripper to expose the upper surface of the oxide layer 27, such as Figure 3E In some embodiments of the present disclosure, the black edge pattern 57 in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo / Si multilayer 15 defines a black edge of the photomask. In addition, the photomask is cleaned, inspected, and repaired as needed to provide a finished photomask.

[0051] Figure 4 1 shows a cross-sectional view of a finished EUV photomask according to an embodiment of the present disclosure. Figure 4 The EUV photomask with the circuit pattern 42 shown includes a substrate 10, a multilayer Mo / Si stack 15 composed of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, an intermediate layer 22, a patterned absorber layer 25, and a patterned oxide layer 27. In addition, a black edge pattern 57 is formed in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo / Si multilayer 15, and a back conductive layer 45 is formed on the back side of the substrate 10. In some embodiments, the patterned absorber layer 25 includes a CrN layer or a nitrogen-rich CrON or CrCON layer, wherein the nitrogen content in some embodiments is in a range from about 10 atomic % to about 30 atomic %.

[0052] Figure 5A , Figure 5B and Figure 5C FIG. 4 shows a cross-sectional view of a multilayer structure of an absorber layer according to another embodiment of the present disclosure. It should be understood that Figure 2A-Figure 3E Additional operations are provided before, during and after the process shown, and for other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of these operations / processes may be interchangeable. The materials, configurations, processes and / or dimensions explained for the aforementioned embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Figure 5A , Figure 5B and Figure 5C The embodiment is for Figure 1D The mask blank shown is one in which no oxide layer is formed on the absorber layer 25 . Figure 5A Shows something like Figure 2F The structure after the first hard mask layer 30 is patterned. The etching of the first hard mask layer 30 is substantially stopped at the absorber layer 25.

[0053] Then, the absorber layer 25 is patterned (etched) by using the patterned first hard mask layer and the patterned second hard mask layer, as shown in FIG. Figure 5B In some embodiments, Figure 5B As shown, the second hard mask layer 32 is removed during the etching of the absorber layer 25. In some embodiments, when the intermediate layer 22 is made of the same or similar material as the first hard mask layer 30, the etching substantially stops at the intermediate layer 22. Then, as shown in FIG. Figure 5C As shown, the first hard mask layer 30 is removed together with a portion of the intermediate layer 22 located at the bottom of the opening pattern of the absorber layer 25 .

[0054] Figure 61 shows a cross-sectional view of a finished EUV photomask according to an embodiment of the present disclosure. Figure 6 The EUV photomask with the circuit pattern 42 shown includes a substrate 10, a multilayer Mo / Si stack 15 composed of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, an intermediate layer 22, and a patterned absorber layer 25. In addition, a black edge pattern 57 is formed in the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo / Si multilayer 15, and a back conductive layer 45 is formed on the back side of the substrate 10. In some embodiments, the patterned absorber layer 25 includes a CrN layer or a nitrogen-rich CrON or CrCON layer, wherein the nitrogen content in some embodiments is in a range from about 10 atomic % to about 30 atomic %.

[0055] Typically, Cr-based materials (CrN, CrON, or CrCON) have a high EUV absorption (extinction) coefficient k. For example, the k value of CrN is 0.0387, which is higher than the k value of TaBN (0.031) and the k value of TaBO (0.027). Therefore, the thickness of the absorber layer can be reduced (for example, from 70 nm of TaBN to 46 nm of CrN), which can suppress the three-dimensional effect of the patterned absorber layer. However, due to the low etching rate of the CrN layer or the nitrogen-rich CrON or CrCON layer, it is difficult to etch. Therefore, directly patterning the CrN layer may result in a poor pattern profile, thereby affecting the resolution of EUV lithography. In the present embodiment, two hard mask layers are used to pattern the absorber layer, and because the thickness of each hard mask layer is relatively thin (2-20 nm), the pattern profile of the etched pattern can be controlled. Therefore, a good pattern profile with a higher etching rate and a higher EUV absorption coefficient can be obtained.

[0056] Figure 7 A flow chart of manufacturing a mask blank for an EUV photomask according to an embodiment of the present disclosure is shown.

[0057] In some embodiments, at S701, a multilayer stack 15 is formed over a substrate 10. Then, at S702, a cap layer 20 is formed on the multilayer stack 15, and at S703, a protective layer 22 is formed on the cap layer 20. Next, at S704, an absorber layer 25 is formed on the protective layer 22. Subsequently, a first hard mask layer 30 and a second hard mask layer 32 are formed on the absorber layer 25 at S705 and S706, respectively. In some embodiments, after forming the absorber layer 25 and before forming the hard mask layer, an oxide layer 27 is formed by oxidation. In some embodiments, when a hard mask layer is formed without breaking a vacuum after forming the absorber layer 25, no oxide layer is formed on a top surface of the absorber layer 25.

[0058] Fig. 8AThe process of a method for manufacturing a semiconductor device is shown. Figure 8B , Figure 8C , Fig.8D and Fig. 8E Sequential manufacturing operations of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. A semiconductor substrate or other suitable substrate is provided, which is to be patterned to form an integrated circuit thereon. In some embodiments, the semiconductor substrate includes silicon. Alternatively or additionally, the semiconductor substrate includes germanium, silicon germanium, or other suitable semiconductor material, such as a III-V semiconductor material. Fig. 8A In S801, a target layer to be patterned is formed on a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer includes a conductive layer such as a metallization layer or a polysilicon layer, a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide, or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed on an underlying structure such as an isolation structure, a transistor, or a wiring. Fig. 8A At S802, a photoresist layer is formed on the target layer, such as Figure 8B As shown. In the subsequent photolithography exposure process, the photoresist layer is sensitive to radiation from the exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. The photoresist layer can be formed on the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to drive out the solvent in the photoresist layer. Fig. 8A In S803, the photoresist layer is patterned using the EUV reflective mask as described above, such as Figure 8B As shown. Patterning the photoresist layer includes performing a photolithography exposure process using an EUV exposure system using an EUV mask. In the exposure process, the integrated circuit (IC) design pattern defined on the EUV mask is imaged onto the photoresist layer to form a latent pattern thereon. Patterning the photoresist layer also includes developing the exposed photoresist layer to form a patterned photoresist layer having one or more openings. In an embodiment where the photoresist layer is a positive photoresist layer, the exposed portion of the photoresist layer is removed in the development process. Patterning the photoresist layer may also include other process steps, such as various baking steps at different stages. For example, a post-exposure baking (PEB) process may be implemented after the photolithography exposure process and before the development process.

[0059] exist Fig. 8A In S804, the target layer is patterned using the patterned photoresist layer as an etching mask, such as Fig.8DIn some embodiments, patterning the target layer includes applying an etching process to the target layer using the patterned photoresist layer as an etching mask. Portions of the target layer exposed within the openings of the patterned photoresist layer are etched, while the remaining portions are not etched. In addition, the patterned photoresist layer can be removed by wet stripping or plasma ashing, such as Fig. 8E shown.

[0060] In this embodiment, two hard mask layers are used to pattern the absorber layer, and because the thickness of each hard mask layer is relatively thin (2-20 nm), the pattern profile of the etched pattern can be controlled. Therefore, a good pattern profile with a higher etching rate and a higher EUV absorption coefficient can be obtained. In addition, because the CrN or nitrogen-rich CrON or CrCON layer has a higher EUV absorption coefficient, the thickness of the absorber layer can be reduced, which in turn suppresses the three-dimensional effect in EUV lithography.

[0061] It will be understood that not all advantages have been discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may have different advantages. According to one aspect of the present application, a reflective mask comprises: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, and an absorber layer disposed on the cap layer. The absorber layer comprises a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic %, or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %. In one or more of the foregoing and following embodiments, the thickness of the absorber layer is in the range of from 20 nm to 50 nm. In one or more of the foregoing and following embodiments, the absorber layer comprises a CrN layer having a nitrogen concentration of 16 atomic % to 40 atomic %. In one or more of the foregoing and following embodiments, the CrN layer comprises a Cr phase and a Cr2N phase. In one or more of the foregoing and following embodiments, the CrN layer consists of a Cr2N phase. In one or more of the foregoing and following embodiments, the CrN layer comprises a Cr2N phase and a CrN phase. In one or more of the foregoing and following embodiments, the reflective mask further comprises an intermediate layer disposed on the cap layer. In one or more of the foregoing and following embodiments, the intermediate layer comprises at least one of the following items: TaB, TaO, TaBO or TaBN, silicon, a silicon-based compound, ruthenium, or a ruthenium-based compound. In one or more of the foregoing and following embodiments, the intermediate layer comprises at least one of the following items: titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS). In one or more of the foregoing and following embodiments, in a plan view, the size of the periphery of the absorber layer is smaller than the size of the periphery of the substrate. In one or more of the foregoing and following embodiments, in a plan view, the size of the periphery of the absorber layer is in the range of from 138 mm×138 mm to 142 mm×142 mm, and in a plan view, the size of the periphery of the substrate is in the range of from 148 mm×148 mm to 152 mm×152 mm.

[0062] According to another aspect of the present disclosure, a reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an absorber layer disposed on the cap layer, and a Cr oxide layer disposed on the absorber layer. The absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic %, or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %. In one or more of the foregoing and following embodiments, the Cr oxide layer includes Cr2O3 or CrO2. In one or more of the foregoing and following embodiments, the thickness of the Cr oxide layer is in the range from 1 nm to 3 nm. In one or more of the foregoing and following embodiments, the reflective mask further includes: an intermediate layer disposed on the cap layer. In one or more of the foregoing and following embodiments, the intermediate layer includes at least one of the following items: TaB, TaO, TaBO, or TaBN.

[0063] According to another aspect of the present disclosure, a reflective mask blank for an EUV mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an intermediate layer disposed on the cap layer, an absorber layer disposed on the intermediate layer, a first hard mask layer disposed on the absorber layer, and a second hard mask layer disposed on the first hard mask layer. In one or more of the foregoing and following embodiments, the second hard mask layer is made of a material having a higher etching rate for a plasma including chlorine and oxygen than the material of the first hard mask layer. In one or more of the foregoing and following embodiments, the first hard mask layer is made of a material having a higher etching rate for a plasma including fluorine than the material of the second hard mask layer. In one or more of the foregoing and following embodiments, the absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic %, or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

[0064] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes: a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer. The photoresist layer is patterned, the second hard mask layer is patterned by using the patterned photoresist layer, the first hard mask layer is patterned by using the patterned second hard mask layer, and the absorber layer is patterned by using the patterned first hard mask layer and the patterned second hard mask layer. In one or more of the foregoing and following embodiments, when patterning the second hard mask layer, a first plasma dry etching using a chlorine-containing gas and an oxygen-containing gas is adopted. In one or more of the foregoing and following embodiments, the second hard mask layer is made of a material having a higher etching rate in plasma dry etching than the material of the first hard mask layer. In one or more of the foregoing and following embodiments, when patterning the absorber layer, a second plasma dry etching using a chlorine-containing gas and an oxygen-containing gas is used. In one or more of the foregoing and following embodiments, the patterned second hard mask layer is removed during the second plasma dry etching. In one or more of the foregoing and following embodiments, when patterning the first hard mask layer, a first plasma dry etching using a fluorine-containing gas is used. In one or more of the foregoing and following embodiments, the first hard mask layer is made of a material having a higher etching rate in plasma dry etching than the material of the second hard mask layer. In one or more of the foregoing and following embodiments, after patterning the absorber layer, the intermediate layer is patterned by using a second plasma dry etching using a fluorine-containing gas. In one or more of the foregoing and following embodiments, the intermediate layer is made of a material having a higher etching rate in the second plasma dry etching than the material of the second hard mask layer. In one or more of the foregoing and following embodiments, the patterned first hard mask layer is removed during the second plasma dry etching.

[0065] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes: a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer. The photoresist layer is patterned, the second hard mask layer is patterned by using the patterned photoresist layer, the first hard mask layer is patterned by using the patterned second hard mask layer, the absorber layer is patterned by using the patterned first hard mask layer and the patterned second hard mask layer, and the first hard mask layer is removed. The second hard mask layer and the absorber layer include a Cr-based compound, and the first hard mask layer and the intermediate layer include a Ta-based compound. In one or more of the foregoing and following embodiments, the second hard mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON with a nitrogen concentration of 10 atomic % to 30 atomic %, or CrCON with a nitrogen concentration of 10 atomic % to 30 atomic %. In one or more of the foregoing and following embodiments, the first hard mask layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O, and the intermediate layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O. In one or more of the foregoing and following embodiments, the second hard mask layer is removed during patterning of the absorber layer. In one or more of the foregoing and following embodiments, a portion of the intermediate layer is patterned during removal of the first hard mask layer.

[0066] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer. The photoresist layer is patterned, the second hard mask layer is patterned by using the patterned photoresist layer, the first hard mask layer is patterned by using the patterned second hard mask layer, the oxide layer and the absorber layer are patterned by using the patterned first hard mask layer and the patterned second hard mask layer, and the intermediate layer is patterned. In one or more of the foregoing and following embodiments, the second hard mask layer and the absorber layer include a material having a higher etching rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than the material of the first hard mask layer and the material of the intermediate layer. In one or more of the foregoing and following embodiments, the thickness of each of the first hard mask layer and the second hard mask layer is in a range from 2 nm to 20 nm. In one or more of the foregoing and following embodiments, the second hard mask layer includes GaN, SiCO, or yttrium oxide. In one or more of the foregoing and following embodiments, the oxide layer includes Cr2O3 or CrO2.

[0067] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0068] Example 1. A reflective mask, comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer comprises a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic %, or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

[0069] Example 2. The reflective mask of Example 1, wherein the absorber layer has a thickness in a range from 20 nm to 50 nm.

[0070] Example 3. The reflective mask of Example 1, wherein the absorber layer comprises a CrN layer having a nitrogen concentration of 16 atomic % to 40 atomic %.

[0071] Example 4. The reflective mask of Example 3, wherein the CrN layer comprises a Cr phase and a Cr2N phase.

[0072] Example 5. The reflective mask of Example 3, wherein the CrN layer consists of a Cr2N phase.

[0073] Example 6. The reflective mask of Example 3, wherein the CrN layer comprises a Cr2N phase and a CrN phase.

[0074] Example 7. The reflective mask according to Example 1 further includes: an intermediate layer disposed on the cap layer.

[0075] Example 8. The reflective mask of Example 7, wherein the intermediate layer comprises at least one of the following: TaB, TaO, TaBO or TaBN, silicon, a silicon-based compound, ruthenium, or a ruthenium-based compound.

[0076] Example 9. The reflective mask of Example 7, wherein the intermediate layer comprises at least one of the following: titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), or cadmium sulfide (CdS).

[0077] Example 10. The reflective mask of Example 1, wherein, in a plan view, a size of an outer periphery of the absorber layer is smaller than a size of an outer periphery of the substrate.

[0078] Example 11. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer; and removing the first hard mask layer, wherein the second hard mask layer and the absorber layer comprise a Cr-based compound, and the first hard mask layer and the intermediate layer comprise a Ta-based compound.

[0079] Example 12. The method of Example 11, wherein the second hard mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON with a nitrogen concentration of 10 atomic % to 30 atomic %, or CrCON with a nitrogen concentration of 10 atomic % to 30 atomic %.

[0080] Example 13. The method of Example 11, wherein the first hard mask layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O, and the intermediate layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O.

[0081] Example 14. The method of Example 11, wherein the second hard mask layer is removed during patterning of the absorber layer.

[0082] Example 15. The method of Example 11, wherein a portion of the intermediate layer is patterned during the removal of the first hard mask layer.

[0083] Example 16. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the oxide layer and the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer; and patterning the intermediate layer.

[0084] Example 17. The method according to Example 16, wherein the second hard mask layer and the absorber layer include a material having a higher etching rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas compared to a material of the first hard mask layer and a material of the intermediate layer.

[0085] Example 18. The method of Example 17, wherein a thickness of each of the first hard mask layer and the second hard mask layer is in a range from 2 nm to 20 nm.

[0086] Example 19. The method of Example 17, wherein the second hard mask layer comprises GaN, SiCO, or yttrium oxide.

[0087] Example 20. The method of Example 17, wherein the oxide layer comprises Cr2O3 or CrO2.

Claims

1. A reflective mask, comprising: substrate; a reflective multilayer disposed on the substrate; A cap layer, disposed on the reflective multilayer; as well as an absorbent layer, disposed on the cap layer, The absorber layer includes a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic % or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

2. The reflective mask according to claim 1, wherein: The thickness of the absorber layer is in the range from 20 nm to 50 nm.

3. The reflective mask according to claim 1, wherein: The absorber layer includes a CrN layer having a nitrogen concentration of 16 atomic % to 40 atomic %.

4. The reflective mask according to claim 3, wherein: The CrN layer includes a Cr phase and a Cr2N phase.

5. The reflective mask according to claim 3, wherein: The CrN layer consists of a Cr2N phase.

6. The reflective mask according to claim 3, wherein: The CrN layer includes a Cr2N phase and a CrN phase.

7. The reflective mask according to claim 1, further comprising: The middle layer is arranged on the cap layer.

8. The reflective mask according to claim 7, wherein: The intermediate layer includes at least one of the following: TaB, TaO, TaBO or TaBN, silicon, a silicon-based compound, ruthenium, or a ruthenium-based compound.

9. The reflective mask according to claim 7, wherein: The intermediate layer includes at least one of the following items: titanium oxide TiO2, tin oxide SnO, zinc oxide ZnO or cadmium sulfide CdS.

10. The reflective mask according to claim 1, wherein: In a plan view, the size of the outer periphery of the absorber layer is smaller than the size of the outer periphery of the substrate.

11. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an intermediate layer on the capping layer, an absorber layer on the intermediate layer, a first hard mask layer over the absorber layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer; as well as removing the first hard mask layer, wherein the second hard mask layer and the absorber layer include a Cr-based compound, and the first hard mask layer and the intermediate layer include a Ta-based compound, The absorber layer includes a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic % or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

12. The method according to claim 11, wherein: The second hard mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON having a nitrogen concentration of 10 to 30 atomic %, or CrCON having a nitrogen concentration of 10 to 30 atomic %.

13. The method according to claim 11, wherein: The first hard mask layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O, and the intermediate layer is made of TaBO, Ta2O5, TaO2, TaO or Ta2O.

14. The method according to claim 11, wherein: The second hard mask layer is removed during patterning of the absorber layer.

15. The method according to claim 11, wherein: During the removal of the first hard mask layer, a portion of the intermediate layer is patterned.

16. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an intermediate layer on the capping layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the oxide layer and the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; as well as patterning the intermediate layer, The absorber layer includes a CrON layer having a nitrogen concentration of 10 atomic % to 30 atomic % or a CrCON layer having a nitrogen concentration of 10 atomic % to 30 atomic %.

17. The method according to claim 16, wherein: The second hard mask layer and the absorber layer include a material having a higher etching rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than a material of the first hard mask layer and a material of the intermediate layer.

18. The method according to claim 17, wherein: A thickness of each of the first hard mask layer and the second hard mask layer is in a range from 2 nm to 20 nm.

19. The method according to claim 17, wherein: The second hard mask layer includes GaN, SiCO, or yttrium oxide.

20. The method according to claim 17, wherein: The oxide layer includes Cr2O3 or CrO2.

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