Page buffer and semiconductor memory device having the same

Abstract

The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes: a first latch circuit configured to store data corresponding to one of a first programming state and a second programming state; a bit line controller connected to a bit line of a memory block and precharges the bit line by applying one of a first setting voltage and a second setting voltage to the bit line according to data stored in the first latch circuit during a bit line precharge operation in a programming verification operation; and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verification data according to a potential level of the main sensing node during the programming verification operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0032792 filed on March 17, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a page buffer and a semiconductor memory device including the page buffer. Background Art

[0004] Currently, the paradigm of computer environment has shifted to ubiquitous computing, which enables computer systems to be used anywhere, anytime. Therefore, the use of portable electronic devices such as mobile phones, digital cameras and notebook computers is rapidly increasing. Such portable electronic devices generally use memory systems that utilize semiconductor memory devices (i.e., data storage devices). The data storage devices are used as primary storage devices or auxiliary storage devices of the portable electronic devices.

[0005] Data storage devices using semiconductor memory devices have the following advantages: excellent stability and durability due to the absence of a mechanical drive, very fast access speed of information, and low power consumption. As examples of memory systems having these advantages, data storage devices include universal serial bus (USB) memory devices, memory cards with various interfaces, solid state drives (SSDs), etc.

[0006] Semiconductor memory devices are mainly classified into volatile memory devices and nonvolatile memory devices.

[0007] The writing speed and reading speed of non-volatile memory devices are relatively slow, however, even if the power is cut off, the non-volatile memory devices still maintain the stored data. Therefore, non-volatile memory devices are used to store data to be maintained regardless of the power supply. Non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR type and NAND type. Summary of the invention

[0008] A page buffer according to an embodiment of the present disclosure may include: a first latch circuit configured to store data corresponding to one of a first programming state and a second programming state; a bit line controller connected to a bit line of a memory block and configured to precharge the bit line by applying one of a first setting voltage and a second setting voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a programming verification operation; and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verification data according to a potential level of the main sensing node during the programming verification operation.

[0009] A page buffer according to an embodiment of the present disclosure may include: a bit line controller, which is connected to the bit lines of a memory block, configured to precharge the bit lines during a bit line precharge operation during a program verification operation corresponding to a first programming state and a second programming state, and configured to control the potential levels of a main sensing node and a sub sensing node according to the amount of current of the bit line during an evaluation operation in the program verification operation; a sensing node connecting component, which is connected between the main sensing node and the sub sensing node, configured to electrically connect the main sensing node and the sub sensing node to each other during a first period in the evaluation operation, and configured to electrically disconnect the main sensing node and the sub sensing node from each other during a second period after the first period; a first latch circuit, which is connected to the main sensing node and configured to sense first verification data according to the potential level of the main sensing node during the program verification operation; and a second latch circuit, which is connected to the sub sensing node and configured to sense second verification data according to the potential level of the sub sensing node during the program verification operation.

[0010] A semiconductor memory device according to an embodiment of the present disclosure includes: a memory block, which may include multiple memory cells programmed to multiple programming states; a voltage generating circuit, which is configured to generate a programming voltage and multiple verification voltages; an address decoder, which is configured to apply a programming voltage to a selected word line among the word lines of the memory block during a programming voltage application operation, and is configured to sequentially apply the multiple verification voltages to the selected word line during a programming verification operation; and page buffers, which are respectively connected to the bit lines of the memory block, and each of the page buffers is configured to simultaneously verify at least two programming states among the multiple programming states when one of the multiple verification voltages is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram for describing a memory system including a memory device according to one embodiment of the present disclosure.

[0012] Figure 2 is used to describe Figure 1 Schematic diagram of a semiconductor memory device included in a memory device of .

[0013] Figure 3 is a diagram for describing a three-dimensional memory block.

[0014] Figure 4 Is used to describe Figure 3 A circuit diagram of one of the memory blocks shown.

[0015] Figure 5 Is used to describe Figure 4 Circuit diagram of the memory string shown.

[0016] Figure 6 It is a threshold voltage distribution diagram used to describe the erased state and multiple programmed states of a memory cell.

[0017] Figure 7 is a diagram for describing a page buffer according to one embodiment of the present disclosure.

[0018] Figure 8 1 is a voltage waveform diagram for describing a program voltage and a verification voltage applied to a selected word line during a program operation according to the present disclosure.

[0019] Fig. 9 It is used to describe an embodiment according to the present disclosure. Figure 7 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0020] Fig.10 is a diagram for describing a cell current variation of two adjacent program states according to a precharge voltage level of a bit line.

[0021] Fig.11 is used to describe another embodiment according to the present disclosure Figure 7 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0022] Fig.12 is a diagram for describing a page buffer according to another embodiment of the present disclosure.

[0023] Fig.13 It is used to describe an embodiment according to the present disclosure. Fig.12 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0024] Fig.14 is a diagram for describing a page buffer according to still another embodiment of the present disclosure.

[0025] Fig.15 It is used to describe an embodiment according to the present disclosure. Fig.141 is a waveform diagram of signals of a program verification operation of a page buffer.

[0026] Fig.16 is a diagram for describing another embodiment of a memory system.

[0027] Fig.17 is a diagram for describing another embodiment of a memory system.

[0028] Fig.18 is a diagram for describing another embodiment of a memory system.

[0029] Fig.19 is a diagram for describing another embodiment of a memory system. DETAILED DESCRIPTION

[0030] The specific structural or functional description of the embodiment according to the concept disclosed in this specification or application is only used to describe the embodiment according to the concept of the present disclosure. The embodiment according to the concept of the present disclosure can be implemented in various forms, and the description is not limited to the embodiment described in this specification or application.

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can carry out the technical spirit of the present disclosure.

[0032] One embodiment of the present disclosure provides a page buffer capable of reducing a program verification time and a semiconductor memory device including the same.

[0033] According to one embodiment, during a program verification operation, at least two program states may be verified together to reduce the program verification operation time.

[0034] Figure 1 is a block diagram for describing a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , the memory system 1000 includes a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 includes a plurality of semiconductor memory devices 100. The plurality of semiconductor memory devices 100 may be divided into a plurality of groups. Although in one embodiment of the present disclosure, the host 1300 is shown and described as being included in the memory system 1000, the memory system 1000 may be configured to include only the controller 1200 and the memory device 1100, and the host may be configured to be disposed outside the memory system 1000.

[0036] exist Figure 1In the embodiment, the plurality of groups GR1-GRn of the memory device 1100 communicate with the controller 1200 through the first to nth channels CH1-CHn, respectively. Figure 2 Each semiconductor memory device 100 is described.

[0037] Each of the groups GR1-GRn is configured to communicate with the controller 1200 through one common channel. The controller 1200 is configured to control the plurality of semiconductor memories 100 of the memory device 1100 through the plurality of channels CH1-CHn.

[0038] In one embodiment of the present disclosure, a plurality of semiconductor memory devices 100 included in the memory device 1100 perform a multi-verification operation of verifying two or more adjacent program states together using one verification voltage during a program verification operation. Therefore, the program verification operation time can be improved.

[0039] The controller 1200 is connected between the host 1300 and the memory device 1100. The controller 1200 is configured to access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 is configured to control the read, program, erase, and background operations of the memory device 1100 in response to the host command Host_CMD received from the host 1300. During the programming operation, the host 1300 may send data DATA and an address ADD to be programmed together with the host command Host_CMD, and during the read operation, the host 1300 may send an address ADD together with the host command Host_CMD. During the programming operation, the controller 1200 sends a command corresponding to the programming operation and data DATA to be programmed to the memory device 1100. During the read operation, the controller 1200 sends a command corresponding to the read operation to the memory device 1100, receives the read data DATA from the memory device 1100, and sends the received data DATA to the host 1300. The controller 1200 is configured to provide an interface between the memory device 1100 and the host 1300. The controller 1200 is configured to drive firmware for controlling the memory device 1100.

[0040] The host 1300 includes a portable electronic device such as a computer, a PDA, a PMP, an MP3 player, a camera, a camcorder, or a mobile phone. The host 1300 may request a program operation, a read operation, an erase operation, etc. of the memory system 1000 through a host command Host_CMD. The host 1300 may send a host command Host_CMD, data DATA, and an address ADD corresponding to a program operation to the controller 1200 for a program operation of the memory device 1100, and may send a host command Host_CMD and an address ADD corresponding to a read operation to the controller 1200 for a read operation. At this time, the address ADD may be a logical address (logical address block) of the data.

[0041] The controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device. For one embodiment, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to configure a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC), and a universal flash device (UFS).

[0042] As another example, the memory system 1000 is configured as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a netbook, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, and a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telecommunications network, an RFID device, or one of various components configuring a computing system.

[0043] In one embodiment, the memory device 1100 or the memory system 1000 may be installed as various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged and installed in the following methods, such as package stacking (PoP), ball grid array (BGA), chip scale package (CSP), plastic lead chip carrier (PLCC), plastic dual in-line package (PDIP), die in stacked packages, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP) or wafer-level processing stacked package (WSP).

[0044] Figure 2 is used to describe Figure 1 Schematic diagram of a semiconductor memory device included in a memory device of .

[0045] When from Figure 1 When the controller 1200 receives a command CMD corresponding to a program operation, the semiconductor memory device 100 according to one embodiment of the present disclosure may perform a program voltage application operation and a program verification operation on a memory cell connected to a selected word line. During the program verification operation, the semiconductor memory device 100 may verify at least two program states together when one verification voltage is applied to the selected word line.

[0046] Reference Figure 2 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, and a voltage generating circuit 150. The address decoder 120, the read / write circuit 130, and the voltage generating circuit 150 may be defined as a peripheral circuit 160 that performs a read operation on the memory cell array 110. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit that operates according to an algorithm and / or a processor that executes a control logic code.

[0047] The memory cell array 110 includes a plurality of memory blocks BLK1-BLKz. The plurality of memory blocks BLK1-BLKz are connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1-BLKz are connected to the read / write circuit 130 via bit lines BL1-BLm. Each memory block in the plurality of memory blocks BLK1-BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells. A plurality of memory cells connected to one word line in the plurality of memory cells may be defined as one page. That is, the memory cell array 110 may be configured with a plurality of pages.

[0048] Each of the plurality of memory blocks BLK1-BLKz of the memory cell array 110 includes a plurality of memory strings. Each of the plurality of memory strings includes a drain select transistor, a plurality of memory cells, and a source select transistor connected in series between a bit line and a source line. In addition, each of the plurality of memory strings may include a pass transistor located between the source select transistor and the memory cell and between the drain select transistor and the memory cell, and may further include a pipe gate transistor located between the memory cells. A description of the memory cell array 110 will be described later.

[0049] The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to address decoder control signals AD_signals generated in the control logic 140. The address decoder 120 receives the address ADDR through an input / output buffer (not shown) within the memory device 100.

[0050] During a programming operation, the address decoder 120 may decode a row address of a received address ADDR, and may apply multiple operating voltages to multiple memory cells of the memory cell array 110 according to the decoded row address, the multiple operating voltages including a programming voltage Vpgm, a pass voltage Vpass, and multiple verification voltages Vverify generated by a voltage generating circuit 150.

[0051] The address decoder 120 is configured to decode the column address of the received address ADDR and send the decoded column address Yi to the read / write circuit 130 .

[0052] The address ADDR received during the program operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line according to the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read / write circuit 130.

[0053] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0054] The read / write circuit 130 includes a plurality of page buffers PB1-PBm. The plurality of page buffers PB1-PBm are connected to the memory cell array 110 through bit lines BL1-BLm. Each of the plurality of page buffers PB1-PBm temporarily stores the to-be-programmed data DATA which is obtained from the memory cell array 110 before the programming voltage application operation. Figure 1 The controller 1200 is received. In addition, during the programming voltage application operation, each of the multiple page buffers PB1-PBm controls the potential level of the bit line BL1-BLm according to the temporarily stored data DATA. In addition, each of the multiple page buffers PB1-PBm precharges the corresponding bit line to a set level according to the temporarily stored data during the programming verification operation, and performs the programming verification operation by sensing the cell current of the bit line. In addition, each of the multiple page buffers PB1-PBm sets the bit line evaluation time according to the temporarily stored data during the programming verification operation, and performs the programming verification operation by evaluating the bit line and the sensing node in the page buffer during the set evaluation time. The description of the multiple page buffers PB1-PBm will be described later.

[0055] The read and write circuit 130 operates in response to the page buffer control signal PB_signals output from the control logic 140 .

[0056] In one embodiment, the read / write circuit 130 may include a page buffer (or page register), a column selection circuit, and the like.

[0057] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, and the voltage generating circuit 150. The control logic 140 receives the command CMD through the input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 is configured to control the overall operation of the semiconductor memory device 100 in response to the command CMD. For example, the control logic 140 receives the command CMD corresponding to the programming operation, and generates and outputs the address decoder control signal AD_signals for controlling the address decoder 120, the page buffer control signal PB_signals for controlling the read / write circuit 130, and the voltage generating circuit control signal VG_signals for controlling the voltage generating circuit 150 in response to the received command CMD.

[0058] During a program operation, the voltage generating circuit 150 generates a program voltage Vpgm, a pass voltage Vpass, and multiple verification voltages Vverify according to the control of the voltage generating circuit control signal VG_signals output from the control logic 140 , and outputs the program voltage Vpgm, pass voltage Vpass, and multiple verification voltages Vverify to the address decoder 120 .

[0059] Figure 3 is a diagram for describing a three-dimensional memory block.

[0060] Reference Figure 3 , the three-dimensional memory blocks BLK1-BLKz may be arranged to be spaced apart from each other along the direction Y, and the bit lines BL1-BLM extend in the direction Y. For example, the first to z-th memory blocks BLK1-BLKz may be arranged to be spaced apart from each other along the second direction Y, and include a plurality of memory cells stacked along the third direction Z. Figure 4 and Figure 5 The configuration of any one of the first to z-th memory blocks BLK1 -BLKz is described in detail.

[0061] Figure 4 Is used to describe Figure 3 A circuit diagram of one of the memory blocks shown.

[0062] Figure 5 Is used to describe Figure 4 Circuit diagram of the memory string shown.

[0063] refer to Figure 4 and Figure 5 , each memory string ST may be connected between the bit lines BL1-BLm and the source line SL. The memory string ST connected between the first bit line BL1 and the source line SL will be described as an example.

[0064] The memory string ST may include a source selection transistor SST, memory cells F1-Fn (n is a positive integer) and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. The gates of the source selection transistors SST included in different memory strings ST connected to different bit lines BL1-BLm may be connected to a first source selection line SSL0 and a second source selection line SSL1. For example, source selection transistors adjacent to each other in a second direction Y in the source selection transistors SST may be connected to the same source selection line. For example, assuming that the source selection transistors SST are arranged sequentially along the second direction Y, the gates of the source selection transistors SST arranged along the first direction X starting from the first source selection transistor SST and included in different strings ST and the gates of the source selection transistors SST arranged along the first direction X starting from the second source selection transistor SST and included in different strings ST may be connected to the first source selection line SSL0. In addition, gates of source selection transistors SST arranged along the first direction X from the third source selection transistor SST and included in different strings ST and gates of source selection transistors SST arranged along the first direction X from the fourth source selection transistor SST and included in different strings ST may be connected to the second source selection line SSL1.

[0065] Gates of the memory cells F1 -Fn may be connected to the word lines WL1 -WLn, and a gate of the drain select transistor DST may be connected to any one of the first to fourth drain select lines DSL0 - DSL3 .

[0066] The gates of the transistors arranged along the first direction X among the drain selection transistors DST may be commonly connected to the same drain selection line (e.g., DSL0), but the transistors arranged in the second direction Y may be connected to different drain selection lines DSL1-DSL3. For example, assuming that the drain selection transistors DST are sequentially arranged along the second direction Y, the gates of the drain selection transistors DST arranged along the first direction X starting from the first drain selection transistor DST and included in different strings ST may be connected to the first drain selection line DSL0. The drain selection transistors DST arranged along the second direction Y starting from the drain selection transistor DST connected to the first drain selection line DSL0 may be sequentially connected to the second to fourth drain selection lines DSL1-DSL3. Therefore, the memory string ST connected to the selected drain selection line may be selected within the selected memory block, and the memory strings ST connected to the remaining unselected drain selection lines may not be selected.

[0067] Memory cells connected to the same word line may form a page PG. Here, page means a physical page. For example, in a string ST connected to the first bit line BL1 to the mth bit line BLm, a group of memory cells connected along the first direction X at the same word line is called a page PG. For example, in the first memory cell F1 connected to the first word line WL1, the memory cells arranged along the first direction X may form a page PG. In the first memory cell F1 commonly connected to the first word line WL1, the cells arranged along the second direction Y may be divided into different pages. Therefore, when the first drain selection line DSL0 is the selected drain selection line and the first word line WL1 is the selected word line, the page connected to the first drain selection line DSL0 becomes the selected page among the multiple page PGs connected to the first word line WL1. The pages commonly connected to the first word line WL1 but connected to the unselected second to fourth drain selection lines DSL1-DSL3 become unselected pages.

[0068] In the accompanying drawings, one source select transistor SST and one drain select transistor DST are included in one string ST, but according to the semiconductor memory device, a plurality of source select transistors SST and a plurality of drain select transistors DST may be included in one string ST. In addition, according to the memory device, a dummy cell may be included between the source select transistor SST, the memory cells F1-Fn, and the drain select transistor DST. The dummy cell cannot store user data like the normal memory cells F1-Fn, but can be used to improve the electrical characteristics of each string ST. However, in the present embodiment, the dummy cell is not an important configuration, so its detailed description is omitted.

[0069] Figure 6 It is a threshold voltage distribution diagram used to describe the erased state and multiple programmed states of a memory cell.

[0070] Each of the memory cells may be a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) capable of storing four data bits. In one embodiment of the present disclosure, a programming operation of a QLC will be described as an example.

[0071] The programming operation may be performed on a plurality of memory cells included in one page, and thus the plurality of memory cells may be programmed to have threshold voltages corresponding to the erase state E and the plurality of program states PV1-PV15. The erase state E and the plurality of program states PV1-PV15 may be programmed by a plurality of verification voltages V PV1 -V PV15 For example, the threshold voltage distribution of the memory cells corresponding to the first programming state PV1 is equal to or higher than the verification voltage V PV1and is lower than the verification voltage V PV2 , and the threshold voltage distribution of the memory cells corresponding to the second programming state PV2 is equal to or higher than the verification voltage V PV2 and is lower than the verification voltage V PV3 .

[0072] Figure 7 is a diagram for describing a page buffer according to one embodiment of the present disclosure.

[0073] Figure 2 The illustrated plurality of page buffers PB1 -PBm may be configured in structures similar to one another, and in one embodiment of the present disclosure, the structure of the page buffer PB1 will be described as an example.

[0074] The page buffer PB1 may include a bit line controller 131 , a bit line discharger 132 , and a plurality of latch circuits S_LATCH, F_LATCH, D_LATCH, and M_LATCH.

[0075] During the programming voltage applying operation of the programming operation, the bit line controller 131 controls the potential level of the corresponding bit line BL1 to a programming inhibition voltage (e.g., VDD) or a programming permission voltage (e.g., VSS). During the programming verification operation of the programming operation, the bit line controller 131 precharges the potential level of the corresponding bit line BL1 to a first setting level or a second setting level according to the data stored in the latch circuit F_LATCH. The first setting level and the second setting level are potential levels higher than the ground power supply VSS and lower than the power supply voltage VDD. Thereafter, during the evaluation period, the bit line controller 131 electrically connects the bit line BL1 and the main sensing node SO to each other to control the potential level of the main sensing node SO according to the current change amount of the bit line BL1.

[0076] The bit line controller 131 may include a plurality of NMOS transistors N1 - N7 and a plurality of PMOS transistors P1 and P2 .

[0077] The NMOS transistor N1 is connected between the bit line BL1 and the node ND1 , and is turned on in response to the page buffer selection signal PBSEL to electrically connect the bit line BL1 and the node ND1 to each other.

[0078] The NMOS transistor N2 is connected between the node ND1 and the first common node CSO1 , and is turned on in response to the first page buffer sensing signal PB_SENSE1 to electrically connect the node ND1 and the first common node CSO1 to each other.

[0079] The NMOS transistor N3 and the NMOS transistor N4 are connected in parallel between the second common node CSO2 and the first common node CSO1. The NMOS transistor N3 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, and the NMOS transistor N4 is turned on in response to the potential of the node QF of the latch circuit F_LATCH to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other. The potential level when the second page buffer sensing signal PB_SENSE2 is at a high level is lower than the potential level when the first page buffer sensing signal PB_SENSE1 is at a high level. In addition, the potential level when the potential of the node QF is at a high level is higher than the potential level when the second page buffer sensing signal PB_SENSE2 is at a high level.

[0080] The PMOS transistor P1 and the PMOS transistor P2 are connected in series between a terminal of a power supply voltage VDD and a main sensing node SO, and are turned on in response to a node QS of a latch circuit S_LATCH and a precharge signal SA_PRECH_N, respectively.

[0081] The NMOS transistor N5 is connected between the second common node CSO2 and a node between the PMOS transistors P1 and P2 and is turned on in response to the control signal SA_CSOC to supply the power supply voltage VDD supplied through the PMOS transistor P1 to the second common node CSO2 .

[0082] The NMOS transistor N6 is connected between the main sensing node SO and the second common node CSO2, and is turned on in response to the transmission signal TRANSO to electrically connect the main sensing node SO and the second common node CSO2 to each other.

[0083] The NMOS transistor N7 is connected between the second common node CSO2 and the node ND2 of the latch circuit S_LATCH, and is turned on in response to the discharge signal SA_DISCH to electrically connect the second common node CSO2 and the node ND2 to each other.

[0084] During the bit line precharge operation of the program verification operation, the bit line controller 131 may precharge the bit line BL1 to a first setting level or a second setting level higher than the first setting level according to the node QS and the node QF.

[0085] For example, when the potential levels of the node QS and the node QF are at a low level, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the NMOS transistor N5 is turned on in response to the control signal SA_CSOC, so that the second common node CSO2 is charged to the level of VDD-Vth (threshold voltage of the NMOS transistor N5). The NMOS transistor N3 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path between the second common node CSO2 and the first common node CSO1, and the first common node CSO1 is charged to the level of the potential level of the second page buffer sensing signal PB_SENSE2-Vth (threshold voltage of the NMOS transistor N3). In addition, the NMOS transistor N1 and the NMOS transistor N2 are turned on in response to the page buffer selection signal PBSEL and the first page buffer sensing signal PB_SENSE1, respectively, so that the potential level of the first common node CSO1 is transmitted to the bit line BL1. At this time, since the potential level of the second page buffer sensing signal PB_SENSE2 is lower than the potential level of the first page buffer sensing signal PB_SENSE1, the potential level of the first common node CSO1 is transmitted to the bit line BL1 without performing a clamping operation. Therefore, the bit line BL1 is precharged to a level (first setting level) of the potential level of the second page buffer sensing signal PB_SENSE2 minus Vth (threshold voltage of the NMOS transistor N3).

[0086] On the other hand, when the potential level of the node QS is at a low level and the potential level of the node QF is at a high level, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the NMOS transistor N5 is turned on in response to the control signal SA_CSOC, thereby charging the second common node CSO2 to the level of VDD-Vth (the threshold voltage of the NMOS transistor N5).

[0087] The NMOS transistor N3 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path between the second common node CSO2 and the first common node CSO1, and the NMOS transistor N4 is turned on in response to the potential level of the node QF to form a current path between the second common node CSO2 and the first common node CSO1. At this time, since the potential level of the node QF applied to the gate of the NMOS transistor N4 is higher than the potential level of the second page buffer sensing signal PB_SENSE2, the potential level of the second common node CSO2 is transferred to the first common node CSO1 without clamping operation. Therefore, the first common node CSO1 is charged to the VDD-Vth (threshold voltage of the NMOS transistor N5) level. In addition, the NMOS transistor N1 and the NMOS transistor N2 are turned on in response to the page buffer selection signal PBSEL and the first page buffer sensing signal PB_SENSE1, respectively, so that the bit line BL1 is precharged. The clamping operation is generated by the NMOS transistor N2 , and thus the bit line BL1 is precharged to a level (a second setting level) of the potential level of the first page buffer sense signal PB_SENSE1 −Vth (a threshold voltage of the NMOS transistor N2 ).

[0088] The bit line discharger 132 is connected to the node ND1 of the bit line controller 131 to discharge the potential level of the bit line BL1 .

[0089] The bit line discharger 132 may include an NMOS transistor N28 connected between the node ND1 and a terminal of the ground power source VSS, and the NMOS transistor N28 is turned on in response to a bit line discharge signal BL_DIS to electrically connect the node ND1 and the terminal of the ground power source VSS.

[0090] The latch circuit S_LATCH may include a plurality of NMOS transistors N8 - N12 and inverters IV1 and IV2 .

[0091] Inverters IV1 and IV2 are connected in anti-parallel between the node QS and the node QS_N.

[0092] NMOS transistors N8 and NMOS transistors N9 are connected in series between the main sensing node SO and a terminal of the ground power source VSS, NMOS transistor N8 is turned on in response to a transmission signal TRANS, and NMOS transistor N9 is turned on or off according to a potential level of a node QS.

[0093] The NMOS transistor N10 is connected between the node QS and the node ND3, and is turned on in response to the reset signal SRST so that the node QS and the node ND3 are electrically connected to each other. The NMOS transistor N11 is connected between the node QS_N and the node ND3, and is turned on in response to the set signal SSET so that the node QS_N and the node ND3 are electrically connected to each other. The NMOS transistor N12 is connected between the node ND3 and the terminal of the ground power supply VSS, and is turned on according to the potential of the main sensing node SO so that the node ND3 and the terminal of the ground power supply VSS are electrically connected to each other. For example, in a state where the main sensing node SO is precharged to a high level, when the reset signal SRST is applied to the NMOS transistor N10 as a high level, the node QS and the node QS_N are initialized to a low level (ground power supply level; 0) and a high level (power supply voltage level; 1), respectively. In addition, in a state where the main sensing node SO is precharged to a high level, the set signal SSET is applied to the NMOS transistor N11 as a high level, and the node QS and the node QS_N are set to a high level (1) and a low level (0), respectively.

[0094] The latch circuit F_LATCH may include a plurality of NMOS transistors N13 - N17 and inverters IV3 and IV4 .

[0095] Inverters IV3 and IV4 are connected in anti-parallel between the node QF and the node QF_N.

[0096] NMOS transistors N13 and NMOS transistors N14 are connected in series between the main sensing node SO and a terminal of the ground power source VSS, NMOS transistor N13 is turned on in response to a transmission signal TRANF, and NMOS transistor N14 is turned on or off according to a potential level of a node QF.

[0097] The NMOS transistor N15 is connected between the node QF and the node ND4, and is turned on in response to the reset signal FRST so that the node QF and the node ND4 are electrically connected to each other. The NMOS transistor N16 is connected between the node QF_N and the node ND4, and is turned on in response to the set signal FSET so that the node QF_N and the node ND4 are electrically connected to each other. The NMOS transistor N17 is connected between the node ND4 and the terminal of the ground power supply VSS, and is turned on according to the potential of the main sensing node SO so that the node ND4 and the terminal of the ground power supply VSS are electrically connected to each other. For example, in a state where the main sensing node SO is precharged to a high level, when the reset signal FRST is applied to the NMOS transistor N15 as a high level, the node QF and the node QF_N are initialized to a low level (0) and a high level (1), respectively. In addition, in a state where the main sensing node SO is precharged to a high level, the set signal FSET is applied to the NMOS transistor N17 as a high level, and the node QF and the node QF_N are set to a high level (1) and a low level (0), respectively.

[0098] The latch circuit D_LATCH may include a plurality of NMOS transistors N18 - N22 and inverters IV5 and IV6 .

[0099] Inverters IV5 and IV6 are connected in anti-parallel between the node QD and the node QD_N.

[0100] NMOS transistor N18 and NMOS transistor N19 are connected in series between the main sensing node SO and a terminal of the ground power source VSS, NMOS transistor N18 is turned on in response to the transmission signal TRAND, and NMOS transistor N19 is turned on or off according to the potential level of the node QD.

[0101] The NMOS transistor N20 is connected between the node QD and the node ND5, and is turned on in response to the reset signal DRST to electrically connect the node QD and the node ND5 to each other. The NMOS transistor N21 is connected between the node QD_N and the node ND5, and is turned on in response to the set signal DSET to electrically connect the node QD_N and the node ND5 to each other. The NMOS transistor N22 is connected between the node ND5 and the terminal of the ground power supply VSS, and is turned on according to the potential of the main sensing node SO to electrically connect the node ND5 and the terminal of the ground power supply VSS to each other.

[0102] For example, when the NMOS transistor N21 is turned on by applying a set signal DSET of a high potential during a programming verification operation, the NMOS transistor N22 is turned on or off according to the potential level of the main sensing node SO (which is maintained or changed according to the current amount of the bit line BL1), so that the verification data can be stored in the latch circuit D_LATCH.

[0103] The latch circuit M_LATCH may include a plurality of NMOS transistors N23 - N27 and inverters IV7 and IV8 .

[0104] Inverters IV7 and IV8 are connected in anti-parallel between the node QM and the node QM_N.

[0105] NMOS transistor N23 and NMOS transistor N24 are connected in series between the main sensing node SO and a terminal of the ground power source VSS, NMOS transistor N23 is turned on in response to the transmission signal TRANM, and NMOS transistor N24 is turned on or off according to the potential level of the node QM.

[0106] The NMOS transistor N25 is connected between the node QM and the node ND6, and is turned on in response to the reset signal MRST to electrically connect the node QM and the node ND6 to each other. The NMOS transistor N26 is connected between the node QM_N and the node ND6, and is turned on in response to the set signal MSET to electrically connect the node QM_N and the node ND6 to each other. The NMOS transistor N27 is connected between the node ND6 and the terminal of the ground power supply VSS, and is turned on according to the potential of the main sensing node SO to electrically connect the node ND6 and the terminal of the ground power supply VSS to each other.

[0107] For example, when the NMOS transistor N26 is turned on by applying a high level of the set signal MSET during a programming verification operation, the NMOS transistor N27 is turned on or off according to the potential level of the main sensing node SO (which is maintained or changed according to the amount of current of the bit line BL1), so that the verification data can be stored in the latch circuit M_LATCH.

[0108] Figure 8 is a voltage waveform diagram for describing a program voltage and a verification voltage applied to a selected word line during a program operation according to the present disclosure.

[0109] refer to Figure 8 During a program operation according to the present disclosure, a program voltage application operation is performed by applying a program voltage Vpgm to a selected word line. At this time, a pass voltage is applied to unselected word lines.

[0110] Thereafter, by setting multiple verification voltages V PV2 、VPV4 、V PV6 、V PV8 、V PV10 、V PV12 、V PV14 and V PV15 Sequentially applied to the selected word line to perform multiple programming states ( Figure 6 During the program verification operation, a verification operation for at least two program states adjacent to each other can be performed simultaneously using one verification voltage. For example, by setting the verification voltage V PV2 is applied to the selected word line to simultaneously perform verification operations on the first programming state PV1 and the second programming state PV2. PV4 is applied to the selected word line to perform verification operations on the third program state PV3 and the fourth program state PV4 together, and by setting the verification voltage V PV6 is applied to the selected word line to perform verification operations on the fifth programming state PV5 and the sixth programming state PV6 together. In addition, by applying the verification voltage V PV8 is applied to the selected word line to perform verification operations on the seventh program state PV7 and the eighth program state PV8 together, and by setting the verification voltage V PV10 is applied to the selected word line to perform verification operations on the ninth programming state PV9 and the tenth programming state PV10 together. In addition, by applying the verification voltage V PV12 The verification operation of the eleventh program state PV11 and the twelfth program state PV12 is performed together by applying the verification voltage V PV14 is applied to the selected word line to perform verification operations on the thirteenth program state PV13 and the fourteenth program state PV14 together. Finally, by setting the verification voltage V PV15 A verification operation on the fifteenth program state PV15 is performed on the selected word line.

[0111] When a verification operation is performed on a plurality of program states together using one verification voltage, Figure 2 The page buffers PB1-PBm of the program memory may perform a program verification operation after precharging the corresponding bit lines to the first setting level or the second setting level according to the data to be programmed (which is temporarily stored during the program operation). For example, when the verification voltage V PV2 When performing verification operations on the first programming state PV1 and the second programming state PV2, the page buffer storing data corresponding to the first programming state PV1 can perform a programming verification operation by precharging the corresponding bit line to a first setting level, and the page buffer storing data corresponding to the second programming state PV2 can perform a programming verification operation by precharging the corresponding bit line to a second setting level higher than the first setting level.

[0112] Fig. 9 It is used to describe an embodiment according to the present disclosure. Figure 7 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0113] The following will refer to Figure 7 and Fig. 9 A program verification operation of a page buffer according to one embodiment of the present disclosure is described.

[0114] In one embodiment of the present disclosure, the verification voltage V PV2 A method of verifying each of a first program state PV1 and a second program state PV2 is applied to a selected word line.

[0115] When the data to be programmed corresponding to the first program state PV1 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH and the node QF of the latch circuit F_LATCH of the page buffer PB1 are set to a low level.

[0116] In the bit line precharge period tBLPRECH, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the PMOS transistor P2 is turned on in response to the low level precharge signal SA_PRECH_N, whereby the main sense node SO is precharged to the level of the power supply voltage VDD. The NMOS transistor N5 is turned on in response to the high level control signal SA_CSOC, so that the second common node CSO2 is charged to the VDD-Vth (threshold voltage of N5) level. The NMOS transistor N3 is turned on in response to the A level second page buffer sense signal PB_SENSE2 to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, whereby the first common node COS1 is charged to the potential A-Vth (threshold voltage of N3) of the second page buffer sense signal PB_SENSE2. Therefore, the bit line BL1 is precharged to the first setting level (PB_SENSE2-Vth).

[0117] When the verification voltage V PV2 When applied to the selected word line, the memory cells connected to the selected word line among the memory cells connected to the bit line BL1 have a threshold voltage higher than the verification voltage V PV1 When the threshold voltage is lower than the verification voltage V PV1 That is, the amount of current flowing through the bit line BL1 changes according to the threshold voltage of the memory cell.

[0118] Thereafter, in the evaluation period tEVAL, the precharge signal SA_PRECH_N is converted to a high level, the power supply voltage VDD applied to the main sensing node SO is cut off, the main sensing node SO and the second common node CSO2 are electrically connected to each other in response to the transmission signal TRANSO, and the main sensing node SO changes according to the current amount of the bit line BL1.

[0119] When the evaluation period tEVAL ends, the transmission signal TRANSO is converted to a low level, the NMOS transistor N6 is turned off, and the main sensing node SO and the bit line BL1 are electrically disconnected from each other. The NMOS transistor N27 of the latch circuit M_LATCH can be turned on or off according to the potential level of the main sensing node SO. Thereafter, a high-level setting signal MSET can be applied to the NMOS transistor N26, whereby the node QM_N can maintain a high level or be converted to a low level to store verification data.

[0120] When data to be programmed corresponding to the second program state PV2 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH of the page buffer PB1 is set to a low level, and the node QF of the latch circuit F_LATCH is set to a high level.

[0121] In the bit line precharge period tBLPRECH, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the PMOS transistor P2 is turned on in response to the low level precharge signal SA_PRECH_N, whereby the main sense node SO is precharged to the level of the power supply voltage VDD. The NMOS transistor N5 is turned on in response to the high level control signal SA_CSOC, so that the second common node CSO2 is charged to the level of VDD-Vth (threshold voltage of N5). The NMOS transistor N3 is turned on in response to the A level second page buffer sense signal PB_SENSE2 to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, and the NMOS transistor N4 is turned on in response to the potential level of the node QF to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other. At this time, since the potential level of the node QF applied to the gate of the NMOS transistor N4 is higher than the potential level of the second page buffer sensing signal PB_SENSE2, the potential level of the second common node CSO2 is transmitted to the first common node CSO1 without a clamping operation. Therefore, the first common node CSO1 is charged to the VDD-Vth (threshold voltage of N5) level. In addition, the NMOS transistor N2 is turned on in response to the B-level first page buffer sensing signal PB_SENSE1 (which is higher than the A of the second page buffer sensing signal PB_SENSE2), whereby the bit line BL1 is precharged, and a clamping operation is generated by the NMOS transistor N2, so that the bit line BL1 is precharged to the second setting level (PB_SENSE1-Vth).

[0122] When the verification voltage V PV2 When the verification voltage V is applied to the selected word line, the memory cells connected to the selected word line among the memory cells connected to the bit line BL1 have a threshold voltage higher than the verification voltage V PV2 When the threshold voltage is lower than the verification voltage V PV2 That is, the amount of current flowing through the bit line BL1 changes according to the threshold voltage of the memory cell.

[0123] Thereafter, in the evaluation period tEVAL, the precharge signal SA_PRECH_N is converted to a high level, the power supply voltage VDD applied to the main sensing node SO is cut off, the main sensing node SO and the second common node CSO2 are electrically connected to each other in response to the transmission signal TRANSO, and the potential level of the main sensing node SO changes according to the current amount of the bit line BL1.

[0124] When the evaluation period tEVAL ends, the transmission signal TRANSO is converted to a low level, the NMOS transistor N6 is turned off, and the main sensing node SO and the bit line BL1 are electrically disconnected from each other. The NMOS transistor N27 of the latch circuit M_LATCH can be turned on or off according to the potential level of the main sensing node SO. Thereafter, a high-level setting signal MSET can be applied to the NMOS transistor N26, whereby the node QM_N can maintain a high level or be converted to a low level to store verification data.

[0125] In the above-mentioned program verification operation, the use of the verification voltage V PV2 A method for performing a program verification operation on a first program state PV1 and a second program state PV2. After performing a program verification operation on the first program state PV1 and the second program state PV2, the verification voltage V PV4 The program verification operation uses the verification voltage V PV15 The program verification operation of the third program state PV3 to the fifteenth program state PV15 is performed by the program verification operation of the first program state PV15.

[0126] Table 1

[0127] Lower programming state Higher programming state Remaining programming status QS 0 (low level) 0 (low level) 1 (High level) QF 0 (low level) 1 (High level) 0 (low level) CSO2 VDD-Vth VDD-Vth GND(VSS) CSO1 PB_SENSE2-Vth VDD–Vth GND(VSS) BL PB_SENSE2-Vth PB_SENSE1-Vth GND(VSS)

[0128] Table 1 is a table showing set states of nodes QS and QF of a latch circuit and precharge levels of first and second common nodes CSO1 and CSO2 and a bit line BL during a program verification operation using one verification voltage.

[0129] In Table 1, a lower program state and an upper program state respectively indicate: in two program states for program verification using one verification voltage, a lower program state in which a threshold voltage distribution is low and an upper program state in which a threshold voltage distribution is high.

[0130] For example, when using the verification voltage V PV2 During the program verification operation of , the lower program state is the first program state PV1, the upper program state is the second program state PV2, and the remaining program states are the third to fifteenth program states PV3-PV15.

[0131] As described above, according to an embodiment of the present disclosure, when the bit line precharge level is adjusted according to the program state of the memory cell to be programmed during the program verification operation, the verification operation for at least two or more program states can be performed using one verification voltage. Therefore, the program verification operation time can be improved.

[0132] In addition, in the above-mentioned embodiment, as an example, the bit line precharge level is adjusted to two levels. However, the bit line precharge level may be adjusted to three or more levels to perform a verification operation on three or more programming states using one verification voltage. To this end, it is possible to additionally configure the bit line precharge level to be connected in parallel. Figure 7 Two NMOS transistors are provided between the second common node CSO2 and the NMOS transistor N3, and the two NMOS transistors are configured to operate in response to the node QF and the page buffer sense signal having a potential level lower than the second page buffer sense signal PB_SENSE2, respectively.

[0133] Fig.10 is a diagram for describing a cell current variation of two adjacent program states according to a precharge voltage level of a bit line.

[0134] refer to Fig.10 , when the bit line is precharged to a relatively high level @High VBL, when the verification voltage V PV2 When applied to the word line, the memory cells PV2 Cell corresponding to the second programming state may be divided into cells in which programming is completed and cells in which programming is not completed based on the reference current I-trip.

[0135] In the case where the bit line is precharged to a relatively low level (@low VBL), when the verification voltage V PV2 When applied to the word line, the memory cells PV1Cell corresponding to the first program state may be divided into cells in which programming is completed and cells in which programming is not completed based on the reference current I-trip.

[0136] That is, when the verification voltage V is applied to the word line in a state where the bit line is precharged to a relatively low level during the program verification operation of the memory cell PV1 Cell corresponding to the first program state, PV2 When performing a program verification operation, the memory cell PV1 Cell can be divided into cells in which programming is completed and cells in which programming is not completed based on the reference current I-trip, which is similar to the case where the bit line is precharged to a relatively high level and a verification voltage V is applied to the word line. PV1 Perform the same program-verify operation.

[0137] Fig.11 is used to describe another embodiment according to the present disclosure Figure 7 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0138] A program verification operation according to another embodiment of the present disclosure will be referred to as follows Figure 7 and Fig.11 Give a description.

[0139] In one embodiment of the present disclosure, by setting the verification voltage V PV2 A method applied to a selected word line to verify each of a first program state PV1 and a second program state PV2 will be described as an example.

[0140] When the data to be programmed corresponding to the first program state PV1 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH and the node QF of the latch circuit F_LATCH of the page buffer PB1 are set to a low level.

[0141] When the data to be programmed corresponding to the second program state PV2 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH of the page buffer PB1 is set to a low level, and the node QF of the latch circuit F_LATCH is set to a high level.

[0142] In the bit line precharge period tBLPRECH, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the PMOS transistor P2 is turned on in response to the low level precharge signal SA_PRECH_N, so the main sensing node SO is precharged to the level of the power supply voltage VDD. The NMOS transistor N5 is turned on in response to the high level control signal SA_CSOC, so the second common node CSO2 is charged to the level of VDD-Vth (threshold voltage of N5).

[0143] When the node QF is set to a low level, the NMOS transistor N3 is turned on in response to the second page buffer sensing signal PB_SENSE2 of the A level to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, whereby the first common node CSO1 is charged to the potential A-Vth (threshold voltage of N3) of the second page buffer sensing signal PB_SENSE2. Therefore, the bit line BL1 is precharged to the first setting level (PB_SENSE2-Vth).

[0144] When the node QF is set to a high level, the NMOS transistor N3 is turned on in response to the second page buffer sensing signal PB_SENSE2 of the A level to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, and the NMOS transistor N4 is turned on in response to the potential level of the node QF to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other. At this time, since the potential level of the node QF applied to the gate of the NMOS transistor N4 is higher than the potential level of the second page buffer sensing signal PB_SENSE2, the potential level of the second common node CSO2 is transmitted to the first common node CSO1 without a clamping operation. Therefore, the first common node CSO1 is charged to the VDD-Vth (threshold voltage of N5) level. In addition, the NMOS transistor N2 is turned on in response to the first page buffer sensing signal PB_SENSE1 higher than the B level (higher than A), and thus the bit line BL1 is precharged, and a clamp operation is generated by the NMOS transistor N2, whereby the bit line BL1 is precharged to a second setting level (PB_SENSE1-Vth).

[0145] When the verification voltage V PV2 When applied to the selected word line, the memory cells connected to the selected word line among the memory cells connected to the bit line BL1 have a threshold voltage higher than the verification voltage V PV1 When the threshold voltage is lower than the verification voltage V PV1 That is, the amount of current flowing through the bit line BL1 changes according to the threshold voltage of the memory cell.

[0146] Thereafter, in an evaluation period tEVAL_LOWER corresponding to the first programming state PV1, the precharge signal SA_PRECH_N is turned to a high level, the power supply voltage VDD applied to the main sensing node SO is cut off, the main sensing node SO and the second common node CSO2 are electrically connected to each other in response to the transmission signal TRANSO, and the potential level of the main sensing node SO varies according to the current amount of the bit line BL1.

[0147] When the evaluation period tEVAL_LOWER corresponding to the first programming state PV1 ends, the transmission signal TRANSO is converted to a low level, the NMOS transistor N6 is turned off, and the main sensing node SO and the bit line BL1 are electrically disconnected from each other. The NMOS transistor N27 of the latch circuit M_LATCH can be turned on or off according to the potential level of the main sensing node SO. Thereafter, a high-level setting signal MSET can be applied to the NMOS transistor N26, whereby the node QM_N can maintain a high level or be converted to a low level to store verification data.

[0148] Thereafter, in the sensing node recovery period tSORECOV, the PMOS transistor P1 is turned on in response to the potential level of the node QS, and the PMOS transistor P2 is turned on in response to the low level precharge signal SA_PRECH_N, so the main sensing node SO is precharged to the power supply voltage VDD level.

[0149] Thereafter, in the evaluation period tEVAL_HIGHER corresponding to the second programming state PV2, the precharge signal SA_PRECH_N is converted to a high level, the power supply voltage VDD applied to the main sensing node SO is cut off, the main sensing node SO and the second common node CSO2 are electrically connected to each other in response to the transmission signal TRANSO, and the potential level of the main sensing node SO varies according to the amount of current of the bit line BL1. It is preferred to set the evaluation period tEVAL_HIGHER to be longer than the evaluation period tEVAL_LOWER. For example, among a plurality of programming states for which program verification is performed using one verification voltage, the evaluation period corresponding to the programming state with a relatively low threshold voltage distribution may be set to be relatively short, and the evaluation period corresponding to the programming state with a relatively high threshold voltage distribution may be set to be relatively long.

[0150] When the evaluation period tEVAL_HIGHER corresponding to the second programming state PV2 ends, the transmission signal TRANSO is converted to a low level, the NMOS transistor N6 is turned off, and the main sensing node SO and the bit line BL1 are electrically disconnected from each other. The NMOS transistor N22 of the latch circuit D_LATCH is turned on or off according to the potential level of the main sensing node SO. Thereafter, a high-level setting signal DSET may be applied to the NMOS transistor N21, whereby the node QD_N may maintain a high level or be converted to a low level to store the verification data corresponding to the second programming state.

[0151] As described above, according to another embodiment of the present disclosure, during the program verification operation, the bit line is precharged to different precharge levels according to the program state, and the evaluation period for reflecting the current amount of the bit line to the potential level of the sensing node is divided according to the program state. That is, by setting the evaluation period during the program verification operation of the program state with a lower threshold voltage distribution to be short and setting the evaluation period during the program verification operation of the program state with a higher threshold voltage distribution to be long, the accuracy of the program verification operation can be further improved, thereby improving the cell current difference between the program states.

[0152] Fig.12 is a diagram for describing a page buffer according to another embodiment of the present disclosure.

[0153] Figure 2The illustrated plurality of page buffers PB1 -PBm may be configured in structures similar to one another, and in one embodiment of the present disclosure, the structure of the page buffer PB1 will be described as an example.

[0154] The page buffer PB1 may include a bit line controller 131 , a bit line discharger 132 , a sensing node connection unit 133 , and a plurality of latch circuits S_LATCH, D_LATCH, and M_LATCH.

[0155] During the program voltage application operation of the program operation, the bit line controller 131 controls the potential level of the corresponding bit line BL1 to a program inhibition voltage (e.g., VDD) or a program permission voltage (e.g., VSS). Thereafter, during the evaluation period, the bit line controller 131 electrically connects the bit line BL1 and the second sensing node SO2 to each other to control the potential levels of the second sensing node SO2 and the first sensing node SO1 connected to the second sensing node SO2 according to the current change amount of the bit line BL1. The second sensing node SO2 may be referred to as a main sensing node, and the first sensing node SO1 may be referred to as a sub sensing node.

[0156] The bit line controller 131 may include a plurality of NMOS transistors N31 - N35 and a plurality of PMOS transistors P11 and P12 .

[0157] The NMOS transistor N31 is connected between the bit line BL1 and the node ND1 , and is turned on in response to the page buffer selection signal PBSEL to electrically connect the bit line BL1 and the node ND1 to each other.

[0158] The NMOS transistor N32 is connected between the node ND1 and the common node CSO, and is turned on in response to the page buffer sense signal PB_SENSE to electrically connect the node ND1 and the common node CSO to each other.

[0159] The PMOS transistor P11 and the PMOS transistor P12 are connected in series between a terminal of a power supply voltage VDD and a second sensing node SO2 , and are turned on in response to a node QS of a latch circuit S_LATCH and a precharge signal SA_PRECH_N, respectively.

[0160] The NMOS transistor N35 is connected between the common node CSO and a node between the PMOS transistors P11 and P12 and is turned on in response to the control signal SA_CSOC to supply the power supply voltage VDD supplied through the PMOS transistor P11 to the common node CSO.

[0161] The NMOS transistor N33 is connected between the second sensing node SO2 and the common node CSO, and is turned on in response to the second transmission signal TRANSO2 to electrically connect the second sensing node SO2 and the common node CSO to each other.

[0162] The NMOS transistor N34 is connected between the common node CSO and the node ND2 of the latch circuit S_LATCH, and is turned on in response to the discharge signal SA_DISCH to electrically connect the common node CSO and the node ND2 to each other.

[0163] The bit line discharger 132 is connected to the node ND1 of the bit line controller 131 to discharge the potential level of the bit line BL1 .

[0164] The bit line discharger 132 may include an NMOS transistor NM1 connected between the node ND1 and a terminal of the ground power source VSS, and the NMOS transistor NM1 is turned on in response to a bit line discharge signal BL_DIS to electrically connect the node ND1 and the terminal of the ground power source VSS.

[0165] The latch circuit S_LATCH may include a plurality of NMOS transistors N36 - N40 and inverters IV11 and IV12 .

[0166] Inverters IV11 and IV12 are connected in anti-parallel between the node QS and the node QS_N.

[0167] NMOS transistor N36 and NMOS transistor N37 are connected in series between the second sensing node SO2 and a terminal of the ground power source VSS, NMOS transistor N36 is turned on in response to the transmission signal TRANS, and NMOS transistor N37 is turned on or off according to the potential level of the node QS.

[0168] The NMOS transistor N38 is connected between the node QS and the node ND3, and is turned on in response to the reset signal SRST so that the node QS and the node ND3 are electrically connected to each other. The NMOS transistor N39 is connected between the node QS_N and the node ND3, and is turned on in response to the set signal SSET so that the node QS_N and the node ND3 are electrically connected to each other. The NMOS transistor N40 is connected between the node ND3 and the terminal of the ground power supply VSS, and is turned on according to the potential of the second sensing node SO2 so that the node ND3 and the terminal of the ground power supply VSS are electrically connected to each other. For example, in a state where the second sensing node SO2 is precharged to a high level, when the reset signal SRST is applied to the NMOS transistor N38 as a high level, the node QS and the node QS_N are initialized to a low level (0) and a high level (1), respectively. In addition, in a state where the second sensing node SO2 is precharged to a high level, the set signal SSET is applied to the NMOS transistor N39 as a high level, and the node QS and the node QS_N are set to a high level (1) and a low level (0), respectively.

[0169] During the program verification operation, the latch circuit D_LATCH senses verification data based on the potential of the second sense node SO2, wherein the evaluation operation is performed during a relatively long evaluation period. For example, in an operation of performing a program verification operation on at least two program states using one verification voltage, the latch circuit D_LATCH senses verification data for a program state having a relatively high threshold voltage distribution.

[0170] The latch circuit D_LATCH may include a plurality of NMOS transistors N41 - N45 and inverters IV13 and IV14 .

[0171] Inverters IV13 and IV14 are connected in anti-parallel between the node QD and the node QD_N.

[0172] NMOS transistors N41 and NMOS transistors N42 are connected in series between the second sensing node SO2 and a terminal of the ground power source VSS, NMOS transistor N41 is turned on in response to the transmission signal TRAND, and NMOS transistor N42 is turned on or off according to a potential level of the node QD.

[0173] The NMOS transistor N43 is connected between the node QD and the node ND4, and is turned on in response to the reset signal DRST to electrically connect the node QD and the node ND4 to each other. The NMOS transistor N44 is connected between the node QD_N and the node ND4, and is turned on in response to the set signal DSET to electrically connect the node QD_N and the node ND4 to each other. The NMOS transistor N45 is connected between the node ND4 and the terminal of the ground power supply VSS, and is turned on according to the potential of the second sensing node SO2 to electrically connect the node ND5 and the terminal of the ground power supply VSS to each other.

[0174] For example, when the NMOS transistor N44 is turned on by applying a high level of the set signal DSET during a programming verification operation, the NMOS transistor N45 is turned on or off according to the potential level of the second sensing node SO2 (which is maintained or changed according to the current amount of the bit line BL1), so that the verification data can be stored in the latch circuit D_LATCH.

[0175] During the program verification operation, the latch circuit M_LATCH senses verification data based on the potential of the first sensing node SO1, wherein the evaluation operation is performed during a relatively short evaluation period. For example, in an operation of performing a program verification operation on at least two program states using one verification voltage, the latch circuit M_LATCH senses verification data for a program state having a relatively low threshold voltage distribution.

[0176] The latch circuit M_LATCH may include a plurality of NMOS transistors N46 - N50 and inverters IV15 and IV16 .

[0177] Inverters IV15 and IV16 are connected in anti-parallel between the node QM and the node QM_N.

[0178] NMOS transistors N46 and NMOS transistors N47 are connected in series between the first sensing node SO1 and a terminal of the ground power source VSS, NMOS transistor N46 is turned on in response to the transmission signal TRANM, and NMOS transistor N47 is turned on or off according to a potential level of the node QM.

[0179] The NMOS transistor N48 is connected between the node QM and the node ND5, and is turned on in response to the reset signal MRST to electrically connect the node QM and the node ND5 to each other. The NMOS transistor N49 is connected between the node QM_N and the node ND5, and is turned on in response to the set signal MSET to electrically connect the node QM_N and the node ND5 to each other. The NMOS transistor N50 is connected between the node ND6 and the terminal of the ground power supply VSS, and is turned on according to the potential of the first sensing node SO1 to electrically connect the node ND5 and the terminal of the ground power supply VSS to each other.

[0180] For example, when the NMOS transistor N49 is turned on by applying a high level of the set signal MSET during a programming verification operation, the NMOS transistor N50 is turned on or off according to the potential level of the first sensing node SO1 (which is maintained or changed according to the current amount of the bit line BL1), so that the verification data can be stored in the latch circuit M_LATCH.

[0181] The sensing node connection part 133 is connected between the first sensing node SO1 and the second sensing node SO2. The sensing node connection part 133 may include a transfer transistor PT that electrically connects or disconnects the first sensing node SO1 and the second sensing node SO2 in response to a first transfer signal TRANSO1 and a first inverted transfer signal TRANSO1_N.

[0182] The sense node connection part 133 performs an evaluation operation to control the potential levels of the first sense node SO1 and the second sense node SO2 according to the current amount of the bit line BL1 by electrically connecting the first sense node SO1 and the second sense node SO2 to each other during the first evaluation period. Thereafter, the sense node connection part 133 performs an evaluation operation to control the potential level of the second sense node SO2 according to the current amount of the bit line BL1 in a state where the first sense node SO1 and the second sense node SO2 are electrically disconnected from each other during the setup time. Therefore, the evaluation operation is performed on the first sense node SO1 during the first evaluation period, and the evaluation operation is performed on the second sense node SO2 during the second evaluation period that is longer than the first evaluation period.

[0183] Therefore, in an operation of performing a program verification operation on at least two program states using one verification voltage, the first sensing node SO1 can reflect verification data according to a program state with a relatively low threshold voltage distribution, and the second sensing node SO2 can reflect verification data according to a program state with a relatively high threshold voltage distribution.

[0184] Fig.13 It is used to describe an embodiment according to the present disclosure. Fig.12 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0185] The following will refer to Fig.12 and Fig.13 A program verification operation of a page buffer is described.

[0186] In one embodiment of the present disclosure, the verification voltage V PV2 A method of verifying each of a first program state PV1 and a second program state PV2 is applied to a selected word line.

[0187] During the program verification operation, the node QS of the latch circuit S_LATCH of the page buffer PB1 is set to a low level.

[0188] In the bit line precharge period tBLPRECH, the PMOS transistor P21 is turned on in response to the potential level of the node QS, and the PMOS transistor P22 is turned on in response to the low level precharge signal SA_PRECH_N, whereby the power supply voltage VDD is applied to the second sense node SO2. At this time, in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, the sensing node connection part 133 electrically connects the first sense node SO1 and the second sense node SO2 to each other, whereby the first sense node SO1 and the second sense node SO2 are precharged to the level of the power supply voltage VDD.

[0189] In addition, the NMOS transistor N35 is turned on in response to the control signal SA_CSOC, and the NMOS transistor N32 and the NMOS transistor N31 are turned on in response to the page buffer sensing signal PB_SENSE and the bit line selection signal PBSEL, respectively, to precharge the bit line BL1 .

[0190] Thereafter, the PMOS transistor P22 is turned off in response to the high level precharge signal SA_PRECH_N, and the power supply voltage VDD applied to the second sense node SO2 is cut off. During the first evaluation period tEVAL PV1 of the program verification operation for the memory cell corresponding to the first programming state PV1, the sense node connection unit 133 electrically connects the first sense node SO1 and the second sense node SO2 to each other in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, thereby performing an evaluation operation on the first sense node SO1 and the second sense node SO2 together during the first evaluation period tEVAL PV1. Therefore, the potential levels of the first sense node SO1 and the second sense node SO2 maintain the precharge level during the first evaluation period tEVALPV1, or decrease according to the threshold voltage value of the memory cell connected to the corresponding bit line.

[0191] When the first evaluation period tEVAL PV1 ends, in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, the sensing node connection unit 133 electrically disconnects the first sensing node SO1 and the second sensing node SO2 from each other. Therefore, only the second sensing node SO2 is electrically connected to the bit line BL1, and the evaluation operation continues to be performed. Therefore, the potential level of the second sensing node SO2 may maintain the precharge level, or may be reduced according to the threshold voltage value of the memory cell connected to the corresponding bit line during the second evaluation period tEVAL PV2 of the program verification operation for the memory cell corresponding to the second programming state PV2. That is, when the evaluation operation is performed on the second sensing node SO2 during the second evaluation period tEVAL PV2 that is longer than the first evaluation period tEVAL PV1, the reduction width of the potential level of the second sensing node SO2 may be greater than the reduction width of the potential level of the first sensing node SO1. That is, the potential level of the second sensing node SO2 may be evaluated to be lower than the potential level of the first sensing node SO1.

[0192] When the second evaluation period tEVAL PV2 ends, the NMOS transistor N33 is turned off in response to the second transmission signal TRANSO2 , whereby the second sense node SO2 and the common node CSO are disconnected from each other.

[0193] The NMOS transistor of the latch circuit M_LATCH is turned on or off according to the potential level of the first sensing node SO1. Thereafter, a high level setting signal MSET may be applied to the NMOS transistor N49, whereby the node QM_N may maintain a high level or convert to a low level to store verification data corresponding to the first program state PV1.

[0194] The NMOS transistor N45 of the latch circuit D_LATCH is turned on or off according to the potential level of the second sensing node SO2. Thereafter, a high level setting signal DSET may be applied to the NMOS transistor N44, whereby the node QD_N may maintain a high level or convert to a low level to store verification data corresponding to the second program state PV2.

[0195] As described above, the page buffer according to another embodiment of the present disclosure can perform a sensing operation on at least two program states together while applying one verification voltage during a program verification operation, electrically disconnect the sensing nodes respectively corresponding to the program states, and perform an evaluation operation on the sensing nodes during different evaluation periods. The evaluation periods can overlap with each other, so the operation time can be shortened.

[0196] In addition, in the above-mentioned embodiment, as an example, by electrically separating the first sensing node and the second sensing node from each other, a sensing operation is performed on two programming states together while applying one verification voltage. However, a verification operation on three or more programming states can be performed by dividing the sensing node into at least three.

[0197] Fig.14 is a diagram for describing a page buffer according to another embodiment of the present disclosure.

[0198] Figure 2 The illustrated plurality of page buffers PB1 -PBm may be configured in structures similar to one another, and in one embodiment of the present disclosure, the structure of the page buffer PB1 will be described as an example.

[0199] Fig.14 The page buffer PB1 shown may be the one described above. Figure 7 The page buffer PB1 and Fig.12 The structures of the page buffers PB1 are combined with each other.

[0200] Reference Fig.14 , the page buffer PB1 may include a bit line controller 131 , a bit line discharger 132 , a sensing node connection part 133 , and a plurality of latch circuits S_LATCH, D_LATCH, and M_LATCH.

[0201] During the program voltage application operation of the program operation, the bit line controller 131 controls the potential level of the corresponding bit line BL1 to a program inhibition voltage (e.g., VDD) or a program permission voltage (e.g., VSS). During the program verification operation of the program operation, the bit line controller 131 precharges the potential level of the corresponding bit line BL1 to a first setting level or a second setting level according to the data stored in the latch F_LATCH. Thereafter, during the first and second evaluation periods, the bit line controller 131 electrically connects the bit line BL1 and the second sense node SO2 to each other to control the potential levels of the first sense node SO1 and the second sense node SO2 according to the current change amount of the bit line BL1. The second sense node SO2 may be referred to as a main sense node, and the first sense node SO1 may be referred to as a sub-sense node.

[0202] The bit line controller 131 may include a plurality of NMOS transistors N51 - N55 and a plurality of PMOS transistors P31 and P32 .

[0203] The NMOS transistor N51 is connected between the bit line BL1 and the node ND1 , and is turned on in response to the page buffer selection signal PBSEL to electrically connect the bit line BL1 and the node ND1 to each other.

[0204] The NMOS transistor N52 is connected between the node ND1 and the first common node CSO1 , and is turned on in response to the first page buffer sensing signal PB_SENSE1 to electrically connect the node ND1 and the first common node CSO1 to each other.

[0205] The NMOS transistor N53 and the NMOS transistor N54 are connected in parallel between the second common node CSO2 and the first common node CSO1. The NMOS transistor N53 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, and the NMOS transistor N54 is turned on in response to the potential of the node QF of the latch circuit F_LATCH to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other. The potential level when the second page buffer sensing signal PB_SENSE2 is high is lower than the potential level when the first page buffer sensing signal PB_SENSE1 is high. In addition, the potential level when the node QF potential is high is higher than the potential level when the second page buffer sensing signal PB_SENSE2 is high.

[0206] The PMOS transistor P31 and the PMOS transistor P32 are connected in series between a terminal of a power supply voltage VDD and a second sensing node SO2 , and are turned on in response to a node QS of a latch circuit S_LATCH and a precharge signal SA_PRECH_N, respectively.

[0207] The NMOS transistor N55 is connected between the second common node CSO2 and a node between the PMOS transistors P31 and P32 , and is turned on in response to the control signal SA_CSOC to supply the power supply voltage VDD supplied through the PMOS transistor P31 to the common node CSO.

[0208] The NMOS transistor N56 is connected between the second sense node SO2 and the second common node CSO2, and is turned on in response to the second transmission signal TRANSO2 to electrically connect the second sense node SO2 and the second common node CSO2 to each other.

[0209] The NMOS transistor N57 is connected between the second common node CSO2 and the node ND2 of the latch circuit S_LATCH, and is turned on in response to the discharge signal SA_DISCH to electrically connect the second common node CSO and the node ND2 to each other.

[0210] During the bit line precharge operation of the program verification operation, the bit line controller 131 may precharge the bit line BL1 to a first setting level or a second setting level higher than the first setting level according to the node QS and the node QF.

[0211] For example, when the potential levels of the node QS and the node QF are low levels, the PMOS transistor P31 is turned on in response to the potential level of the node QS, and the NMOS transistor N55 is turned on in response to the control signal SA_CSOC, so that the second common node CSO2 is charged to the level of VDD-Vth (threshold voltage of N55). The NMOS transistor N53 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path between the second common node CSO2 and the first common node CSO1, and the first common node CSO1 is charged to the level of the potential level of the second page buffer sensing signal PB_SENSE2-Vth (threshold voltage of N53). In addition, the NMOS transistor N51 and the NMOS transistor N52 are turned on in response to the page buffer selection signal PBSEL and the first page buffer sensing signal PB_SENSE1, respectively, so that the potential level of the first common node CSO1 is transmitted to the bit line BL1. At this time, since the potential level of the second page buffer sensing signal PB_SENSE2 is lower than the potential level of the first page buffer sensing signal PB_SENSE1, the potential level of the first common node CSO1 is transmitted to the bit line BL1 without performing a clamping operation. Therefore, the bit line BL1 is precharged to a level (first setting level) of the potential level of the second page buffer sensing signal PB_SENSE2 - Vth (threshold voltage of N53).

[0212] On the other hand, when the potential level of the node QS is at a low level and the potential level of the node QF is at a high level, the PMOS transistor P31 is turned on in response to the potential level of the node QS, and the NMOS transistor N55 is turned on in response to the control signal SA_CSOC, so that the second common node CSO2 is charged to the level of VDD-Vth (threshold voltage of N55).

[0213] The NMOS transistor N53 is turned on in response to the second page buffer sensing signal PB_SENSE2 to form a current path between the second common node CSO2 and the first common node CSO1, and the NMMOS transistor N54 is turned on in response to the potential level of the node QF to form a current path between the second common node CSO2 and the first common node CSO1. At this time, since the potential level of the node QF applied to the gate of the NMOS transistor N54 is higher than the potential level of the second page buffer sensing signal PB_SENSE2, the potential level of the second common node CSO2 is transmitted to the first common node CSO1 without a clamping operation. Therefore, the first common node CSO1 is charged to the VDD-Vth (threshold voltage of N55) level. In addition, the NMOS transistor N51 and the NMOS transistor N52 are turned on in response to the page buffer selection signal PBSEL and the first page buffer sensing signal PB_SENSE1, respectively, whereby the bit line BL1 is precharged. The clamping operation is generated by the NMOS transistor N52 , and thus the bit line BL1 is precharged to a level (a second setting level) of the potential level of the first page buffer sense signal PB_SENSE1 −Vth (threshold voltage of N52 ).

[0214] The bit line discharger 132 is connected to the node ND1 of the bit line controller 131 to discharge the potential level of the bit line BL1 .

[0215] The bit line discharger 132 may include an NMOS transistor N58 connected between the node ND1 and a terminal of the ground power source VSS, and the NMOS transistor N58 is turned on to electrically connect the node ND1 and the terminal of the ground power source VSS in response to a bit line discharge signal BL_DIS.

[0216] The sensing node connection part 133 is connected between the first sensing node SO1 and the second sensing node SO2. The sensing node connection part 133 may include a pass transistor PT that electrically connects or disconnects the first sensing node SO1 and the second sensing node SO2 in response to a first transfer signal TRANSO1 and a first inverted transfer signal TRANSO1_N.

[0217] By electrically connecting the first sense node SO1 and the second sense node SO2 to each other during the first evaluation period, the sense node connection part 133 performs an evaluation operation to control the potential levels of the first sense node SO1 and the second sense node SO2 according to the current amount of the bit line BL1. Thereafter, in a state where the first sense node SO1 and the second sense node SO2 are electrically disconnected from each other during the setup time, the sense node connection part 133 performs an evaluation operation to control the potential level of the second sense node SO2 according to the current amount of the bit line BL1. Therefore, the evaluation operation is performed on the first sense node SO1 during the first evaluation period, and the evaluation operation is performed on the second sense node SO2 during the second evaluation period longer than the first evaluation period.

[0218] Therefore, in an operation of performing a program verification operation on at least two program states using one verification voltage, the first sensing node SO1 can reflect verification data according to a program state with a relatively low threshold voltage distribution, and the second sensing node SO2 can reflect verification data according to a program state with a relatively high threshold voltage distribution.

[0219] The latch circuit S_LATCH may include a plurality of NMOS transistors N59 - N63 and inverters IV21 and IV22 .

[0220] Inverters IV21 and IV22 are connected in anti-parallel between the node QS and the node QS_N.

[0221] NMOS transistor N59 and NMOS transistor N60 are connected in series between the second sensing node SO2 and a terminal of the ground power source VSS, NMOS transistor N59 is turned on in response to the transmission signal TRANS, and NMOS transistor N60 is turned on or off according to a potential level of the node QS.

[0222] The NMOS transistor N61 is connected between the node QS and the node ND3, and is turned on in response to the reset signal SRST so that the node QS and the node ND3 are electrically connected to each other. The NMOS transistor N63 is connected between the node ND3 and the terminal of the ground power supply VSS, and is turned on according to the potential of the second sensing node SO2 so that the node ND3 and the terminal of the ground power supply VSS are electrically connected to each other. For example, in a state where the second sensing node SO2 is precharged to a high level, when the reset signal SRST is applied to the NMOS transistor N61 as a high level, the node QS and the node QS_N are initialized to a low level (0) and a high level (1), respectively. In addition, in a state where the second sensing node SO2 is precharged to a high level, the set signal SSET is applied to the NMOS transistor N62 as a high level, and the node QS and the node QS_N are set to a high level (1) and a low level (0), respectively.

[0223] The latch circuit F_LATCH may include a plurality of NMOS transistors N64 - N68 and inverters IV23 and IV24 .

[0224] Inverters IV23 and IV24 are connected in anti-parallel between the node QF and the node QF_N.

[0225] NMOS transistors N64 and NMOS transistors N65 are connected in series between the second sensing node SO2 and a terminal of the ground power source VSS, NMOS transistor N64 is turned on in response to a transmission signal TRANS, and NMOS transistor N65 is turned on or off according to a potential level of a node QS.

[0226] The NMOS transistor N66 is connected between the node QF and the node ND4, and is turned on in response to the reset signal FRST so that the node QF and the node ND4 are electrically connected to each other. The NMOS transistor N67 is connected between the node QF_N and the node ND4, and is turned on in response to the set signal FSET so that the node QF_N and the node ND4 are electrically connected to each other. The NMOS transistor N66 is connected between the node ND4 and the terminal of the ground power supply VSS, and is turned on according to the potential of the second sensing node SO2 so that the node ND4 and the terminal of the ground power supply VSS are electrically connected to each other. For example, in a state where the second sensing node SO2 is precharged to a high level, when the reset signal FRST is applied to the NMOS transistor N66 as a high level, the node QF and the node QF_N are initialized to a low level (0) and a high level (1), respectively. In addition, in a state where the second sensing node SO2 is precharged to a high level, the set signal FSET is applied to the NMOS transistor N68 as a high level, and the node QF and the node QF_N are set to a high level (1) and a low level (0), respectively.

[0227] The latch circuit D_LATCH may include a plurality of NMOS transistors N69 - N73 and inverters IV25 and IV26 .

[0228] Inverters IV25 and IV26 are connected in anti-parallel between the node QD and the node QD_N.

[0229] NMOS transistor N69 and NMOS transistor N70 are connected in series between the second sensing node SO2 and a terminal of the ground power source VSS, NMOS transistor N69 is turned on in response to the transmission signal TRAND, and NMOS transistor N70 is turned on or off according to the potential level of the node QD.

[0230] The NMOS transistor N71 is connected between the node QD and the node ND5, and is turned on in response to the reset signal DRST to electrically connect the node QD and the node ND5 to each other. The NMOS transistor N72 is connected between the node QD_N and the node ND5, and is turned on in response to the set signal DSET to electrically connect the node QD_N and the node ND5 to each other. The NMOS transistor N73 is connected between the node ND5 and the terminal of the ground power supply VSS, and is turned on according to the potential of the second sensing node SO2 to electrically connect the node ND5 and the terminal of the ground power supply VSS to each other.

[0231] For example, when the NMOS transistor N72 is turned on by applying a high level of the set signal DSET during a programming verification operation, the NMOS transistor N73 is turned on or off according to the potential level of the second sensing node SO2 (which is maintained or changed according to the current amount of the bit line BL1), whereby the verification data evaluated on the second sensing node SO2 can be stored in the latch circuit D_LATCH.

[0232] The latch circuit M_LATCH may include a plurality of NMOS transistors N74 - N78 and inverters IV27 and IV28 .

[0233] Inverters IV27 and IV28 are connected in anti-parallel between the node QM and the node QM_N.

[0234] NMOS transistors N74 and NMOS transistors N75 are connected in series between the first sensing node SO1 and a terminal of the ground power source VSS, NMOS transistor N74 is turned on in response to the transmission signal TRANM, and NMOS transistor N75 is turned on or off according to a potential level of the node QM.

[0235] The NMOS transistor N76 is connected between the node QM and the node ND6, and is turned on in response to the reset signal MRST to electrically connect the node QM and the node ND6 to each other. The NMOS transistor N77 is connected between the node QM_N and the node ND6, and is turned on in response to the set signal MSET to electrically connect the node QM_N and the node ND6 to each other. The NMOS transistor N78 is connected between the node ND6 and the terminal of the ground power supply VSS, and is turned on according to the potential of the first sensing node SO1 to electrically connect the node ND6 and the terminal of the ground power supply VSS to each other.

[0236] For example, when the NMOS transistor N77 is turned on by applying a high level of the set signal MSET during a programming verification operation, the NMOS transistor N78 is turned on or off according to the potential level of the first sensing node SO1 (which is maintained or changed according to the current amount of the bit line BL1), whereby the verification data evaluated on the first sensing node SO1 can be stored in the latch circuit M_LATCH.

[0237] Fig.15 It is used to describe an embodiment according to the present disclosure. Fig.14 1 is a waveform diagram of signals of a program verification operation of a page buffer.

[0238] The following will refer to Fig.14 and Fig.15 A program verification operation of a page buffer according to another embodiment of the present disclosure is described.

[0239] In one embodiment of the present disclosure, the verification voltage V PV2 A method of verifying each of a first program state PV1 and a second program state PV2 is applied to a selected word line.

[0240] When the data to be programmed corresponding to the first program state PV1 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH and the node QF of the latch circuit F_LATCH of the page buffer PB1 are set to a low level.

[0241] In the bit line precharge period tBLPRECH, the PMOS transistor P31 is turned on in response to the potential level of the node QS, and the PMOS transistor P32 is turned on in response to the low level precharge signal SA_PRECH_N, so the first and second sense nodes SO1 and SO2 are precharged to the level of the power supply voltage VDD. The NMOS transistor N55 is turned on in response to the high level control signal SA_CSOC, so the second common node CSO2 is charged to the VDD-Vth (threshold voltage of N55) level. The NMOS transistor N53 is turned on in response to the A level second page buffer sense signal PB_SENSE2 to form a current path that connects the second common node CSO2 and the first common node CSO1 to each other, so the first common node CSO1 is charged to the potential A-Vth (threshold voltage of N53) of the second page buffer sense signal PB_SENSE2. Therefore, the bit line BL1 is precharged to the first setting level (PB_SENSE2-Vth).

[0242] When the verification voltage V PV2When applied to the selected word line, the memory cells connected to the selected word line among the memory cells connected to the bit line BL1 have a threshold voltage higher than the verification voltage V PV1 When the threshold voltage is lower than the verification voltage V PV1 That is, the amount of current flowing through the bit line BL1 changes according to the threshold voltage of the memory cell.

[0243] Thereafter, in the first evaluation period tEVAL PV1 of the evaluation period tEVAL, the PMOS transistor P32 is turned off in response to the high level precharge signal SA_PRECH_N, and the power supply voltage VDD applied to the second sense node SO2 is cut off. During the first evaluation period tEVALPV1 of the program verification operation for the memory cell corresponding to the first programming state PV1, the sense node connection part 133 electrically connects the first sense node SO1 and the second sense node SO2 to each other in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, thereby performing an evaluation operation on the first sense node SO1 and the second sense node during the first evaluation period tEVAL PV1. Therefore, during the first evaluation period tEVAL PV1, the potential levels of the first sense node SO1 and the second sense node SO2 maintain the precharge level, or decrease according to the threshold voltage value of the memory cell connected to the corresponding bit line.

[0244] When the first evaluation period tEVAL PV1 ends, in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, the sensing node connection unit 133 electrically disconnects the first sensing node SO1 and the second sensing node SO2 from each other, and therefore, only the second sensing node SO2 is electrically connected to the bit line BL1, and the evaluation operation continues to be performed. Therefore, during the second evaluation period tEVAL PV2 of the program verification operation for the memory cell corresponding to the second programming state PV2, the potential level of the second sensing node SO2 may maintain the precharge level, or may be reduced according to the threshold voltage value of the memory cell connected to the corresponding bit line. That is, when the evaluation operation is performed on the second sensing node SO2 during the second evaluation period tEVALPV2 longer than the first evaluation period tEVAL PV1, the reduction width of the potential level of the second sensing node SO2 may be greater than the reduction width of the potential level of the first sensing node SO1. That is, the potential level of the second sensing node SO2 may be evaluated to be lower than the potential level of the first sensing node SO1.

[0245] When the second evaluation period tEVAL PV2 ends, the NMOS transistor N33 is turned off in response to the second transmission signal TRANSO2 , whereby the second sense node SO2 and the common node CSO are disconnected from each other.

[0246] The NMOS transistor N78 of the latch circuit M_LATCH is turned on or off according to the potential level of the first sensing node SO1. Thereafter, a high level setting signal MSET may be applied to the NMOS transistor N77, whereby the node QM_N may maintain a high level or convert to a low level to store verification data corresponding to the first program state PV1.

[0247] The NMOS transistor N73 of the latch circuit D_LATCH is turned on or off according to the potential level of the second sensing node SO2. Thereafter, a high level setting signal DSET may be applied to the NMOS transistor N72, whereby the node QD_N may maintain a high level or convert to a low level to store verification data corresponding to the second program state PV2.

[0248] In one embodiment, since the program verification operation is a program verification operation in which the page buffer PB1 stores data to be programmed corresponding to the first program state PV1, the verification operation is performed using verification data sensed by the latch circuit M_LATCH.

[0249] When data to be programmed corresponding to the second program state PV2 is stored in the page buffer PB1 among the plurality of page buffers, the node QS of the latch circuit S_LATCH of the page buffer PB1 is set to a low level, and the node QF of the latch circuit F_LATCH is set to a high level.

[0250] In the bit line precharge period tBLPRECH, the PMOS transistor P31 is turned on in response to the potential level of the node QS, and the PMOS transistor P32 is turned on in response to the low level precharge signal SA_PRECH_N, so that the first and second sense nodes SO1 and SO2 are precharged to the level of the power supply voltage VDD. The NMOS transistor N55 is turned on in response to the high level control signal SA_CSOC, so that the second common node CSO2 is charged to the VDD-Vth (threshold voltage of N55) level. The NMOS transistor N53 is turned on in response to the A level second page buffer sense signal PB_SENSE2 to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other, and the NMOS transistor N54 is turned on in response to the potential level of the node QF to form a current path connecting the second common node CSO2 and the first common node CSO1 to each other. At this time, since the potential level of the node QF applied to the gate of the NMOS transistor N54 is higher than the potential level of the second page buffer sensing signal PB_SENSE2, the potential level of the second common node CSO2 is transferred to the first common node CSO1 without a clamping operation. Therefore, the first common node CSO1 is charged to the VDD-Vth (threshold voltage of N55) level. In addition, the NMOS transistor N52 is turned on in response to the first page buffer sensing signal PB_SENSE1 of the B level higher than A, whereby the bit line BL1 is precharged, and the clamping operation is generated by the NMOS transistor N52, so that the bit line BL1 is precharged to the second setting level (PB_SENSE1-Vth).

[0251] When the verification voltage V PV2 When applied to the selected word line, the memory cells connected to the selected word line among the memory cells connected to the bit line BL1 have a threshold voltage higher than the verification voltage V PV2 is turned on when the threshold voltage is lower than the verification voltage V PV2 That is, the amount of current flowing through the bit line BL1 varies according to the threshold voltage of the memory cell.

[0252] Thereafter, in the first evaluation period tEVAL PV1 of the evaluation period tEVAL, the PMOS transistor P32 is turned off in response to the high level precharge signal SA_PRECH_N, and the power supply voltage VDD applied to the second sense node SO2 is cut off. During the first evaluation period tEVALPV1 of the program verification operation for the memory cell corresponding to the first programming state PV1, the sense node connection unit 133 electrically connects the first sense node SO1 and the second sense node SO2 to each other in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, thereby performing an evaluation operation on the first sense node SO1 and the second sense node SO2 during the first evaluation period tEVAL PV1. Therefore, during the first evaluation period tEVAL PV1, the potential levels of the first sense node SO1 and the second sense node SO2 maintain the precharge level, or decrease according to the threshold voltage value of the memory cell connected to the corresponding bit line.

[0253] When the first evaluation period tEVAL PV1 ends, in response to the first transmission signal TRANSO1 and the first inverted transmission signal TRANSO1_N, the sensing node connection unit 133 electrically disconnects the first sensing node SO1 and the second sensing node SO2 from each other. Therefore, only the second sensing node SO2 is electrically connected to the bit line BL1, and the evaluation operation continues to be performed. Therefore, during the second evaluation period tEVAL PV2 of the program verification operation for the memory cell corresponding to the second programming state PV2, the potential level of the second sensing node SO2 may maintain the precharge level, or may be reduced according to the threshold voltage value of the memory cell connected to the corresponding bit line. That is, when the evaluation operation is performed on the second sensing node SO2 during the second evaluation period tEVALPV2 that is longer than the first evaluation period tEVAL PV1, the reduction width of the potential level of the second sensing node SO2 may be greater than the reduction width of the potential level of the first sensing node SO1. That is, the potential level of the second sensing node SO2 may be evaluated to be lower than the potential level of the first sensing node SO1.

[0254] When the second evaluation period tEVAL PV2 ends, the NMOS transistor N33 is turned off in response to the second transmission signal TRANSO2 , whereby the second sense node SO2 and the second common node CSO2 are disconnected from each other.

[0255] The NMOS transistor N78 of the latch circuit M_LATCH is turned on or off according to the potential level of the first sensing node SO1. Thereafter, a high level setting signal MSET may be applied to the NMOS transistor N77, whereby the node QM_N may maintain a high level or convert to a low level to store verification data corresponding to the first program state PV1.

[0256] The NMOS transistor N73 of the latch circuit D_LATCH is turned on or off according to the potential level of the second sensing node SO2. Thereafter, a high level setting signal DSET may be applied to the NMOS transistor N72, whereby the node QD_N may maintain a high level or convert to a low level to store verification data corresponding to the second program state PV2.

[0257] In one embodiment, since the program verification operation is a program verification operation in which the page buffer PB1 stores data to be programmed corresponding to the second program state PV1, the verification operation is performed using verification data sensed by the latch circuit D_LATCH.

[0258] Table 2

[0259] Lower programming state Higher programming state Remaining programming status QS 0 (low level) 0 (low level) 1 (High level) QF 0 (low level) 1 (High level) 0 (low level) CSO2 VDD-Vth VDD-Vth GND(VSS) CSO1 PB_SENSE2-Vth VDD–Vth GND(VSS) BL PB_SENSE2-Vth PB_SENSE1-Vth GND(VSS)

[0260] Table 2 is a table showing set states of nodes QS and QF of the d latch circuit and precharge levels of first and second common nodes CSO1 and CSO2 and a bit line BL during a program verification operation using one verification voltage.

[0261] In Table 2, the lower program state and the upper program state respectively indicate a lower program state with a lower threshold voltage distribution and an upper program state with a higher threshold voltage distribution in two program states for program verification using one verification voltage. PV2 During the program verification operation of , the lower program state is the first program state PV1, the upper program state is the second program state PV2, and the remaining program states are the third to fifteenth program states PV3-PV15.

[0262] As described above, according to another embodiment of the present disclosure, during a programming verification operation, a bit line is precharged to different precharge levels according to a programming state, and an evaluation period for reflecting the current amount of the bit line as a potential level of a sensing node is divided according to the programming state. That is, by setting the evaluation period during the programming verification operation of a programming state with a lower threshold voltage distribution to be short and setting the evaluation period during the programming verification operation of a programming state with a higher threshold voltage distribution to be long, the accuracy of the programming verification operation can be further improved, thereby improving the cell current difference between programming states. In addition, the sensing nodes corresponding to the programming states, respectively, are disconnected from each other, and evaluation operations are performed on the sensing nodes during different evaluation periods. The evaluation periods may overlap with each other, thereby reducing the operation time.

[0263] Fig.16 is a diagram for describing another embodiment of a memory system.

[0264] Reference Fig.16 , the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet computer, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control data access operations of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

[0265] Under the control of the memory controller 1200 , data programmed in the memory device 1100 may be output through the display 3200 .

[0266] The radio transceiver 3300 may transmit and receive radio signals through the antenna ANT. For example, the radio transceiver 3300 may convert the radio signal received through the antenna ANT into a signal that may be processed by the processor 3100. Therefore, the processor 3100 may process the signal output from the radio transceiver 3300 and send the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 may program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 may convert the signal output from the processor 3100 into a radio signal and output the converted radio signal to an external device through the antenna ANT. The input device 3400 may be a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 may be implemented as a pointing device, a keyboard, or a keypad such as a touch pad or a computer mouse. The processor 3100 may control the operation of the display 3200 so that data output from the controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0267] According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100, and may also be implemented as a chip separate from the processor 3100. In addition, the memory controller 1200 may be implemented by Figure 1 The example of the controller 1200 shown is implemented.

[0268] Fig.17 is a diagram for describing another example of a memory system.

[0269] Reference Fig.17 , the memory system 40000 can be implemented as a personal computer (PC), a tablet computer, a net book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0270] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0271] The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keyboard, or a keypad.

[0272] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 1200. According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100, or may be implemented as a chip separate from the processor 4100. In addition, the memory controller 1200 may be implemented by Figure 1 The example of the controller 1200 shown is implemented.

[0273] Fig.18 is a diagram for describing another embodiment of a memory system.

[0274] Reference Fig.18 The memory system 50000 may be implemented as an image processing device, such as a digital camera, a mobile phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet computer provided with a digital camera.

[0275] The memory system 50000 includes a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0276] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signal may be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. In addition, the data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0277] According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100, or may be implemented as a chip separate from the processor 5100. In addition, the memory controller 1200 may be implemented by Figure 1The example of the controller 1200 shown is implemented.

[0278] Fig.19 is a diagram for describing another embodiment of a memory system.

[0279] Reference Fig.19 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0280] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. Figure 1 The example of the controller 1200 shown is implemented.

[0281] The card interface 7100 may interface data exchange between the host 60000 and the memory controller 1200 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and a chip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0282] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, a tablet computer, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0283] Although the present disclosure has been described with reference to some embodiments and the accompanying drawings, the present disclosure is not limited to the above-mentioned embodiments, and those skilled in the art to which the present disclosure pertains may make various changes and modifications based on the description of the disclosure.

Claims

1. A page buffer, comprising: A first latch circuit configured to store data corresponding to one of a first programming state and a second programming state; a bit line controller connected to a bit line of a memory block and configured to precharge the bit line by applying one of a first setting voltage and a second setting voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verification operation; as well as A second latch circuit is connected to the bit line controller through a main sensing node and is configured to sense first verification data according to a potential level of the main sensing node during the program verification operation. 2 . The page buffer of claim 1 , wherein the first program state and the second program state are program states in which threshold voltage distributions are adjacent to each other among a plurality of program states.

3. The page buffer according to claim 2 , wherein if the data stored in the first latch circuit corresponds to the first programming state, the bit line controller precharges the bit line to the first setting voltage, and If the data stored in the first latch circuit corresponds to the second programming state, the page buffer precharges the bit line to the second setting voltage, the potential level of the second setting voltage being higher than the potential level of the first setting voltage. 4 . The page buffer of claim 3 , wherein a threshold voltage distribution of the first program state is lower than a threshold voltage distribution of the second program state.

5. The page buffer according to claim 3, wherein the bit line controller comprises: a first transistor connected between the bit line and a first common node and configured to connect the bit line and the first common node to each other in response to a first page buffer sensing signal; a second transistor connected between the first common node and a second common node and configured to form a first current path by connecting the first common node and the second common node to each other in response to a second page buffer sensing signal; a third transistor connected between the first common node and the second common node and configured to form a second current path by connecting the first common node and the second common node to each other in response to a first node potential of the first latch circuit; as well as A fourth transistor is connected to the second common node and is configured to apply a power supply voltage to the second common node in response to a control signal.

6. The page buffer of claim 5, wherein during the bit line precharge operation, the first page buffer sensing signal is activated to a first level, and the second page buffer sensing signal is activated to a second level, and wherein the second level is lower than the first level.

7. The page buffer according to claim 6 , wherein if the data corresponding to the first programming state is stored in the first latch circuit, the first node potential is set to a third level, if the data corresponding to the second programming state is stored in the first latch circuit, the first node potential is set to a fourth level, and Wherein the third level is a ground power level and the fourth level is a power supply voltage level. 8 . The page buffer of claim 7 , wherein the fourth level is higher than the second level.

9. The page buffer according to claim 5, wherein the bit line controller further comprises a fifth transistor connected between the second common node and the main sensing node and electrically connecting the second common node and the main sensing node to each other in response to a transmission signal, and wherein in the evaluation operation after the bit line precharge operation, the fifth transistor performs an evaluation operation of controlling a potential level of the main sensing node according to a current amount of the bit line by connecting the second common node and the main sensing node to each other.

10. The page buffer according to claim 1, further comprising: A sensing node connecting component connected between the main sensing node and the sub-sensing node; as well as A third latch circuit is connected to the sub sensing node and is configured to sense second verification data according to a potential level of the sub sensing node during the program verification operation.

11. The page buffer according to claim 10, wherein the first verification data corresponds to a program verification result for the second program state, and The second verification data corresponds to a program verification result for the first program state.

12. The page buffer according to claim 10, wherein the main sensing node and the sub sensing node perform an evaluation operation by the bit line controller after the bit line precharge operation, and The sensing node connecting part electrically connects the main sensing node and the sub sensing node to each other during a first period in the evaluation operation, and electrically disconnects the main sensing node and the sub sensing node from each other during a second period after the first period.

13. The page buffer of claim 12 , wherein during the first period and the second period, the evaluation operation is performed on the master sensing node, and During the first period, the evaluation operation is performed on the child sensing node.

14. The page buffer according to claim 13 , wherein the evaluation operation corresponding to the second program state is performed on the main sensing node, and Wherein the evaluation operation corresponding to the first programming state is performed on the sub-sensing node.

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