A multi-channel clock output and input alignment zero-delay circuit

Abstract

The present application provides a multi-channel clock output and input alignment zero-delay circuit, including: a bus, a phase detector, and a phase shifter. Multiple input clocks and output clocks can be transmitted to the phase detector through the bus. In the present application, the clock signals to be aligned are transmitted through the bus. Therefore, the clock signals to be aligned can be located at any position on the chip, and their positions can be relatively far apart. The circuit architecture of the multi-channel clock output and input alignment zero-delay circuit provided by the present application is simple and can be flexibly adjusted. It can achieve multiple different clock alignment signals simultaneously, achieve zero delay of the clock signals, and thus ensure the accuracy of clock signal time synchronization.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular, to a multi-channel clock output and input alignment zero-delay circuit. Background Art

[0002] With the continuous development of communication networks, there is an increasingly widespread demand for the time synchronization of clock signals, and the accuracy requirements for its time synchronization are also getting higher and higher. If the accuracy of clock signal time synchronization is poor, it will affect the communication quality and data transmission efficiency of the communication network.

[0003] In the prior art, the time synchronization of clock signals is mainly achieved through clock alignment. In some cases, multiple output clocks need to be aligned with the input clock, or multiple different output clocks need to be aligned; in other cases, multiple different clock alignment signals need to exist at the same time to meet different application requirements. How to take these two situations into account has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0004] In view of the problems existing in the above background technology, the present application provides a simple and flexibly adjustable multi-channel clock output and input alignment zero-delay circuit to achieve zero delay of the clock signal, thereby ensuring the accuracy of clock signal time synchronization.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A multi-channel clock output and input alignment zero-delay circuit comprises: a bus, a phase detector and a phase modulator, wherein:

[0007] The bus is used to transmit the input clock and the output clock of the phase modulator to the phase detector;

[0008] The first input terminal of the phase detector is used to obtain the clock signal transmitted on the bus;

[0009] The second input end of the phase detector is connected to the output end of the phase modulator, and the phase detector is used to compare the phase of the clock signal transmitted on the bus with the phase of the output clock processed by the phase modulator to obtain a signal indicating the phase difference between the two;

[0010] The first input end of the phase modulator is used to obtain a local clock, the second input end of the phase modulator is connected to the output end of the phase detector, and the phase modulator is used to adjust the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the clock signal transmitted on the bus;

[0011] When the output clock needs to be aligned with the input clock, the input clock is transmitted to the phase detector through the bus; the phase detector compares the phases of the input clock and the output clock processed by the phase modulator to obtain a signal representing the phase difference between the two; the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the input clock, achieving zero delay between the output clock and the input clock.

[0012] When different output clocks need to be aligned, the target output clock processed by the phase modulator is transmitted to the phase detector through the bus; the phase detector compares the phases of the target output clock and the output clock to be adjusted to obtain a signal representing the phase difference between the two; the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the target output clock, achieving zero delay of the output clock.

[0013] Furthermore, the bus can simultaneously access multiple different clock signals.

[0014] Furthermore, the number of buses is consistent with the number of types of different clock alignment signals.

[0015] Furthermore, the clock signal alignment method is rising edge alignment and / or falling edge alignment.

[0016] The multi-channel clock output and input alignment zero-delay circuit described in this application includes: a bus, a phase detector, and a phase modulator. Multiple input clocks and output clocks can be transmitted to the phase detector through the bus; when the output clock needs to be aligned with the input clock, the input clock is transmitted to the phase detector through the bus, and then the phase detector compares the phases of the input clock and the output clock processed by the phase modulator to obtain a signal representing the phase difference between the two, and then the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the input clock; when different output clocks need to be aligned, the target output clock processed by the phase modulator is transmitted to the phase detector through the bus, and then the phase detector compares the phases of the target output clock and the output clock to be adjusted to obtain a signal representing the phase difference between the two, and then the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the target output clock.

[0017] In this application, the clock signals to be aligned are transmitted through the bus, so the clock signals to be aligned can be at any position on the chip, and their positions can be far apart; at the same time, the circuit architecture of the multi-channel clock output and input alignment zero-delay circuit provided in this application is simple and can be flexibly adjusted. It can achieve multiple different clock alignment signals simultaneously and achieve zero delay of the clock signals, thereby ensuring the accuracy of clock signal time synchronization. Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of a multi-channel clock output and input alignment zero-delay circuit provided by an embodiment of the present application;

[0020] Figure 2 It is a schematic structural diagram of another multi-channel clock output and input alignment zero-delay circuit provided by an embodiment of the present application. Detailed Embodiments

[0021] The present application provides a simple and flexibly adjustable multi-channel clock output and input alignment zero-delay circuit to achieve zero delay of the clock signal, thereby ensuring the accuracy of clock signal time synchronization and being used to achieve clock signal time synchronization in a communication network.

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0023] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will give a detailed description of the specific embodiments of the present invention with reference to the drawings.

[0024] For the convenience of understanding, in the technical solutions disclosed in the embodiments of the present application, the principle of the embodiments of the present application is illustrated by taking two input clocks, two output clocks, and one bus as an example.

[0025] Please refer to the attached Figure 1 , which is a schematic structural diagram of a multi-channel clock output and input alignment zero-delay circuit provided by an embodiment of the present application. As Figure 1 shown, the multi-channel clock output and input alignment zero-delay circuit includes: bus 10, phase detector 21, phase shifter 31, phase detector 22, and phase shifter 32, where:

[0026] The bus 10 is used to connect the input clock Clk in1 , input clock Clk in2 , and the output clock Clk of the phase shifter 31 out1, and the output clock Clk of the phase modulator 32 out2 is transmitted to the phase detector 21 and the phase detector 22.

[0027] The first input terminal of the phase detector 21 is used to obtain the clock signal transmitted on the bus 10. The second input terminal of the phase detector 21 is connected to the output terminal of the phase modulator 31. The phase detector 21 is used to compare the clock signal transmitted on the bus 10 with the output clock Clk processed by the phase modulator 31 out1 in terms of phase, and obtain a signal V representing the phase difference between the clock signal transmitted on the bus 10 and the output clock Clk out1 processed by the phase modulator 31. pd1 .

[0028] The first input terminal of the phase modulator 31 is used to obtain the local clock Clk local1 . The second input terminal of the phase modulator 31 is connected to the output terminal of the phase detector 21. The phase modulator 31 is used to adjust the phase of the local clock Clk pd1 according to the output signal V of the phase detector 21 local1 to obtain an output clock Clk aligned with the clock signal transmitted on the bus 10 out1 .

[0029] The first input terminal of the phase detector 22 is used to obtain the clock signal transmitted on the bus 10. The second input terminal of the phase detector 22 is connected to the output terminal of the phase modulator 32. The phase detector 22 is used to compare the clock signal transmitted on the bus 10 with the output clock Clk out2 processed by the phase modulator 32 in terms of phase, and obtain a signal V representing the phase difference between the clock signal transmitted on the bus 10 and the output clock Clk out2 processed by the phase modulator 32. pd2 .

[0030] The first input terminal of the phase modulator 32 is used to obtain the local clock Clk local2 . The second input terminal of the phase modulator 32 is connected to the output terminal of the phase detector 22. The phase modulator 32 is used to adjust the phase of the local clock Clk pd2 according to the output signal V of the phase detector 22 local2 to obtain an output clock Clk aligned with the clock signal transmitted on the bus 10 out2 .

[0031] When the output clock Clk out1 and the output clock Clk out2 are required to be aligned with the input clock Clk in1 or the input clock Clkin2 When aligning, the input clock Clk in1 or the input clock Clk in2 is transmitted to the phase detector 21 and the phase detector 22 through the bus 10. Then, the phase of the input clock Clk in1 or the input clock Clk in2 is compared with the output clock Clk processed by the phase modulator 31 out to obtain a signal V representing the phase difference between the two. Then, the phase modulator 31 adjusts the phase of the local clock Clk pd1 according to the output signal V of the phase detector 21 pd1 to obtain an output clock Clk local1 aligned with the input clock Clk in1 or the input clock Clk in2 ; The phase of the input clock Clk out1 is compared with the output clock Clk processed by the phase modulator 32 in1 or the input clock Clk in2 to obtain a signal V representing the phase difference between the two. Then, the phase modulator 32 adjusts the phase of the local clock Clk out2 according to the output signal V of the phase detector 22 pd2 to obtain an output clock Clk pd2 aligned with the input clock Clk local2 or the input clock Clk in1 or the input clock Clk in2 ; out2 .

[0032] When the output clock Clk out1 and the output clock Clk out2 need to be aligned, the output clock Clk processed by the phase modulator 31 out1 or the output clock Clk processed by the phase modulator 32 out2 is transmitted to the phase detector 22 or the phase detector 21 through the bus 10. Then, the phase detector 22 or the phase detector 21 compares the phase of the output clock Clk out1 and the output clock Clk out2 to obtain a signal representing the phase difference between the two. Then, the phase modulator 32 or the phase modulator 31 adjusts the phase of the local clock Clk local2 or the local clock Clk local1 according to the output signal of the phase detector 22 or the phase detector 21 to obtain aligned output clocks Clk out1 and Clk out2 .

[0033] For ease of understanding, in the technical solution disclosed in the embodiments of the present application, the principle of the embodiments of the present application is described by taking two input clocks, two output clocks, and two buses as examples.

[0034] Please refer to the attached Figure 2 , Figure 2 which is a schematic structural diagram of another multi-channel clock output and input alignment zero-delay circuit disclosed in the embodiments of the present application. As Figure 2 shown, the multi-channel clock output and input alignment zero-delay circuit includes: bus 20, bus 30, data selector 11, phase detector 21, phase shifter 31, data selector 12, phase detector 22, and phase shifter 32, where:

[0035] The bus 20 and the bus 30 are used to transmit the input clock Clk in1 , input clock Clk in2 , the output clock Clk out1 of the phase shifter 31, and the output clock Clk out2 of the phase shifter 32 to the data selector 11 and the data selector 12.

[0036] The first input terminal of the data selector 11 is used to obtain the clock signal transmitted on the bus 20, the second input terminal of the data selector 11 is used to obtain the clock signal transmitted on the bus 30, and the data selector 11 is used to select, as needed, the clock signal transmitted on the bus 20 or the bus 30 as the output signal Clk 1 of the data selector 11.

[0037] The first input terminal of the phase detector 21 is connected to the output terminal of the data selector 11, the second input terminal of the phase detector 21 is connected to the output terminal of the phase shifter 31, and the phase detector 21 is used to compare the phase of the output signal Clk 1 of the data selector 11 with the output clock Clk out1 processed by the phase shifter 31 to obtain a signal V 1 representing the phase difference between the output signal Clk out1 of the data selector 11 and the output clock Clk pd1 processed by the phase shifter 31.

[0038] The first input terminal of the phase shifter 31 is used to obtain the local clock Clk local1 , the second input terminal of the phase shifter 31 is connected to the output terminal of the phase detector 21, and the phase shifter 31 is used to adjust the local clock Clk pd1 according to the output signal V local1The phase of the bus 20 or the bus 30 is obtained to align the output clock Clk with the clock signal transmitted on the bus 20 or the bus 30. out1 .

[0039] The first input end of the data selector 12 is used to obtain the clock signal transmitted on the bus 20, and the second input end of the data selector 12 is used to obtain the clock signal transmitted on the bus 30. The data selector 12 is used to select the clock signal transmitted on the bus 20 or the bus 30 as required as the output signal Clk of the data selector 12. 2 ;

[0040] The first input end of the phase detector 22 is connected to the output end of the data selector 12, and the second input end of the phase detector 22 is connected to the output end of the phase modulator 32. The phase detector 22 is used to compare the output signal Clk of the data selector 12. 2 and the output clock Clk processed by the phase modulator 32 out2 The phase of the data selector 12 is obtained to obtain the output signal Clk 2 and the output clock Clk processed by the phase modulator 32 out2 The phase difference of the signal V pd2 .

[0041] The first input terminal of the phase modulator 32 is used to obtain the local clock Clk local2 The second input end of the phase modulator 32 is connected to the output end of the phase detector 22. The phase modulator 32 is used to generate a phase signal V according to the output signal V of the phase detector 22. pd2 Adjust the local clock Clk local2 The phase of the bus 20 or the bus 30 is obtained to align the output clock Clk with the clock signal transmitted on the bus 20 or the bus 30. out2 .

[0042] When the output clock Clk is required out1 With the input clock Clk in1 aligned, the output clock Clk out2 With the input clock Clk in2 When aligned, the input clock Clk in1 , the input clock Clk in2 The data is transmitted to the data selector 11 and the data selector 12 through the bus 20 and the bus 30 respectively; then the data selector 11 selects the input clock Clk in1 The data selector 12 selects the input clock Clk as an output signal. in2 Finally, the output signal Clk of the data selector 11 is compared by the phase detector 21.1 and the phase of the output clock Clk processed by the phase modulator 31 out1 to obtain a signal V representing the phase difference between the two pd1 , and then the phase modulator 31 adjusts the local clock Clk pd1 according to the output signal V of the phase detector 21 local1 to obtain an output clock Clk aligned with the input clock Clk in1 ; the phase detector 22 compares the output signal Clk of the data selector 12 out1 with the phase of the output clock Clk processed by the phase modulator 32 2 to obtain a signal V representing the phase difference between the two out2 , and then the phase modulator 32 adjusts the local clock Clk pd2 according to the output signal V of the phase detector 22 pd2 to obtain an output clock Clk aligned with the input clock Clk local2 ; in2 out2 It should be noted that the clock signal alignment method is rising edge alignment and / or falling edge alignment.

[0043]

[0044]

[0045] The embodiment of the present application provides a multi-channel clock output and input alignment zero-delay circuit, including: a bus, a phase detector, and a phase modulator. Multiple input clocks and output clocks can be transmitted to the phase detector through the bus; when it is necessary to align the output clock with the input clock, the input clock is transmitted to the phase detector through the bus, and then the phase detector compares the phase of the input clock with the output clock processed by the phase modulator to obtain a signal representing the phase difference between the two. Then, the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the input clock; when it is necessary to align different output clocks, the target output clock processed by the phase modulator is transmitted to the phase detector through the bus, and then the phase detector compares the phase of the target output clock with the output clock to be adjusted to obtain a signal representing the phase difference between the two. Then, the phase modulator adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the target output clock.

[0045] The multi-channel clock output and input alignment zero-delay circuit provided by the embodiment of the present application transmits the clock signals to be aligned through the bus. Therefore, the clock signals to be aligned can be at any position on the chip, and their positions can be far apart; at the same time, the multi-channel clock output and input alignment zero-delay circuit provided by the embodiment of the present application has a simple circuit architecture and can be flexibly adjusted. It can realize multiple different clock alignment signals at the same time, achieve zero delay of the clock signals, and thus ensure the accuracy of clock signal time synchronization.

[0046] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the element.

[0047] The above are only embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0048] At this point, those skilled in the art should recognize that although multiple exemplary embodiments of the present application have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present application can still be directly determined or derived from the content disclosed in the present application without departing from the spirit and scope of the present application. Therefore, the scope of the present application should be understood and construed as covering all such other variations or modifications.

Claims

1. A multi-channel clock output and input alignment zero-delay circuit, characterized in that, it includes: a bus, a data selector, a phase detector and a phase shifter, where: The bus is used to transmit the input clock and the output clock of the phase shifter to the data selector, and the bus supports simultaneous access to multiple different clock signals; The data selector is used to select the clock signal to be aligned from the multiple different clock signals and use it as the output signal of the data selector; The first input terminal of the phase detector is used to obtain the output signal transmitted on the data selector; The second input terminal of the phase detector is connected to the output terminal of the phase shifter. The phase detector is used to compare the phase of the output signal transmitted on the data selector with the output clock processed by the phase shifter to obtain a signal representing the phase difference between the two; The first input terminal of the phase shifter is used to obtain the local clock, and the second input terminal of the phase shifter is connected to the output terminal of the phase detector. The phase shifter is used to adjust the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the clock signal transmitted on the bus; When it is necessary to align the output clock with the input clock, the input clock is transmitted to the data selector through the bus; the data selector selects the input clock as the output signal; the phase detector compares the output signal of the data selector with the output clock processed by the phase shifter to obtain a signal representing the phase difference between the two; the phase shifter adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the input clock, realizing zero delay between the output clock and the input clock; When it is necessary to align different output clocks, the target output clock processed by the phase shifter is transmitted to the data selector through the bus; the data selector selects the target output clock as the output signal; the phase detector compares the phase of the output signal of the data selector with the output clock to be adjusted to obtain a signal representing the phase difference between the two; the phase shifter adjusts the phase of the local clock according to the output signal of the phase detector to obtain an output clock aligned with the target output clock, realizing zero delay of the output clock.

2. The multi-channel clock output and input alignment zero-delay circuit according to claim 1, characterized in that, The number of the buses is consistent with the number of types of different clock alignment signals simultaneously available.

3. The multi-channel clock output and input alignment zero-delay circuit according to claim 1, characterized in that, The clock signal alignment method is rising edge alignment and / or falling edge alignment.

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