Non-volatile memory device and method of reading thereof

Abstract

Non-volatile memory devices and methods of reading the same are provided. The non-volatile memory devices include a memory cell array, a word line driver, a bit line driver, a read circuit, and control logic. The memory cell array includes a plurality of memory banks. Each memory bank includes a plurality of blocks. Each block includes a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines. The word line driver selects one of the plurality of word lines in response to an input address. The bit line driver selects one of the plurality of bit lines in response to the input address. The read circuit reads a codeword from the memory cell array in a read operation. The control logic is configured to control the word line driver, the bit line driver, and the read circuit in the read operation. In the read operation, the control logic performs address scrambling on the input address and provides the scrambled address to the read circuit to access the plurality of blocks.

Description

[0001] This patent application claims the benefit of priority to Korean Patent Application No. 10-2020-0025983, filed on March 2, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of the present invention relate to a non-volatile memory device, a storage device having the non-volatile memory device, and a method for reading the non-volatile memory device. Background Technology

[0003] Phase-change random access memory (PRAM) is a type of non-volatile memory that utilizes the unique behavior of phase-change materials (such as chalcogenide alloys) to store data. Chalcogenide alloys can change into either a crystalline or amorphous state after being heated and cooled. Phase-change materials have low resistance in their crystalline state and high resistance in their amorphous state. The crystalline state can represent data set or logic level 0, while the amorphous state can represent data reset or logic level 1. Summary of the Invention

[0004] Example embodiments of the present invention can provide a non-volatile memory device with improved read margin, a storage device having the non-volatile memory device, and a method for reading the non-volatile memory device.

[0005] According to an exemplary embodiment of the present invention, a non-volatile memory device includes a memory cell array, a word line driver, a bit line driver, read circuitry, and control logic. The memory cell array includes a plurality of memory banks having multiple blocks. Each of the multiple blocks has a plurality of resistive memory cells connected to multiple bit lines and multiple word lines. The word line driver is configured to select one of the multiple word lines in response to an input address. The bit line driver is configured to select one of the multiple bit lines in response to an input address. The read circuitry is configured to read a codeword from the memory cell array during a read operation. The control logic is configured to control the word line driver, the bit line driver, and the read circuitry during a read operation. During a read operation, the control logic performs address scrambling on the input address and provides the scrambled address to the read circuitry to access the multiple blocks.

[0006] According to an exemplary embodiment of the present invention, a non-volatile memory device includes a first block and a second block, wherein each of the first block and the second block includes: a first resistive memory cell formed on a first layer and connected between a first word line and a bit line; a second resistive memory cell formed on a second layer disposed on the first layer and connected between a second word line and a bit line; and peripheral circuitry disposed below the first layer, wherein each of the first word line, the second word line, and the bit line is connected to each other through at least one via, wherein each of the first block and the second block is driven according to address scrambling during a read operation.

[0007] According to an exemplary embodiment of the present invention, a method for reading a non-volatile memory device includes: determining a read level based on an address input in a read operation; performing a read operation using the determined read level to read data; performing an error correction operation on the read data to generate error-corrected data; and outputting the error-corrected data to an external device, wherein the read operation is performed by address scrambling based on a combination of different blocks, different word lines, or different bit lines.

[0008] According to an exemplary embodiment of the present invention, a storage device includes: at least one memory device; and a memory controller configured to control the at least one non-volatile memory device, wherein the at least one non-volatile memory device includes a memory cell array. The memory cell array includes a plurality of memory banks, wherein each of the plurality of memory banks includes a plurality of blocks. The plurality of blocks are driven according to address scrambling. Attached Figure Description

[0009] The inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a diagram illustrating a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0011] Figure 2 This is a diagram illustrating adjacent blocks (Tile 1 and Tile 2) with address scrambling according to an example embodiment of the present disclosure;

[0012] Figure 3 This is a diagram illustrating one of a plurality of blocks according to an exemplary embodiment of the present disclosure;

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D This is a diagram illustrating a memory cell according to an exemplary embodiment of the present disclosure;

[0014] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F This is a diagram illustrating the three-dimensional structure of a memory cell according to an exemplary embodiment of the present disclosure;

[0015] Figure 6A This is a diagram illustrating a three-dimensional stacked structure of a memory cell array 110 according to an exemplary embodiment of the present disclosure;

[0016] Figure 6B This is a diagram showing a layer that includes multiple blocks;

[0017] Figure 6C This is a diagram showing blocks formed in multiple layers;

[0018] Figure 6D This is a diagram showing multiple memory banks with multiple blocks in multiple layers;

[0019] Figure 7 This illustrates an example embodiment according to the present disclosure. Figure 6A A diagram showing a single memory cell layer 110-1;

[0020] Figure 8 This is a diagram illustrating a memory cell array 110a according to another exemplary embodiment of the present disclosure;

[0021] Figure 9 This is a diagram illustrating a memory cell array 110b according to another exemplary embodiment of the present disclosure;

[0022] Figure 10 This is a diagram illustrating the layers of a non-volatile memory device 100 according to another exemplary embodiment of the present disclosure;

[0023] Figure 11 It is shown that it includes Figure 10 A diagram showing the memory cells in the block;

[0024] Figure 12 This is a diagram illustrating the sense amplifier (SA) of the readout circuit 142 according to an exemplary embodiment of the present disclosure;

[0025] Figure 13 This is a diagram illustrating blocks according to an example embodiment of the present disclosure;

[0026] Figure 14 It is along Figure 13 A sectional view of line I-I' in the middle;

[0027] Figure 15 It is along Figure 13A sectional view of line II-II' in the middle;

[0028] Figure 16A and Figure 16B This is a diagram illustrating a read operation of a non-volatile memory device;

[0029] Figure 17A and Figure 17B This is a diagram illustrating an application of address scrambling in a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0030] Figure 18 This is a diagram illustrating an application of address scrambling in a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0031] Figure 19 This is a diagram illustrating address scrambling of a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0032] Figure 20 This is a diagram illustrating the read levels of each block group of a non-volatile memory device according to an exemplary embodiment of the present disclosure;

[0033] Figure 21A , Figure 21B and Figure 21C This is a diagram illustrating an application of an example embodiment of the present disclosure with address scrambling of a block group;

[0034] Figure 22 This is a flowchart illustrating a write operation of a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0035] Figure 23 This is a flowchart illustrating a write operation of a non-volatile memory device 100 according to an embodiment of the present disclosure;

[0036] Figure 24 This is a flowchart illustrating a read operation of a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure;

[0037] Figure 25 This is a diagram illustrating a storage device 1000 according to an exemplary embodiment of the present disclosure;

[0038] Figure 26 This is a diagram illustrating a memory system 2000 with a specific read level applied according to an example embodiment of the present disclosure;

[0039] Figure 27 This is a diagram illustrating a memory system 2000a that can use environmental information to compensate for read voltage according to an example embodiment of the present disclosure;

[0040] Figure 28This is a diagram illustrating a server system 3000 according to an example embodiment of the present disclosure;

[0041] Figure 29 This is a diagram illustrating a computing system 4000 according to an exemplary embodiment of the present disclosure;

[0042] Figure 30 This is a diagram illustrating an electronic system 5000 for a vehicle according to an exemplary embodiment of the present disclosure;

[0043] Figure 31 This is a diagram illustrating a mobile device 6000 according to an exemplary embodiment of the present disclosure; and

[0044] Figure 32 This is a diagram illustrating a data server system 7000 according to an example embodiment of the present disclosure. Detailed Implementation

[0045] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0046] In a non-volatile memory device and its operation method according to an example embodiment, the read margin of a tile (or "block" or "data block") of the non-volatile memory device can be balanced by applying address scrambling to the address-based activated tile during a read operation. Address scrambling can be configured by a combination of different tiles, different word lines, or different bit lines that are not adjacent to each other during the read operation. Therefore, when word line bridging is generated, the number of erroneous bits can be reduced. Thus, read margin and yield can be improved.

[0047] Figure 1 This is a diagram illustrating a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 1 The non-volatile memory device 100 includes a memory cell array 110, a word line (WL) driver 120 (e.g., driver circuitry), a bit line (BL) driver 130 (e.g., driver circuitry), a read and write circuit (RWC) 140, a data input and output (I / O) circuit 150, an error correction circuit (ECC) 160, and control logic 170 (e.g., logic circuitry).

[0048] The memory cell array 110 can be connected to the word line driver 120 via multiple word lines WLs, and can be connected to the bit line driver 130 via multiple bit lines BLs.

[0049] The memory cell array 110 may include multiple banks (Bank 1 to Bank i; where i is an integer equal to or greater than 2). Each of the multiple banks may include multiple blocks (Tile 1 to Tile j; where j is an integer equal to or greater than 2). Each of the multiple blocks may include multiple memory cells connected to multiple word lines WLs and multiple bit lines BLs. Each of the multiple memory cells may be connected between a word line and a bit line. The memory cells may use resistive material to store at least one bit. In one exemplary embodiment, each block is capable of storing the same amount of data or includes the same number of memory cells.

[0050] In one example embodiment, multiple blocks can be driven by address scrambling during a read operation. Therefore, multiple blocks can include memory cells configured to receive the same address based on address scrambling and to be activated at different locations. Address scrambling can be configured using combinations of different blocks, different word lines, or different bit lines.

[0051] Word line driver 120 can be connected to memory cell array 110 via word lines WLs. Word line driver 120 may include at least one row decoder (e.g., one or more row decoding circuits). Peripheral circuitry may include at least one row decoder. The row decoder can select one of the word lines using a row address according to the control logic 170. For example, the row decoder can select one of the word lines using a row address in response to a control signal from control logic 170. Word line driver 120 can apply a word line voltage to the selected word line. The word line voltage may include read word line voltage, write word line voltage, etc. Although Figure 1 Although not shown, word line driver 120 may include voltage generator circuitry configured to generate such word line voltages.

[0052] In one example embodiment, in response to the same address, word line driver 120 can select a word line to activate memory cells located at different locations in at least two of a plurality of blocks.

[0053] Bit line driver 130 can be connected to memory cell array 110 via bit lines BLs. Bit line driver 130 may include at least one column decoder (e.g., one or more column decoding circuits). The column decoder can select one of the bit lines using a column address according to the control logic 170. For example, the column decoder can select one of the bit lines using a column address in response to a control signal from control logic 170. Furthermore, bit line driver 130 can apply a bit line voltage to the selected bit line. The bit line voltage may include a read voltage, a set bit line voltage, a reset bit line voltage, etc. Although... Figure 1Although not shown, the bit line driver 130 may include voltage generator circuitry for generating bit line voltages.

[0054] In one example embodiment, in response to the same address, bit line driver 130 can select a bit line to activate memory cells located at different locations in at least two of a plurality of blocks.

[0055] The read and write circuit 140 can perform read or write operations on the memory cell array 110 according to the control logic 170. The read and write circuit 140 includes a write circuit 141 and a read circuit 142.

[0056] Write circuitry 141 can be connected to word line driver 120 and bit line driver 130. Write circuitry 141 can be implemented to perform write operations (set or reset operations) on memory cells connected to selected bit lines and selected word lines according to control logic 170. For example, in response to a write control signal from control logic 170, write circuitry 141 can apply word line voltages to selected word lines and bit line voltages to selected bit lines. In one example embodiment, write circuitry 141 generates a set or reset pulse corresponding to the data to be written in the write operation and applies the generated pulse to the selected word line / bit line.

[0057] In one example embodiment, when writing data to a selected memory cell, the write circuit 141 determines the write current based on the resistance of the selected memory cell.

[0058] Read circuitry 142 can be connected to word line driver 120 and bit line driver 130. Read circuitry 142 can be implemented to read data from memory cells connected to selected bit lines and selected word lines according to control of control logic 170. For example, read circuitry 142 can read data from memory cells connected to selected bit lines and selected word lines in response to a read control signal from control logic 170. In one example embodiment, read circuitry 142 can perform a sensing operation to sense the voltage difference between the voltage of the selected word line / bit line and a reference voltage, and distinguish between on / off cells based on the sensed voltage difference.

[0059] In one example embodiment, such as Figure 1 As shown, the read and write circuitry 140 is positioned below the word line driver 120. In alternative embodiments, the read and write circuitry 140 may be located in different positions.

[0060] The data input and output circuitry 150 can be implemented to transfer write data received from an external device (e.g., a memory controller) to a data latch of the control logic 170 during a write operation, under the control of the control logic 170. Furthermore, the data input and output circuitry 150 can be implemented to output data read from the data latch to an external device (e.g., a memory controller) during a read operation. In one example embodiment, the data input and output circuitry 150 can be implemented to input and output data to sector units. For example, the data input and output circuitry 150 can be configured to input and output data on a sector-by-sector basis.

[0061] Error correction circuit 160 can receive written data from data input and output circuit 150 and can generate error correction code (or parity check, low-density parity check (LDPC) code). The codeword containing the written data and error correction code can then be stored in a memory cell array corresponding to the written address.

[0062] Furthermore, the error correction circuit 160 can use error correction codes to correct errors in the read data during the read operation. For example, a codeword can be read from the memory cell array corresponding to the read address, and a checksum can be generated from the read codeword. Errors in the read codeword can be corrected using the checksum.

[0063] Control logic 170 can be implemented to control the overall operation of the non-volatile memory device 100. Control logic 170 can control word line driver 120, bit line driver 130, write circuitry 141, read circuitry 142, data input and output circuitry 150, and / or error correction circuitry 160 in response to commands (CMD), addresses (ADD), or control signals input from an external entity. For example, the external entity can be a memory controller located outside the non-volatile memory device 100.

[0064] In one example embodiment, control logic 170 selects one of a plurality of write modes and performs a write operation according to the selected write mode. In one example embodiment, control logic 170 may use the selected write mode, written data, or read data to generate a write control signal, or may use the selected write mode or written data to generate a read control signal. In one example embodiment, among the plurality of write modes, the write operation may be performed using one of the following modes: normal mode, data comparison write (DCW) mode, aggressive data comparison write (aDCW) mode, and read skip active data comparison write (RDSKIP aDCW) mode. Normal mode may be a mode that does not reflect resistance drift, DCW mode may be a mode that reflects resistance drift in the reset state, and aDCW mode and RDSKIP aDCW mode may be modes that reflect both resistance drift in the set state and resistance drift in the reset state.

[0065] Non-volatile memory devices can configure sectors (e.g., 64 bits) by merging bits of data corresponding to the same location in several blocks in response to an address. The processing properties of the blocks are then identical. However, problems may occur in sectors of the worst-performing regions within a block (e.g., near or far regions of the word line decoder / bit line decoder). For example, memory cells closer to the decoder than memory cells further away from the decoder may have more errors. In another example, memory cells further away from the decoder than memory cells closer to the decoder may have more errors.

[0066] Conversely, in the example embodiment, even when a read operation is performed at any address, the non-volatile memory device 100 can guarantee the same level of read margin by applying address scrambling to the blocks activated (or selected) in response to the address. Therefore, failures caused by combinations of the worst-case regions in the non-volatile memory device can be mitigated. Furthermore, when word line bridging or bit line bridging is generated, the consumption rate of error correction codes can be reduced. As a result, yield can be improved.

[0067] Figure 2 This is a diagram illustrating an application of an example embodiment of the inventive concept with address-scrambled adjacent blocks (Tile 1 and Tile 2).

[0068] Reference Figure 2In the first Tile 1, multiple word lines can be allocated from the bottom to the top of the cell array (WL1 to WLm; where m is an integer equal to or greater than 2), and in the second Tile 2, multiple word lines can be allocated from the bottom (the fifth word line) to the top. For example, the row decoder X-DEC of the first Tile 1 can activate the first word line WL1 located at the bottom (i.e., the first word line WL1 of the first Tile 1) in response to the row address, and the row decoder X-DEC of the second Tile 2 can activate the fifth word line from the bottom (i.e., the first word line WL1 of the second Tile 2) in response to the same row address.

[0069] like Figure 2 As shown, the first block Tile 1 may include a first word line group WL1 to WLm, in which the word line numbers are along a first direction (e.g., as shown in the diagram). Figure 2 The bits (as shown in the diagram, from bottom to top) are sequentially assigned. The first direction can be the direction along which the bit lines extend. Furthermore, the second block Tile 2 may include second word line groups WL1 to WLm-4 and remaining word line groups WLm-3 to WLm, in which the word line numbers are assigned along the first direction from a predetermined position (e.g., as shown in the diagram). Figure 2 The fifth word line (shown from the bottom) is assigned sequentially, and the remaining word line groups WLm-3 to WLm correspond to the remaining word line numbers assigned sequentially along the first direction. The predetermined position can be a random position of the sequentially assigned word lines. For example, the predetermined position can be the center portion of the sequentially assigned word lines.

[0070] As described above, address scrambling in the example embodiments may include word line scrambling. Word line scrambling refers to a configuration in which word lines activated in response to the same row address are physically located differently from each other. However, the example embodiments of word line scrambling are not limited thereto. Figure 2 The word line scrambling shown is a feasible example.

[0071] Refer to the return Figure 2 In the first Tile 1, bit line numbers can be assigned from left to right (BL1 to BLn; where n is an integer equal to or greater than 2), and in the second Tile 2, bit line numbers can be assigned from right to left.

[0072] like Figure 2As shown, the first block Tile 1 may include first bit line groups BL1 to BLn, which correspond to bit line numbers sequentially assigned along a second direction. The second direction is the direction along which the word lines extend. Furthermore, the second block Tile 2 may include second bit line groups BL1 to BLn, which correspond to bit line numbers sequentially assigned along a direction opposite to the second direction.

[0073] The allocation of bit line numbers for blocks in the example embodiments is not limited to the foregoing examples. The first block Tile 1 may include the first bit line group BL1 to BLn corresponding to the bit line numbers sequentially allocated along the second direction, and the second block Tile 2 may include the second bit line group corresponding to the bit line numbers sequentially allocated from a predetermined position along the second direction and the remaining bit line group corresponding to the remaining bit line numbers sequentially allocated along the second direction.

[0074] As described above, address scrambling in the example embodiments may include bit-line scrambling. Bit-line scrambling refers to a configuration in which the physical locations of the bit lines activated (or selected) in response to the same column address are different from each other. However, the example embodiments of bit-line scrambling are not limited thereto. Figure 2 The bit-line scrambling shown is a feasible example.

[0075] Figure 3 This is a diagram illustrating one of a plurality of blocks according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 3 The block may include multiple memory cells MC located at the intersection of multiple word lines WL1 to WLm and multiple bit lines BL1 to BLn.

[0076] In one example embodiment, Figure 3 Each memory cell MC shown includes a variable resistor.

[0077] Figure 4A , Figure 4B , Figure 4C and Figure 4D This is a diagram illustrating a memory cell according to an example embodiment of the inventive concept.

[0078] Reference Figure 4AThe memory cell MC includes a variable resistor R and a diode D. In one example embodiment, the variable resistor R is made of a phase change material. For example, phase change materials can include various types of materials such as GaSb, InSb, InSe, Sb2Te3 and GeTe formed by combining two elements; GeSbTe, GaSeTe, InSbTe, SnSb2Te4 and InSbGe formed by combining three elements; and AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and Te formed by combining four elements. 81 Ge 15 (e.g., Sb2S2). In another example embodiment, the variable resistor R comprises a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, rather than a phase change material.

[0079] Reference Figure 4B The memory cell MC includes a variable resistor R and a bidirectional diode BD.

[0080] Reference Figure 4C The memory cell MC includes a variable resistor R and a transistor T. The word line WL can be connected to the gate of transistor T.

[0081] Reference Figure 4D The memory cell MC includes a bidirectional threshold switch (OTS) and a variable resistor R. The bidirectional threshold switch (OTS) can include materials similar to germanium-antimony-telluride (GST; Ge2Sb2Te5). For example, the bidirectional threshold switch (OTS) can include chalcogenides that can be changed to a crystalline or amorphous state. Chalcogenides can include combinations of selenium (Se), arsenic (As), germanium (Ge), and silicon (Si).

[0082] The structure of the memory cell MC is not limited to Figure 4A , Figure 4B , Figure 4C and Figure 4D The example shown is shown in the image.

[0083] In the following description, an example of a three-dimensional structure of a memory cell configured as a switching device will be described.

[0084] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F This is a diagram illustrating the three-dimensional structure of a memory cell according to various exemplary embodiments of the inventive concept.

[0085] Figure 5AA first memory cell MC1 and a second memory cell MC2 are shown arranged between multiple conductors 101, 102, and 103. The first memory cell MC1 and the second memory cell MC2 can operate as independent memory cells. In an example embodiment, when the first conductor 101 and the second conductor 102 are word lines, the third conductor 103 can be a bit line. In the following description, for ease of description, the first conductor 101 and the second conductor 102 are referred to as the first word line and the second word line, respectively, and the third conductor 103 is referred to as the bit line.

[0086] In an example embodiment, the first memory cell MC1 includes a first heating electrode 111, a first data storage device 112, and a first switching device 113. In an example embodiment, the first switching device 113 includes a first switching electrode 113-1, a second switching electrode 113-2, and a first selection layer 113-3 disposed between the first switching electrode 113-1 and the second switching electrode 113-2. In an example embodiment, the first selection layer 113-3 may include a bidirectional threshold switch (OTS) material. When a voltage greater than the threshold voltage is applied between the first switching electrode 113-1 and the second switching electrode 113-2, current can flow through the first selection layer 113-3. The first data storage device 112 may include a phase change material. In an example embodiment, the first data storage device 112 may include, for example, a chalcogenide material. For example, the first data storage device 112 may include Ge-Sb-Te (GST). The crystallization temperature, melting point, and phase transition rate based on crystallization energy of the first data storage device 112 can be determined based on the type and chemical composition ratio of the elements included in the first data storage device 112.

[0087] The second memory cell MC2 can be implemented with a structure similar to that of the first memory cell MC1.

[0088] In the following description, a method for storing and erasing data will be described with reference to the first memory cell MC1. When a voltage is supplied through the first word line 101 and the bit line 103, Joule heating can be generated at the interface between the first heating electrode 111 and the first data storage device 112, depending on the voltage. Due to Joule heating, the phase change material within the first data storage device 112 can change from an amorphous state to a crystalline state, or vice versa. The first data storage device 112 can have high resistance in the amorphous state and low resistance in the crystalline state. In an example embodiment, data "0" and data "1" can be defined based on the resistance value of the first data storage device 112.

[0089] To store data in the first memory cell MC1, a programming voltage can be supplied via the first word line 101 and the bit line 103. The programming voltage can be greater than the threshold voltage of the bidirectional threshold switching material included in the first switching device 113. Therefore, current can flow through the first switching device 113. Due to the application of the programming voltage, the phase change material included in the first data storage device 112 can change from an amorphous state to a crystalline state. Therefore, data can be stored in the first memory region. In the example embodiment, when the phase change material included in the first data storage device 112 is in a crystalline state, the state of the first memory cell MC1 can be referred to as the set state.

[0090] To remove (or erase) data stored in the first memory cell MC1, the phase change material included in the first data storage device 112 can be restored from a crystalline state to an amorphous state. For example, a predetermined erase voltage can be supplied through the first word line 101 and the bit line 103. Due to the application of the erase voltage, the phase change material included in the first data storage device 112 can change from a crystalline state to an amorphous state. When the phase change material included in the first data storage device 112 is in an amorphous state, the state of the first memory cell MC1 can be referred to as the reset state. In the example embodiment, the maximum value of the erase voltage can be greater than the maximum value of the programming voltage. The time for applying the erase voltage can be shorter than the time for applying the programming voltage.

[0091] exist Figure 5A In this embodiment, the first memory cell MC1 and the second memory cell MC2 can be implemented to have the same orientation. However, other embodiments of the memory cells are not limited to this.

[0092] Reference Figure 5B When the first conductor 101 and the second conductor 102 are the first word line and the second word line respectively, and... Figure 5A Compared to the memory cells shown, the directionality of the first memory cell MC1 and the second memory cell MC2 can be different from each other. For example, the first heating electrode 111 of the first memory cell MC1 can be connected to the first word line 101, and the second heating electrode 114 of the second memory cell MC2 can be connected to the bit line 103.

[0093] Figure 5A Each of the first memory cell MC1 and the second memory cell MC2 shown in the figure may have a second orientation. Figure 5B The first memory cell MC1 shown may have a second orientation, and the second memory cell MC2 may have a first orientation.

[0094] exist Figure 5A and Figure 5BIn this embodiment, a first memory cell MC1 connected to a first word line 101 formed on the first level and a second memory cell MC2 connected to a second word line 102 formed on the second level can share a bit line 103. However, the structure of the memory cells in the example embodiment is not limited to this.

[0095] Reference Figure 5C The first memory cell MC1 can be arranged at the point where the first word line 101 and the first bit line 102 formed on the first level intersect. The second memory cell MC2 can be arranged at the point where the second word line 103 and the second bit line 104 formed on the second level intersect. The first memory cell MC1 can have a second orientation, and the second memory cell MC2 can have a first orientation.

[0096] Reference Figure 5D ,and Figure 5C The memory cells shown are different; each of the first memory cell MC1 and the second memory cell MC2 may have a second orientation.

[0097] However, the memory cell in the example embodiment may not include a heating electrode and may be self-heating.

[0098] Figure 5E The memory cell shown has a... Figure 5C The memory cell shown in the image has its heating electrode removed. Figure 5F The memory cell shown has a... Figure 5D The memory cell shown has a structure that removes the heating electrode. In one example, element 115 is an electrode layer.

[0099] In one example embodiment, the memory cell array 110 has a three-dimensional stacked structure.

[0100] Figure 6A This is a diagram illustrating a three-dimensional stacked structure of a memory cell array 110 according to an exemplary embodiment of the inventive concept. The three-dimensional stacked structure may refer to a stacked structure in which multiple memory cell layers 110-1 to 110-8 are vertically stacked on a substrate.

[0101] Figure 6A An example of eight stacked memory cell layers 110-1 to 110-8 is shown, but the number of layers is not limited thereto. Each of the memory cell layers 110-1 to 110-8 may include multiple groups of resistive memory cells or multiple groups of redundant memory cells. When the memory cell array 110 has a three-dimensional stacking structure, in the example embodiment, the multiple memory cell layers 110-1 to 110-8 may have a cross-point structure.

[0102] In the example embodiment, at least two of the plurality of memory cell layers 110-1 to 110-8 can perform write operations according to different write modes. In the example embodiment, at least two of the plurality of memory cell layers 110-1 to 110-8 can perform read operations according to different read levels.

[0103] Figure 6A Each of the layers shown can include multiple blocks.

[0104] Figure 6B This is a diagram illustrating layers comprising multiple blocks. Each layer can include 64 blocks. However, the number of blocks included in each layer is not limited to this.

[0105] Figure 6B The blocks shown can be formed on a single layer. However, the example embodiments of blocks are not limited to this. For example, in one example embodiment, blocks can be formed on multiple layers.

[0106] Figure 6C This is a diagram showing blocks formed across multiple layers. (See reference...) Figure 6C Each of the cell arrays CA1 in layers one through four can be included in a single block. Figure 6C In this configuration, the corresponding cell arrays of the four layers are configured as single blocks. However, the block configuration is not limited to this. As an example, Figure 6C The various layers, consisting of 64 cell arrays CA1 to CA64, are shown.

[0107] Figure 6D This is a diagram illustrating multiple memory banks with multiple blocks across multiple layers. (Refer to...) Figure 6D Each of the three tiers can include two storage units, and each storage unit can include 64 blocks. However, the configuration of storage units, blocks, and tiers is not limited to this.

[0108] Figure 7 This illustrates an example embodiment based on the inventive concept. Figure 6A A diagram showing a single memory cell layer 110-1 is provided. (Refer to...) Figure 7 The memory cell layer 110-1 may include an intersection structure. An intersection structure can refer to a structure in which a single memory cell MC (e.g., a resistive memory cell) is formed in a region where one line (e.g., a bit line) intersects with another line (e.g., a word line). For example, bit lines BL1_1 to BL4_1 may extend and be formed along a first direction, and word lines WL1_1 to WL3_1 may extend and be formed along a second direction to intersect with bit lines BL1_1 to BL4_1. Memory cells MC may be formed in the regions where bit lines BL1_1 to BL4_1 intersect with word lines WL1_1 to WL3_1, respectively.

[0109] In an example embodiment, the memory cell MC can be configured as a single-level cell (SLC) for storing one bit of data. In another example embodiment, the memory cell MC can be configured as a multi-level cell (MLC) for storing two or more bits of data. In yet another example embodiment, a portion of the memory cells MC are single-level cell (SLCs), and the other memory cells MC are multi-level cell (MLCs).

[0110] The memory cell array 110 in the example embodiment may include a cell array that performs buffering functions.

[0111] Figure 8 This is a diagram illustrating a memory cell array 110a according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 8 The memory cell array 110a may include a first memory cell array 110a-1 and a second memory cell array 110a-2. In an example embodiment, the first memory cell array 110a-1 may function as a master cell, and the second memory cell array 110a-2 may function as a buffer.

[0112] In the example embodiment, the first memory cell array 110a-1 and the second memory cell array 110a-2 can perform write operations according to different write modes.

[0113] In addition, such as Figure 8 As shown, the RWC layer can be disposed below the memory cell array 110a. RWC ( Figure 1 The RWC140 (including write circuitry 141 and read circuitry 142) can perform write and read operations on multiple memory cells included in the memory cell array 110a. Although the RWC layer is... Figure 8 It is shown as being positioned below the memory cell array 110a, but the location of the RWC layer is not limited to this.

[0114] Figure 8 The first memory cell array 110a-1 and the second memory cell array 110a-2 shown can be disposed on the same layer. However, the example embodiments of the first memory cell array 110a-1 and the second memory cell array 110a-2 are not limited thereto. The first memory cell array and the second memory cell array can be disposed on different layers.

[0115] Figure 9 This is a diagram illustrating a memory cell array 110b according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 9The memory cell array 110b may include a plurality of first memory cell arrays 110b-1 disposed on different layers and a second memory cell array 110b-2 disposed on a different layer from the layer on which the first memory cell arrays 110b-1 are disposed.

[0116] In an example embodiment, at least two of the first memory cell array 110b-1 and the second memory cell array 110b-2 can perform write operations according to different write modes.

[0117] In the following description, for ease of description, it is assumed that the non-volatile memory device 100 includes two layers having multiple blocks.

[0118] Figure 10 This is a layered diagram illustrating an example embodiment of a non-volatile memory device 100 according to the inventive concept. Figure 10 As shown, the two rows of blocks Tile 1 to Tile 8 are placed on the first layer, and the two rows of blocks are placed on the second layer. However, the number of blocks and rows placed on a single layer is not limited to this.

[0119] Figure 11 It is shown that it includes Figure 10 A diagram showing the memory cells within a block. (Refer to...) Figure 11 The first-level memory cell MC is connected between the first-level word line WL_L1 and the bit line BL, and the second-level memory cell MC is connected between the second-level word line WL_L2 and the bit line BL. Each of the first and second memory cells may include a variable device (e.g., GST) and a switching device (e.g., OTS). The memory cell MC may be arranged symmetrically with respect to the bit line BL.

[0120] Figure 11 The structure of the memory cell shown is only an example.

[0121] Figure 12 This is a diagram illustrating the sense amplifier (SA) 152 of the readout circuit 142 according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 12 The sensing amplifier (SA) 152 compares the voltage of the word line WL connected to the memory cell MC with a reference voltage Vref and outputs the sensing result SAOUT. The memory cell MC can be positioned between a selected word line WL and a selected bit line BL. During a read operation, a read voltage Vread can be applied to the selected bit line BL.

[0122] In the example embodiment, the read voltage Vread can vary depending on the mode of the write operation (normal mode, DCW mode, aDCW mode, and RDSKIP aDCW mode).

[0123] In another example embodiment, the read voltage Vread can vary according to an internal strategy of the non-volatile memory device 100. This internal strategy may include sensing the degree of degradation of memory cells, environmental information, time information, location information, etc., and adjusting the read level of the read voltage Vread based on the sensing results.

[0124] In another example embodiment, the read voltage Vread can vary based on information transmitted from an external device (e.g., a memory controller).

[0125] Figure 12 The sense amplifier (SA) 152 shown is merely an example. For instance, the sense amplifier in one example embodiment can also sense data by comparing the voltage of the bit line with a reference voltage Vref.

[0126] Figure 13 This is a diagram illustrating blocks according to an example embodiment of the inventive concept. (Refer to...) Figure 13 The row decoder 221 used to select the memory cells of the first layer ( Figure 15 The 1F LX) and the row decoder 222 for selecting memory cells in the second layer Figure 15 The 2F LX bits can all be set along the X-axis and can be alternately set along the Y-axis. To select the bit lines shared by the memory cells of the first and second layers, the column decoder 231 (LY) can be set along the Y-axis. The Y-axis can be perpendicular to the X-axis. Word line 213 ( Figure 14 WL_L1 and WL_L2 can be set at the top of the second layer line decoder 222 along the X-axis.

[0127] Figure 14 It is along Figure 13 A cross-sectional view of line I-I' in the diagram. (Refer to...) Figure 14 Non-volatile memory devices can be implemented with a cell-on-peripheral (CoP) structure. For example, the memory cells MC of the first layer 211 and the second layer MC of the second layer 212 can be disposed on the upper part of the peripheral region 202. The peripheral region 202 may include Figure 1The diagram shows a word line driver 120 (row decoder), a bit line driver 130 (column decoder), read and write circuitry 140, data input and output circuitry 150, error correction circuitry 160, and / or control logic 170. In an example embodiment, a peripheral region 202 may be disposed on a substrate 201. The peripheral region 202 may include peripheral circuitry, including at least one of the word line driver 120, bit line driver 130, read and write circuitry 140, data input and output circuitry 150, error correction circuitry 160, and control logic 170.

[0128] like Figure 14 As shown, the bit line BL shared by the first layer 211 and the second layer 212 can be connected to the peripheral region 202 via at least one via. Furthermore, as... Figure 14 As shown, the first memory cell MC in the first layer 211 and the second memory cell MC in the second layer 212 can be arranged symmetrically with respect to the bit line BL.

[0129] Figure 15 It is along Figure 13 The sectional view of line II-II' in the middle.

[0130] like Figure 15 As shown, the word line WL_L1 of the first layer 211 can be connected to the line decoder 221 (1F LX) formed in the peripheral region 202 via at least one via. Furthermore, the word line WL_L2 of the second layer 212 can be connected to the line decoder 222 (2F LX) formed in the peripheral region 202 via at least one via.

[0131] like Figure 15 As shown, there may be near units connected to the line decoder 222 at a relatively short distance, and there may be far units connected to the line decoder 222 at a relatively far distance.

[0132] Figure 16A and Figure 16B This is a diagram illustrating a read operation of a non-volatile memory device. Non-volatile memory devices can configure sector data by merging data bits corresponding to the same location within a block. For example, as... Figure 16AAs shown, four bits can be included in a single block, allowing 64 bytes of sector data to be configured through 128 blocks, Tile 1 to Tile 128. However, it is highly likely that the sector data of memory cells in the worst-case region (the near-field region of LY / LX) within a block may be problematic due to the block having the same processing attributes. In other words, because edge bits within a block can be merged, failures may occur during read operations when the edge region of a block is the worst. Even if the ECC bits of the central region are reserved, the chip may be processed as failed when all read operations in the central region pass.

[0133] In addition, such as Figure 16B As shown, when word line bridging (WL BRG) occurs, the error correction circuit 160 (see...) Figure 1 It may consume 4 bits / 64 bytes for error correction. When the error correction circuit 160 (see...) Figure 1 With a 5-bit / 64-byte capability, it is highly likely that read operations will be invalidated when word line bridging occurs. In other words, even when a single word line bridging occurs, read operations may be invalidated. Furthermore, when bit line bridging occurs, the error correction circuit 160 may consume 2 bits / 64 bytes for error correction.

[0134] Conversely, in the non-volatile memory device 100 of the example embodiment, address scrambling (read scrambling) is configured by combining different blocks, different word lines, and / or different bit lines during read operations, allowing read operations to be performed at equal levels within blocks. Therefore, even when word line / bit line bridging occurs, the number of one or more ECC bits consumed in the error correction circuit 160 for error correction can be minimized.

[0135] Figure 17A and Figure 17B This is a diagram illustrating an example embodiment of a non-volatile memory device 100 with address scrambling according to an inventive concept.

[0136] Reference Figure 17A In blocks Tile 1 to Tile 128, the locations of memory cells activated by selected word lines (e.g., selected) can be different from each other.

[0137] In the example embodiment, the physical locations activated by selected word lines in tiles 1 through 128 can be determined along the word line direction (from top to bottom) according to an arithmetic sequence. For example, as Figure 17AAs shown, the activated physical location can be set along the word line direction at a distance of 2k+1 from below (k is a natural number). Therefore, in each block of the example embodiment, the location of the memory cell activated by the address can have a regular pattern.

[0138] In the example embodiment, the physical locations activated by selected word lines in blocks Tile 1 to Tile 128 can be determined in an arithmetic sequence along the bit line direction (from left to right). For example, as Figure 17A As shown, the activated physical location can be set at a distance of 1 from one side along the bit line direction.

[0139] Therefore, as Figure 17A As shown, the physical location activated by the sector read operation can be set in the central region of the decoder (LX / LY), and rarely in the region adjacent to the decoder (LX / LY). Therefore, the non-volatile memory device 100 in the example embodiment can perform read operations to balance the overall performance of the blocks. For example, if Figure 17A The sector read operation is associated with the first row address to the fourth row address and the first column address to the fourth column address. Using these addresses to select the word lines and bit lines of the first block can select word line 1, word line 3, word line 5 and word line 7 as well as bit line 1, bit line 3, bit line 5 and bit line 7. At the same time, using the same addresses to select the word lines and bit lines of the second block can select word line 3, word line 5, word line 7 and word line 9 as well as bit line 3, bit line 5, bit line 7 and bit line 9.

[0140] like Figure 17B As shown, when address scrambling is applied in the example embodiment, even when word line bridging occurs, the error correction circuit 160 (see...) Figure 1 It is also possible to correct errors caused by word line bridging using only 1 bit / 64 bytes. Therefore, the yield can be improved compared to using 4 bits / 64 bytes.

[0141] exist Figure 17A and Figure 17B In this example, sector data (e.g., data for a sector) can be configured by selecting four word lines within a single block. However, the example embodiments of sector data are not limited to this. The non-volatile memory device in the example embodiments can configure sector data by selecting a single word line within a single block. In one exemplary embodiment, when multiple word lines and bit lines represent sector data, they are selected such that they are spaced apart from each other.

[0142] Figure 18 This is a diagram illustrating an example embodiment of a non-volatile memory device 100 with address scrambling according to an inventive concept. (Refer to...) Figure 18 ,and Figure 17A and Figure 17BUnlike the example embodiment shown, in each of blocks Tile 1 to Tile 128, four memory cells connected to a single select word line (i.e., the selected word line) can be activated. Each block can perform a burst read operation from the four memory cells in response to a single row address. For example, if Figure 18 The sector read operation is associated with the first row address and the first to fourth column addresses. Using these addresses to select the word lines and bit lines of the first block can select word line 1 and bit lines 1 to 4. At the same time, using the same addresses to select the word lines and bit lines of the second block can select word line 3 and bit lines 1 to 4.

[0143] In the non-volatile memory device 100 of the example embodiment, the physical location of activation in the corresponding block can vary depending on the layer.

[0144] Figure 19 This is a diagram illustrating address scrambling in a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 19 The physical location activated in a block on the first level (1F) can be different from the physical location activated in a block on the second level (2F). For example, if Figure 19 The sector read operation is associated with the first row address, the second row address, the first column address, and the second column address. Using these addresses to select the word lines and bit lines of the first block can select word lines 1 and 5, and bit lines 1 and 5 of the first block of the first layer, and word lines 3 and 7, and bit lines 3 and 7 of the first block of the second layer. At the same time, using the same addresses to select the word lines and bit lines of the second block can select word lines 3 and 7, and bit lines 2 and 6 of the second block of the first layer, and word lines 5 and 9, and bit lines 4 and 8 of the second block of the second layer.

[0145] In addition, such as Figure 19 As shown, the non-volatile memory device in the example embodiment may have different read levels (RD Level 1 and RD Level 2) for each different layer. For example, the voltage applied to a given word line or bit line in one layer may be different from the voltage applied to a given word line or bit line in another layer.

[0146] The non-volatile memory device in the example embodiment can have different read levels for each different block group. For example, if blocks 1 to 4 are part of a first block group, and blocks 5 to 9 in the same layer are part of a second block group, then the read levels of the first block group can be different from those of the second block group.

[0147] Figure 20This is a diagram illustrating the read levels of each block group of a non-volatile memory device according to an example embodiment. (Refer to...) Figure 20 The first block group TG1 (the first block and the second block) has a first read level RD Level 1, the second block group TG2 (the third block) has a second read level RD Level 2, and the fourth block group TG4 (the 128th block) has a fourth read level RD Level 4.

[0148] The number of blocks included in a single block group is not limited to Figure 20 The example shown is illustrated. A variety of numbers of blocks can exist within a single block group. Furthermore, a corresponding read level can exist for each block group.

[0149] exist Figures 17A to 20 In this example, address scrambling is applied to each block. However, the example implementation of address scrambling is not limited to this. In the example implementation, address scrambling may be applied to each block group.

[0150] Figure 21A , Figure 21B and Figure 21C This is a diagram illustrating each of a block group that is address scrambled according to an exemplary embodiment of the inventive concept.

[0151] Reference Figure 21A Word line scrambling can be applied to the first block group TILE_GR1 and the second block group TILE_GR2. The first block group TILE_GR1 can be assigned word line numbers sequentially from the bottom edge to the top edge, while the second block group TILE_GR2 can be assigned word line numbers alternately along the top and bottom edges. Figure 21A The method of assigning word line numbers shown is one example. For example, a rightward cyclic offset of two word lines can be performed for the word lines of the first block group TILE_GR1 to produce the word lines of the second block group TILE_GR2. For example, if m = 6, and the bottommost word line of the first block group TILE_GR1 corresponds to the first word line WL1, then a rightward cyclic offset twice results in three, so the bottommost word line of the second block group TILE_GR2 corresponds to the third word line (WL6 / 2)WL3. In an alternative embodiment, the unit of offset may be different from two (e.g., the unit of offset may be 1, 3, 4, etc.).

[0152] Reference Figure 21BBit line scrambling can be applied to the first block group TILE_GR1 and the second block group TILE_GR2. The first block group TILE_GR1 can be assigned bit line numbers sequentially from left to right, while the second block group TILE_GR2 can be assigned bit line numbers alternately from the center to the right and left. For example, a rightward cyclic offset of two bit lines can be performed on the bit lines of the first block group TILE_GR1 to produce the bit lines of the second block group TILE_GR2. For example, if n = 6, and the leftmost bit line of the first block group TILE_GR1 corresponds to the first bit line BL1, then a rightward cyclic offset twice produces three; therefore, the leftmost bit line of the second block group TILE_GR2 corresponds to the third bit line (BL6 / 2)BL3. In an alternative embodiment, the unit of offset can be different from two (e.g., the unit of offset can be 1, 3, 4, etc.). Figure 21B The method of allocating bit lines in [the code] is a feasible example.

[0153] Reference Figure 21C Word line scrambling and bit line scrambling can be applied simultaneously to the first block group TILE_GR1 and the second block group TILE_GR2.

[0154] Figure 22 This is a flowchart illustrating a write operation of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept. (Refer to...) Figures 1 to 22 Write operations on the non-volatile memory device 100 can be performed as follows.

[0155] When a write command, address, and write data (sector data) are received, a sensing operation is performed on the data of the memory cell corresponding to the address in each block (S110). The write command, address, and write data (sector data) can be received from an external entity (such as a memory controller). For example, a read operation can be performed on the memory cell located at the address in the memory cell array 110 to obtain the sensed data. The write data is compared with the sensed data according to the sensing operation (S120). Thereafter, it is determined whether the write data is the same as the sensed data (S130).

[0156] When the written data is the same as the sensed data, determine whether the written data is set data (S140). When the written data is set data, perform a set operation on the memory cell (S145). When the written data is not set data, the write operation can be terminated.

[0157] When the written data differs from the sensed data, determine whether the written data is reset data (S160). When the written data is not reset data, perform a set operation on the memory cell (S150). When the written data is reset data, perform a reset operation on the memory cell (S170).

[0158] The write operation in the example embodiment can use a data comparison write method, and read skipping can be applied simultaneously based on the data being written.

[0159] Figure 23 This is a flowchart illustrating a write operation of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept. (Refer to...) Figures 1 to 23 Write operations on the non-volatile memory device 100 can be performed as follows.

[0160] The non-volatile memory device 100 receives a write command, sector data, and an address (S210). The write command, address, and write data (sector data) can be received from an external entity (such as a memory controller). It is determined whether the write data to be written to each block is a data "1" corresponding to a set state (S220). When the write data is "1", a set operation is performed on the memory cell corresponding to the address (S230).

[0161] When the data written is "0" corresponding to the reset state, a read operation is performed on the memory cell corresponding to the address (S240). The read operation can be performed using a read voltage that is at a level equal to or higher than the read voltage level used during normal mode.

[0162] Next, it is determined whether the data to be read is in a reset state (S250). If the data to be read is in a reset state, no write operation is performed. If the data to be read is not in a reset state, a reset operation is performed on the memory cell (S260).

[0163] Figure 24 This is a flowchart illustrating a read operation of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept. (Refer to...) Figures 1 to 24 The reading method of the non-volatile memory device 100 can be performed as follows.

[0164] When a read command and address are received from an external device (e.g., a memory controller), the non-volatile memory device determines the read level corresponding to the address scrambling (S310). For example, since address scrambling can be implemented in various ways depending on combinations of block location, word line location, and bit line location, the read level corresponding to the application of address scrambling can vary. A read operation is performed on each block using the determined read level (S320). An error correction operation is performed on the read data (S330). Thereafter, the data whose errors have been corrected (e.g., error-corrected data) can be output to the external device (S340).

[0165] In an example embodiment, during a read operation, data can be read from memory cells corresponding to word lines and bit lines selected at specific intervals in response to the same address in different blocks.

[0166] In an example embodiment, multiple layers formed on a substrate may be included, multiple blocks may be included in each of the multiple layers, and determining the read level may include determining the read level of the corresponding layer among the multiple layers based on the input address.

[0167] In the example embodiment, the read operation can perform a one-bit burst read operation for each block. The read operation of the four read commands for the address can be executed in each block to output four bits of data corresponding to the selected word line.

[0168] For example, it can be assumed that a read operation is performed in units of 64-bit cells in a memory comprising 3,000 bit lines and 5,000 word lines. A first read operation can output data from memory cells corresponding to (Tile1, W1, B1), (Tile2, W64, B32), (Tile3, W128, B64)...(Tile64, W4032, B2016) in response to a first address. A second read operation can output data from memory cells corresponding to (Tile1, W1, B2), (Tile2, W64, B33), (Tile3, W128, B65)...(Tile64, W4032, B2017) in response to a second address. Terms such as “W1”, “W64”, “W128”, and “W4032” can be abbreviations of the physical location number of a word line, and terms such as “B1”, “B64”, “B128”, and “B2017” can be abbreviations of the physical location number of a bit line.

[0169] In the read operation of the example embodiment, a four-bit burst read operation can be performed for each block. To output the four bits of data corresponding to the selected word line, a four-bit burst read operation for the row address can be performed in each block.

[0170] Figure 25 This is a diagram illustrating a storage device 1000 according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 25 The storage device 1000 includes at least one non-volatile memory device 1100 (one or more NVMs) and a memory controller 1200.

[0171] like Figures 1 to 24As shown, the non-volatile memory device 1100 can be implemented to equalize read levels by applying address scrambling during read operations. In an example embodiment, the non-volatile memory device 1100 can be optionally provided with an external high voltage.

[0172] The memory controller 1200 can be connected to the non-volatile memory device 1100. The memory controller 1200 can be a solid-state disk controller. The memory controller 1200 may include at least one processor 1210 (one or more CPUs), a buffer memory 1220, an error correction circuit 1230, a code memory 1240, a host interface (I / F) 1250, and a non-volatile memory interface (NVM I / F) 1260.

[0173] The processor 1210 can be implemented to control overall operations. The processor 1210 can be implemented by a central processing unit (CPU) or an application processor (AP).

[0174] The buffer memory 1220 can temporarily store data required for the operation of the memory controller 1200. Figure 25 The buffer memory 1220 shown may be located within the memory controller 1200, but the example embodiments of the buffer memory 1220 are not limited thereto. The buffer memory 1220 may be externally configured as separate intellectual property (IP).

[0175] Error correction circuit 1230 can calculate the error correction code value of the data to be written in a write operation, and can correct errors in the data read in a read operation based on the error correction code value, and can also correct errors in the data recovered from the non-volatile memory device 1100. Error correction circuit 1230 can use low-density parity-check (LDPC) codes, Bose-Chauhuri-Hochquenghem (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), and coded modulation (such as trellis-coded modulation (TCM) and block-coded modulation (BCM)) for error correction. Code memory 1240 can store code data required for the operation of memory controller 1200. Code memory 1240 can be implemented as a non-volatile memory device. Host interface 1250 provides functionality for interfacing with external devices. Non-volatile memory interface 1260 provides functionality for interfacing with non-volatile memory device 1100. Although not shown in the accompanying drawings, the memory controller 1200 may include wireless communication capabilities (e.g., Wi-Fi).

[0176] In an example embodiment, the memory controller 1200 can manage the read level of a block to be balanced.

[0177] The storage device 1000 in the example embodiment may include a non-volatile memory device 1100 or a memory controller 1200 that can equalize the read levels of read operations, thereby improving the reliability of the storage device.

[0178] Figure 26 This is a diagram illustrating a memory system 2000 where a specific read level is applied to a specific portion according to an example embodiment. The memory system 2000 includes a memory controller 2200 and a non-volatile memory device 2100. (Refer to...) Figure 26 The control logic 2170 of the non-volatile memory device 2100 can be implemented as follows: when the address ADD is received from the memory controller 2200, the location of the corresponding layer is identified according to the received address ADD, and the corresponding read level is compensated according to the identified layer. The control logic 2170 may include a layer identifier 2171 and a read voltage compensator 2172.

[0179] Different read voltages can be determined based on environmental information (lifespan, degree of degradation, temperature, error bits, etc.).

[0180] Figure 27 This is a diagram illustrating a memory system 2000a that can compensate for read voltage based on environmental information. (Refer to...) Figure 27 The memory system 2000a can collect environmental information and select an optimized read level based on the collected information. Environmental information may include cycle information, temperature information, and / or the number of error bits, relating to the number of one or more write operations and one or more read operations performed on the memory cell.

[0181] like Figure 27 As shown, temperature sensor 2180 can sense the temperature of non-volatile memory device 2100 and can transmit the sensing result to read voltage compensator 2172a. Read voltage compensator 2172a can determine an optimized read level based on the sensed temperature.

[0182] The non-volatile memory device in the example embodiment can be used in a server system.

[0183] Figure 28 This is a diagram illustrating a server system 3000 according to an example embodiment of the inventive concept. (Refer to...) Figure 28The server system 3000 may include at least one memory module 3100 (DIMM), at least one non-volatile memory module 3200 (NVDIMM), and at least one processor 3300. The at least one non-volatile memory module 3200 may include the non-volatile memory device described in the foregoing example embodiments. Therefore, the server system 3000 can improve data reliability through address scrambling, thereby managing data more effectively.

[0184] The example implementation can also be applied to various types of computing systems (e.g., central processing unit (CPU) platforms / graphics processing unit (GPU) platforms / neural processing unit (NPU) platforms).

[0185] Figure 29 This is a diagram illustrating a computing system 4000 according to an example embodiment of the inventive concept. (Refer to...) Figure 29 The computing system 4000 may include a central processing unit (CPU) 4110, a graphics processing unit (GPU) 4120, a neural processing unit (NPU) (not shown) and / or a dedicated processing unit connected to a system bus 4001; a memory device 4210 and / or a storage device 4220 connected to the system bus 4001; an input and output (I / O) device 4310, a modem 4320, a network device 4330 and / or a storage device 4340 connected to an expansion bus 4002. The GPU 4120 may be referred to as an accelerator. The expansion bus 4002 may be connected to the system bus 4001 via an expansion bus interface 4003.

[0186] In the example embodiment, CPU 4110 and GPU 4120 may each include an on-chip cache device 4111 and an on-chip cache device 4121, respectively. Although in Figure 29 It is not shown in the figure, but the NPU may include on-chip cache devices.

[0187] In the example embodiment, CPU 4110 may include off-chip cache 4112, and GPU 4120 may include off-chip cache 4122. Although in Figure 29 Although not shown, the NPU may include off-chip cache devices. In the example embodiment, off-chip cache devices 4112 and 4122, etc., can be connected to the CPU 4110, GPU 4120, and NPU via different buses.

[0188] In example embodiments, on-chip cache devices / off-chip cache devices may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and non-volatile memory devices (such as NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0189] In the example embodiment, main memories 4114 and 4124 can be connected to CPU 4110 and GPU 4120 via corresponding memory controllers 4113 and 4123. Although in Figure 29 Not shown, but additional main memory can be connected to the NPU via a corresponding memory controller. In an example embodiment, memories 4116 and 4126 can be connected to the CPU 4110 and GPU 4120 via bridges 4115 and 4125. In this case, bridges 4115 and 4125 may include memory controllers for controlling the corresponding memories 4116 and 4126. In an example embodiment, each of bridges 4115 and 4125 can be implemented as a network device, wireless network device, switch, bus, cloud, or optical channel. Although in Figure 29 It is not shown in the diagram, but the memory can be connected to the NPU via a corresponding bridge.

[0190] In an example embodiment, main memory 4124 may include GPU memory. GPU memory can hold commands and data that can interact with the GPU. Commands and data can be copied from main memory or a storage device. GPU memory can store image data and can have a bandwidth greater than that of main memory. GPU memory can decouple its clock from the CPU. The GPU can read and process image data from GPU memory and can write image data back to GPU memory. GPU memory can be configured to accelerate graphics processing.

[0191] In an example embodiment, additional memory, including NPU memory, may be present. The NPU memory can hold commands and data that can interact with the NPU. Commands and data can be copied from main memory or a storage device. The NPU memory can hold weight data used for the neural network. The NPU memory can have a bandwidth greater than that of the main memory. The NPU memory can decouple the clock from the CPU. The NPU can read weight data from and update the weight data from the NPU memory, and can write weight data back to the NPU memory. The NPU memory can be configured to accelerate machine learning (such as neural network training and inference).

[0192] In the example embodiment, each of main memories 4114 and 4124, memories 4116 and 4126, and additional main memories and memories connected to the NPU can be implemented as referenced. Figures 1 to 24 The memory chip described in the foregoing example embodiments is an executable application with address scrambling read operations.

[0193] In an example embodiment, the main memory may include volatile memory (such as DRAM, SRAM, etc.) and non-volatile memory (such as NAND flash memory, PRAM, RRAM, etc.). The main memory may have lower latency and capacity than the secondary storage devices 4220 and 4340.

[0194] CPU 4110, GPU 4120, or NPU can access secondary storage devices 4220 and 4340 via system bus 4001. Storage device 4210 can be controlled by memory controller 4211. Memory controller 4211 can be connected to system bus 4001. Storage device 4220 can be controlled by memory controller 4221. Memory controller 4221 can be connected to system bus 4001. Storage device 4340 can be controlled by memory controller 4341. Memory controller 4341 can be connected to expansion bus 4002.

[0195] Storage device 4220 can be implemented to store data. Storage controller 4221 can be implemented to read data from storage device 4220 and transfer the read data to a host. Storage controller 4221 can be implemented to store the transferred data in storage device 4220 in response to a request from the host. Each of storage device 4220 and storage controller 4221 may include a buffer configured to store metadata, a read cache to store frequently accessed data, or a storage cache to improve write efficiency. For example, a write cache device can receive and process a specific number of write requests. Furthermore, storage device 4220 may include volatile memory (such as DRAM and SRAM) and non-volatile memory (such as hard disk drive (HDD), NVRAM, SSD, SCM, and new memory).

[0196] The memory device 100 in the example embodiment can be applied to an automotive system.

[0197] Figure 30 This is a diagram illustrating an electronic system 5000 for a vehicle according to an example embodiment of the inventive concept. (Refer to...) Figure 30The electronic system 5000 may include an electronic control unit (ECU) 5100, a memory device 5200, at least one dynamic range sensor (DVS) 5300, a display 5400, and a communication processor 5500.

[0198] ECU 5100 can be implemented to control overall operation. ECU 5100 can process image data received from DVS 5300. ECU 5100 may include a neural processing unit (NPU). The NPU can compare the images received from DVS 5300 with a learned model and can quickly drive optimized images for driving.

[0199] Memory device 5200 can be implemented to store learning models related to the operation of the NPU. Memory device 5200 can include volatile memory devices or non-volatile memory devices. For example, memory device 5200 can be implemented using DRAM or PRAM. Memory device 5200 can also be implemented as described in reference... Figures 1 to 24 The address scrambling described in the foregoing example embodiments is used to perform the read operation. Because address scrambling (or read scrambling) is applied, the memory device 5200 can improve data reliability.

[0200] The DVS 5300 can be implemented to sense the external environment of a vehicle. The DVS 5300 can output an event signal in response to changes in relative light intensity. The DVS 5300 may include a pixel array and an address event processor; the pixel array includes multiple DVS pixels.

[0201] The display 5400 can be implemented to display images processed by the ECU 5100 or transmitted by the communication processor 5500.

[0202] The communication processor 5500 can be implemented to transmit processed images to an external device (e.g., an external vehicle) or to receive images from an external vehicle. Therefore, the communication processor can be implemented to communicate with the external device in a wired or wireless manner.

[0203] The example embodiments can be applied to mobile devices.

[0204] Figure 31 This is a diagram illustrating a mobile device 6000 according to an exemplary embodiment of the inventive concept. (Refer to...) Figure 31The mobile device 6000 may include an application processor (AP) 6100, at least one DRAM / PRAM 6200, at least one storage device 6300, at least one sensor 6400, a display device 6500, an audio device 6600, a network processor 6700, and at least one input and output (I / O) device 6800. For example, the mobile device 6000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0205] Application processor 6100 can be implemented to control the overall operation of mobile device 6000. Application processor 6100 can execute applications providing internet browsers, games, videos, etc. In example embodiments, application processor 6100 may include single-core or multi-core processors. For example, application processor 6100 may include multi-core processors (such as dual-core, quad-core, and hexa-core). In example embodiments, application processor 6100 may also include cache memory disposed internally or externally to application processor 6100. Application processor 6100 may also include a controller (CNTL) 6110, a neural processing unit (NPU) 6120, and an interface (IF) 6130. In example embodiments, NPU 6120 may be optionally included.

[0206] In an example embodiment, the application processor 6100 may be implemented as a system-on-chip (SoC). The kernel of the operating system driving the SoC may include a device driver for controlling the I / O scheduler and storage device 6300. The device driver may control the access performance of the storage device 6300, or control the CPU mode, DVFS level, etc. of the SoC by referring to the number of synchronization queues managed in the I / O scheduler.

[0207] The DRAM / PRAM 6200 can be connected to the controller 6110. The DRAM / PRAM 6200 can store data required for the operation of the application processor 6100. For example, the DRAM / PRAM 6200 can temporarily store the operating system (OS) and application data, or it can be used as execution space for various software codes. Furthermore, the DRAM / PRAM 6200 can be connected to the NPU 6120. The DRAM / PRAM 6200 can include executable functions as described in the reference... Figures 1 to 24 The aforementioned example embodiments describe a non-volatile memory device with address scrambling read operations.

[0208] Furthermore, the DRAM / PRAM 6200 can store data related to artificial intelligence computing. The DRAM / PRAM 6200 can have a latency and bandwidth (BW) faster than I / O devices or flash memory. The DRAM / PRAM 6200 can be initialized when the mobile device is powered on. When the OS and application data can be loaded, the DRAM / PRAM 6200 can be used as temporary storage space for application data or as execution space for various software codes. The mobile device can perform multitasking operations to simultaneously load various applications; the switching and execution speed between applications can be used as performance metrics for the mobile device.

[0209] Storage device 6300 can be connected to interface 6130. In an example embodiment, interface 6130 can operate via a communication protocol such as DDR, DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), Non-Volatile Memory High Speed ​​(NVMe), Peripheral Component Interconnect High Speed ​​(PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), Fibre Channel, and Fibre Channel over Ethernet (FCoE). In an example embodiment, a storage device 6300 can be included and embedded in mobile device 6000. In another example embodiment, one of the storage devices 6300 can be included in mobile device 6000 and can be attached to and detached from mobile device 6000.

[0210] Storage device 6300 can be implemented to store user data. For example, storage device 6300 can store data collected from sensor 6400, or it can store network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. For example, storage device 6300 may include solid-state drives (SSDs), embedded multimedia cards (eMMC), etc.

[0211] In an example embodiment, the storage device 6300 may be implemented as a separate chip in the application processor 6100, or it may be implemented together with the application processor 6100 in a single package.

[0212] In the example embodiment, the storage device 6300 can be mounted using various forms of packaging. For example, the storage device 6300 can be mounted using packages such as: package on package (PoP), ball grid array (BAG), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stacked package (WSP), etc.

[0213] Sensor 6400 can be implemented to sense the external environment of mobile device 6000. In one example embodiment, sensor 6400 may include an image sensor for sensing images. In this case, sensor 6400 can transmit the generated image information to application processor 6100. In another example embodiment, sensor 6400 may include a biosensor for sensing biometric information. For example, sensor 6400 can sense fingerprints, iris patterns, vascular patterns, heart rate, blood glucose, etc., and can generate sensing data corresponding to the sensed information. However, sensor 6400 is not limited to image sensors or biosensors. Sensor 6400 in the example embodiments may include sensors such as brightness sensors, acoustic sensors, accelerometers, etc.

[0214] The display device 6500 can be implemented to output data. For example, the display device 6500 can output image data sensed by the sensor 6400, or it can output data calculated by the application processor 6100.

[0215] The audio device 6600 can be implemented to output voice data or sense external voice.

[0216] The network processor 6700 can be implemented to connect and communicate with external devices via wired or wireless communication methods.

[0217] The input and output device 6800 can be implemented to input data to or output data from the mobile device 6000. The input and output device 6800 may include devices that provide digital input and output functions (such as Universal Serial Bus (USB) or storage devices, digital cameras, SD cards, touch screens, DVDs, modems, network adapters, etc.).

[0218] The example implementation can be applied to a data server system.

[0219] Figure 32 This is a diagram illustrating a data server system 7000 according to an example embodiment of the inventive concept. (Refer to...) Figure 32 The data server system 7000 includes a first server 7100 (application server), a second server 7200 (storage server), a memory device 7310, and at least one storage device 7320.

[0220] Each of the first server 7100 and the second server 7200 may include at least one processor and memory. In an example embodiment, each of the first server 7100 and the second server 7200 may be implemented as a memory-processor pair. In another example embodiment, the first server 7100 and the second server 7200 may include different numbers of processors and memory depending on their intended use.

[0221] In an example embodiment, the first server 7100 and the second server 7200 can communicate via the first network 7010. In one example embodiment, each of the first server 7100 and the second server 7200 can access the storage device 7310 via the first network 7010 and / or the second network 7020. In one example embodiment, each of the first server 7100 and the second server 7200 can access the storage device 7320 directly or indirectly via the first network 7010 and / or the second network 7020.

[0222] In one example embodiment, the interface I / F of storage device 7320 may include SATA, SAS, PCIe, DIMM, high-bandwidth memory (HBM), hybrid memory cube (HMC), or NVDIMM. In one example embodiment, the second network 7020 may have connections from a direct-attached storage (DAS) method, a network-attached storage (NAS) method, or a storage area network (SAN) method.

[0223] In one example embodiment, each of the memory device 7310 and the storage device 7320 can transmit device information to the server 7200 via command or independently. In one example embodiment, the memory device 7310 may include a reference... Figures 1 to 24 The application described in the foregoing example embodiments has an address scrambling memory chip.

[0224] The Data Server System 7000 can perform big data artificial intelligence calculations. Big data can include voice, images, video, or weight / training data.

[0225] According to reference Figures 1 to 32 In the foregoing example embodiments described, address scrambling can be applied to a single memory chip. However, the example embodiments of address scrambling are not limited to this. Address scrambling can also be applied to multiple memory chips.

[0226] According to the foregoing example embodiments, by using a non-volatile memory device, a storage device having the non-volatile memory device, and a reading method for the non-volatile memory device, the read level of a block can be equalized by applying address scrambling. Therefore, read margin can be improved.

[0227] Furthermore, by using a non-volatile memory device, a storage device having the non-volatile memory device, and a method for reading the non-volatile memory device, the yield can be improved by using address scrambling to disperse erroneous bits caused by generated word line / bit line bridging.

[0228] Although exemplary embodiments of the inventive concept have been shown and described above, it will be clear to those skilled in the art that various modifications can be made without departing from the spirit and scope of the inventive concept.

Claims

1. A non-volatile memory device, comprising: A memory cell array includes multiple memory banks, each memory bank having multiple blocks, and each of the multiple blocks having multiple resistive memory cells connected to multiple bit lines and multiple word lines; A word line driver is configured to select one of the plurality of word lines in response to an input address; A bit line driver is configured to select one of the plurality of bit lines in response to the input address; The read circuit is configured to read codewords from the memory cell array during a read operation; An error correction circuit is configured to use error correction codes included in the codeword to correct at least one error in the read data during the read operation; The data input and output circuitry is configured to output the read or corrected data to an external device. as well as The control logic is configured to control the word line driver, the bit line driver, the read circuit, the error correction circuit, and the data input and output circuit during the read operation. In the read operation, the control logic performs address scrambling on the input address and provides the scrambled input address to the read circuit to access the plurality of blocks. The plurality of blocks include blocks corresponding to a first block group scrambled with the application address and blocks corresponding to a second block group scrambled with the application address, and the read level of the first block group is different from the read level of the second block group.

2. The non-volatile memory device according to claim 1, wherein, The address scrambling is achieved by combining different blocks, different word lines, and / or different bit lines.

3. The non-volatile memory device according to claim 1, wherein, In at least two of the plurality of blocks, memory cells located at different corresponding physical locations in the at least two blocks are activated in response to an address in a scrambled input address.

4. The non-volatile memory device according to claim 1, in, Among the plurality of blocks, the first block includes a first group of word lines corresponding to word line numbers sequentially assigned in one direction. Among the plurality of blocks, the second block includes a second word line group and a remaining word line group. The second word line group corresponds to word line numbers sequentially assigned from a predetermined position along the one direction, and the remaining word line group corresponds to remaining word line numbers sequentially assigned along the one direction.

5. The non-volatile memory device according to claim 4, wherein, The predetermined position is the central portion of the plurality of word lines located in the second block.

6. The non-volatile memory device according to claim 1, in, Of the plurality of blocks, the first block includes a first bit group corresponding to bit line numbers sequentially assigned in one direction, and Among the plurality of blocks, the second block includes a second bit line group and a remaining bit line group. The second bit line group corresponds to the bit line numbers sequentially assigned from a predetermined position along the one direction, and the remaining bit line group corresponds to the remaining bit line numbers sequentially assigned along the one direction.

7. The non-volatile memory device according to claim 1, in, Among the plurality of blocks, the first block includes a first bit group corresponding to bit line numbers sequentially assigned along a first direction, and Among the plurality of blocks, the second block includes a second bit line group corresponding to bit line numbers sequentially assigned along a second direction, which is opposite to the first direction.

8. The non-volatile memory device according to any one of claims 1 to 7, further comprising: Multiple layers are formed along a direction perpendicular to the substrate. Wherein, at least one of the plurality of layers includes at least one of the plurality of memory banks.

9. The non-volatile memory device according to any one of claims 1 to 7, in, The error correction circuit receives write data during the write operation, generates an error correction code corresponding to the received write data, and generates a codeword corresponding to the write data and the generated error correction code. The non-volatile memory device further includes a write circuit configured to store generated codewords in multiple blocks of the memory cell array by applying scrambled addresses.

10. The non-volatile memory device according to claim 8, wherein, At least one of the plurality of layers includes at least one of the word line driver, the bit line driver, the error correction circuit, the read circuit, the write circuit, the data input and output circuit, and the control logic.

11. A non-volatile memory device, comprising: First block; as well as Second block, Each of the first block and the second block includes: A first resistive memory cell is formed on the first layer and connected between the first word line and the bit line; A second resistive memory cell is formed on a second layer disposed on the first layer and connected between the second word line and the bit line; and Peripheral circuitry is disposed below the first layer, wherein each of the first word line, the second word line, and the bit line is connected to the peripheral circuitry via at least one via. In this process, each of the first and second blocks is driven by address scrambling during the read operation. The first block and the second block are classified into multiple block groups, and the read operation is performed in each of the multiple block groups according to different read levels.

12. The non-volatile memory device according to claim 11, wherein, The first resistive memory cell and the second resistive memory cell are arranged symmetrically about the bit line.

13. The non-volatile memory device according to claim 11, in, The peripheral circuit includes: The first line decoder is configured to be connected to the first word line on the substrate; and The second line decoder is configured to be connected to the second word line on the substrate.

14. The non-volatile memory device according to claim 11, wherein, In the read operation, one bit of data is output from each of the first block and the second block in response to the address.

15. The non-volatile memory device according to claim 11, wherein, The read operation is performed in response to multiple addresses in each of the first block and the second block to read codewords.

16. The non-volatile memory device according to claim 11, wherein, In the read operation, at least two bits of data are output from each of the first block and the second block in response to the address.

17. A method for reading a non-volatile memory device, the method comprising: The read level is determined based on the address entered during the read operation; The read operation is performed using a defined read level to read data; Perform error correction on the read data to generate corrected data; as well as Output the error-corrected data to an external device. The read operation is performed by scrambling the address based on combinations of different blocks, word lines, and / or bit lines. The non-volatile memory device includes multiple layers formed on a substrate, each layer including multiple blocks, and the step of determining the read level includes determining the read level of the corresponding layer among the multiple layers based on the input address.

18. The reading method according to claim 17, wherein, The read operation retrieves data from a memory cell of the non-volatile memory device, the memory cell corresponding to a word line and bit line selected at constant intervals in response to the same address in the different blocks.

Images