Structure and method for source-down vertical semiconductor devices

Abstract

The invention is entitled "Structure and method for source-down vertical semiconductor device." A semiconductor device includes a region of semiconductor material having a first side and a second side opposite the first side. An active device structure is adjacent the first side, the active device structure including a source region and a gate electrode. A first gate conductor is electrically connected to the gate electrode at the first side, a drain region is at the second side, a second gate conductor is at the second side, and a through-semiconductor via extends from the first side toward the side and electrically connects the first gate electrode to the second gate electrode. A source electrode is electrically connected to the source region at the first side, and a drain electrode is electrically connected to the drain region at the second side. The through-semiconductor via is electrically isolated from the source region and the drain region. The structure provides gate / drain-up with a source-down configuration.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 993,389, filed on March 23, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to semiconductor device structures and methods of forming semiconductor devices. Background Art

[0004] Existing semiconductor devices and methods for forming semiconductor devices are inadequate, resulting in, for example, excessive cost, inadequate integration, reduced reliability, relatively low performance, or excessive size. Further limitations and shortcomings of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 shows a cross-sectional view of a semiconductor device according to the present specification;

[0006] Figure 2 Shown according to the instructions Figure 1 A partial cross-sectional view of a portion of a semiconductor device;

[0007] Figure 3 A portion of a semiconductor wafer according to the present specification is shown at a stage of manufacture. Figure 1 a top plan view of a semiconductor device;

[0008] Figure 4 Shown along the Figure 3 a cross-sectional view of the semiconductor device taken along reference line 4A-4B;

[0009] Figure 5 Shows a manufacturing stage according to this specification Figure 1 a top plan view of a semiconductor device;

[0010] Figure 6 Shown along the Figure 5 a cross-sectional view of the semiconductor device taken along reference line 6A-6B;

[0011] Figure 7 shows a cross-sectional view of a semiconductor device at a manufacturing stage according to the specification;

[0012] Figure 8 shows a cross-sectional view of a semiconductor device at a manufacturing stage according to the specification;

[0013] Figure 9 Shows the manufacturing stage according to this specification Figure 1 a bottom plan view of a semiconductor device;

[0014] Figure 10 Shown along Figure 9 a cross-sectional view of the semiconductor device taken along reference line 10A-10B;

[0015] Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 illustrates cross-sectional views of semiconductor devices at various other stages of fabrication according to the present description;

[0016] Figure 16 is a top perspective view of a semiconductor device incorporated into an exemplary subassembly according to the present description;

[0017] Figure 17 shows a cross-sectional view of a semiconductor device at a stage of fabrication according to the present description;

[0018] Figure 18 shows a cross-sectional view of a semiconductor device at a stage of fabrication according to the present description; and

[0019] Figure 19 A plan view of an annular isolated through-semiconductor via for use with a semiconductor device according to the present description is shown.

[0020] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0021] For simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale, and the same reference numerals in different figures indicate the same elements. In addition, for simplicity of description, descriptions and details of well-known steps and elements are omitted.

[0022] For clarity of the drawings, certain regions of the device structure, such as doped regions or dielectric regions, may be illustrated as having substantially straight edges and precise angled corners. However, those skilled in the art understand that due to diffusion and activation of dopants or formation of layers, the edges of such regions may not be straight lines and the corners may not have precise angles.

[0023] Although semiconductor devices are explained herein as having certain N-type conductivity regions and certain P-type conductivity regions, a person of ordinary skill in the art understands that the conductivity types may be reversed, and any necessary polarity reversal of voltage, reversal of transistor type and / or current direction, etc., may also be contemplated in accordance with this specification.

[0024] In addition, the terms used herein are for the purpose of describing particular examples only and are not intended to limit the present disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0025] As used herein, a “current-carrying electrode” refers to an element within a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and a “control electrode” refers to an element within a device that controls the current flowing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0026] Additionally, the term "major surface," when used in conjunction with a semiconductor region, wafer, or substrate, refers to the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The major surface may have topographical features that vary along the x, y, and z directions.

[0027] When used in this specification, the terms "comprises," "comprising," "having," and / or "containing" are open-ended terms that specify the presence of stated features, numbers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, and / or groups thereof.

[0028] The term "or" refers to any one or more items in a list connected by "or." For example, "x or y" refers to any element in the three-element group {(x), (y), (x,y)}. Another example is "x, y, or z" refers to any element in the seven-element group {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0029] Although the terms "first," "second," etc. may be used herein to describe various components, elements, regions, layers, and / or sections, these components, elements, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one component, element, region, layer, and / or section from another component, element, region, layer, and / or section. Thus, for example, a first component, first element, first region, first layer, and / or first section discussed below may be referred to as a second component, second element, second region, second layer, and / or second section without departing from the teachings of the present invention.

[0030] Those skilled in the art will understand that the phrases "during," "at the same time," and "when" used herein with respect to circuit operation do not necessarily imply that an action occurs immediately after an initiating action. Rather, they imply that there may be some small but reasonable delay, such as propagation delay, between the initial action and the resulting reaction. Furthermore, the term "at the same time" means that an action occurs for at least a period of time while the initiating action continues.

[0031] The words "about," "approximately," or "substantially" are used to indicate that an element's value is expected to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that prevent a value or position from being exactly the stated value or position.

[0032] As used herein, unless otherwise indicated, the phrases "on" or "over" include orientations, placements, or relationships wherein the specified elements may be in direct or indirect physical contact.

[0033] As used herein, unless otherwise indicated, the phrase "overlying" encompasses an orientation, placement, or relationship in which the specified elements can be at least partially or completely coincident or aligned in the same plane or in different planes.

[0034] It will also be understood that the examples illustrated and described below, as appropriate, may have examples lacking any elements not expressly disclosed herein and / or may be practiced without any elements not expressly disclosed herein. DETAILED DESCRIPTION

[0035] A typical vertical FET semiconductor device is configured with a source electrode and a gate electrode on the top side of the device, and a drain electrode on the reverse or lower side of the device. Certain applications, such as die stacking, may require a vertical device with a drain electrode and a gate electrode on the upwardly oriented side and a source electrode on the downwardly oriented side, where the orientation is referenced by packaging requirements. Therefore, there is a need for a low-cost method to achieve this using standard FET manufacturing and FET design. Previous source-down devices have had several problems, including, for example, limited scalability due to processing requirements within the trench structure; unique device structures and architectures that require lengthy pull-out process development activities; and difficulty matching the electrical performance of source-up devices.

[0036] In general, the present specification and examples relate to semiconductor device structures and methods of preparing drain / gate-up semiconductor structures having a source-down configuration using as few as two (2) additional masking steps compared to standard source-up semiconductor devices. The structures and methods can use a typical source-up fabrication flow with modifications to provide the structure as described herein to achieve the source-down configuration. The active device structure can include a trench gate device with or without a shield electrode. The structure can be a power semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) structure, an insulated gate bipolar transistor (IGBT) structure, a MOS gated thyristor, or other power semiconductor device. Furthermore, the structures and methods are relevant to other electronic devices where electrodes are on opposing surfaces of a workpiece and electrical connectivity between the opposing surfaces would be beneficial.

[0037] In some examples, a first gate conductor on one side of a semiconductor wafer or semiconductor material region is electrically connected to a second gate conductor on a second side using one or more conductive structures (such as through-semiconductor or through-silicon via structures) that extend at least partially through the semiconductor wafer. The through-semiconductor vias can have various shapes. The through-semiconductor vias can be filled with one or more conductive materials, including doped polysilicon, metals, resistive materials, capacitive materials, other materials described below, or other materials known to those of ordinary skill in the art (including combinations of such materials).

[0038] In some examples, a through-semiconductor via extends through one or more regions of a semiconductor wafer (such as one or more epitaxial regions) into the underlying substrate. In other examples, the through-semiconductor via may be used in conjunction with or replaced by a heavily doped portion of the epitaxial region. In some examples, the reverse side of the semiconductor wafer may be recessed to connect to the through-semiconductor via. In other examples, the reverse side may be heavily doped at least proximal to the through-semiconductor via to improve ohmic contact. In other examples, the through-semiconductor via may be lined with a dielectric material such as an oxide, nitride, or oxynitride. In some examples, the through-semiconductor via may extend completely through the semiconductor wafer. The through-semiconductor via structure may be isolated using an isolation structure (such as an isolation trench positioned around the through-semiconductor via structure). In addition, the isolation structure may be placed in a scribe grid location to provide improved reliability. The isolation trench may have a variable width and design, depending on the device requirements. The isolation trench may be partially filled with at least one dielectric layer (such as an oxide, nitride, or oxynitride). The isolation trenches may also be partially filled with dielectric and partially filled with other materials such as polysilicon.

[0039] Some of the through-semiconductor via structures and / or isolation trenches may function as electrical devices (such as capacitor structures) by adding additional dielectric and second conductive plates to the through-semiconductor via structures.

[0040] In some examples, the source electrode can be one or more capping conductive layers electrically isolated from the first gate conductor by one or more dielectric layers or structures. The source electrode can primarily comprise copper, in some cases with a capping layer to protect the copper from oxidation and / or provide a solder-compatible layer.

[0041] In some examples, the semiconductor wafer is thinned from the reverse side to expose the isolation trench. In some examples, the isolation trench can serve as a stop structure or endpoint detection structure for the thinning process. During the thinning process, the semiconductor wafer can be attached to a carrier substrate (such as a carrier tape or a wafer carrier). For the thinning process, grinding, lapping, or etching can be used.

[0042] In some examples, the thinning step can expose a through-semiconductor via extending from the first gate conductor on the opposite side of the semiconductor wafer. In other examples, additional etching or other removal steps are used to expose the through-semiconductor via. In other examples, the through-semiconductor via terminates within the semiconductor wafer, which can have a high dopant concentration to provide a low-resistance and ohmic contact between the through-semiconductor via and a conductive layer used to provide a reverse-side gate contact. In other examples, a recess can be etched from the reverse side to expose the through-semiconductor via.

[0043] In some examples, after the removal step, a dielectric can be deposited on the reverse side of the semiconductor wafer. Isolation trenches or through-semiconductor vias can be used as backside alignment marks, eliminating the need for front-to-back alignment capabilities. Openings can be provided in the dielectric above the through-semiconductor via and other portions of the second side. In some cases, the patterned dielectric can be used as a mask to etch the exposed semiconductor material and, in some cases, expose the semiconductor via. Another opening provides a drain region, while the opening above the through-semiconductor via provides a gate region.

[0044] In some examples, a plasma etching step is used to etch through the semiconductor wafer from the reverse side toward the top side, wherein the active device structures are positioned close to the top side to expose the dielectric structure and / or source electrode. During the plasma etching step, the semiconductor wafer can be attached to a carrier substrate (such as a carrier tape).

[0045] When the semiconductor wafer is attached to a carrier substrate, another singulation process, such as sawing or laser processing, may be used to cut through the source electrodes on the top side.The carrier substrate may be the same as the carrier substrate used for the plasma etching step.

[0046] More specifically, in an example, a method of forming a semiconductor device includes providing a semiconductor wafer having a first side and a second side opposite the first side, and semiconductor devices, wherein each semiconductor device includes a gate pad and an active device structure, the active device structure including a source region and a gate electrode adjacent to the first side and a drain region and a gate region at the second side, and wherein the gate pad is electrically connected to the gate electrode. The method includes providing a conductive structure that extends at least partially through the semiconductor wafer from the gate pad toward the second side to electrically connect the gate pad to the gate region at the second side. The method includes providing a first electrode on the first side that is electrically coupled to the source region and electrically isolated from the gate pad. The method includes providing a second electrode on the second side that is adjacent to the gate region and electrically connected to the conductive structure. The method includes providing a third electrode on the second side that is electrically connected to the drain region. In some examples, the conductive structure includes a through-semiconductor via.

[0047] In an example, a semiconductor device includes a region of semiconductor material having a first side and a second side opposite the first side. An active device structure is adjacent to the first side, the active device structure including a first current-carrying region. A first control electrode is electrically connected to the active device structure at the first side, a second current-carrying region is at the second side, and a second control electrode is at the second side. A conductive structure is located in the semiconductor material region and electrically connects the first control electrode to the second control electrode. The first current-carrying electrode is electrically connected to the first current-carrying region at the first side, and the second current-carrying electrode is electrically connected to the second current-carrying region at the second side. The conductive structure is electrically isolated from the first and second current-carrying regions.

[0048] In an example, a semiconductor device includes a region of semiconductor material having a first side and a second side opposite the first side. An active device structure is adjacent to the first side, the active device structure including a source region and a gate electrode. A first gate conductor is at the first side and electrically connected to the gate electrode, a drain region is at the second side, a second gate conductor is at the second side, and a through-semiconductor via extends from the first side toward the second side and electrically connects the first gate electrode to the second gate electrode. A source electrode is electrically connected to the source region at the first side, and a drain electrode is electrically connected to the drain region at the second side. The through-semiconductor via is electrically isolated from the source region and the drain region. The structure provides a gate / drain-up configuration with a source-down configuration.

[0049] Other examples are included in the present disclosure. Such examples can be found in the drawings, in the claims, and / or in the description of the present disclosure.

[0050] Figure 1A cross-sectional view of an electronic device 10, semiconductor device 10, or semiconductor structure 10 according to the present description having a source-down configuration is shown. In this example, the electronic device 10 is shown as a MOSFET device, but it is understood that other types of devices may be used, including but not limited to insulated gate bipolar transistor (IGBT) devices, MOS gated thyristors, sensor devices, and other types of electronic devices. Figure 2 An enlarged partial cross-sectional view of a portion of the semiconductor device 10 including the trench gate structure 13 is shown.

[0051] In some examples, semiconductor device 10 includes a workpiece, such as a semiconductor material region 11 having a major surface 18 as a first side and an opposing major surface 19 as a second side. Semiconductor material region 11 may include a bulk semiconductor substrate 12, such as an N-type conductive silicon substrate having a resistivity in a range of about 0.001 ohm-cm to about 0.005 ohm-cm. By way of example, substrate 12 may be doped with phosphorus, arsenic, or antimony.

[0052] In some examples, the semiconductor material region 11 also includes a semiconductor layer 14, a doped region 14, a doped layer 14, or multiple doped layers 14, which can be formed in, on, or covering the substrate 12. In one example, when the substrate 12 is a layer of N-type conductivity, the doped layer 14 can be an N-type conductivity region or layer and can be formed using epitaxial growth techniques, ion implantation and diffusion techniques, or other techniques known to those skilled in the art. In one example, the semiconductor layer 14 includes the main surface 18 of the semiconductor material region 11. It should be understood that the semiconductor material region 11, the semiconductor substrate 12, and / or the semiconductor layer 14 can include other types of materials, including but not limited to heterojunction semiconductor materials, and that the semiconductor substrate 12 and the semiconductor layer 14 can each include different materials. Such materials can include SiGe, SiGeC, SiC, GaN, AlGaN, and other similar materials known to those skilled in the art.

[0053] In some examples, semiconductor layer 14 has a dopant concentration that is less than the dopant concentration of substrate 12. The dopant concentration and thickness of semiconductor layer 14 may be determined based on, for example, the desired breakdown voltage (BV) of semiconductor device 10. DSS ) rating and layout design. In some examples, semiconductor layer 14 may have a dopant profile that varies across its depth from major surface 18 inward. Such variations may include linear and nonlinear profiles across the thickness of semiconductor layer 14 perpendicular to major surface 18.

[0054] like Figure 2As shown, trench gate structures 13 extend inwardly from main surface 18 into semiconductor material region 11. In some examples, trench gate structures 13 each include a shield electrode 21 in a lower portion of each trench, a shield dielectric layer 264 separating shield electrode 21 from semiconductor layer 14, a gate dielectric layer 26 above the upper surface of each trench, a control electrode 28 (such as gate electrode 28 disposed adjacent to gate dielectric layer 26), and a dielectric fill structure 27 electrically isolating shield electrode 21 from gate electrode 28. In some examples, shield electrode 21 and gate electrode 28 include doped polycrystalline semiconductor material, such as doped polysilicon. In some examples, polysilicon is doped with N-type conductive dopants, such as phosphorus or arsenic. In other examples, polysilicon may be doped with P-type conductive dopants, such as boron.

[0055] In some examples, the semiconductor device 10 further includes a body region 31, which in this example includes a P-type conductive doped region and is disposed adjacent to the trench gate structure 13. Figure 2 . The body region 31 may be a plurality of separate doped regions, or may be a continuous, interconnected doped region. The body region 31 has a dopant concentration suitable for forming an inversion layer that serves as a conductive channel or channel region for the semiconductor device 10 when an appropriate bias voltage is applied to the gate electrode 28. The body region 31 may extend from the major surface 18 to a depth of, for example, about 0.7 microns to about 1.0 microns. Doping techniques, such as ion implantation and annealing techniques, may be used to form the body region 31. The body region 31 may also be referred to as a base region or a PHV region.

[0056] In some examples, a first current-carrying region 33 (such as a source region 33) can be formed within, in, or overlying body region 31 and can extend from major surface 18 to a depth of, for example, about 0.2 micrometers to about 0.4 micrometers. In some examples, source region 33 can be an N-type conductive doped region and can be formed using, for example, a phosphorus or arsenic dopant source. Source region 33 can also be referred to as a current-conducting region or a current-carrying region. Source region 33 can be formed using ion implantation and annealing techniques.

[0057] In some examples, an ILD structure 41 may be formed to cover the major surface 18. In one embodiment, the ILD structure 41 includes one or more dielectric or insulating materials or layers. In some examples, the ILD structure 41 may include an oxide, a nitride, an oxynitride, or a combination thereof, and may include a dopant (such as an N-type dopant, a P-type dopant, or a combination thereof) or fluorine. The ILD structure 41 may be planarized to provide a more uniform surface topography, which improves manufacturability.

[0058] In some examples, conductive region 43 may be formed within contact opening 422 or contact via 422 and configured to provide electrical contact to source region 33 and body region 31 through contact region 36. In some examples, conductive region 43 may be a conductive plug or plug structure. In some examples, conductive region 43 may include a conductive barrier structure or liner and a conductive fill material. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those of ordinary skill in the art. In other examples, the barrier structure may also include a metal silicide structure. In some examples, the conductive fill material includes tungsten. In some examples, conductive region 43 may be planarized to provide a more uniform surface morphology. In some examples, source pad 33A is above ILD structure 41 and electrically connected to source region 33 through conductive region 43. In this example, trench gate structure 13 (including, for example, shield electrode 21, shield dielectric 264, dielectric fill structure 27, gate electrode 28, and gate dielectric 26), body region 31, source region 33, and contact region 36 may be referred to as an active device structure 130 provided adjacent to major surface 18 of semiconductor device 10. To avoid complicating the drawings, individual elements of active device structure 130 may not be labeled in other drawings described later.

[0059] According to this specification and return reference Figure 1 , the semiconductor device 10 also includes a first control electrode 28A, a first gate control electrode 28A, or a gate liner 28A above the main surface 18. The gate liner 28A is electrically connected to each gate electrode 28 in the trench gate structure 13 and is electrically coupled to the gate region 196 at the second main surface 10 through a conductive structure 28B. In some examples, the conductive structure 28B includes a through-semiconductor via 28B, such as a through-silicon via (TSV) 28B, which extends from the gate liner 28A inwardly into the semiconductor material region 11 toward the gate region 196. The through-semiconductor via 28B includes a trench 28C or a recess 23C that can be etched into the semiconductor region 11 using a photomask and etching technique.

[0060] Through-hole semiconductor via 28B may be filled with one or more filler materials 28D. Filler material 28D may include a single material or multiple materials, which may be in the form of a single layer, multiple layers, a single film, or multiple films. Filler material 28D may be conductive, resistive, an insulator, or a combination thereof (e.g., when forming a capacitor within the trench). In some examples, filler material 28D may be a conductive material and include doped amorphous silicon, doped polysilicon, a metal (elemental metal, as opposed to a molecular compound), an alloy, a metal nitride, a metal-semiconductor compound, a metal-semiconductor-nitride compound, or other materials known to those of ordinary skill in the art. The composition of the conductive material may depend on when the conductive material is formed. Filler material 28D may include an adhesion film, a barrier film, and a conductive filler film. In one specific embodiment, the adhesion film includes a refractory metal, the barrier film includes a refractory metal nitride, and the conductive filler film includes a refractory metal different from the adhesion film. In another specific example, the filler material includes doped polysilicon. In some examples, filler material 28D includes titanium / titanium nitride / tungsten.

[0061] In some examples, the through-semiconductor via 28B extends completely through the semiconductor material region 11 to directly contact the gate electrode 12B above the major surface 19. In some examples, the through-semiconductor via 28B can be lined with an optional dielectric material 28E, such as an oxide, nitride, oxynitride, other materials known to those of ordinary skill in the art, or combinations thereof. It should be understood that the opposite end of the fill material 28D is devoid of the dielectric material 28E to allow electrical communication between the gate liner 28A and the gate electrode 12B. In some examples, the source pad 33A and the gate liner 28A include a barrier material (such as titanium / titanium nitride) and another conductive material (such as an aluminum-copper alloy).

[0062] In some examples, the semiconductor device 10 further includes an isolation structure 63 configured to electrically isolate the through-semiconductor via 28B from other regions of the semiconductor device 10 (e.g., from the source region 33 and the drain region 198). In some examples, the isolation structure 63 electrically isolates the gate region 196 from the drain region 198 at the main surface 19. In some examples, the isolation structure 63 may include isolation portions 63A and 63B on opposite sides of the through-semiconductor via 28B in a cross-sectional view. In some examples, the isolation portions 63A and 63B are part of the same continuous isolation structure, which may continuously (i.e., without interruption in the structure) surround the through-semiconductor via 28B. In some examples, an isolation portion 63C may be placed in the scribe grid region 100A of the semiconductor device 10 to provide additional isolation for the active region of the semiconductor device 10. The isolation portion 63C is an example of an edge isolation structure disposed at the outer edge of the semiconductor material region 11.

[0063] In some examples, isolation portions 63A, 63B, and 63C may be trench structures filled with a dielectric. In some examples, oxide, nitride, or oxynitride may be used. In other examples, the trenches may be filled with other materials, such as undoped polysilicon in combination with a dielectric. In some examples, isolation portions 63A, 63B, and 63C may include voids. In some examples, isolation portions 63A, 63B, and 63C may extend completely from the first side through semiconductor material region 11 to the second side, such as Figure 1 63. Other types of isolation structures may be used in place of or in combination with isolation structure 63. In some examples, one or more of through-semiconductor via 28B or isolation structure 63 may be configured as a capacitor structure by filling the corresponding trenches with a pair of conductive plates separated by a dielectric.

[0064] In some examples, dielectric 67 is above gate pad 28A and source pad 33A. An opening is provided in dielectric 67 to expose a portion of source pad 33A. Dielectric 67 is configured to isolate gate pad 28A from source pad 33A. Dielectric 67 may include one or more layers of dielectrics, such as oxides, doped oxides, nitrides, oxynitrides, organic materials, or other insulating materials known to those of ordinary skill in the art (including combinations of such materials). Conductor 44A is disposed above dielectric 67 and within the opening to provide an electrical connection to source pad 33A. In this example, conductor 44A provides a source electrode for semiconductor device 10 and may include a conductive material, such as copper, a copper alloy, or other conductive materials known to those of ordinary skill in the art. In some examples, conductor 44A also includes a capping layer to protect the copper from oxidation or provide solder compatibility. In some examples, the capping layer includes tin / silver.

[0065] Semiconductor device 10 also includes a current-carrying electrode 12A and a control electrode 12B. In this vertical MOSFET example, the current-carrying electrode can be a drain electrode, and in this example, the control electrode is a gate electrode. In some examples, gate pad 28A can be referred to as a first gate conductor, and gate electrode 12B can be referred to as a second gate conductor. Electrodes 12A and 12B are disposed on a major surface 19 of the semiconductor device, which is the reverse side of semiconductor device 10. Electrodes 12A and 12B can comprise one or more metals or other conductive materials. In some examples, electrodes 12A and 12B can comprise a barrier material and copper-nickel-gold or other wire-bondable and / or solderable material. In some examples, a dielectric 68 is first provided on major surface 19, and then patterned to provide contact openings for electrodes 12A and 12B. In some examples, dielectric 68 comprises an oxide, a nitride, or an organic insulating material. In some examples, portions of semiconductor material region 11 can be recessed (indicated by dashed line 19A) prior to forming electrodes 12A and 12B. In some examples, recess 19A below electrode 12B may expose portions of one or more through-semiconductor vias 28B, such that electrode 12B directly contacts fill material 28D.

[0066] Figure 3 A top plan view of a semiconductor device 10 at a stage of fabrication in accordance with the present description is shown as part of a semiconductor wafer 100 . Figure 4 Shown along Figure 3 4A-4B is a cross-sectional view of the semiconductor device 10 .

[0067] At this stage of manufacturing, active device structures 130 have been provided adjacent to the main surface 18 of the semiconductor material region 11 that is part of the semiconductor wafer 100. According to the present description, the manufacturing flow up to this stage advantageously follows a typical source-up flow, which helps to reduce manufacturing costs. That is, by utilizing a portion of a pre-existing process, manufacturing costs can be reduced. In some examples, a patterning step (such as a first patterning step) is used to provide openings in a mask for forming isolation structures 63 in the semiconductor wafer 100. The openings in the mask expose portions of the semiconductor material region 11 at the main surface 18. Next, a trench etch can be used to form deep trenches for the isolation structures 63. For example, the trenches for the isolation structures 63 can be etched using a plasma etching technique with a fluorocarbon chemistry or a fluorinated chemistry (e.g., SF6 / O2) or other chemistry, or a removal technique known to those of ordinary skill in the art.

[0068] In some examples, the trenches for the isolation structures 63 extend from the main surface 18 to a depth in the semiconductor material region 11 that can be achieved using a removal process that removes a portion of the main surface 191 and reduces the thickness of the semiconductor wafer 100 to a desired thickness. In some examples, the trenches for the isolation structures 63 extend to within about 25 microns to about 75 microns of the main surface 191. After etching the trenches for the isolation structures 63, a dielectric fill material is provided in the trenches, and the dielectric fill material can include oxides, nitrides, oxynitrides, other materials known to those of ordinary skill in the art, or combinations thereof. The dielectric fill material can be planarized using a chemical mechanical planarization (CMP) process or an etch-back process. Depending on the rated voltage of the semiconductor device 10, the width or number of the trenches can, for example, increase with increasing voltage.

[0069] Figure 4 Optional isolation portions 63C are shown positioned within the scribe grid region 100A of the semiconductor wafer 100. Isolation portions 63C can provide additional electrical isolation and / or protection against contamination at the edges of the semiconductor device 10. Isolation portions 63A and 63B define the periphery or perimeter of the gate liner 28A and through-semiconductor via 28B, which can be disposed within the perimeter. After forming the isolation structure 63, an ILD structure 41 can be disposed over the major surface 18. In some examples, the ILD structure 41 comprises an oxide, which can be doped or undoped, a nitride, an oxynitride, or a combination thereof, and can be formed using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or other deposition processes known to those skilled in the art. The ILD structure 41 can be planarized using, for example, CMP techniques. In other examples, the ILD structure 41 is provided before the isolation structure 63 and can serve as a hard mask to facilitate the formation of the isolation structure 63.

[0070] Figure 5 A top plan view of semiconductor device 10 is shown after further processing in accordance with the present description. Figure 6 Shown along Figure 5 6A-6B . In some examples, a patterning step (such as a second patterning step) is used to provide an opening in the ILD structure 41 for forming a through-semiconductor via 28B extending from the main surface 18 of the semiconductor material region 11 into the semiconductor material region 11. Photomasking and etching techniques can be used to provide an opening in the ILD 41 for a trench 28C for the through-semiconductor via 28B. The shape and amount of the trench 28C for the through-semiconductor via 28B can vary and can include, for example, a plurality of trenches 28C or a single trench or recess 28C.

[0071] The trench 28C for the through-semiconductor via 28B can be formed using a plasma etching technique with a fluorocarbon chemistry or a fluorinated chemistry (e.g., SF6 / O2) or other chemistry, or a removal technique known to those skilled in the art. The depth of the trench 28C for the through-semiconductor via 28B can be the same as the depth of the trench for the isolation structure 63, or the depth can be shallower than the depth of the trench for the isolation structure 63 (which is less than the depth of the trench for the isolation structure 63). Figure 6 28D). In some examples, an optional dielectric material 28E may be used to line the sidewall surfaces of trench 28C. In some examples, dielectric material 28E includes an oxide, a nitride, an oxynitride, or other materials known to those of ordinary skill in the art, or a combination thereof. A portion of dielectric material 28E along the bottom surface of trench 28C is removed to expose semiconductor material region 11 at the bottom surface of trench 28C. In some examples, removal of dielectric material 28E at the bottom surface may occur before providing fill material 28D, or if, for example, the bottom surface of dielectric material 28E is exposed at major surface 19, the dielectric material may be removed in a later removal.

[0072] Next, a filler material 28D is disposed within trench 28C (and, if dielectric 28E is used, on the dielectric), and can be planarized using, for example, CMP techniques. Filler material 28D can include materials as previously described. Filler material 28D can be formed using CVD, PECVD, atomic layer deposition (ALD), sputtering, evaporation, or other processing techniques known to those of ordinary skill in the art. In other examples, a pair of through-semiconductor vias 28B can be configured as trench capacitors, wherein the pair of through-semiconductor vias are configured as opposing conductive plates separated by a dielectric. In some examples, the dielectric can include an oxide, a low-k dielectric, a high-k dielectric, or other materials known to those of ordinary skill in the art. When filler material 28D comprises a semiconductor material, the semiconductor material can be doped in situ or ex situ, or both in situ and ex situ.

[0073] In some examples, after forming through-semiconductor via 28B, contact via 422 may be formed in ILD structure 41, and conductive region 43 may be provided for electrical contact with source region 33 and contact region 36, as shown in FIG. Figure 2 shown.

[0074] Figure 7A cross-sectional view of semiconductor device 10 after additional processing is shown. In some examples, a conductive material is deposited over major surface 18. In some examples, the conductive material includes one or more metallic materials, polycrystalline semiconductor materials, silicide materials, other materials known to those skilled in the art, or combinations thereof. In some examples, the conductive layer comprises titanium / titanium nitride / aluminum copper and has a thickness in a range from about 5,000 angstroms to about 10,000 angstroms. The conductive layer can be formed using, for example, evaporation, sputtering, CVD, or other deposition processes known to those skilled in the art.

[0075] After forming the conductive layer, a patterning step is used to pattern the conductive layer to provide a source pad 33A and a gate pad 28A (also referred to as a first gate conductor). Photomasking and etching techniques may be used to provide the source pad 33A and the gate pad 28A. The source pad 33A is electrically connected to the conductive region 43, and the gate liner 28A is electrically connected to the gate electrode 28 and the through-semiconductor via 28B. In some examples, a dielectric 67 is then provided over the gate liner 28A and the source pad 33A, electrically isolating the gate liner 28A from the source pad 33A. The dielectric 67 may include one or more layers of dielectrics, such as oxides, doped oxides, nitrides, oxynitrides, organic materials, or other insulating materials known to those skilled in the art (including combinations of such materials). The dielectric 67 may be formed using CVD, LPCVD, PECVD, ALD, spin coating, or other deposition processes known to those skilled in the art. Next, an opening 67A is provided in the dielectric 67 to expose a portion of the source pad 33A. Photomasking and etching techniques may be used to provide opening 67A.

[0076] Figure 8 A cross-sectional view of semiconductor device 10 after further processing is shown. In some examples, conductor 44A is disposed above dielectric 67 and within opening 67A to provide an electrical connection to source pad 33A. Conductor 44A is an example of a source electrode. In some examples, conductor 44A comprises copper, a copper alloy, or other conductive material known to those skilled in the art. In some examples, conductor 44A also includes a capping layer to protect the copper from oxidation or provide solder compatibility. In some examples, the capping layer comprises tin / silver. Conductor 44A can be formed using evaporation, sputtering, CVD, plating, or other deposition processes known to those skilled in the art. In some examples, conductor 44A can have a thickness in a range of approximately 10,000 angstroms to approximately 20,000 angstroms. It should be understood that conductor 44A can include other structures, such as a prefabricated interconnect structure attached to source pad 33A using, for example, a conductive adhesive or solder.

[0077] Figure 9shows a bottom plan view of semiconductor device 10 after further processing, and Figure 10 Shown along Figure 9 10B. In some examples, semiconductor wafer 100 is attached to carrier 91, such as a carrier tape or a carrier substrate. Carrier 91 is configured to support semiconductor wafer 100 during, for example, a wafer thinning process. In this example, semiconductor wafer 100 is positioned with active device structures 130 proximate carrier 91 such that major surface 18 is interposed between carrier 91 and major surfaces 191 / 19. In some examples, one or more removal processes are used to remove the active device structures 130 from major surface 191 ( Figure 8 ) removes portions of semiconductor wafer 100. In some examples, a grinding or lapping process may be used, followed by an etching process to remove any damage from the grinding or lapping process. This provides a major surface 19, and in some examples, isolation structures 63 are exposed from major surface 19, as shown. Figure 10 . One feature of isolation structure 63 is that it can be used for endpoint detection during the removal process, which provides improved thickness control for semiconductor wafer 100. In other words, isolation structure 63 can serve as a stop structure for the removal process. In some examples, this step defines gate region 196 and drain region 198 at major surface 19 of semiconductor material region 11.

[0078] Figure 11 A cross-sectional view of semiconductor device 10 after additional processing is shown. In an example, dielectric 68 is disposed over major surface 19 and then patterned to provide opening 68A that exposes a portion of major surface 19. In some examples, dielectric 68 comprises an oxide deposited using LPCVD, PECVD, or other low-temperature deposition techniques known to those skilled in the art. In some examples, dielectric 68 can be formed using a spin-on process or a lamination process. In other examples, dielectric 68 can be provided using a printing process, such as a 3D printing process. In other examples, dielectric 68 comprises an organic material, such as polyimide.

[0079] Dielectric 68 is used to isolate electrodes 12A and 12B to be formed later. Photomasking and etching techniques can be used to provide opening 68A. When using photomasking and etching techniques to form opening 68A, the isolation structure exposed from major surface 19 advantageously provides an alignment structure for a photomask alignment device to effectively align opening 68A in a desired position.

[0080] In some examples, dielectric 68 laterally overlaps isolation structure 63 along major surface 19 , as shown in FIG. Figure 116A. In some examples, a recessed etch or other removal process can be used to provide a recess 19A extending inward from the main surface 19 within the opening 68A. The recess 19A can be formed using an etching process in which the dielectric 68 acts as a hard mask. In some examples, a fluorine-based chemistry can be used to form the recess 19A extending inward from the main surface 19. In some examples, the recess 19A aligned with the semiconductor via 28B can extend to a depth sufficient to expose the end of the semiconductor via 28B near the main surface 19. If it is necessary to remove the dielectric material 28E at the head end of the trench 28C, the removal can occur after forming the recess 19A. In other examples, dopants can be added to the semiconductor material region 11 through the opening 68A to increase the dopant concentration for a more ohmic contact. In some examples, ion implantation and laser annealing techniques can be used to provide the additional dopants.

[0081] Figure 12 A cross-sectional view of semiconductor device 10 after further processing is shown. In some examples, conductors are disposed above major surface 19 and dielectric 68 and within opening 68A, and are then patterned to provide electrodes 12A and 12B. The conductors may comprise one or more metals or other conductive materials. In some examples, the conductors include a barrier material and copper-nickel-gold or other solderable material that can be wire bonded. In some examples, evaporation, sputtering, plating, or processes may be used to provide the conductors, and a photomask and etch may be used to provide electrodes 12A and 12B. In other examples, electrodes 12A and 12B may be provided first, and dielectric 68 may be provided after electrodes 12A and 12B to provide electrical isolation between electrodes 12A and 12B. In this vertical MOSFET example, electrode 12A is configured as a drain electrode, and electrode 12B is configured as a gate electrode.

[0082] Figure 13 A cross-sectional view of semiconductor device 10 after further processing is shown. In some examples, carrier 91 is removed and another carrier 92 is attached to semiconductor wafer 100 near major surface 18. In some examples, carrier 92 comprises a material that is selective to the plasma dicing process. In some examples, carrier 92 comprises carrier tape. In other examples, carrier 91 remains in place for subsequent processing. In some examples, a plasma etching step is used to remove a portion of semiconductor material region 11 from major surface 19 in the openings between isolation portions 63C corresponding to scribe grid region 100A. More specifically, a plasma etching process is used to remove a portion of semiconductor material region 11 from scribe grid region 100A.

[0083] In some examples, semiconductor wafer 100 can be etched through openings between isolation portions 63C to form or define singulation lines or openings 100B extending from major surface 19 to major surface 18 of semiconductor material region 11. The etching process can be performed using a chemistry (generally represented by arrows 96) that selectively etches semiconductor material (e.g., silicon) of the semiconductor material region at a much higher rate than dielectrics and / or metals. In some examples, semiconductor wafer 100 can be etched using a process commonly referred to as a Bosch etch process. In some examples, semiconductor wafer 100 can be etched using a Bosch etch process in a deep reactive ion etching system. In some examples, the width of singulation lines 100B can be from about forty (40) microns to about sixty (60) microns. Such a width is sufficient to ensure that the opening forming singulation lines 100B can be formed completely through semiconductor material region 11 and accommodate the width of a laser singulation device or a cutting or saw blade used in a subsequent singulation step according to the present specification.

[0084] Due to the etch selectivity, the singulation line 100B stops near or on the ILD structure 41, as shown in FIG. Figure 13 . In some examples, ILD structure 41 and / or dielectric 67 can serve as a stop layer for the plasma etch singulation process. In some examples, singulation lines 100B can be formed using a Bosch etch process in about five to about thirty minutes. In this step, singulation lines 100B can be defined on three (3) sides by dielectric material. In other examples, isolation portion 63C is not used.

[0085] Figure 14 A cross-sectional view of semiconductor device 10 after further processing is shown. In some examples, a singulation process is used to form singulation lines 100C through conductor 44A. In some examples, a laser singulation process may be used. In other examples, a cutting or sawing process may be used with a cutting blade having a width narrower than singulation lines 100B to provide singulation lines 100C. In some examples, a protective layer is first provided over electrodes 12A and 12B, but in some examples, singulation lines 100B are left exposed for the laser or dicing process. In some examples, a water-soluble protective layer may be used, such as DISCO Corporation, Tokyo, Japan. brand protective material. In some examples, singulation line 100C has a width between about 15 microns and about 30 microns. More specifically, in some examples, singulation line 100C is narrower than singulation line 100B to provide a shoulder region 100D that can provide a protective structure to prevent solder from subsequent subassemblies connected to electrodes 12A and 12B from shorting to source pad 28A along outer edge 11A of semiconductor device 10. Shoulder region 100D may also be referred to as a step region or solder dam region. In other words, utilizing the multi-step singulation process of the present description, conductor 44A extends to overlap outer edge 11A of semiconductor material region 11 and provides shoulder region 100D defined by singulation lines 100B and 100C.

[0086] In some examples, the post-plasma etch singulation process may include using a reverse cutting process to minimize any possibility of burn defects. In some examples, singulation line 100C extends substantially completely through conductor 44A, meaning that a small amount of material may remain. Figure 15 As shown, this small amount of material may separate when semiconductor device 10 is removed from carrier 92. In other examples, singulation line 100C extends completely through conductor 44A and partially into carrier 92, as shown. Figure 14 shown.

[0087] In some examples, pick and place equipment can be used to Figure 15 Individual semiconductor components 10 are shown removed from carrier 92 and placed into a next-level assembly. Figure 16 A top perspective view of a semiconductor device 10 as part of an example subassembly 200 according to the present specification is shown. In some examples, the subassembly 200 includes a package substrate 201, such as a lead frame 201. In some examples, the lead frame 201 includes a conductive material (such as a copper alloy), which may also be plated with another conductive material. In some examples, the lead frame 201 includes a die pad 202 and leads 203A and 203B.

[0088] According to the present specification, conductor 44A of semiconductor device 10 (which is a source electrode in this configuration) is attached to die pad 202 using an attachment material (such as a conductive organic material or solder). Electrode 12A (which is a drain electrode in this configuration) is electrically connected to lead 203A using a connection structure 206 (such as a conductive clip). Electrode 12B, which is electrically connected to through-semiconductor via 28B and gate pad 28A, is electrically connected to lead 203B using a connection structure 207 (such as a wire bond or ribbon bond). In this example, electrode 12B is a gate electrode electrically connected to lead 203B.

[0089] In some examples, subassembly 200 can be packaged with a package body (not shown), wherein leads 203A and 203B and portions of die pad 202 are exposed for electrical connection to another level of assembly (such as a printed circuit board). According to the present specification, subassembly 200 is in a drain-and-gate-up configuration with a source-down configuration. In this vertical MOSFET example, lead 203A corresponds to the drain lead, lead 203B corresponds to the gate lead, and die pad 202 corresponds to the source lead.

[0090] Figure 17 A cross-sectional view of an electronic device 300, semiconductor device 300, or semiconductor structure 300 having a source-down configuration according to the present description is shown. In this example, semiconductor device 300 is a vertical MOSFET device, but it should be understood that other types of devices may be used, including but not limited to IGBT devices and MOS-gated thyristors. Semiconductor device 300 is similar to semiconductor device 10, and only certain differences will be described. In semiconductor device 300, isolation structure 63 surrounding through-semiconductor via 28B includes a wide isolation ring 630 surrounding through-semiconductor via 28B. In some examples, isolation ring 630 includes multiple isolation portions 630A, which may be individual rings, interdigitated structures, structures having different shapes, or other structures that provide electrical isolation between through-semiconductor via 28B and source region 33 and drain region 198. In other examples, multiple isolation portions 630A also include shapes and materials that reduce stress caused by the mismatch in thermal expansion coefficients between isolation ring 630 and semiconductor material region 11. Isolation portion 630A may include similar materials as described for isolation portions 63A, 63B, and 63C. In semiconductor device 300, optional dielectric material 28E may not be included.

[0091] Figure 18A cross-sectional view of an electronic device 400, semiconductor device 400, or semiconductor structure 400 having a source-down configuration according to the present description is shown. In this example, semiconductor device 400 is a vertical MOSFET device, but it should be understood that other types of devices may be used, including but not limited to IGBT devices and MOS-gated thyristors. Semiconductor device 400 is similar to semiconductor device 10, and only certain differences will be described. In semiconductor device 400, a through-semiconductor structure is used, which includes an annular isolated through-semiconductor via structure 280. The annular isolated through-semiconductor via structure may include a recessed region etched through semiconductor material region 11, which leaves portion 110A of semiconductor material region 11 in place in a desired pattern. In some examples, dielectric 128 is provided along the sidewalls of portion 110a, and then filler material 28D is provided adjacent to dielectric 128. Filler material 28D may be similar to the other filler materials described above. Dielectric 128 can be an oxide, a nitride, an oxynitride, an organic dielectric, other dielectric materials known to those skilled in the art, or a combination thereof. In some examples, the recess including portion 110A therein can be formed using a photomask and etching technique, such as using a fluorine-based chemistry. Figure 18 As shown, dielectric 128 may extend across the entire vertical extent of semiconductor material region 11 between major surface 18 and major surface 19 .

[0092] In some examples, outermost portion 111 of portion 110A is in the shape of a ring surrounding the rest of the structure, and dielectric 128 provided along the ring isolates filler material 28D from other portions of semiconductor device 400. Figure 18 As shown, the filling material 28D is exposed near the main surface 18 and the main surface 19 to provide electrical connectivity between the gate pad 28A (e.g., the first gate conductor) and the electrode 12B (e.g., the second gate conductor). Other portions of the portion 110A within the ring may have different shapes, such as a columnar, S-shaped, L-shaped, interdigitated, or other shapes. In some examples, the annular isolated through-semiconductor via structure 280 extends completely through the semiconductor material region 11 to directly connect to the electrode 12B at the main surface 19 of the semiconductor device 400. In other examples, the annular isolated through-semiconductor via structure 280 may terminate within the semiconductor material region 11. In such examples, a recess 19A may be used. In other examples, the dopant content within the substrate 12 adjacent to the main surface 19 may be high enough to provide an ohmic contact.

[0093] Figure 19is a plan view of an annular isolated through-semiconductor via structure 280 suitable for use in a semiconductor device 400. The annular isolated through-semiconductor via structure 280 is another example of a conductive structure. The plan view may be at the first major surface 18 or the second major surface 19 of the semiconductor material region 11. The annular isolated through-semiconductor via structure 280 includes an outer ring portion 281 at the outermost portion 111 defining the periphery of the structure 280. The outer ring portion 281 also includes a dielectric ring 128A or a dielectric material ring 128A along the sidewall surface of the semiconductor material region 11. The periphery including the dielectric ring 128A laterally surrounds the filling material 28D. In this example, the portion 110A includes an S-shape in the plan view. As previously described, the portion 110A includes a portion of the semiconductor material region 11. The dielectric 128 is adjacent to the sidewall of the outer ring portion 281 and along the sidewall portion 110A as the dielectric ring 128A, and the filling material 28D is adjacent to the dielectric 128 / 128A. As Figure 18 As shown, fill material 28D is exposed proximate major surfaces 18 and 19 to provide electrical communication between gate liner 28A (eg, first gate conductor) and electrode 12B (eg, second gate conductor).

[0094] From all of the foregoing, one of ordinary skill in the art can determine that, in an example, the removing step can include sawing. In another example, the removing step can include laser processing. In yet another example, the plasma etching step and the removing step can form a solder dam structure for each semiconductor device. In another example, providing the conductive structure includes providing a through-semiconductor via comprising a conductive filler material. In another example, providing the conductive structure includes providing a conductive structure that partially extends through the semiconductor wafer such that a portion of the semiconductor wafer is interposed between the proximal end of the conductive structure and the second electrode. In yet another example, providing the conductive structure includes providing a conductive structure comprising a dielectric ring surrounding the conductive filler material.

[0095] From all of the foregoing, one of ordinary skill in the art can determine that, in an example, the structure can also include an edge isolation structure including a dielectric at an edge of the semiconductor material region, the edge isolation structure extending from the first side to the second side.

[0096] From all of the foregoing, one of ordinary skill in the art can determine that, in an example, a semiconductor device includes: a semiconductor material region having a first side and a second side opposite the first side; an active device structure adjacent to the first side, the active device structure including a source region and a gate electrode; a first gate conductor electrically connected to the gate electrode at the first side; a drain region at the second side; a second gate conductor at the second side; a through-semiconductor via extending from the first side toward the second side and electrically coupling the first gate electrode to the second gate electrode; a source electrode electrically connected to the source region at the first side; and a drain electrode electrically connected to the drain region at the second side, wherein the through-semiconductor via is electrically isolated from the source region and the drain region.

[0097] In another example, an isolation structure may be located in the semiconductor material region to electrically isolate the through-semiconductor via from the source region and the drain region. In another example, the isolation structure surrounds the through-semiconductor via. In yet another example, the isolation structure extends from the first side to the second side. In another example, the through-semiconductor via may include a conductive fill material separated from the semiconductor material region by a dielectric.

[0098] In view of all of the above, it is apparent that a novel structure and method are disclosed. Among other features, a semiconductor wafer is provided having a first side and a second side. An active device structure is located at the first side. A first gate conductor is located at the first side, and a second gate conductor is located at the second side. A conductive structure electrically connects the first gate conductor to the second gate conductor. In some examples, an isolation structure electrically isolates the conductive structure from other portions of the semiconductor wafer. In some examples, the isolation structure provides an endpoint detection structure when a portion of the semiconductor wafer is removed. In some examples, the isolation structure provides an alignment structure for forming an opening in the dielectric at the second side. In some examples, the method uses a plasma etch process to singulate the semiconductor wafer and uses a second singulation process to separate the source conductors at the first side. In some examples, the multi-step singulation process provides a solder dam structure that reduces the likelihood of electrical short failures. The structure and method provide a source-down configuration that can utilize a typical source-up process flow and adds as few as two (2) photomask steps to provide the source-down configuration. In some examples, the source-down configuration enables a stacked die structure and eliminates the need for additional gate leads in the package.

[0099] Although the subject matter of the present invention has been described in conjunction with specific preferred embodiments, the foregoing drawings and their description are intended only to depict typical examples of the subject matter of the present invention and, therefore, should not be considered to limit the scope of the subject matter of the present invention. Obviously, many alternatives and variations will be apparent to those skilled in the art. For example, the filler material may include a combination of materials that can be deposited individually and annealed to deposit multiple layers and annealed to form a composite structure. Various deposition techniques may be used for the filler material, including sputtering, plating, evaporation, CVD, LPCVD, PECVD, MOCVD, ALD, and other deposition techniques known to those of ordinary skill in the art.

[0100] As reflected in the claims below, aspects of the invention may have fewer than all of the features of a single example disclosed above. The claims set forth below are hereby expressly incorporated into the Detailed Description, with each claim standing on its own as a separate example of the invention. Furthermore, while some examples described herein include some features included in other examples, but not others, those skilled in the art will understand that combinations of features from different examples are intended to fall within the scope of the invention and to form distinct examples.

Claims

1. A method for forming a semiconductor device, the method comprising: providing a semiconductor wafer including a first side, a second side opposite the first side, and semiconductor devices, wherein each semiconductor device includes a gate pad and an active device structure, the active device structure including a source region and a gate electrode adjacent to the first side and a drain region and a gate region at the second side, and wherein the gate pad is electrically coupled to the gate electrode; providing a conductive structure extending from the gate pad at least partially through the semiconductor wafer toward the second side to electrically couple the gate pad to the gate region at the second side; providing a first electrode over the first side, the first electrode electrically coupled to the source region and electrically isolated from the gate pad; providing a second electrode at the second side, the second electrode being adjacent to the gate region and electrically coupled to the conductive structure; as well as A third electrode is provided, the third electrode being electrically coupled to the drain region at the second side.

2. The method according to claim 1, further comprising: plasma etching the semiconductor wafer from the second side toward the first side to provide a first singulation line while the semiconductor wafer is attached to a carrier substrate; as well as A second singulation line is formed through the first singulation line to separate the first electrodes.

3. The method according to claim 2, wherein: The first singulation line is wider than the second singulation line.

4. The method according to claim 1, further comprising: providing an isolation structure, wherein the isolation structure electrically isolates the conductive structure from the source region and the drain region; providing a dielectric over the gate pad to electrically isolate the gate pad from the first electrode; as well as A portion of the second side is removed using the isolation structure for endpoint detection.

5. The method according to claim 1, wherein: Providing the conductive structure includes: providing the conductive structure extending completely through the semiconductor wafer; and The proximal end of the conductive structure directly contacts the third electrode.

6. A semiconductor device, comprising: a region of semiconductor material having a first side and a second side opposite the first side; an active device structure adjacent to the first side, the active device structure including a first current-carrying region; a first control electrode electrically connected to the active device structure at the first side; a second current-carrying region at the second side; a second control electrode at the second side; a conductive structure in the semiconductor material region, the conductive structure electrically coupling the first control electrode to the second control electrode; a first current-carrying electrode electrically connected to the first current-carrying region at the first side; and a second current-carrying electrode electrically connected to the second current-carrying region at the second side, wherein: The conductive structure is electrically isolated from the first current-carrying region and the second current-carrying region.

7. The semiconductor device according to claim 6, wherein: The conductive structure includes a through-semiconductor via having a conductive fill material; and The through-semiconductor via terminates within the semiconductor material region such that a portion of the semiconductor material region is interposed between a proximal end of the through-semiconductor via and the second control electrode.

8. The semiconductor device according to claim 6, wherein: The conductive structure includes a recessed area and a conductive filling material within the recessed area; and The conductive fill material contacts both the first control electrode and the second control electrode.

9. The semiconductor device according to claim 6, wherein: The conductive structure is electrically isolated from an isolation structure comprising a dielectric; The isolation structure surrounds the conductive structure; and The isolation structure extends from the first side to the second side.

10. The semiconductor device according to claim 6, further comprising: a dielectric having a first opening and a second opening at the second side, wherein: The second current-carrying electrode is electrically connected to the second current-carrying region through the first opening; and The second control electrode is electrically coupled to the conductive structure through the second opening.

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