Semiconductor substrate, semiconductor package including the same, and testing method thereof

Abstract

A semiconductor substrate, a semiconductor package including the same, and a test method thereof. A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit arranged on the upper surface. The semiconductor substrate may also include a test pad arranged on the upper surface or the lower surface. The semiconductor substrate may also include a trace configured to connect the bump pad unit and the test pad. The bump pad unit includes a main bump pad arranged on the upper surface, and a plurality of side bump pads arranged on the upper surface to be spaced apart from the main bump pad. The trace may connect the main bump pad and the plurality of side bump pads to the test pad in a one-to-one manner.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor substrate, a semiconductor package including the semiconductor substrate, and a testing method of the semiconductor substrate. Background Art

[0002] Typically, a semiconductor package is configured to include a semiconductor substrate having a printed circuit and a semiconductor chip mounted on the semiconductor substrate. The semiconductor chip formed by performing various semiconductor processes on a wafer is electrically connected to the semiconductor substrate through a connection device such as a bump or wiring. For example, a flip chip package as a type of semiconductor package includes a structure in which a semiconductor chip and a package substrate are opposite to each other and the semiconductor chip and the package substrate are connected through conductive bumps and pads. In this case, if the semiconductor chip and the package substrate are not electrically connected because the bumps and pads are not properly engaged, the semiconductor package may not operate normally. In order to identify such connection failures, various non-destructive testing means such as X-rays have been used. Summary of the invention

[0003] According to one aspect of the present disclosure, a semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include a test pad disposed on the upper surface or the lower surface. The semiconductor substrate may also include a trace configured to connect the bump pad unit and the test pad. The bump pad unit may include a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The trace may connect the main bump pad and the plurality of side bump pads to the test pad in a one-to-one manner.

[0004] A semiconductor package according to another aspect of the present disclosure may include: a semiconductor substrate including an upper surface and a lower surface; a bump pad unit including a main bump pad disposed on the upper surface and a plurality of side bump pads disposed on the upper surface and spaced apart from the main bump pad; a bump bonded to the bump pad unit; a test pad disposed on the upper surface or the lower surface; and a trace disposed in the semiconductor substrate to connect the main bump pad and the plurality of side bump pads to the test pad in a one-to-one manner. The test pad may be electrically connected to the main bump pad and the plurality of side bump pads, respectively, so that whether the main bump pad and the plurality of side bump pads are electrically connected is detected by a test signal input from the outside of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagram schematically illustrating an example of a configuration of a semiconductor substrate and a test apparatus for testing the semiconductor substrate according to an embodiment of the present disclosure.

[0006] Figure 2is an example Figure 1 A flow chart of a method for testing a semiconductor substrate is shown.

[0007] Figures 3 to 5 Is used for Figure 1 The semiconductor substrate and the test apparatus shown are diagrams that explain an example of the test method in more detail.

[0008] Figures 6 to 9 Is used for Figure 1 The semiconductor substrate and the testing device shown are diagrams illustrating another example of the testing method in more detail.

[0009] Fig.10 is a diagram schematically illustrating another example of the configuration of a semiconductor substrate and a test apparatus for testing the semiconductor substrate according to an embodiment of the present disclosure.

[0010] Figures 11 to 15 Is used for Fig.10 The semiconductor substrate and the test apparatus shown are diagrams that explain an example of the test method in more detail. DETAILED DESCRIPTION

[0011] The term used herein may correspond to the words selected considering their functions in the present embodiment, and the meaning of the term may be interpreted as different according to the ordinary technicians in the field of the embodiment. If the term is defined in detail, the term may be interpreted according to the definition. Unless otherwise defined, the term used herein (including technical terms and scientific terms) has the same meaning as the ordinary technicians in the field of the embodiment. It will be understood that although the terms "first" and "second", "top" and "bottom", "upper surface" and "lower surface", "left" and "right" etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish an element from another element, and are not used to only define the element itself or represent a specific order.

[0012] In this specification, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically connected or coupled and / or mechanically connected or coupled to another element, or may form a connection relationship or coupling relationship by other elements interposed therebetween. In addition, in this specification, when a part "includes (or has)" a certain component, this means that other components may be further "included" without excluding other components unless otherwise explicitly mentioned. In addition, when describing the embodiments disclosed herein, when it is determined that the detailed description of the relevant known technology may make the subject matter of the embodiments disclosed herein unclear, the detailed description is omitted.

[0013] Throughout this specification, the same reference numerals may refer to the same components. Although the same reference numerals or similar reference numerals are not mentioned or described in a particular figure, the reference numerals may be described based on other figures. In addition, even if there are components that are not shown with reference numerals in a particular figure, these components may be described based on other figures. In addition, the number, shape, size, and relative differences of the components included in the drawings of the present application are configured to facilitate understanding, are not intended to limit the embodiments, and may be implemented in various forms.

[0014] The semiconductor chip described in the present disclosure may include a shape in which a semiconductor substrate with an electronic circuit integrated therein is cut into a wafer shape. A semiconductor package may refer to a memory chip in which a memory integrated circuit such as a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) is integrated. In addition, a semiconductor chip may refer to an ASIC chip or a logic chip in which a logic circuit is integrated on a semiconductor substrate. According to the cutting shape, a semiconductor chip may be referred to as a semiconductor wafer.

[0015] Figure 1 is a diagram schematically illustrating an example of a configuration of a semiconductor wafer 100 and a test apparatus 500 for testing the semiconductor wafer 100 according to an embodiment of the present disclosure.

[0016] Reference Figure 1 , the semiconductor substrate 100 may include an upper surface 100S1 and a lower surface 100S2. The bump pad unit 200 configured to be bonded to the conductive structure may be disposed on the upper surface 100S1. The conductive structure may be Figure 1The bump 600 shown. Test pads 300a, 300b and 300c may be arranged to be spaced apart from each other on the upper surface 100S1 or the lower surface 100S2. Traces 400a, 400b and 400c may be arranged in the substrate 100 to connect the pads 210, 220 and 230 included in the bump pad unit 200 to the test pads 300a, 300b and 300c one-to-one. The test pads 300a, 300b and 300c may be electrically connected to the pads 210, 220 and 230 included in the bump pad unit 200, so that the main bump pad 210 and the plurality of side bump pads 220 and 230 are electrically connected to each other by a test signal applied from the outside of the semiconductor substrate 100. According to the present embodiment, the semiconductor package including the semiconductor substrate 100 , the bump pad unit 200 , the bumps 600 , the test pads 300 a , 300 b , and 300 c , and the traces 400 a , 400 b , and 400 c may be provided in various forms.

[0017] Reference Figure 1 , the bump pad unit 200 may include a main bump pad 210 disposed on the upper surface 100S1, and a plurality of side bump pads 220 and 230 disposed on the upper surface 100S1 and spaced apart from the main bump pad 210. The plurality of side bump pads 220 and 230 may include a first side bump pad 220 and a second side bump pad 230. The first side bump pad 220 and the second side bump pad 230 may have the same shape and size. The main bump pad 210, the first side bump pad 220 and the second side bump pad 230 may be used to determine the bonding state of the bump pad unit 200 with the conductive structure bonded to the bump pad unit 200.

[0018] The first side bump pad 220 and the second side bump pad 230 may be arranged in a row with the main bump pad 210. The first side bump pad 220 may be arranged on the upper surface of the semiconductor substrate 100 in a first side direction of the main bump pad 210 and spaced apart from the main bump pad 210. The second side bump pad 230 may be arranged on the upper surface of the semiconductor substrate 100 in a second side direction of the main bump pad 210 and spaced apart from the main bump pad 210. The main bump pad 210 may be arranged in the center between the first side bump pad 220 and the second side bump pad 230. The first side bump pad 220 and the second side bump pad 230 may be arranged to be spaced apart from the main bump pad 210 by the same distance in the first direction and the second direction. The first direction and the second direction are opposite directions. That is, the first side bump pads 220 and the second side bump pads 230 may be symmetrically disposed on the upper surface 100S1 of the semiconductor substrate 100 with respect to the main bump pads 210 .

[0019] The shapes and sizes of the main bump pad 210, the first side bump pad 220, and the second side bump pad 230 and the intervals therebetween may be implemented in various ways. As an example, the main bump pad 210 may have a larger shape and size than the first side bump pad 220 and the second side bump pad 230. In this regard, when the contact area of ​​the main bump pad 210 for bonding with the conductive structure is formed to be larger than that of the other pads, the bonding force between the bump pad unit 200 and the conductive structure may be increased.

[0020] Reference Figure 1 , the test pads 300a, 300b and 300c may be disposed on the lower surface 100S2 of the semiconductor substrate 100. When the semiconductor substrate 100 is provided in the form of a semiconductor package, the test pads 300a, 300b and 300c may be disposed in a specific region of the semiconductor substrate 100. As an example, the specific region may correspond to an outer region of the semiconductor substrate 100. The test pads 300a, 300b and 300c may be electrically connected to the main bump pad 210, the first side bump pad 220 and the second side bump pad 230 through traces 400a, 400b and 400c, respectively. The first test pad 300a may be electrically connected to the main bump pad 210, the second test pad 300b may be electrically connected to the first side bump pad 220, and the third test pad 300c may be electrically connected to the second side bump pad 230. In some unshown embodiments, the test pads 300a, 300b, and 300c may be disposed on the upper surface 100S1 or the lower surface 100S2 of the semiconductor substrate 100. In addition, the positions where the test pads 300a, 300b, and 300c are disposed may be implemented in various variations within the region of the semiconductor substrate 100.

[0021] Reference Figure 1 , traces 400a, 400b, and 400c may connect the test pads 300a, 300b, and 300c to the main bump pad 210, the first side bump pad 220, and the second side bump pad 230, respectively. That is, traces 400a, 400b, and 400c may be provided in the semiconductor substrate 100 to electrically connect the corresponding bump pads to the test pads, respectively. The first trace 400a may be provided in the semiconductor substrate 100 to electrically connect the main bump pad 210 to the first test pad 300a. The second trace 400b may be provided in the semiconductor substrate 100 to electrically connect the first side bump pad 220 to the second test pad 300b. The third trace 400c may be provided in the semiconductor substrate 100 to electrically connect the second side bump pad 230 to the third test pad 300c. The arrangement of the traces 400 a , 400 b , and 400 c may also be implemented in various variations within the region of the semiconductor substrate 100 .

[0022] Reference Figure 1 , the bump 600 may be provided as a conductive structure bonded to the bump pad unit 200. The bump 600 may be provided above the bump pad unit 200 to bond to the bump pad unit 200. The bump pad unit 200 and the bump 600 may be electrically connected to each other. The bump 600 may be bonded to at least one of the pads included in the bump pad unit 200. The bump 600 may include a main body 610 used as a support body and a bonding portion 620 connected to the main body 610. The bonding portion 620 may include, for example, a solder for bonding. The main body 610 may have a cylindrical shape, and the bonding portion 620 may have a hemispherical shape, but is not limited thereto. The bonding portion 620 may be bonded to the main bump pad 210, and may be further bonded to the first side bump pad 220 and the second side bump pad 230. In this case, it may be determined whether the bonding state of the bump pad unit 200 and the bump 600 is normal or abnormal according to the bonding type of the bonding portion 620 and the pad.

[0023] Reference Figure 1 , a test device 500 for testing the semiconductor substrate 100 may be provided. In another embodiment of the present disclosure, a test system including the above-mentioned semiconductor substrate 100 and the test device 500 to be described below may be provided. The test device 500 may detect the electrical connection between the main bump pad 210 and each of the plurality of side bump pads 220 and 230 through the test pads 300a, 300b, and 300c, respectively, and may determine whether a failure occurs. The test device 500 may include a detection unit 510 and a determination unit 520.

[0024] Reference Figure 1, the detection unit 510 can detect the power-on state between the main bump pad 210 and the first side bump pad 220 and the power-on state between the main bump pad 210 and the second side bump pad 230 through the test pads 300a, 300b and 300c. When the conductive structure is bonded to the bump pad unit 200 in various forms, the detection unit 510 can detect whether the power-on state is an open circuit state or a short circuit state by applying a test signal to the test pads 300a, 300b and 300c. The detection unit 510 can apply a test signal to the first test pad 300a and the second test pad 300b to identify whether the main bump pad 210 electrically connected to the first test pad 300a and the first side bump pad 220 electrically connected to the second test pad 300b are electrically short-circuited or open-circuited, respectively. Similarly, the detection unit 510 can apply a test signal to the first test pad 300a and the third test pad 300c to identify whether the main bump pad 210 electrically connected to the first test pad 300a and the second side bump pad 230 electrically connected to the third test pad 300c are electrically shorted or open, respectively. As an example, the detection unit 510 can be implemented as a test pin such as a probe.

[0025] Reference Figure 1 , the determination unit 520 may determine whether a failure has occurred based on the detection result of the detection unit 510. As an example of determining whether a failure has occurred, it may be determined whether a bonding state of the bump pad unit 200 and the bump 600 bonded to the bump pad unit 200 is normal. As another example, it may be determined whether an arrangement state of a semiconductor chip mounted on the semiconductor substrate 100 through the pad and the bump 600 is normal. The determination unit 520 may be implemented in the form of a test circuit using a test pin.

[0026] As a detection result of the detection unit 510, when both the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230 are in a short-circuit state, the determination unit 520 may determine that no failure has occurred. Alternatively, as a detection result of the detection unit 510, when at least one of the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230 is in an open-circuit state, the determination unit 520 may determine that a failure has occurred.

[0027] Figure 2 This is an example test Figure 1 1. A flow chart of a method for manufacturing a semiconductor substrate 100 is shown in FIG.

[0028] Reference Figure 1 and Figure 2, the method of testing the semiconductor substrate 100 may include preparing the semiconductor substrate 100 (S21), detecting whether the main bump pad 210 and the plurality of side bump pads 220 and 230 disposed on the semiconductor substrate 100 are electrically connected (S22), and determining whether a failure has occurred (S23). When preparing the semiconductor substrate 100 (S21), as described above with reference to Figure 1 As described, the semiconductor substrate 100 may be provided with: a bump pad unit 200 configured to be bonded to a conductive structure on an upper surface 100S1; test pads 300a, 300b, and 300c spaced apart from each other on the upper surface 100S1 or the lower surface 100S2; and traces 400a, 400b, and 400c provided in the semiconductor substrate 100 to connect the pads included in the bump pad unit 200 with the test pads 300a, 300b, and 300c one-to-one.

[0029] In detecting electrical connection (S22), as described above with reference to Figure 1 As described above, the test device 500 can be used to detect the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230. Figure 1 The inspection unit 510 shown performs inspection on whether the main bump pad 210 and the plurality of side bump pads 220 and 230 are electrically connected ( S22 ).

[0030] In determining whether a failure has occurred (S23), as described above with reference to Figure 1 As described above, the test device 500 may be used to determine whether a failure occurs based on the power-on states of the main bump pad 210 and the first side bump pad 220 and the power-on states of the main bump pad 210 and the second side bump pad 230. Figure 1 The determination unit 520 shown performs a determination as to whether a failure has occurred (S23).

[0031] In determining whether a failure has occurred (S23), when each power-on state between the main bump pad 210 and the plurality of side bump pads 220 and 230 is a short-circuit state, it can be determined that no failure has occurred. That is, as a result of detecting the electrical connection (S22), when both the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230 are a short-circuit state, it can be determined that no failure has occurred in the bonding position between the conductive structure and the bump pad unit 200.

[0032] On the other hand, in determining whether a failure has occurred (S23), when at least one of the power-on states between the main bump pad 210 and the plurality of side bump pads 220 and 230 is an open state, it can be determined that a failure has occurred. That is, as a result of detecting the electrical connection (S22), when the power-on state of the main bump pad 210 and the first side bump pad 220 and one of the power-on states of the main bump pad 210 and the second side bump pad 230 are an open state, it can be determined that a failure has occurred in the bonding position between the conductive structure and the bump pad unit 200.

[0033] In addition, in determining whether a failure has occurred (S23), when the power-on states between the main bump pad 210 and the plurality of side bump pads 220 and 230 are all in an open state, it can be determined that a wetting failure has occurred. That is, as a result of detecting the electrical connection (S22), when the power-on states of the main bump pad 210 and the first side bump pad 220 and the power-on states of the main bump pad 210 and the second side bump pad 230 are both in an open state, it can be determined that a connection failure has occurred between the conductive structure and the bump pad unit 200.

[0034] although Figure 1 Not shown, but refer to Figure 6 As described, the semiconductor chip can be arranged on the conductive structure. Here, in determining whether a fault has occurred (S23), when each power-on state between the main bump pad 210 and the plurality of side bump pads 220 and 230 is a short circuit state, it can be determined that there is no misalignment between the semiconductor substrate 100 and the semiconductor chip. On the other hand, in determining whether a fault has occurred (S23), when at least one of the power-on states between the main bump pad 210 and the plurality of side bump pads 220 and 230 is an open circuit state, it can be determined that there is a misalignment between the semiconductor substrate 100 and the semiconductor chip.

[0035] Figures 3 to 5 Is used for Figure 1 The semiconductor substrate 100 and the testing device 500 shown in FIG. 1 are further illustrated in detail. Figure 1 The bump pad unit 200 of the semiconductor substrate 100 is shown.

[0036] Figure 3 The case where the bonding state between the bump pad unit 200 and the bump 600 is normal is illustrated. Figure 3, the central axis C600 of the bump 600 may be configured to be parallel to the z-axis and pass through the center of the bump 600. The central axis C600 may be configured to intersect the center of the width of the body 610 disposed along the x-axis and the center of the width of the coupling portion 620 disposed along the x-axis.

[0037] Reference Figure 3 , the bonding portion 620 may be bonded to all of the main bump pad 210, the first side bump pad 220, and the second side bump pad 230 to be electrically connected to each other. As an example, the bump pad unit 200 and the bump 600 may be bonded so that the central axis C600 passes through the center of the main bump pad 210. In this case, the detection unit 510 may detect the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230 through the test pads 300a, 300b, and 300c. The main bump pad 210, the first side bump pad 220, and the second side bump pad 230 are all electrically connected through the bonding portion 620, so that the detection results of the detection unit 510 may all be short-circuit states. Because the detection results of the detection unit 510 are all short-circuit states, the determination unit 520 may determine that no failure has occurred. Furthermore, in this case, since a bonding failure between the bump pad unit 200 and the bump 600 does not occur, the determination unit 520 may determine that the bonding state of the bump pad unit 200 and the bump 600 is normal.

[0038] Figure 4 An example in which the bonding state of the bump pad unit 200 and the bump 600 is abnormal is illustrated. Figure 4 , the bonding portion 620 may be bonded only to the main bump pad 210 and the first side bump pad 220, and may not be bonded to the second side bump pad 230. As a result, only the main bump pad 210 and the first side bump pad 220 are electrically connected to each other through the bonding portion 620. Therefore, the detection result of the detection unit 510 may be that the power-on state of the main bump pad 210 and the first side bump pad 220 is a short circuit state, and the power-on state of the main bump pad 210 and the second side bump pad 230 is an open circuit state. Because at least one of the detection results of the detection unit 510 is an open circuit state, the determination unit 520 can determine that a failure has occurred. In addition, in this case, because a bonding failure of the bump pad unit 200 and the bump 600 has occurred, the determination unit 520 can determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal. In addition, based on the above detection results, the determination unit 520 may recognize that the bonding portion 620 has been offset and bonded relative to the main bump pad 210 in a direction opposite to the second side bump pad 230 (ie, the direction of the first side bump pad 220 ).

[0039] Although not shown, when the bonding state of the bump pad unit 200 and the bump 600 is abnormal, the bonding portion 620 may be bonded only to the main bump pad 210 and the second side bump pad 230, and may not be bonded to the first side bump pad 220. As a result, only the main bump pad 210 and the second side bump pad 230 may be electrically connected to each other through the bonding portion 620. Therefore, as a detection result of the detection unit 510, the power-on state of the main bump pad 210 and the first side bump pad 220 is an open circuit state, and the power-on state of the main bump pad 210 and the second side bump pad 230 is a short circuit state. As shown in Figure 4 In the case of, since at least one of the detection results of the detection unit 510 is an open state, the determination unit 520 may determine that a failure has occurred. In this case, the determination unit 520 may determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal.

[0040] Figure 5 Another example in which the bonding state of the bump pad unit 200 and the bump 600 is abnormal is illustrated. Figure 5 , the bonding portion 620 may be bonded only to the main bump pad 210, and may not be bonded to the first side bump pad 220 and the second side bump pad 230. As a result, the bonding portion 620 may be electrically connected only to the main bump pad 210. As a result of the determination of the detection unit 510, the power-on state of the main bump pad 210 and the first side bump pad 220 is an open state, and the power-on state of the main bump pad 210 and the second side bump pad 230 is an open state. Because at least one of the detection results of the detection unit 510 is an open state, the determination unit 520 may determine that a failure has occurred.

[0041] In addition, when the detection results of the detection unit 510 are all open circuit states as described above, this may be a case where a wetting failure has occurred. At this time, the determination unit 520 may determine that a wetting failure has occurred. Figure 5 , even when a wetting failure occurs, the bump pad unit 200 and the bump 600 can be joined so that the central axis C600 passes through the center of the main bump pad 210, so that the joining state of the bump pad unit 200 and the bump 600 can appear normal. However, in this case, because only a small amount of solder provided to the bonding portion 620 contacts the main bump pad 210, the bump pad unit 200 and the bump 600 form a contact point, but the bump pad unit 200 and the bump 600 cannot form a physically stable joint. In this way, according to the present embodiment, not only a failure in the joining position according to the joining type between the pad and the bump can be detected, but also a wetting failure as a connection failure type can be detected.

[0042] Figures 6 to 9 Is used for Figure 1 The semiconductor substrate 100 and the test device 500 shown in FIG. 1 are further diagrams for explaining another example of the test method. Figure 1 The bump pad unit 200 and the bump 600 are shown to bond the semiconductor chip 700 to the semiconductor substrate 100 .

[0043] Figure 6 The semiconductor substrate 100 and the semiconductor chip 700 are normally aligned. Figure 7 7 is a plan view of the semiconductor substrate 100 when the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is normal.

[0044] Reference Figure 6 and Figure 7 , the semiconductor chip 700 may be mounted on the semiconductor substrate 100. The bump 600 bonded to the bump pad unit 200 provided on the semiconductor substrate 100 may be provided on the surface of the semiconductor chip 700. In addition, a bonding pad 1200 consisting of a single pad may also be provided on the semiconductor substrate 100. In order to connect the semiconductor chip 700 to the semiconductor substrate 100, the bump 600 may be bonded to the bonding pad 1200 and the bump pad unit 200. A solder ball 800 for connecting the semiconductor substrate 100 to other semiconductor devices and the like may be provided on the lower surface 100S2 of the semiconductor substrate 100. According to the present embodiment, a semiconductor package including the semiconductor substrate 100, the bump pad unit 200, the bump 600, the test pads 300a, 300b and 300c, the traces 400a, 400b and 400c, the bonding pad 1200 and the semiconductor chip 700 may be provided in various forms.

[0045] Reference Figure 6 and Figure 7 , the bonding portion 620 of each bump 600 can be bonded and electrically connected to all of the main bump pad 210, the first side bump pad 220, and the second side bump pad 230. Here, the detection unit 510 can detect the power-on state of the main bump pad 210 and the first side bump pad 220 and the power-on state of the main bump pad 210 and the second side bump pad 230. In this case, all the detection results of the detection unit 510 can become a short-circuit state. Because the detection results of the detection unit 510 are all short-circuit states, the determination unit 520 can determine that no failure has occurred. In addition, because there is no misalignment of the semiconductor substrate 100 and the semiconductor chip 700 in this case, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is normal.

[0046] Reference Figure 6 and Figure 7, a plurality of bump pad units 200 may be provided on the upper surface 100S1 of the semiconductor substrate 100. In addition, a plurality of bumps 600 may be provided on the plurality of bump pad units 200 and the plurality of bump pad units 200 may be joined to mount the semiconductor chip 700 on the semiconductor substrate 100 corresponding to each other. As an example, four bump pad units 200 including a main bump pad 210, a first side bump pad 220, and a second side bump pad 230 may be provided in four corner regions of the upper surface 100S1, respectively, and the joining pads 1200, respectively consisting of a single pad, may be arranged in two rows on the upper surface 100S1. In addition, the bumps 600 may be provided on the four bump pad units 200 and the joining pads 1200 and the four bump pad units 200 and the joining pads 1200 may be joined, and the semiconductor chip 700 may be provided on the bumps 600. When the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is normal, the bonding portion 620 of each bump 600 may be electrically connected to all of the main bump pad 210, the first side bump pad 220, and the second side bump pad 230. At this time, each bump 600 and each bump pad unit 200 may be bonded so that the center of the bump 600 coincides with the center of the bump pad unit 200.

[0047] Figure 8 The semiconductor substrate 100 and the semiconductor chip 700 are abnormally aligned, and Fig. 9 is a plan view of the semiconductor substrate 100 when the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal.

[0048] Reference Figure 8 and Fig. 9 , the bonding portion 620 may be bonded only to the main bump pad 210 and the first side bump pad 220, and may not be bonded to the second side bump pad 230. In this case, as a detection result of the detection unit 510, the power-on state of the main bump pad 210 and the first side bump pad 220 is a short circuit state, and the power-on state of the main bump pad 210 and the second side bump pad 230 is an open circuit state. Since at least one of the detection results of the detection unit 510 is an open circuit state, the determination unit 520 can determine that a failure has occurred. In addition, in this case, because misalignment of the semiconductor substrate 100 and the semiconductor chip 700 occurs, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal. In addition, the determination unit 520 can determine that the bonding between the semiconductor substrate 100 and the semiconductor chip 700 has been offset in the opposite direction of the second side bump pad 230 (i.e., in the direction of the first side bump pad 220).

[0049] Reference Figure 8 and Fig. 9As an example of an abnormal alignment state of the semiconductor substrate 100 and the semiconductor chip 700, the bump 600 may be electrically connected only to the main bump pad 210 and the first side bump pad 220, and may not be electrically connected to the second side bump pad 230. Therefore, the semiconductor chip 700 may be misaligned and disposed on the semiconductor substrate 100 while the semiconductor chip 700 is shifted to the left along the x-axis.

[0050] Although not shown, when the semiconductor substrate 100 and the semiconductor chip 700 are abnormally aligned, the bonding portion 620 may be bonded only to the main bump pad 210 and the second side bump pad 230, and may not be bonded to the first side bump pad 220. In this case, as a detection result of the detection unit 510, the power-on state of the main bump pad 210 and the first side bump pad 220 is an open circuit state, and the power-on state of the main bump pad 210 and the second side bump pad 230 is a short circuit state. Because at least one of the detection results of the detection unit 510 is an open circuit state, the determination unit 520 can determine that a failure has occurred. In addition, in this case, because misalignment of the semiconductor substrate 100 and the semiconductor chip 700 has occurred, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal. In addition, the determination unit 520 may determine, based on the detection result, that the bonding position of the semiconductor substrate 100 and the semiconductor chip 700 has shifted in the opposite direction (i.e., in the direction of the first-side bump pad 220) relative to the second-side bump pad 230. In this case, the semiconductor chip 700 may be misaligned and disposed on the semiconductor substrate 100 while the semiconductor chip 700 is shifted to the left along the x-axis.

[0051] Fig.10 is a diagram schematically illustrating another example of the configuration of a semiconductor wafer 100 and a test apparatus 500 for testing the semiconductor wafer 100 according to an embodiment of the present disclosure. Figure 1 The same components as shown in Fig.10 Therefore, the same reference numerals as in Figure 1 The content described overlaps the content.

[0052] Reference Fig.10, the bump pad unit 200 may include a main bump pad 210, a first side bump pad 220, a second side bump pad 230, a third side bump pad 240 and a fourth side bump pad 250 arranged on the upper surface 100S1 of the semiconductor substrate 100. The first side bump pad to the fourth side bump pad 220, 230, 240 and 250 may have the same shape and size as each other. The first side bump pad 220 and the second side bump pad 230 may be arranged in a horizontal line form along the x direction around the main bump pad 210. The first side bump pad 220 and the second side bump pad 230 may be arranged on the upper surface 100S1 to be spaced apart from each other in opposite directions based on the main bump pad 210. In addition, the first side bump pad 220 and the second side bump pad 230 may be arranged to be symmetrical relative to the main bump pad 210. Here, the main bump pad 210, the first side bump pad 220 and the second side bump pad 230 can be arranged to share a horizontal axis HS1, which is configured to be parallel to the x-axis. The third side bump pad 240 and the fourth side bump pad 250 can be arranged in a vertical line form around the main bump pad 210 along the y-axis. The third side bump pad 240 and the fourth side bump pad 250 can be arranged on the upper surface 100S1 of the semiconductor substrate 100 spaced apart from each other in opposite directions based on the main bump pad 210. In addition, the third side bump pad 240 and the fourth side bump pad 250 can be arranged to be symmetrical relative to the main bump pad 210. Here, the main bump pad 210, the third side bump pad 240 and the fourth side bump pad 250 can be arranged to share a vertical axis VS1, and the vertical axis VS1 is configured to be parallel to the y-axis.

[0053] Reference Fig.10, the test pads 300a, 300b, 300c, 300d, and 300e may be electrically connected to the main bump pad 210, the first side bump pad 220, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250 through the traces 400a, 400b, 400c, 400d, and 400e, respectively. The traces 400a, 400b, 400c, 400d, and 400e may be provided in the semiconductor substrate 100 to electrically connect the main bump pad 210, the first side bump pad 220, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250 to the test pads 300a, 300b, 300c, 300d, and 300e, respectively. The first trace 400a may be provided in the semiconductor substrate 100 to electrically connect the main bump pad 210 to the first test pad 300a. The second trace 400b may be provided in the semiconductor substrate 100 to electrically connect the first side bump pad 220 to the second test pad 300b. The third trace 400c may be provided in the semiconductor substrate 100 to electrically connect the second side bump pad 230 to the third test pad 300c. The fourth trace 400d may be provided in the semiconductor substrate 100 to electrically connect the third side bump pad 240 to the fourth test pad 300d. The fifth trace 400e may be provided in the semiconductor substrate 100 to electrically connect the fourth side bump pad 250 to the fifth test pad 300e.

[0054] Reference Fig.10 The detection unit 510 can detect the power-on status of the main bump pad 210 and the first side bump pad 220, the power-on status of the main bump pad 210 and the second side bump pad 230, the power-on status of the main bump pad 210 and the third side bump pad 240, and the power-on status of the main bump pad 210 and the fourth side bump pad 250 through the test pads 300a, 300b, 300c, 300d and 300e respectively.

[0055] Reference Fig.10, the determination unit 520 may determine whether a fault has occurred based on the detection result of the detection unit 510. As an example, the determination unit 520 may determine whether the bonding state of the bump pad unit 200 and the conductive structure bonded to the bump pad unit 200 is normal. As the detection result of the detection unit 510, when the power-on state of the main bump pad 210 and the first side bump pad 220, the power-on state of the main bump pad 210 and the second side bump pad 230, the power-on state of the main bump pad 210 and the second side bump pad 230, the main bump pad 210 and the third side bump pad 240, and the main bump pad 210 and the fourth side bump pad 250 are all in a short circuit state, the determination unit 520 may determine that no fault has occurred. On the contrary, as a detection result of the detection unit 510, when at least one of the power-on state of the main bump pad 210 and the first side bump pad 220, the power-on state of the main bump pad 210 and the second side bump pad 230, the power-on state of the main bump pad 210 and the third side bump pad 240, and the power-on state of the main bump pad 210 and the fourth side bump pad 250 is an open state, the determination unit 520 can determine that a failure has occurred. In addition, the determination unit 520 can determine in which direction the bonding position of the conductive structure bonded to the bump pad unit 200 is offset relative to the main bump pad 210 based on the detection result of the detection unit 510.

[0056] Figures 11 to 15 Is used for Fig.10 The semiconductor substrate 100 and the testing device 500 are shown in more detail to illustrate an example of the testing method. Figures 3 to 9 The same components as in Figures 11 to 15 Therefore, in the following text, the reference numerals will be omitted. Figures 3 to 9 The content described overlaps the content.

[0057] Fig.11 A case where the bonding state of the bump pad unit 200 and the bump 600 bonded to the bump pad unit 200 is normal is illustrated. Fig.12 and Fig.13 1 is a plan view of the semiconductor substrate 100 in a case where the arrangement state of the semiconductor chip 700 bonded to the semiconductor substrate 100 via the bump pad unit 200 and the bump 600 is normal.

[0058] Reference Fig.11 and Fig.12, in a state where the bump pad unit 200 and the bump 600 are bonded to each other, the bonding portion 620 may be bonded and electrically connected to all of the main bump pad 210, the first side bump pad 220, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250. In this case, the detection unit 510 may detect the power-on state of the main bump pad 210 and the first side bump pad 220, the power-on state of the main bump pad 210 and the second side bump pad 230, the power-on state of the main bump pad 210 and the third side bump pad 240, and the power-on state of the main bump pad 210 and the fourth side bump pad 250 through the test pads 300a, 300b, 300c, 300d, and 300e. The main bump pad 210 is electrically connected to all the first side bump pads to the fourth side bump pads 220, 230, 240 and 250 through the bonding portion 620, so that the detection results of the detection unit 510 can all be short-circuit states. Because the detection results of the detection unit 510 are all short-circuit states, the determination unit 520 can determine that no failure has occurred. In addition, in this case, because the bonding failure of the bump pad unit 200 and the bump 600 has not occurred, the determination unit 520 can determine that the bonding state of the bump pad unit 200 and the bump 600 is normal. At this time, if the semiconductor chip 700 is bonded to the semiconductor substrate 100 through the bump pad unit 200 and the bump 600, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is normal.

[0059] Reference Fig.12 , including a main bump pad 210, a bump pad unit 200 of a first side bump pad to a fourth side bump pad 220, 230, 240 and 250 can be disposed in the center of the upper surface 100S1 of the semiconductor substrate 100. Although not shown, a plurality of bump pad units 200 can be disposed on the upper surface 100S1 of the semiconductor substrate 100. In this case, the bonding pads 1200 consisting of a single pad can be arranged in two rows on the upper surface 100S1 of the semiconductor substrate 100, but are not limited thereto. In other words, although not shown, the bonding pads 1200 can be arranged in multiple columns on the upper surface 100S1 of the semiconductor substrate 100. In addition, the bumps 600 can be disposed on the bump pad unit 200 and the bonding pads 1200 for connecting the semiconductor chip 700 to the semiconductor substrate 100 and bonding the bump pad unit 200 and the bonding pads 1200. As Fig.12 As shown, when the semiconductor substrate 100 is configured to include one bump pad unit 200 , the space occupied by the bumps and the test pads connected to the bump pad unit 200 in the semiconductor substrate 100 can be reduced.

[0060] Reference Fig.13, the bump pad unit 200 including the main bump pad 210 and the first side bump pad to the fourth side bump pad 220, 230, 240 and 250 can be arranged in at least two of the four corner areas of the upper surface 100S1 of the semiconductor substrate 100. In addition, the bonding pad 1200 as a single pad can be arranged in two rows, but is not limited to this. In other words, although not shown, the bonding pad 1200 can be arranged in multiple columns on the upper surface 100S1 of the semiconductor substrate 100. In addition, the bump 600 can be arranged on a plurality of bump pad units 200 and bonding pads 1200 and bond a plurality of bump pad units 200 and bonding pads 1200.

[0061] Reference Fig.12 and Fig.13 , when the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is normal, the bump 600 may be electrically connected to all of the main bump pad 210, the first side bump pad 220, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250. In this case, the bump 600 and the bump pad unit 200 may be joined so that the center of the bump 600 and the center of the bump pad unit 200 coincide with each other. Although not shown, Fig.12 and Fig.13 The semiconductor substrate 100 may be configured by arranging the bump pad unit 200 and the bonding pad 1200 in various forms, unlike those shown in FIG.

[0062] With reference to the above description, as an example, the bump pad unit 200 is disposed in the center of the upper surface 100S1, thereby enabling detection of a phenomenon in which the center is lifted when the semiconductor substrate 100 and the semiconductor chip 700 are bonded. In addition, as another example, a plurality of bump pad units 200 are disposed on the upper surface 100S1, thereby enabling effective detection of a tilting phenomenon occurring when the substrate 100 and the semiconductor chip 700 are bonded. In addition, as another example, the bump pad unit 200 is disposed in a corner region of the semiconductor substrate 100, thereby enabling detection of a phenomenon in which the edge portion is lifted when the substrate 100 and the semiconductor chip 700 are bonded. In this way, according to an embodiment of the present disclosure, it is also possible to detect a wetting failure caused by warping of the semiconductor substrate 100 or the semiconductor chip 700.

[0063] Fig.14 The case where the bonding state between the bump pad unit 200 and the bump 600 bonded to the bump pad unit 200 is abnormal is illustrated. Fig.15 1 is a plan view of the semiconductor substrate 100 when the alignment state of the semiconductor chip 700 bonded to the semiconductor substrate 100 via the bump pad unit 200 and the bump 600 is abnormal.

[0064] Reference Fig.14 and Fig.15 , when the bump pad unit 200 and the bump 600 are bonded to each other, the bonding portion 620 may be bonded only to the main bump pad 210, the first side bump pad 220, the third side bump pad 240, and the fourth side bump pad 250, and may not be bonded to the second side bump pad 230. Because only the main bump pad 210, the first side bump pad 220, the third side bump pad 240, and the fourth side bump pad 250 are electrically connected through the bonding portion 620, as a detection result of the detection unit 510, only the power-on states of the main bump pad 210 and the second side bump pad 230 are open circuit states, and the remaining power-on states are short circuit states. At least one of the detection results of the detection unit 510 is an open circuit state, so that the determination unit 520 can determine that a failure has occurred. Furthermore, in this case, since a bonding failure of the bump pad unit 200 and the bump 600 has occurred, the determination unit 520 can determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal. Furthermore, based on the detection result, the determination unit 520 can determine that the bonding position of the semiconductor chip 700 has shifted in the opposite direction of the second side bump pad 230 relative to the main bump pad 210. At this time, if the semiconductor chip 700 is bonded to the semiconductor substrate 100 through the bump pad unit 200 and the bump 600, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal.

[0065] Reference Fig.15 , as an example of a case where the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal, the bump 600 may be electrically connected to the remaining pads except the second side bump pad 230. Therefore, the semiconductor chip 700 may be bonded to the semiconductor substrate 100 in a form shifted to the left along the x-axis. As described above, when the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal, the bump 600 and the bump pad unit 200 may be bonded to each other so that the center of the bump 600 and the center of the bump pad unit 200 are not aligned.

[0066] Although not shown, in a state where the bump pad unit 200 and the bump 600 are bonded to each other, the bonding portion 620 may be bonded only to the main bump pad 210, the first side bump pad 220, the second side bump pad 230, and the third side bump pad 240, and may not be bonded to the fourth side bump pad 250. Since only the main bump pad 210, the first side bump pad 220, the second side bump pad 230, and the third side bump pad 240 are electrically connected through the bonding portion 620, only the power-on states of the main bump pad 210 and the fourth side bump pad 250 are open circuit states as a detection result of the detection unit 510, and the remaining power-on states are short circuit states. Since at least one of the detection results of the detection unit 510 is an open circuit state, the determination unit 520 can determine that a failure has occurred. Furthermore, in this case, because a bonding failure of the bump pad unit 200 and the bump 600 has occurred, the determination unit 520 can determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal. In addition, based on the detection result, the determination unit 520 can determine that the bonding position of the bump pad unit 200 and the bump 600 has shifted in the opposite direction of the fourth side bump pad 250 relative to the main bump pad 210. Here, if the semiconductor chip 700 is bonded to the semiconductor substrate 100 through the bump pad unit 200 and the bump 600, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal. At this time, the semiconductor chip 700 can be bonded to the semiconductor substrate 100 in the form that the semiconductor chip 700 has moved upward along the y-axis.

[0067] Although not shown, in a state where the bump pad unit 200 and the bump 600 are bonded to each other, the bonding portion 620 may be bonded only to the main bump pad 210, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250, and may not be bonded to the first side bump pad 220. As a detection result of the detection unit 510, since the main bump pad 210, the second side bump pad 230, the third side bump pad 240, and the fourth side bump pad 250 are electrically connected to each other through the bonding portion 620, only the power-on state of the main bump pad 210 and the first side bump pad 220 is an open state, and the remaining power-on states are short states. Since at least one of the detection results of the detection unit 510 is an open state, the determination unit 520 can determine that a failure has occurred. In addition, in this case, a bonding failure of the bump pad unit 200 and the bump 600 has occurred, so that the determination unit 520 can determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal. In addition, based on the detection result, the determination unit 520 can determine that the bonding position of the bump pad unit 200 and the bump 600 has shifted in the opposite direction of the first side bump pad 220 relative to the main bump pad 210. Here, if the semiconductor chip 700 is bonded to the semiconductor substrate 100 through the bump pad unit 200 and the bump 600, the determination unit 520 can determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal. At this time, the semiconductor chip 700 can be bonded to the semiconductor substrate 100 in the form that the semiconductor chip 700 has moved rightward along the x-axis.

[0068] Although not shown, in a state where the bump pad unit 200 and the bump 600 are bonded to each other, the bonding portion 620 may be bonded only to the main bump pad 210, the first side bump pad 220, the second side bump pad 230, and the fourth side bump pad 250, and may not be bonded to the third side bump pad 240. As a detection result of the detection unit 510, since the main bump pad 210, the first side bump pad 220, the second side bump pad 230, and the fourth side bump pad 250 are electrically connected to each other through the bonding portion 620, only the power-on state of the main bump pad 210 and the third side bump pad 240 is an open circuit state, and the remaining power-on states are short circuit states. Since at least one of the detection results of the detection unit 510 is an open circuit state, the determination unit 520 can determine that a failure has occurred. Furthermore, in this case, since a bonding failure of the bump pad unit 200 and the bump 600 has occurred, the determination unit 520 may determine that the bonding state of the bump pad unit 200 and the bump 600 is abnormal. Furthermore, based on the detection result, the determination unit 520 may determine that the bonding position of the bump pad unit 200 and the bump 600 has shifted in the opposite direction of the first side bump pad 220 relative to the main bump pad 210. Here, if the semiconductor chip 700 is bonded to the semiconductor substrate 100 through the bump pad unit 200 and the bump 600, the determination unit 520 may determine that the alignment state of the semiconductor substrate 100 and the semiconductor chip 700 is abnormal. At this time, the semiconductor chip 700 may be bonded to the semiconductor substrate 100 in the form that the semiconductor chip 700 has moved downward along the y-axis.

[0069] As described above, embodiments of the present disclosure have been described with reference to the accompanying drawings included in this specification. However, this is to explain what will be presented in the present disclosure and is not intended to limit what will be presented in the present disclosure to the form presented in detail. Various other variations will be possible as long as they reflect the technical concepts proposed in the present disclosure.

[0070] CROSS-REFERENCE TO RELATED APPLICATIONS

[0071] This application claims priority from Korean Application No. 10-2020-0028051, filed on Mar. 6, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor substrate, comprising an upper surface and a lower surface, the semiconductor substrate comprising: a bump pad unit, the bump pad unit being arranged on the upper surface; A test pad, wherein the test pad is arranged on the upper surface or the lower surface; a trace configured to connect the bump pad unit and the test pad; a bonding pad disposed on the upper surface; as well as a bump including a first bump bonded to the bump pad unit and a second bump bonded to the bonding pad, The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface and spaced apart from the main bump pad. wherein the trace connects the main bump pad and the plurality of side bump pads to the test pad in a one-to-one manner, wherein the test pads are electrically connected to the main bump pad and the plurality of side bump pads, respectively, so that whether the main bump pad and the plurality of side bump pads are electrically connected is detected by a test signal input from outside the semiconductor substrate, and The power-on state between the main bump pad and the plurality of side bump pads is detected to determine a bonding state between the bump pad unit and the first bump.

2. The semiconductor substrate according to claim 1, wherein The plurality of side bump pads include: a first side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a first side direction of the main bump pad; and A second side bump pad is disposed on the upper surface of the semiconductor substrate to be spaced apart from the main bump pad in a second side direction of the main bump pad.

3. The semiconductor substrate according to claim 2, wherein: The first side bump pad and the second side bump pad have the same shape and size, and are symmetrically arranged relative to the main bump pad by being spaced the same distance from the main bump pad in the first side direction and the second side direction, wherein the first side direction and the second side direction are opposite directions.

4. The semiconductor substrate according to claim 3, wherein: The test pads include a first test pad, a second test pad and a third test pad, The traces include a first trace, a second trace and a third trace, The first trace is arranged to electrically connect the main bump pad to the first test pad, The second trace is arranged to electrically connect the first side bump pad to the second test pad, and The third trace is disposed to electrically connect the second side bump pad to the third test pad.

5. The semiconductor substrate according to claim 1, wherein The plurality of side bump pads include a first side bump pad, a second side bump pad, a third side bump pad, and a fourth side bump pad, The first side bump pad and the second side bump pad have the same shape and size, are arranged laterally around the main bump pad, and are symmetrically disposed on the upper surface of the semiconductor substrate with respect to the main bump pad, and The third side bump pad and the fourth side bump pad have the same shape and size, are longitudinally arranged around the main bump pad, and are symmetrically disposed on the upper surface of the semiconductor substrate with respect to the main bump pad.

6. The semiconductor substrate according to claim 5, wherein: The test pads include a first test pad, a second test pad, a third test pad, a fourth test pad and a fifth test pad, The traces include a first trace, a second trace, a third trace, a fourth trace and a fifth trace, The first trace is arranged to electrically connect the main bump pad to the first test pad, The second trace is configured to electrically connect the first side bump pad to the second test pad, The third trace is configured to electrically connect the second side bump pad to the third test pad, The fourth trace is configured to electrically connect the third side bump pad to the fourth test pad, and The fifth trace is disposed to electrically connect the fourth side bump pad to the fifth test pad.

7. A semiconductor package, comprising: a semiconductor substrate, the semiconductor substrate comprising an upper surface and a lower surface; a bump pad unit including a main bump pad disposed on the upper surface and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad; a bonding pad disposed on the upper surface; a bump including a first bump bonded to the bump pad unit and a second bump bonded to the bonding pad; A test pad, wherein the test pad is arranged on the upper surface or the lower surface; as well as a trace disposed in the semiconductor substrate and connecting the main bump pad and the plurality of side bump pads to the test pad in a one-to-one manner, wherein the test pads are electrically connected to the main bump pad and the plurality of side bump pads, respectively, so that whether the main bump pad and the plurality of side bump pads are electrically connected is detected by a test signal input from outside the semiconductor substrate, and The power-on state between the main bump pad and the plurality of side bump pads is detected to determine a bonding state between the bump pad unit and the first bump.

8. The semiconductor package according to claim 7, further comprising: A semiconductor chip is disposed on the bumps to be mounted on the semiconductor substrate.

9. The semiconductor package according to claim 8, in, The bump pad unit is disposed at the center of the semiconductor substrate, and The bumps are disposed on the bump pad unit and the bonding pad to connect the semiconductor chip to the semiconductor substrate.

10. The semiconductor package according to claim 8, in, At least one additional bump pad unit is disposed on the upper surface of the semiconductor substrate, and Wherein, the additional bump is arranged on the at least one additional bump pad unit.

11. The semiconductor package according to claim 8, in, The semiconductor package includes a plurality of bump pad units. The plurality of bump pad units are disposed in at least two of four corner regions of the semiconductor substrate.

12. The semiconductor package according to claim 7, wherein: The plurality of side bump pads include: a first side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a first side direction of the main bump pad; and A second side bump pad is disposed on the upper surface of the semiconductor substrate to be spaced apart from the main bump pad in a second side direction of the main bump pad.

13. The semiconductor package according to claim 12, wherein: The first side bump pad and the second side bump pad have the same shape and size, and are symmetrically arranged relative to the main bump pad by being spaced the same distance from the main bump pad in the first side direction and the second side direction, wherein the first side direction and the second side direction are opposite directions.

14. The semiconductor package according to claim 13, wherein: The test pads include a first test pad, a second test pad and a third test pad, The traces include a first trace, a second trace and a third trace, The first trace is arranged to electrically connect the main bump pad to the first test pad, The second trace is arranged to electrically connect the first side bump pad to the second test pad, and The third trace is disposed to electrically connect the second side bump pad to the third test pad.

15. The semiconductor package according to claim 7, in, The plurality of side bump pads include a first side bump pad, a second side bump pad, a third side bump pad, and a fourth side bump pad, wherein the first side bump pad and the second side bump pad have the same shape and size, are arranged laterally around the main bump pad, and are symmetrically disposed on the upper surface of the semiconductor substrate relative to the main bump pad, and The third side bump pad and the fourth side bump pad have the same shape and size, are arranged longitudinally around the main bump pad, and are symmetrically disposed on the upper surface of the semiconductor substrate relative to the main bump pad.

16. The semiconductor package according to claim 15, wherein: The test pads include a first test pad, a second test pad, a third test pad, a fourth test pad and a fifth test pad, The traces include a first trace, a second trace, a third trace, a fourth trace and a fifth trace, The first trace is arranged to electrically connect the main bump pad to the first test pad, The second trace is configured to electrically connect the first side bump pad to the second test pad, The third trace is configured to electrically connect the second side bump pad to the third test pad, The fourth trace is configured to electrically connect the third side bump pad to the fourth test pad, and The fifth trace is disposed to electrically connect the fourth side bump pad to the fifth test pad.

17. A method for testing a semiconductor substrate, the method comprising the following steps: preparing a semiconductor substrate, the semiconductor substrate comprising: an upper surface and a lower surface, a bump pad unit arranged to be bonded with a first bump of a conductive structure, a bonding pad arranged on the upper surface and bonded with a second bump of the conductive structure, and a test pad arranged on the upper surface or the lower surface, wherein the bump pad unit comprises a main bump pad arranged on the upper surface and a plurality of side bump pads arranged on the upper surface to be spaced apart from the main bump pad, a trace is arranged in the semiconductor substrate to connect the main bump pad and the plurality of side bump pads one-to-one to the test pad, and the test pad is electrically connected to the main bump pad and the plurality of side bump pads, respectively, so that an electrical connection between the main bump pad and the plurality of side bump pads is detected by a test signal input from outside the semiconductor substrate; detecting a power-on state between the main bump pad and each of the plurality of side bump pads; and determining whether a failure occurs based on the power-on state of each of the main bump pad and the plurality of side bump pads detected in the step of detecting the power-on state, The power-on state between the main bump pad and each of the plurality of side bump pads is detected to determine a bonding state between the bump pad unit and the first bump.

18. The test method according to claim 17, in, The step of determining whether a failure occurs includes determining that a failure of a bonding position between the first bump and the bump pad unit does not occur when the power-on states between the main bump pad and each of the plurality of side bump pads are all in a short circuit state.

19. The testing method according to claim 17, in, The step of determining whether a failure occurs includes determining that a failure of a bonding position between the first bump and the bump pad unit occurs when one of the power-on states between the main bump pad and each of the plurality of side bump pads is an open state.

20. The test method according to claim 17, in, The step of determining whether a failure occurs includes determining that a connection failure between the first bump and the bump pad unit occurs when the power-on states between the main bump pad and each of the plurality of side bump pads are all open circuit states.

21. The testing method according to claim 17, in, A semiconductor chip is disposed on the conductive structure, and The step of determining whether a failure occurs includes: when the power-on states between the main bump pad and each of the plurality of side bump pads are all in a short circuit state, determining that misalignment between the semiconductor substrate and the semiconductor chip does not occur.

22. The testing method according to claim 17, in, A semiconductor chip is disposed on the conductive structure, and Wherein, when determining whether a failure occurs, when at least one of the power-on states between the main bump pad and each of the plurality of side bump pads is an open state, it is determined that misalignment occurs between the semiconductor substrate and the semiconductor chip.

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