Compensation of low dropout voltage regulator

Abstract

The invention relates to compensation for low dropout voltage regulators. In one form, a low dropout voltage regulator configured to provide a drive signal to adjust an output voltage in response thereto includes an error amplifier, an intermediate amplifier, a buffer amplifier, and a compensation network. The error amplifier has a first input to receive a reference voltage, a second input to receive a feedback signal representative of the output voltage, a first output, and a second output. The intermediate amplifier has a first input coupled to the first output of the error amplifier, a second input coupled to the second output of the error amplifier, and an output. The buffer amplifier has a first input coupled to the output of the intermediate amplifier and an output to provide the drive signal. The compensation network has a first terminal coupled to the first input of the intermediate amplifier and a second terminal coupled to the output of the intermediate amplifier.

Description

Technical Field

[0001] This disclosure relates in general to voltage regulators, and more specifically to low dropout voltage regulators (LDOs). Background Technology

[0002] Linear regulators provide a direct current (DC) voltage from another DC voltage source. For example, a low-dropout regulator (LDO) is a linear regulator that controls the voltage drop across a channel element to regulate the output voltage to the desired level. LDOs are common in linear voltage regulation applications. An LDO is a linear regulator that provides an output voltage even when the desired output voltage is very close to the input voltage. An LDO typically includes an amplifier circuit, a channel element, and a reference circuit. The amplifier circuit adjusts the voltage drop across the channel element based on the output voltage and the reference voltage.

[0003] Figure 1 A known LDO 100 in the prior art is shown in partial block diagram and partial schematic diagram. The LDO 100 includes a reference voltage generator 101, an amplifier 102, a compensation capacitor 103, a compensation resistor 104, a parasitic capacitance 105, a buffer 106, a channel transistor 107, a first resistor 108, a second resistor 109, an output capacitor 110, and a third resistor 111. In operation, resistors 108 and 109 provide feedback signals based on the output voltage. Amplifier 102 provides an adjustment signal in response to the feedback signal and the reference voltage. Buffer 106 provides a drive signal to adjust the voltage drop across channel transistor 107 in response to the adjustment signal. Buffer 106 has a parasitic capacitance 105 at its input. Compensation capacitor 103 and compensation resistor 104 form a compensation network to mitigate the effect of parasitic capacitance 105; however, the frequency bandwidth is still limited.

[0004] LDOs are sensitive to changes in system supply voltage, charging noise, or other disturbances. The response time to these effects is limited by the LDO's bandwidth. Parasitic capacitances (such as...) Figure 1 The parasitic capacitance 105 in the LDO reduces the main frequency of the LDO and slows down the LDO's response to noise and other interference.

[0005] To provide good load transient performance, LDOs need to offer a reasonably large bandwidth, while also providing low current consumption and a small circuit area. Attached Figure Description

[0006] This disclosure will be better understood by referring to the accompanying drawings, in which many features and advantages of this disclosure will be apparent to those skilled in the art, as shown in the drawings:

[0007] Figure 1 A voltage regulator known in the prior art is shown in the form of a partial block diagram and a partial schematic diagram;

[0008] Figure 2 A voltage regulation circuit according to an embodiment of the present invention is shown in partial block diagram and partial schematic diagram.

[0009] Figure 3 The diagrams shown are in the form of partial block diagrams and partial schematic diagrams and can be used as... Figure 2 A voltage regulator;

[0010] Figure 4 A voltage regulator according to another embodiment of the present invention is shown in the form of a partial block diagram and a partial schematic diagram;

[0011] Figure 5 The diagrams and schematic representations show the possible uses of other embodiments. Figure 3 and Figure 4 The intermediate level of the intermediate level; and

[0012] Figure 6 The diagram shows a partial block diagram and a partial schematic diagram, illustrating a possible embodiment according to yet another embodiment. Figure 3 and Figure 4 Another intermediate level of the intermediate level; and

[0013] Figure 7 The diagram illustrates what can be used as a tool. Figure 3 and Figure 4 The differential amplifier of the differential amplifier.

[0014] The same reference numerals are used in different figures to indicate the same or similar elements. Unless otherwise stated, the word “coupled” and its associated verb form include both direct connection and indirect electrical connection by means known in the art; and unless otherwise stated, any description of direct connection also implies alternative embodiments using suitable forms of indirect electrical connection. Detailed Implementation

[0015] Figure 2 A voltage regulation circuit 200 according to an embodiment of the present invention is shown in partial block diagram and partial schematic diagram. The voltage regulation circuit 200 is a low-dropout regulation circuit that uses the polarity splitting effect to increase frequency bandwidth. The voltage regulation circuit 200 includes a low-dropout regulator (LDO) 201, a channel element 202, a first resistor 203, a second resistor 204, an input capacitor 205, and an output capacitor 206.

[0016] The LDO 201 is an integrated circuit that uses the polarity splitting effect to regulate the output voltage of a voltage regulation circuit 200 to increase the frequency bandwidth. The LDO 201 has a set of terminals labeled "GATE", "IN", "FB", and "GND". The IN terminal is connected to receive signals labeled "V". IN The input voltage source is the GND terminal, which is connected to ground. Channel element 202 is a P-channel metal-oxide-semiconductor (MOS) transistor with a source connected to the IN terminal of LDO 201 for supplying voltage to the load. Figure 2 (Not shown in the image) is marked "V" OUT The output voltage drain of the LDO 202 and the gate of the LDO 201 are connected to the GATE terminal. The first resistor 203 has a first terminal connected to the drain of the channel element 202 and a second terminal connected to the FB terminal of the LDO 201. The second resistor 204 has a first terminal connected to the FB terminal of the LDO 201 and a second terminal connected to ground. The input capacitor 205 has a first terminal connected to the IN terminal of the LDO 201 and a second terminal connected to primary ground. The output capacitor 206 has a first terminal connected to the drain of the channel element 202 and a second terminal connected to primary ground.

[0017] Input capacitor 205 makes the V at the input of voltage regulation circuit 200... IN Smoothing. Output capacitor 206 reduces the V at the output of voltage regulation circuit 200. OUT The instability of LDO 201 is due to the V at the IN terminal. IN powered by.

[0018] The first resistor 203 and the second resistor 204 form a feedback network that provides a V value representing a scaled-down value to the FB terminal of the LDO 201. OUT The LDO 201 uses the feedback signal to generate a gate drive signal to control the voltage drop across the channel element 202. For example, if the load current decreases, V... OUT The feedback signal will increase. In response, LDO 201 will increase the voltage across channel element 202 to increase V. OUT Reduce it to its target value.

[0019] Figure 3 The diagrams shown are in the form of partial block diagrams and partial schematic diagrams and can be used as... Figure 2 The regulator 300 is an integrated circuit LDO 201 that uses the polarity splitting effect to increase frequency bandwidth. The regulator 300 includes an IN terminal 301, a GND terminal 302, a GATE terminal 303, an FB terminal 304, a differential stage 310, an intermediate stage 320, and a buffer stage 330.

[0020] The differential amplifier 310 includes a voltage reference circuit 311 and a differential amplifier 312. The voltage reference circuit 311 has an input connected to the IN terminal 301 and an output for supplying a reference voltage. The differential amplifier 312 has a non-inverting input for receiving the reference voltage, an inverting input connected to the FB terminal 304, a power supply input connected to the IN terminal 301, a first output for providing the positive component of the differential output signal, and a second output for providing the negative component of the differential output signal.

[0021] Intermediate stage 320 includes intermediate amplifier 321, resistor element 322, and capacitor 323. Intermediate amplifier 321 has an inverting input connected to the second output of differential amplifier 312, a non-inverting input connected to the first output of differential amplifier 312, a power input connected to IN terminal 301, and an output for providing an intermediate signal. Resistor element 322 is an adjustable resistor having a first terminal and a second terminal connected to the inverting input of intermediate amplifier 321. Capacitor 323 has a first terminal connected to the second terminal of resistor element 322 and a second terminal connected to the output of intermediate amplifier 321.

[0022] The buffer stage 330 is an inverting buffer that has an input terminal connected to the output of the intermediate amplifier 321, a power input connected to the IN terminal 301, and an output for providing a drive signal.

[0023] In operation, the regulator 300 operates as an LDO and is suitable for use as... Figure 2 The voltage regulator 201 is an integrated circuit. The voltage regulator 300 regulates the output voltage (V) by generating a gate drive signal in response to a feedback signal received from the FB terminal 304 and a reference voltage output from the voltage reference circuit 311. OUT A parasitic capacitance exists at the input of buffer stage 330, which limits the bandwidth of the regulator. However, unlike known low-dropout regulators, regulator 300 includes an intermediate stage that provides a pole splitting effect to push the poles caused by the parasitic capacitance at the input of buffer stage 330 to higher frequencies, thereby increasing the bandwidth of the regulator.

[0024] Resistor 322 and capacitor 323 provide a compensation network between the inverting input and output of intermediate amplifier 321. The compensation network generates a low-frequency pole at the inverting input of intermediate amplifier 321. The frequency of the low-frequency pole is given by the following formula:

[0025]

[0026] Where C lfeq The equivalent capacitance is the pole, and R lfeq The equivalent resistance of the pole is C.lfeq It can be calculated as:

[0027]

[0028] Where C comp A1 is the capacitance of capacitor 323, A2 is the gain of differential amplifier 312, and A2 is the gain of intermediate amplifier 321. lfeq It can be calculated as:

[0029]

[0030] Where g m3 and g m2 This represents the transconductance component of the differential amplifier 312. According to formulas 1, 2, and 3, the frequency of the low-frequency stage can be calculated as:

[0031]

[0032] As mentioned earlier, parasitic capacitance exists at the input of buffer stage 330. This parasitic capacitance generates a high-frequency electrode, which limits the bandwidth of regulator 300. The frequency of the high-frequency electrode is given by the following formula:

[0033]

[0034] Where C hfeq The equivalent capacitance is the pole, and R hfeq The equivalent resistance of the pole is C. hfeq It can be calculated as:

[0035]

[0036] Where C parasitic This is the value of the parasitic capacitance, R. hfeq It can be calculated as:

[0037]

[0038] Where g dsi This represents the output conductance component of the intermediate amplifier 321. According to formulas 5, 6, and 7, the frequency of the high-frequency electrode can be calculated as:

[0039]

[0040] By using a compensation network, regulator 300 divides the high-frequency pole by the voltage gain A1 of differential amplifier 312 and the voltage gain A2 of intermediate amplifier 321, which pushes the high-frequency pole to a higher frequency, thereby increasing the bandwidth.

[0041] Figure 4A voltage regulator 400 according to another embodiment of the present invention is shown in partial block diagrams and partial schematic diagrams. The voltage regulator 400 is an LDO, and its operation is similar to... Figure 3 The voltage regulator 300 has some differences as described below. The voltage regulator 400 typically includes an input terminal 401 marked "IN", a ground terminal 402 marked "GND", an output terminal 403 marked "OUT", a differential stage 410, an intermediate stage 420, a buffer stage 330, an output stage 440, and a feedback stage 450.

[0042] The differential amplifier 410 includes a voltage reference circuit 411 and a differential amplifier 412. The voltage reference circuit 411 has an input connected to the IN terminal 401 and an output for supplying a reference voltage. The differential amplifier 412 has a non-inverting input for receiving the reference voltage, an inverting input for receiving a feedback voltage, a power supply input connected to the IN terminal 401, a first output for providing the positive component of the differential output signal, and a second output for providing the negative component of the differential output signal.

[0043] Intermediate stage 420 includes intermediate amplifier 421, resistor element 422, and capacitor 423. Intermediate amplifier 421 has an inverting input connected to the second output of differential amplifier 412, a non-inverting input connected to the first output of differential amplifier 412, a power input connected to IN terminal 401, and an output for providing an intermediate signal. Resistor element 422 is an adjustable resistor having a first terminal and a second terminal connected to the inverting input of intermediate amplifier 421. Capacitor 423 has a first terminal connected to the second terminal of resistor element 422 and a second terminal connected to the output of intermediate amplifier 421.

[0044] The buffer stage 430 is an inverting buffer that has an input terminal connected to the output of the intermediate amplifier 421, a power input connected to the IN terminal 401, and an output for providing a drive signal.

[0045] Output stage 440 is a P-channel metal-oxide-semiconductor (MOS) transistor having a source connected to IN terminal 401, a gate for receiving a drive signal, and a drain connected to OUT terminal 403. Feedback stage 450 has a first terminal connected to OUT terminal 403, a second terminal for providing a feedback signal, and a third terminal connected to GND terminal 402. Feedback stage 450 includes a first resistor 451 and a second resistor 452. Resistor 451 has a first terminal connected to OUT terminal 403 and a second terminal connected to the inverting input of differential amplifier 412. Resistor 452 has a first terminal connected to the second terminal of resistor 451 and a second terminal connected to GND terminal 402.

[0046] Apart from Figure 2 In addition to integrating channel element 202 and resistors 203 and 204 on the same die as output stage 440 and feedback stage 450, regulator 400 is used for Figure 2 In the voltage regulator circuit 200, when it is in conjunction with Figure 3 It operates in a similar manner to the voltage regulator 300.

[0047] Voltage regulators 300 and 400 offer applications such as Figure 1 An exemplary embodiment of a low-dropout regulator in the application of voltage regulation circuit 100. Resistive elements 322 and 422 are depicted as adjustable resistors. The resistance values ​​of resistive elements 322 and 422 can be adjusted during processing, during manufacturing, by the user, or in response to a voltage signal. In some embodiments, the feedback current decreases as the output voltage increases, and in these alternatives, differential amplifiers 312 and 412 and intermediate amplifiers 321 and 421 may switch their polarities to account for differences in feedback signal behavior. Although transistor 440 is shown as a P-channel MOS transistor, other embodiments may use other transistors, such as bipolar junction transistors (BJTs), junction gate field-effect transistors (JFETs), or N-channel MOS transistors.

[0048] Figure 5 The diagrams shown are in the form of partial block diagrams and partial schematic diagrams and can be used as... Figure 3 The intermediate 320 or Figure 4 The intermediate level 420 and the intermediate level 500. Intermediate level 500 behaves similarly to... Figure 3 The intermediate stage 320 is an intermediate stage, but with some differences as described below. Intermediate stage 500 includes an intermediate amplifier 521, a bias circuit 522, a transistor 523, and a capacitor 524. Intermediate amplifier 521 has an inverting input for receiving an inverted differential output signal, a non-inverting input for receiving a non-inverted differential output signal, and an output for providing an intermediate signal. Bias circuit 522 has a bias circuit for receiving V... OUT The intermediate amplifier 521 has an input and an output for providing a bias signal. Transistor 523 is a P-channel MOS transistor having a drain connected to the inverting input of intermediate amplifier 521, a gate for receiving the bias signal, and a source. Capacitor 524 has a first terminal connected to the source of transistor 523 and a second terminal connected to the output of intermediate amplifier 521.

[0049] In operation, the behavior of the intermediate level 500 is similar to Figure 3 The intermediate stage 320 is different in that the bias circuit 522 and transistor 523 are replaced. Figure 3 The resistor element 322. The bias circuit 522 receives V. out And provide a bias signal according to Vout Adjust the drain-source resistance of transistor 523. Transistor 523 generates zero, the position of which is changed by adjusting its drain-source resistance.

[0050] Figure 6 The diagrams shown are in the form of partial block diagrams and partial schematic diagrams and can be used as... Figure 3 The intermediate 320 or Figure 4 Another intermediate level, 600, is the intermediate level 420. Intermediate level 600 behaves similarly to... Figure 3 The intermediate stage 600 is an intermediate stage of intermediate stage 320, but with some differences as described below. Intermediate stage 600 includes intermediate amplifier 621, resistor 622, and capacitor 623. Intermediate amplifier 621 has an inverting input for receiving an inverted differential output signal, a non-inverting input for receiving a non-inverted differential output signal, and an output for providing an intermediate signal. Resistor 622 has a first terminal connected to the inverting input of intermediate amplifier 621, and a second terminal. Capacitor 623 has a first terminal connected to the second terminal of resistor 622, and a second terminal connected to the output of intermediate amplifier 621.

[0051] In operation, the intermediate level 600 behaves similarly to Figure 3 The intermediate stage 320 is different from the 622 resistor, which has a fixed resistance value.

[0052] Intermediate stages 320, 420, 500, and 600 provide exemplary implementations of intermediate stages for low-dropout regulators. By using intermediate stages, regulators 300 and 400 can have higher bandwidth, which allows for a faster response to disturbances such as charge noise and power supply noise.

[0053] Figure 7 The diagram illustrates what can be used as a tool. Figure 3 Differential amplifier 312 or Figure 4 Differential amplifier 412 and differential amplifier 700. Differential amplifier 700 behaves similarly to... Figure 3 The differential amplifier 700 is an amplifier chain of differential amplifier 312, but with some differences as described below. Differential amplifier 700 includes a first amplifier 711, a gain inverter 712, and a second amplifier 713. The first amplifier 711 has features for receiving a feedback signal (V0). FB The gain inverter 712 has an inverting input for receiving an inverted differential output signal and an output connected to the output of the first amplifier 711. The second amplifier 713 has an inverting input for receiving a reference voltage, a non-inverting input for receiving a reference voltage, and an output for providing a non-inverting differential output signal. FB It has a non-inverting input, an inverting input for receiving a reference voltage, and an output for providing an inverted differential output signal.

[0054] In operation, the differential amplifier 700 uses only a single-ended output amplifier. Figure 3 The differential amplifier 312.

[0055] Therefore, various implementations of regulators, intermediate stages, and their operation have been described. These implementations provide improved bandwidth for low-dropout regulators. They also provide improved power supply ripple rejection (PSRR) in DC / DC converters.

[0056] The subject matter disclosed above should be considered exemplary and not limiting, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the true scope of the claims. For example, specific values ​​of the start and end frequencies supported by the voltage regulator chip may vary in different embodiments. Furthermore, in other embodiments, Figure 2 and Figure 3 The different components of the voltage regulation circuit shown can be integrated on a single semiconductor chip or included in a single integrated circuit package.

[0057] In one form, a low-dropout regulator, in one configuration, provides a drive signal to adjust the output voltage in response to it, comprising an error amplifier, an intermediate amplifier, a buffer amplifier, and a compensation network. The error amplifier has a first input for receiving a reference voltage, a second input for receiving a feedback signal representing the output voltage, a first output, and a second output. The intermediate amplifier has a first input coupled to the first output of the error amplifier, a second input coupled to the second output of the error amplifier, and an output. The buffer amplifier has a first input coupled to the output of the intermediate amplifier and an output for providing the drive signal. The compensation network has a first terminal coupled to the first input of the intermediate amplifier and a second terminal coupled to the output of the intermediate amplifier.

[0058] According to one aspect, the error amplifier includes a first amplifier, a second amplifier, and a third amplifier. The first amplifier has a first input for receiving a feedback signal, a second input for receiving a reference voltage, and an output for providing a second output of the error amplifier. The second amplifier has a first input for receiving a feedback signal, a second input for receiving a reference voltage, and an output for providing a first output of the error amplifier. The third amplifier has an input coupled to the output of the second amplifier and an output coupled to the output of the first amplifier.

[0059] According to another aspect, the low-dropout regulator also includes an output transistor having a first current electrode for receiving an input voltage, a second current electrode for providing an output voltage, and a control electrode coupled to the output of a buffer amplifier. In this case, the output transistor may be a p-channel MOSFET. Furthermore, the regulator may also include a voltage divider circuit having a first terminal coupled to the second current electrode of the output transistor, a second terminal coupled to the second input of an error amplifier, and a third terminal coupled to a power supply terminal.

[0060] In another form, the voltage regulation circuit includes a differential stage, an intermediate stage, a buffer stage, an output stage, and a feedback stage. The differential stage has an output for providing a differential signal in response to the difference between a feedback signal and a reference signal. The intermediate stage responds to the differential signal and has an output for providing a first output signal, wherein the intermediate stage includes a compensation network for providing a polarity splitting effect to the differential signal and the first output signal. The buffer stage responds to the first output signal and has an output for providing a buffered signal. The output stage responds to the buffered signal and has an output for providing an output voltage. The feedback stage provides a feedback signal in response to the output voltage.

[0061] According to one aspect, the compensation network includes a series combination of a resistive element and a capacitor coupled between the input and output of an intermediate stage, wherein the capacitor has a defined electrode size, the frequency of which is lower than the frequency of the electrode generated by the parasitic capacitance at the input of the buffer stage, and the frequency of the electrode is also proportional to the gain of the intermediate stage. In this case, the resistive element may have an adjustable resistance value. The resistive element may also be an adjustable resistive circuit including a transistor having a control input for changing the adjustable resistance value in response to the output voltage.

[0062] According to another aspect, the differential amplifier includes a first amplifier, a second amplifier, and a third amplifier. The first amplifier has a first input for receiving a feedback signal, a second input for receiving a first reference voltage, and an output for providing a first component of the differential signal. The second amplifier has a first input for receiving a feedback signal, a second input for receiving a second reference voltage, and an output for providing a second component of the differential signal. The third amplifier has an input coupled to the output of the second amplifier and an output coupled to the output of the first amplifier.

[0063] On the other hand, differential stages, intermediate stages, buffer stages, output stages, and feedback stages are combined within a single integrated circuit chip.

[0064] According to another aspect, the differential stage, intermediate stage, and buffer stage are combined within the integrated circuit package, while the output stage and feedback stage are outside the integrated circuit package.

[0065] In another form, the method for regulating voltage includes: amplifying the difference between a feedback voltage and a reference voltage proportional to the output voltage to form a differential signal, wherein the differential signal has positive and negative components; compensating the differential signal; amplifying the intermediate signal to provide a buffer signal; and using the buffer signal to generate the output voltage. The compensation includes: amplifying the differential signal to provide an intermediate signal; and adjusting the intermediate signal with a capacitance between the negative component of the differential signal and the intermediate signal. According to one aspect, the resistor is adjusted in response to modulation of the output voltage.

[0066] Therefore, to the fullest extent permitted by law, the scope of this invention shall be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be constrained or limited by the detailed description above.

Claims

1. A low dropout regulator providing a drive signal in a configuration to adjust an output voltage in response thereto, comprising: an error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback signal representative of the output voltage, a first output, and a second output; an intermediate amplifier having a first input coupled to the first output of the error amplifier, a second input coupled to the second output of the error amplifier, and an output; a buffer amplifier having a first input coupled to the output of the intermediate amplifier, and an output for providing the drive signal; and a compensation network having a first terminal coupled to the first input of the intermediate amplifier, and a second terminal coupled to the output of the intermediate amplifier, and formed from a series combination of a resistor element having an adjustable resistance value and a capacitor coupled between the first input of the intermediate amplifier and the output of the intermediate amplifier, wherein the compensation network pushes a pole frequency produced by a parasitic capacitance at an input of the buffer amplifier to a higher frequency based on a gain of the intermediate amplifier.

2. The low dropout regulator of claim 1, wherein the capacitor has a size defining a low frequency pole, the low frequency pole having a frequency lower than the pole frequency produced by the parasitic capacitance, and the low frequency pole having a frequency further proportional to a gain of the intermediate amplifier.

3. The low dropout regulator of claim 1, wherein the resistor element is an adjustable resistance circuit including a transistor having a control input for varying the adjustable resistance value in response to the output voltage.

4. A voltage regulation circuit, comprising: a differential stage having an output for providing a differential signal in response to a difference between a feedback signal and a reference signal; an intermediate stage responsive to the differential signal, the intermediate stage having an output for providing a first output signal, wherein the intermediate stage includes a compensation network formed from a series combination of an adjustable resistance element and a capacitor coupled between an input of the intermediate stage and the output of the intermediate stage for providing a pole splitting effect to the differential signal and the first output signal; a buffer stage responsive to the first output signal, the buffer stage having an output for providing a buffer signal, wherein the compensation network pushes a pole frequency produced by a parasitic capacitance at an input of the buffer stage to a higher frequency based on a gain of the intermediate stage; an output stage responsive to the buffer signal, the output stage having an output for providing an output voltage; and a feedback stage for providing the feedback signal in response to the output voltage. ​ ​ ​ 5. The voltage regulation circuit of claim 4, wherein the capacitor has a size that defines a low frequency pole, the low frequency pole having a frequency lower than the frequency of the pole created by the parasitic capacitance, and the low frequency pole having a frequency that is also proportional to a gain of the intermediate stage.

6. A method for regulating a voltage, the method comprising: amplifying a difference between a feedback voltage proportional to an output voltage and a reference voltage to form a differential signal, wherein the differential signal has a positive component and a negative component; and compensating the differential signal, wherein the compensating comprises: amplifying the differential signal to provide an intermediate signal; and adjusting the intermediate signal with a series capacitance and adjustable resistance between the negative component of the differential signal and the intermediate signal, amplifying the intermediate signal to provide a buffered signal, wherein the adjusting comprises pushing a frequency of a pole created by a parasitic capacitance associated with amplifying the intermediate signal to a higher frequency based on a gain of amplifying the differential signal; and generating the output voltage using the buffered signal.

7. The method of claim 6, wherein the compensating further comprises: adjusting a resistance between the negative component of the differential signal and the intermediate signal.

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