Memory devices and memory device operation methods

Abstract

This invention discloses a memory device and a method for operating the memory device, for field-configurable bad block repair of a memory array comprising multiple blocks, utilizing a block repair information memory to identify data of one or more bad blocks in the array. The block repair information memory includes at least one-write-once non-volatile memory. The block repair circuitry on the device is configurable to redirect commands to access bad blocks identified in the bad block repair data memory into reserved blocks in the memory array. A controller responds to the command to write bad block repair data, such as identifiers of bad blocks among the multiple blocks, into the field-configured block repair information memory, and uses the updated data to reconfigure the field-configured block repair circuitry.

Description

Technical Field

[0001] This disclosure relates to the repair of bad blocks in a large memory device comprising NAND flash memory. Background Technology

[0002] Large memory arrays, containing large NAND gate flash memory, may not be perfect; their specifications may allow for approximately 2% or more bad blocks in the array during the device's lifespan. Bad blocks can cause problems for users in some cases.

[0003] Bad block redundancy repair methods have been configured in some types of memory. In the factory, these techniques replace a limited number of bad blocks with redundant blocks using fuse circuits or similar circuitry, thus redirecting access to the bad blocks back to an additional set of blocks built into the device and located outside the user-addressable memory portion. This typical redundancy repair operation cannot satisfy blocks that become corrupted during field operation, nor can it satisfy the large number of blocks that may be encountered on large NAND gate flash memory devices.

[0004] Therefore, there is a need for a technology that allows for greater resilience in repairing bad blocks in large memories, including methods for repairing bad blocks in the field. Summary of the Invention

[0005] This disclosure describes a technique that supports field-configurable bad block repair for large-scale integrated circuit memories.

[0006] This disclosure describes a memory device comprising a large NAND gate flash memory array, the memory array including multiple blocks for storing data. A block repair information memory is provided for identifying signals of one or more bad blocks among the multiple blocks. The block repair information memory includes at least one-write-once non-volatile memory. Block repair circuitry on the device can be configured with a redirection command to access bad blocks identified in the bad block repair information memory into reserved blocks in the memory array. A controller, in response to the command, writes identifiers of the bad blocks among the multiple blocks into the block repair information memory and, in response to a block repair event, configures the block repair circuitry using data in the block repair information memory. If the block repair information memory is not part of the block repair circuitry, block repair data is copied from the block repair information memory to the block repair circuitry.

[0007] In the embodiments described in this disclosure, the block repair information memory can be updated, the block repair circuit can be automatically updated, and block repair can be performed in response to field commands.

[0008] In the embodiments described below, the memory array includes available regions, each containing multiple blocks, while reserved blocks comprise a set of hidden blocks outside the available regions. In other embodiments, reserved blocks comprise blocks within the available regions that can be identified in block repair information. In other embodiments, both hidden reserved blocks and reserved blocks within the available regions can be utilized. Furthermore, the controller can, in response to a command, write a list of reserved blocks from at least one available region into the block repair information memory.

[0009] This technology can be implemented in a NAND flash memory array containing multiple NAND gate blocks for storing signals. The block repair circuit can be field-configured with redirection commands to access bad blocks identified in the block repair information memory to reserved blocks in the memory array.

[0010] In addition, a method for operating a memory device to perform field-configurable bad block repair is provided.

[0011] In general, the technology provided in this case increases the flexibility of block repair operations for large memory, enabling more reliable use of memory in the field.

[0012] Other embodiments and advantages of the invention can be seen by reviewing the following figures, detailed description and scope of claims. Attached Figure Description

[0013] Figure 1 This is a block diagram showing the host and an integrated circuit memory device containing field-configurable block repair circuitry.

[0014] Figure 2 The diagram shows how it can be used as Figure 1 The block repair list maintained by the controller of the device shown.

[0015] Figure 3 The diagram illustrates on-site configurable block repair in a system that employs hidden reserved blocks.

[0016] Figure 4 The diagram illustrates on-site configurable block repair in a system that employs both hidden blocks and available reserved blocks.

[0017] Figure 5 It is a flowchart of an executable program that supports on-site configurable bad block repair.

[0018] Figure 6 It is a flowchart of another executable program that supports on-site configurable bad block repair.

[0019] Figure 7 It is a flowchart of another executable program that supports on-site configurable bad block repair.

[0020] [Symbol Explanation]

[0021] 102: Host

[0022] 108: Memory device

[0023] 114, 116, 126: Signal lines

[0024] 118: Input / Output Interface

[0025] 128: Cache circuit

[0026] 134: Command decoder / control circuit (field-configurable block repair and listing)

[0027] 145, 165: Arrows

[0028] 158: Page Buffer Circuit

[0029] 164: Bias setting power supply voltage

[0030] 166: Bitline

[0031] 172: Line decoder

[0032] 176: Column decoder

[0033] 177: Word Line

[0034] 178: Memory Array

[0035] 179: Block Repair Information Table

[0036] 300: Block Repair List

[0037] 301: Bad Block

[0038] 401, 501: Stack

[0039] 402, 403, 502, 503: Areas

[0040] 410, 510: Block Repair Information Table

[0041] 600, 601, 602, 603, 700, 701, 702, 800, 801, 802: Operation Detailed Implementation

[0042] The detailed description of the embodiments of this disclosure is based on... Figures 1-7 supply.

[0043] Figure 1This is a simplified schematic diagram of a memory system that includes a NAND flash memory device 108 implemented with integrated circuits and a host 102. As an example, the memory system includes field-configurable block repair logic as described in this disclosure.

[0044] In various embodiments, the memory device 108 can be implemented as a single integrated circuit chip, a multi-chip module, or configured as multiple chips to suit specific needs. In other embodiments of this disclosure, the memory device may have other types of non-volatile memory cells, including programmable resistance memory cells, metal oxide memory cells, magnetoresistive memory cells, or phase-change based memory cells, etc.

[0045] In this disclosure, the memory array 178 can be implemented as a two-dimensional or three-dimensional array of NAND gate flash memory. The memory array 178 is arranged in an array of blocks containing multiple memory cells. A block of memory cells contains memory cells within a specific range of addresses in the memory array and is said to have a block address. In some embodiments of the flash memory, during an erase operation, an erase operation performed on a sector in the memory array can be electrically separated from other sectors. A block of memory cells may contain a single sector and thus can be used as an erase region. In other embodiments, a block of memory cells for the purposes of this disclosure may contain more than one sector or a configuration of other memory cells.

[0046] Input / output interface 118 is included to provide address and data on a shared online basis via address / data bus 114. Additionally, a serial interface can also be configured.

[0047] Column decoder 176 is coupled to multiple word lines 177 arranged along columns in memory array 178. Word line decoders are included within column decoder 176. Page buffer circuits 158 are coupled to multiple bit lines 166 arranged along rows in memory array 178 for reading and writing data from memory array 178. Addresses from host 102 are provided on line 114 to row decoder 172 and column decoder 176 via input / output interface 118 and control circuitry 134 implementing command decoder and controller modules. Row decoder 172 is coupled to cache circuitry 128, and column decoder 176 is coupled to word lines 177. In one implementation, the page buffer may have the same width as the memory array.

[0048] Page buffer circuit 158 ​​is coupled to cache circuit 128 via data line 126 and stores data pages. Bit line 166 is coupled to page buffer circuit 158 ​​and memory array. Bit line 166 may include global bit lines (GBLs) and local bit lines. Bit lines are typically contained within conductors in higher patterned layers. These conductors can pass through multiple blocks or sectors of memory cells in the array and are connected to the local bit lines within the blocks via selected transistors. The local bit lines are connected to the memory cells, allowing current to flow in and out of the bit lines, which in turn connect to bit line 166 and page buffer circuit 158.

[0049] During a read operation, data from the page buffer circuit 158 ​​is provided to the cache circuit 128 via data line 126, which in this example is coupled to the input / output interface 118 via data line 116. Furthermore, in this example, input data is applied from the input / output interface 118 to the cache circuit 128 via data line 116 and to the page buffer circuit 158 ​​via data line 126 to support write operations.

[0050] Input / output interface 118 provides a communication path to the destination of data outside of memory device 108. Input / output data and control signals are transferred between input / output interface 118 and control circuitry 134 via data line 114. In some embodiments, other data sources, such as general-purpose processors or special-purpose application circuitry, may be included inside or outside of memory device 108, or a combination of modules that provide the system-on-a-chip functionality supported by memory array 178.

[0051] In such Figure 1In the example shown, control circuitry 134 includes a control module configured as one or more bias setting state machines for controlling applications related to multiple operating voltages. These operating voltages are generated or supplied by one or more power supplies in block (bias setting power supply voltage) 164. Applications of these operating voltages include read voltages, erase voltages, verification voltages, and programming voltages including pre-charge voltages, used for a range of optional programming and read operations. As indicated by arrow 165, the power supply voltage is applied to memory device 108. As indicated by arrow 145, control circuit signals are distributed to circuitry within memory device 108.

[0052] The control circuit 134 is coupled to the cache circuit 128, the memory array 178, and other components required for the integrated circuit.

[0053] Control circuitry 134 may include modules for using special-purpose logic circuitry, which includes state machines as known in the art. In an alternative embodiment, control circuitry 134 may include modules for using a general-purpose processor, which may be implemented on the same integrated circuit for executing a calculator program to control the operation of memory device 108. In still other embodiments, modules of control circuitry 134 may be implemented using a combination of special-purpose logic circuitry and a general-purpose processor.

[0054] As described in this disclosure, control circuitry 134 includes field-configurable bad block repair circuitry. The field-configurable bad block repair circuitry may include circuitry or memory for identifying a list of reserved blocks, and circuitry or memory for providing an image of bad blocks and reserved blocks in an array of lists. The field-configurable bad block repair circuitry may include circuit components such as lookup tables, configuration buffers, content-addressable memory, comparators, and enable and disable circuitry. The field-configurable bad block repair circuitry can be configured by writing data to the lookup table, configuration buffer, or content-addressable memory.

[0055] Block Repair Information (BRI) table 179 can be used to configure bad block repair circuitry by transmitting information to the circuitry in a list or mapping or both. Furthermore, Block Repair Information table 179 can be part of the bad block repair circuitry. Block Repair Information table 179 can be stored in non-volatile memory on the device, such as in a pre-defined area of ​​memory array 178. In other embodiments, Block Repair Information table 179 can be stored in a configuration buffer located on other parts of memory device 108 and can be written to at least once. This configuration buffer can comprise flash memory cells or other types of non-volatile memory cells suitable for a particular embodiment.

[0056] The field-configurable bad block repair circuitry can retrieve or read block repair information table 179 in response to a block repair event. A block repair event can occur at the end of an operation using the memory, or as a reset event, such as during chip power-on initialization, upon completion of an operation to identify additional reserved blocks or additional bad blocks for repair, at the end of an operation to write the bad block identifier, or in response to other types of events, such as timer timeouts or host-issued reset signals. Block repair events can occur automatically on the device by the controller during operation, without user intervention. The block repair information can be used to configure circuitry to mirror user commands that redirect access to bad blocks to the reserved blocks identified by the information.

[0057] Memory array 178 may include floating gate memory cells or dielectric charge trapping memory cells, each capable of storing multiple bits. Threshold voltage V of the memory cells is sequentially established by creating multiple programming potentials corresponding to the amount of stored charge. T This technology can be used in flash memory with a single bit per memory cell, as well as multi-level memory cells (such as MLC, TLC, or XLC) with multiple bits per memory cell (each memory cell storing more than one bit), and single-bit memory technologies (single-level memory cell (SLC)). In other examples, memory cells may include programmable resistive memory cells, phase-change memory cells, and other types of non-volatile and volatile memory cell technologies.

[0058] In the illustrated example, host 102 is coupled to address lines 144 and data lines 114 on memory device 108, as well as other control terminals not shown, such as chip select terminals, etc., and host 102 can provide commands or instructions to memory device 108 in the field. In some examples, host 102 may be coupled to memory device using serial bus technology, using shared address and data lines. Host 102 may include a general-purpose processor, a special-purpose processor, a processor configured as a memory controller, or other processor using memory device 108. All or part of host 102 may be implemented on the same integrated circuit as the memory.

[0059] Host 102 may include one or more file systems that store, restore, and update data stored in memory based on requests from one or more applications. Generally, host 102 may also include programs that perform memory management functions and other functions that generate status information for the data stored in memory, including information marking data as invalid due to these functions. These functions may include, for example, wear leveling, bad block recovery, power loss recovery, garbage collection, error correction, etc. Furthermore, host 102 may include applications, file systems, flash translation layer programs, and other components that generate status information for the data stored in memory, including information marking data as invalid due to these functions.

[0060] For clarity, the circuit is described as "field-configurable" or "responding to field commands" because it is designed to be configured post-manufacturing via on-chip logic or via a customer or user. Examples of field-configurable circuitry include writing data to a block repair information table in response to the detection of bad blocks by error detection logic; writing data to the block repair information table in response to a user command originating from the host system identifying bad blocks; writing data to block repair information table 179 in response to a user command originating from the host system identifying reserved blocks; and resetting and re-establishing the block repair list in control circuitry 134.

[0061] Figure 2 This is a schematic diagram of a block repair list 300, which can be stored in a register accessible by the control circuitry 134. In this example, the block repair list 300 contains a first line listing reserved blocks. In this example, the reserved blocks include hidden blocks 0-5 and reserved blocks 1018-1021 for the available area. A register associated with each reserved block stores the address of the bad block mapped to the corresponding reserved block. Therefore, in this example, bad block 2 is mapped to hidden block 0. Bad block 6 is mapped to hidden block 1. The next reserved block for repairing bad blocks can be identified in the repair circuitry by indicating "next repair" in the next register in the temporary file.

[0062] In operation, the bad block repair circuit can read a list of bad blocks from a block repair information table and repair them sequentially, for example, by mapping the first bad block to the first reserved block, the second bad block to the second reserved block, and so on. Furthermore, the block repair information table can identify bad reserved blocks (e.g., bad block 301) and bad reserved blocks that can be skipped during the repair process.

[0063] Figure 3 This is a diagram illustrating the block repair operation. Figure 3The available area of ​​memory array region 403 is illustrated, comprising blocks 0 to 1023. Reserved blocks are hidden blocks 0 to 5 in region 402, located outside the user-accessible address space. Block repair information table 410, outside the normal area of ​​the memory array, is illustrated in this example, such as special non-volatile temporary files accessible by the controller.

[0064] The block repair circuitry is represented by stack 401, which contains one input for each reserved block. During configuration operations, such as after a memory device reset, the block repair circuitry maps bad block 2 to a first reserved block and bad block 4 to a second reserved block. Additional bad blocks in the available areas of memory array region 403 can be sequentially mapped until all hidden reserved blocks in region 402 have been used.

[0065] Figure 4 This is a schematic diagram of block repair operations in a selective embodiment, which includes both hidden blocks and reserved blocks of available areas. Figure 4 In this example, the available area of ​​memory array region 503 contains blocks 0 to 1023. The hidden area of ​​memory array region 502 contains hidden blocks. A list of reserved blocks containing the available area of ​​blocks 1017 to 1021 is stored in block repair data table 510 for use by the block repair circuitry. In this example, block repair data table 510 is stored in the user-addressable area of ​​the memory array.

[0066] In this example, there are three hidden blocks, from block 0 to block 2. However, in this example, hidden block 1 is a bad block.

[0067] The block repair circuitry is represented by stack 501, which contains the inputs for each good hidden block, omitting hidden block 1 since it is bad. The block repair circuitry first uses the hidden blocks to map bad block 2 to hidden block 0, and bad block 4 to hidden block 2. Starting with the first reserved block 1017, subsequent bad blocks, including bad block 7, are sequentially mapped to reserved blocks in the available area. Utilizing the reserved blocks in the available area specified by the user in the block repair data table 510, additional techniques are provided to the user to configure the memory array to handle various bad block conditions.

[0068] By using field-configurable circuitry such as FPGA circuits or general-purpose processors, the field-configurable block repair circuitry can be contained within a state machine implemented in hardware. For a description of the functions performed by the repair circuitry, please refer to [reference needed]. Figures 5-7 .

[0069] Figure 5 This illustrates a function executed by the controller for dynamic field bad block repair. Figure 5In the sequence shown, this procedure begins with a block repair event received in the field (e.g., operation 600). A block repair event can occur at the end of an operation using memory, or as a reset event, such as during chip power-on initialization, upon completion of an operation to identify and repair additional reserved blocks or bad blocks, at the end of an operation to write the bad block identifier, or in response to other types of events, such as timer timeouts or host reset signals. Upon detecting or receiving a block repair event, the controller reads block repair data from the non-volatile block repair information memory on the device (e.g., operation 601). The controller uses the data read from the block repair information memory to create a block repair table in a register file accessible to the controller (e.g., operation 602). After the block repair table is created in the controller, the controller maps user access to add blocks to reserved blocks (e.g., operation 603).

[0070] Figure 6 This diagram illustrates a function performed by the controller when a bad block is detected. In this procedure, a command is received to write the bad block identifier into the list of blocks to be repaired (e.g., operation 700). In response to the command received in the field, the bad block data is stored in the block repair information memory on the device (e.g., operation 701). Finally, on one event, such as at the end of the operation of writing the bad block identifier or during the operation, or on another event selected according to a specific implementation, the block repair circuitry is reconfigured to repair the bad blocks identified in the field (e.g., operation 702).

[0071] Figure 7 Another function performed by the controller is illustrated to extend the device's ability to repair bad blocks. In this procedure, a command is received to add a reserved block to the reserved blocks available for use by the block repair circuitry (e.g., operation 800). In response to the command received in the field, the block repair circuitry is able to store the reserved block data into the block repair information memory (e.g., operation 801). Finally, on an event such as the end of the operation of adding the reserved block to the block repair memory or during the operation, the block repair circuitry is reconfigured to repair bad blocks using the newly identified reserved blocks (e.g., operation 802).

[0072] Therefore, this disclosure describes a technique for providing a set of reserved blocks on an integrated circuit memory, such as a large NAND gate flash memory array, for the purpose of repairing blocks. Reserved blocks may include hidden blocks, and in addition to hidden blocks that may be used for redundancy repair during manufacturing, reserved blocks may, for example, include reserved blocks in available areas specified by user commands in the field. Furthermore, reserved blocks may include both hidden blocks and reserved blocks in available areas.

[0073] In the examples of this disclosure, block repair data is established in the controller based on the reserved block group. Bad block repair can be implemented using block repair commands, which write the bad block addresses into a block repair data table. The data is established in the field controller. For example, data can be written to the table during block repair events such as when an operation using memory ends, such as a reset event that may occur during chip power-on initialization, and after the user adds additional reserved blocks or additional bad blocks for block repair.

[0074] The field-configurable bad block repair described in this disclosure can resolve some system failure scenarios that may be caused by field block failures. Embodiments can be configured using NOR flash memory, where all bad blocks in the memory device can be repaired, thereby achieving a highly reliable device in the field without any visible bad blocks to the user. Embodiments can be configured with large embedded NAND flash memory, and repair can be focused on certain areas with higher reliability specifications than other areas, so the number of bad blocks in any given area is within the requirements of the application using the device.

[0075] Several flowcharts are described herein, illustrating logic executed by a memory device or memory controller. This logic can be implemented using a processor programmed with a computer program stored in memory accessible to the computer system and executed by the processor, special-purpose logic hardware including field-programmable integrated circuits, or a combination of a computer program and special-purpose logic hardware. For all flowcharts in this disclosure, it will be understood that numerous steps can be combined, executed in parallel, or executed in different orders without affecting the functionality achieved. In some cases, as the reader will understand, rearranging the steps will only yield the same result if certain other changes are made. In other cases, as the reader will understand, rearranging the steps will only achieve the same result if certain conditions are met. Furthermore, it will be understood that the flowcharts of this disclosure only show steps relevant to understanding the contents of this disclosure, and it will be understood that numerous additional steps for performing other functions may be performed before, after, and between the steps shown.

[0076] Although this disclosure has been made with reference to the embodiments and examples described in the foregoing detailed description, it should be understood that these examples are exemplary only and not restrictive. Those skilled in the art can make various modifications, combinations, and refinements without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. A memory device comprising: An array of memories on an integrated circuit contains multiple blocks for storing data; A block repair information memory for identifying block repair data of one or more bad blocks among the plurality of blocks, the block repair information memory comprising non-volatile memory on an integrated circuit and capable of being written at least once; A block repair circuit is used to configure redirection commands in the field to access bad blocks identified in the block repair information memory to reserved blocks in the memory array; as well as A controller, in response to an event in the field, writes the block repair data into the block repair information memory.

2. The memory device of claim 1, wherein the memory array includes an available region comprising a plurality of blocks, and reserved blocks comprise a set of hidden blocks outside the available region.

3. The memory device of claim 1, wherein the memory array includes an available region comprising a plurality of blocks, the reserved blocks comprising blocks listed in the available region in the block repair information memory.

4. The memory device of claim 1, wherein the memory array includes an available region comprising a plurality of blocks, the reserved blocks comprising a list of blocks in the available region in the block repair information memory, and the controller, in response to a command, writes a list of available region reserved blocks into the block repair information memory.

5. The memory device of claim 1, wherein the memory array includes an available region comprising a plurality of blocks, the reserved blocks comprising blocks listed in the available region in the block repair information memory, and a set of hidden blocks outside the available region.

6. The memory device of claim 1, wherein the block repair event includes a power-on reset of the device.

7. The memory device of claim 1, wherein the block repair information memory is contained in a region of the memory array.

8. The memory device of claim 1, wherein the memory array comprises NAND gate flash memory.

9. The memory device of claim 1, wherein the controller, in response to a command in the field, writes an identifier of a bad block among the plurality of blocks into the block repair information memory, and in response to a block repair event in the field, configures the block repair circuitry using data in the block repair information memory.

10. The memory device of claim 1, wherein the controller includes circuitry for configuring the block repair circuitry by mapping bad blocks identified in the block repair information memory to reserved blocks in a reserved block list.

11. The memory device of claim 1, wherein the controller includes circuitry for configuring the block repair circuitry by mapping bad blocks identified in the block repair information memory to reserved blocks in a reserved block list, wherein the block repair circuitry skips bad reserved blocks.

12. A memory device comprising: A NAND gate flash memory array on an integrated circuit contains multiple blocks for storing data; A block repair information memory for identifying data of one or more bad blocks in a plurality of blocks, the block repair information memory comprising non-volatile memory on an integrated circuit and capable of being written at least once; A block repair circuit is used to configure redirection commands in the field to access bad blocks identified in the block repair information memory to reserved blocks in the memory array; as well as A controller, in response to a command in the field, writes an identifier of a bad block in one of the plurality of blocks into the block repair information memory.

13. A method of operating a memory device, wherein the memory includes a memory array on an integrated circuit, the memory array including a plurality of blocks for storing data, the method of operating the memory device comprising: Data identifying one or more bad blocks from multiple blocks is stored in a block repair information memory on the device, the block repair information memory comprising non-volatile memory on an integrated circuit and capable of being written at least once; In response to a command provided to the integrated circuit from the field, an identifier of a bad block in the plurality of blocks is written into the block repair information memory; as well as In response to a block repair event, a block repair circuit is configured to use a field-configured redirection command to access bad blocks identified in the block repair information memory to reserved blocks in the memory array.

14. The method of operating a memory device as claimed in claim 13, wherein the memory array includes an available region comprising a plurality of blocks, and reserved blocks comprise a set of hidden blocks outside the available region.

15. The memory device operation method of claim 13, wherein the memory array includes an available region comprising a plurality of blocks, the reserved blocks including blocks listed in the available region in the block repair information memory.

16. The memory device operation method of claim 13, wherein the memory array includes an available region, the available region includes a plurality of blocks, the reserved blocks include a list of blocks in the available region in a block repair information memory, and includes writing a list of the reserved blocks in the available region into the block repair information memory.

17. The memory device operation method of claim 13, wherein the memory array includes an available region comprising a plurality of blocks, the reserved blocks comprising blocks listed within the available region in the block repair information memory, and a set of hidden blocks outside the available region.

18. The memory device operation method of claim 13, wherein the block repair event includes a power-on reset of the device.

19. The method of operating a memory device as claimed in claim 13, wherein the block repair information memory is contained in a region of the memory array.

20. The method of operating a memory device as claimed in claim 13, wherein the memory array comprises NOT gate flash memory.

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