Internal loopback of input / output circuit

Abstract

The present invention is entitled "Internal Loopback of Input / Output Circuits". The present invention discloses technologies for semiconductor dies and control operations of semiconductor dies. In some aspects, the semiconductor die is configured to test the I / O circuits on the semiconductor die. The semiconductor die has an input circuit that compares a voltage signal at one of a first input or a second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The first input is connectable to an I / O contact. During normal mode, a control circuit on the die provides a reference voltage to the second input. During test mode, the control circuit internally loops back a test signal from the output circuit to the second input of the input circuit. Thus, the test signal avoids the I / O contacts.

Description

Background Art

[0001] Semiconductor dies typically have input / output (I / O) circuits to allow data input and data output. The input / output circuits may provide other functions, such as allowing control signals to be provided to the semiconductor die. Typically, the semiconductor die has some type of I / O contacts that provide an electrical interface to the semiconductor die to allow input / output of data, control signals, etc. The I / O contacts may include, for example, contact pads on the surface of the semiconductor die. Depending on the context, the I / O contacts may include other conductive elements. For example, the semiconductor die may be placed in a package having contact pins electrically connected to the contact pads.

[0002] As an example, a semiconductor die may contain memory and I / O circuitry that is accessible via I / O contacts to allow data to be stored in and retrieved from the memory. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Such semiconductor dies are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Like numbered elements refer to common parts in different figures.

[0004] Figure 1 is a functional block diagram of one embodiment of a memory device.

[0005] Figure 2 is a block diagram depicting one embodiment of a memory system.

[0006] Figure 3 One embodiment of a semiconductor die is depicted.

[0007] Figure 4 One embodiment of a memory die is depicted.

[0008] Figure 5 One embodiment of a portion of an input / output circuit connected to an I / O contact is depicted.

[0009] Fig. 6A Depicted Figure 5 Input / output circuits wherein the switching logic is in a position usable during normal operating mode.

[0010] Figure 6B Depicted Figure 5Input / output circuitry of the present invention wherein the switching logic is in a position usable during a test mode of operation.

[0011] Figure 7 A flow chart depicting one embodiment of a process for operating a data input circuit in two modes.

[0012] Figure 8 A flow chart of one embodiment of a process of controlling a semiconductor die during a test mode is depicted.

[0013] Fig. 9 A flow chart of one embodiment of a process for controlling a memory die in normal mode is depicted.

[0014] Fig.10 is a schematic diagram of one embodiment of a portion of a data output circuit.

[0015] Fig.11 is a schematic diagram of one embodiment of a portion of a data input circuit. DETAILED DESCRIPTION

[0016] The present invention discloses a technology for semiconductor die and control operation of semiconductor die. Some embodiments include a semiconductor die configured to test an I / O circuit on the semiconductor die. In one embodiment, the semiconductor die has an input circuit associated with a first I / O contact and an output circuit associated with a second I / O contact. The input circuit may have a first input and a second input. The input circuit may be configured to compare a voltage signal at one of the first input or the second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. Herein, "voltage signal" refers to a voltage that switches back and forth between two states (e.g., between two voltages). In contrast, the reference voltage does not switch back and forth between two states. The result of the comparison is referred to as the input voltage signal in this article.

[0017] The first input of the input circuit may be connected to the first I / O contact. In one embodiment, the semiconductor die has a control circuit that is configured to operate in a first mode in which the control circuit provides a reference voltage to a second input of the input circuit. During the first mode, a voltage signal at the first I / O contact may be provided to the first input. In one embodiment, the control circuit is further configured to operate in a second mode in which the control circuit provides a voltage signal from the output circuit to the second input of the input circuit. The second mode may be a test mode in which the control circuit internally loops a test voltage signal from the output circuit back to the input circuit. Thus, the entire input circuit and substantially the entire output circuit may be tested. During the first mode, a reference voltage at the first I / O contact may be provided to the first input. Under some conditions, it may be impractical or expensive to provide a voltage signal to the first input via the first I / O contact. For example, in a test environment, it may be impractical or expensive to provide a high-speed voltage signal to the first input via the first I / O contact.

[0018] Under at least some conditions, the I / O contacts may have high capacitance. For example, the I / O contacts may have high capacitance during die sorting (also known as wafer sorting). Die sorting refers to testing memory dies after manufacturing. As a result of such testing, the tested semiconductor dies may be sorted for different usage categories. For example, the best performing semiconductor dies may be sorted for the most demanding uses, and semiconductor dies that perform less well but are still at an acceptable level are sorted for less demanding uses. Some semiconductor dies may be discarded.

[0019] Testing semiconductor dies can be challenging due to factors such as high capacitance at I / O contacts. For example, it can be difficult to test whether an I / O circuit is capable of transmitting signals at high speeds due to high capacitance at the I / O contacts. For example, if a test voltage signal is transmitted through a node that is in contact with one of the I / O contacts, the high capacitance at the node may make the test voltage signal itself unreliable, thereby compromising the test.

[0020] In one embodiment, the I / O circuit in the semiconductor die is tested by looping back the test voltage signal from the output circuit to the input circuit. By looping back the test voltage signal internally, high capacitance nodes (such as I / O contacts) are avoided. If the test voltage signal is transmitted through a node connected to the I / O contact, the integrity of the test voltage signal may be compromised. Therefore, the test of the I / O circuit may be inaccurate. This may be especially true if the test voltage signal is a high-speed voltage signal. For some technologies, the test of the I / O circuit is only practical for low-speed voltage signals. The technology disclosed herein can accurately test the I / O path for transmitting high-speed voltage signals. In addition, the test of the I / O circuit does not require expensive or complex circuits and is therefore economical.

[0021] Figure 1 to Figure 2 One example of a memory system that can be used to implement the techniques presented herein is described. Figure 1 is a functional block diagram of an exemplary memory system 100 . Figure 1 The components depicted in are circuits. The memory system 100 includes one or more memory dies 108. In one embodiment, each memory die 108 includes a memory structure 126, a control circuit 110, a read / write circuit 128, a row decoder 124, a column decoder 132, and an input / output circuit 136. The memory structure 126 can be addressed by a word line via the row decoder 124 and by a bit line via the column decoder 132. The read / write circuit 128 includes a plurality of sense blocks 150, including SB1, SB2, ..., SBp (sense circuits), and allows pages of memory cells to be read or programmed in parallel. Moreover, many memory cell strings can be erased in parallel. The input / output (I / O) circuit 136 provides data I / O using the controller 122. The I / O circuit 136 may include an input circuit and an output circuit. The I / O circuit 136 provides at least a portion of the I / O data path between the read / write circuit 128 and the line 118.

[0022] In some systems, the controller 122 is included in the same package as one or more memory dies 108 (e.g., a removable memory card). However, in other systems, the controller may be separate from the memory die 108. In some embodiments, the controller will be located on a die different from the memory die 108. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transmitted between the host 140 and the controller 122 via the data bus 120, and are transmitted between the controller 122 and one or more memory dies 108 via the line 118. In one embodiment, the memory die 108 includes a set of input and / or output (I / O) contacts connected to the line 118. The I / O contacts may include contact pads that are electrically in contact with the memory die. In one embodiment, the contact pads are bonded to the surface of the memory die 108. The I / O contacts may also include contact pins that are electrically connected to the contact pads and provide connections to the line 118. Any of the memory die 108, the combination of the memory die 108 and the controller 122, or the combination of the memory die 108, the controller 122, and the host 140 may be referred to herein as a device.

[0023] The control circuit 110 cooperates with the read / write circuit 128 to perform memory operations (e.g., write, read, erase, etc.) on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, a power control circuit 116, and a built-in self-test circuit 134. In one embodiment, the control circuit 110 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​such as base voltage and other parameters. In one embodiment, the state machine 112 can be programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuits).

[0024] The on-chip address decoder 114 provides an address interface between the address used by the host 140 or the controller 122 to the hardware address used by the decoder 124 and the decoder 132. The power control circuit 116 controls the power and voltage provided to the word lines, bit lines, and select lines during memory operations. In one embodiment, the power control circuit 116 includes a voltage circuit. The power control circuit 116 may include a charge pump for generating voltage. The sense block includes a bit line driver. The sense block may include a sense amplifier. In one embodiment, the power control circuit 116 executes under the control of the state machine 112.

[0025] In one embodiment, all or a subset of the control circuit 110 may be considered to be Figure 1All or a subset of the other circuits depicted on the memory die 108 in the embodiment are control circuits that perform the functions described herein. In one embodiment, the built-in self-test circuit 134 and the state machine 112 may be considered to be control circuits that perform the functions described herein. In one embodiment, the control circuit 110 and / or the controller 122 (or circuits of equivalent functions) may be considered to be control circuits that perform the functions described herein. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit may include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), an integrated circuit, or other types of circuits.

[0026] In one embodiment, control circuit 110 operates input / output circuit 136 in a normal mode to transmit data over line 118 so that controller 122 can program data into structure 126 and read data from structure 126. Built-in self-test circuit 134 is capable of testing the correct operation of at least some of the circuits on die 108. In one embodiment, built-in self-test circuit 134 tests input / output circuit 136. In one embodiment, control circuit 110 operates input / output circuit 136 in a test mode in which, for example, input / output circuit 136 can be tested. During one embodiment of the test mode, voltage signals (e.g., data) are not transmitted over line 118. Instead, built-in self-test circuit 134 generates a test voltage signal and provides the test voltage signal to an output circuit in I / O circuit 136. The test voltage signal is looped back internally to the input circuit in I / O circuit 136 instead of transmitting the test voltage signal over line 118. The input circuit provides a test voltage signal back to the built-in self-test circuit 134, which compares the test voltage signal with the test voltage signal provided to the output circuit. The built-in self-test circuit 134 generates a test result based on the comparison. The test result can be provided via line 118 to report whether the I / O circuit 136 is operating correctly.

[0027] Under at least some conditions, the I / O contacts may have very high capacitance. For example, the I / O contacts may have very high capacitance during die sorting (also known as wafer sorting). Die sorting refers to testing the memory dies 108 after manufacturing. As a result of such testing, the tested memory dies may be sorted for different usage categories. For example, the best performing memory dies may be sorted for the most demanding uses, and memory dies that perform less well but are still at an acceptable level are sorted for less demanding uses. Some memory dies may be discarded.

[0028] Testing memory die 108 may be challenging due to factors such as high capacitance at the I / O contacts. For example, it may be difficult to test whether I / O circuitry 136 is capable of transmitting data at high speeds due to high capacitance at the I / O contacts. For example, if a test voltage signal is transmitted through a node that is in contact with one of the I / O contacts, the high capacitance at the node may make the test voltage signal itself unreliable, thereby compromising the test.

[0029] In one embodiment, by looping back the voltage signal internally, high capacitance nodes (such as I / O contacts) are avoided. In one embodiment, the input circuit operates by comparing the voltage signal with a reference voltage. A voltage signal refers to a voltage signal that switches back and forth between two states (e.g., two voltages). The input circuit generates an input voltage signal based on a comparison of the voltage signal with a reference voltage. Therefore, if the voltage signal is transmitted through a high capacitance node, the integrity of the voltage signal may be compromised. If the voltage signal cannot rise above the reference voltage (or fall below the reference voltage), the output of the input circuit is incorrect.

[0030] In one embodiment, the input circuit has two input nodes to compare the voltage signal with the reference voltage. In one embodiment, during normal mode, the voltage signal is provided to the first input node of the input circuit via the I / O contact, and the control circuit 110 provides the reference voltage to the second input node of the input circuit. In one embodiment, during the test mode, the effects of the two input nodes are opposite to the operation during the normal mode. In one embodiment, during the test mode, the control circuit 110 routes the test voltage signal from the output circuit to the first input node of the input circuit, and provides the reference voltage to the second input node of the input circuit. In one embodiment, the reference voltage is provided to the second input node of the input circuit via the I / O contact. Since the reference voltage does not switch back and forth, the high capacitance at the I / O contact is not a problem. The high capacitance can actually help stabilize the reference voltage. Therefore, the high-speed operation of the I / O circuit 136 can be effectively and accurately tested.

[0031] The (on-chip or off-chip) controller 122 (circuitry in one embodiment) may include one or more processors 122c, ROM 122a, RAM 122b, memory interface (MI) 122d, and host interface (HI) 122e, all of which are interconnected. The storage devices (ROM 122a, RAM 122b) store code (software) such as a set of instructions (including firmware), and the one or more processors 122c are operable to execute the set of instructions to provide the functionality described herein. Alternatively or in addition, the one or more processors 122c may access code from a storage device in a memory structure, such as a reserved area of ​​memory cells connected to one or more word lines. RAM 122b may be used to store data for the controller 122, including cached program data (discussed below). The memory interface 122d, which communicates with ROM 122a, RAM 122b, and processor 122c, is a circuit that provides an electrical interface between the controller 122 and one or more memory dies 108. For example, the memory interface 122d may change the format or timing of a signal, provide a buffer, isolate from surges, latch I / O, etc. The one or more processors 122c may issue commands to the control circuit 110 (or another component of the memory die 108) through the memory interface 122d. The host interface 122e provides an electrical interface to the host 140 data bus 120 to receive commands, addresses, and / or data from the host 140 to provide data and / or status to the host 140.

[0032] In one embodiment, memory structure 126 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate (such as a wafer). The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of an array of memory cells having an active region disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings having charge trapping material.

[0033] In another embodiment, the memory structure 126 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR type flash memory) may also be used.

[0034] The exact type of memory array architecture or memory cells included in the memory structure 126 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 126. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of technologies suitable for memory cells of the memory structure 126 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 126 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0035] An example of ReRAM, or PCMRAM, cross-point memory includes a reversible resistance switching element arranged in a cross-point array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0036] Magnetoresistive memory (MRAM) stores data via magnetic storage elements. The element is formed by two ferromagnetic plates, each of which can remain magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write wires that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0037] Phase change memory (PCM) exploits the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by changing the coordination state of the germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes (continuous or non-continuous) vibrations or pulse trains of sound, current, voltage light or other waves.

[0038] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by those of ordinary skill in the art.

[0039] Figure 2 is a block diagram of an exemplary memory system 100 depicting further details of one embodiment of the controller 122 . Figure 2 The controller in is a flash memory controller, but it should be noted that the non-volatile memory 108 is not limited to flash memory. Therefore, the controller 122 is not limited to the example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host such as a computer or an electronic device. In addition to the specific functions described herein, a flash memory controller can have various functions. For example, a flash memory controller can format a flash memory to ensure that the memory operates properly, map out bad flash memory cells, and allocate spare memory cells to replace future failed cells. Some of the spare cells in the spare cells can be used to accommodate firmware to operate the flash memory controller and implement other features. In operation, when the host needs to read data from the flash memory or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller can convert the logical address received from the host into a physical address in the flash memory. (Or, the host can provide a physical address). The flash memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific memory blocks that would otherwise be written repeatedly) and garbage collection (moving only valid data pages to new blocks after a block is full so the complete block can be erased and reused).

[0040] The interface between the controller 122 and the non-volatile memory die 108 may be any suitable flash memory interface, such as switch mode 200, 400, or 800. In one embodiment, the memory system 100 may be a card-based system, such as a secure digital card (SD) or a micro secure digital (micro-SD) card. In an alternative embodiment, the memory system 100 may be part of an embedded memory system. For example, the flash memory may be embedded in a host. In other examples, the memory system 100 may be in the form of a solid state drive (SSD).

[0041] In some embodiments, the non-volatile memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there are 2, 4, 8 or more channels between the controller and the memory die, depending on the capabilities of the controller. In any of the embodiments described herein, even if a single channel is shown in the figures, there can be more than a single channel between the controller and the memory die.

[0042] like Figure 2 As depicted in FIG. 1 , the controller 122 includes a front end module 208 that interacts with a host, a back end module 210 that interacts with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

[0043] Figure 2 The components of the controller 122 depicted in the figure may take the form of, for example, packaged functional hardware units (e.g., circuits) designed for use with other components, portions of program code (e.g., software or firmware) that can be executed by a specific function (micro)processor or processing circuit that generally performs related functions, or independent sets of hardware or software components that interact with a larger system. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof. Alternatively or in addition, each module may include software stored in a processor readable device (e.g., a memory) to program the processor to cause the controller 122 to perform the functions described herein. Figure 2 The architecture depicted in this example may (or may not) use Figure 1 An exemplary implementation of the components of controller 122 (ie, RAM, ROM, processor, interfaces) is depicted in FIG.

[0044] Referring again to the modules of controller 122, buffer manager / bus controller 214 manages buffers in random access memory (RAM) 216 and controls internal bus arbitration of controller 122. Read only memory (ROM) 218 ​​stores system boot code. Figure 2 122, but in other embodiments, one or both of RAM 216 and ROM 218 may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located within the controller 122 and outside the controller. Furthermore, in some implementations, the controller 122, RAM 216, and ROM 218 may be located on separate semiconductor dies.

[0045] The front-end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provide an electrical interface with a host or a next-level storage controller. The type of host interface 220 can be selected depending on the type of memory used. Examples of host interface 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 generally facilitates the transmission of data, control signals, and timing signals.

[0046] The backend module 210 includes an error correction code (ECC) engine 224 that encodes data bytes received from the host and decodes and error corrects data bytes read from the non-volatile memory. The command sequencer 226 generates command sequences, such as a program command sequence and an erase command sequence, for transmission to the non-volatile memory die 108. The RAID (Redundant Array of Independent Dies) module 228 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the non-volatile memory system 100. In some cases, the RAID module 228 can be part of the ECC engine 224. Note that RAID parity can be added as an additional die or dies, as the common name implies, but can also be added within an existing die, for example, as an additional plane, or an additional block, or an additional WL within a block. The memory interface 230 provides command sequences to the non-volatile memory die 108 and receives status information from the non-volatile memory die 108. In one embodiment, the memory interface 230 may be a double data rate (DDR) interface, such as a switched mode 200, 400, or 800 interface. The flash control layer 232 controls the overall operation of the back end module 210.

[0047] Figure 2Additional components of the system 100 shown include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108. The system 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, the RAID module 228, the media management layer 238, and the buffer management / bus controller 214 are optional components that are not necessary in the controller 122.

[0048] A flash translation layer (FTL) or media management layer (MML) 238 may be integrated as part of flash management that can handle flash errors and interface with the host. Specifically, the MML may be a module in flash management and may be responsible for the internals of NAND management. Specifically, the MML 238 may include an algorithm in the memory device firmware that converts writes from the host into writes to the memory 126 of the die 108. The MML 238 may be required because: 1) the memory may have limited endurance; 2) the memory 126 may only be written to multiple pages; and / or 3) the memory 126 may not be written unless it is erased as a block. The MML 238 understands these potential limitations of the memory 126, which may not be visible to the host. Therefore, the MML 238 attempts to convert writes from the host into writes to the memory 126. As described below, the MML 238 may be used to identify and record unstable bits. The recording of the unstable bits can be used to assess the health of the blocks and / or word lines (memory cells on the word lines).

[0049] The controller 122 may interface with one or more memory dies 108. In one embodiment, the controller 122 and the plurality of memory dies (together comprising the non-volatile storage system 100) implement a solid-state drive (SSD) that may emulate, replace, or be used in place of a hard disk drive within a host (e.g., a NAS device), in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not function as a hard disk drive.

[0050] Some embodiments of the non-volatile storage system will include a memory die 108 connected to a controller 122. However, other embodiments may include multiple memory die 108 that communicate with one or more controllers 122. In one example, multiple memory dies can be grouped into a group of memory packages. Each memory package includes one or more memory dies that communicate with the controller 122. In one embodiment, the memory package includes a printed circuit board (or similar structure) on which one or more memory dies are mounted. In some embodiments, the memory package may include a molding material to encapsulate the memory die of the memory package. In some embodiments, the controller 122 is physically separated from any memory package.

[0051] Figure 3 An embodiment of a semiconductor die 300 is depicted. In one embodiment, the semiconductor die 300 is a memory die 108 having a memory structure 126. However, the semiconductor die 300 need not be a memory die. The semiconductor die 300 has a control circuit 302, an input circuit 304, an output circuit 306, and an input / output (I / O) contact 308. In one embodiment, the I / O contact 308 includes a contact pad located on a surface of the semiconductor die 300. The contact pad may be bonded to the surface of the semiconductor die 300. In addition to the contact pad, the I / O contact 308 may also include other conductive elements. In some embodiments, the semiconductor die 300 is placed in a package. In some embodiments, there are contact pins that provide electrical connections from the contact pad to the outside of the package. If the semiconductor die 300 is in a package, the contact pins (etc.) may be considered to be part of the I / O contact 308.

[0052] The control circuit 302 is configured to control the operation of the input circuit 304 and the output circuit 306. In one embodiment, the control circuit 302 operates the semiconductor die 300 in a normal mode and a test mode. During the normal mode, the output circuit 306 is used to send data through the I / O contact 308, and the input circuit 304 is used to receive data from the I / O contact 308. During the test mode, the data is routed from the output circuit 306 to the input circuit 304. Therefore, the I / O contact 308 can be avoided during the test mode. Under at least some conditions, there may be very high capacitance at the I / O contact 308. For example, during die sorting, the capacitance at the I / O contact 308 may be very high. However, the capacitance at the I / O contact 308 may be high at other times. Such high capacitance may make it difficult to test the operation of the input circuit 304 and / or the output circuit 306. This article describes a technique for effectively and accurately testing the input circuit 304 and / or the output circuit 306. In some embodiments, high speed operation of input circuit 304 and / or output circuit 306 is tested. High speed operation may be, for example, a rate greater than 400 Mbs.

[0053] Control circuit 302 may include only hardware or a combination of hardware and software (including firmware). Control circuit 302 may include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), an integrated circuit, or other types of circuits. Semiconductor die 300 may be referred to herein as a device.

[0054] In one embodiment, the input circuit 304 has a comparator 310 having two inputs 312, 314. The comparator 310 compares the magnitude of the voltage at the first input 312 (e.g., V1) with the magnitude of the voltage at the second input 314 (e.g., V2), and outputs a voltage (Vout) at the output 316 based on the comparison. For example, if V1 is greater than V2, Vout may have a first magnitude (e.g., a high voltage), but if V1 is not greater than V2, Vout may have a second magnitude (e.g., a low voltage). In one embodiment, the comparator 310 may include an input receiver.

[0055] In one embodiment, one input voltage is a voltage signal, and the other input voltage is a reference voltage. The voltage signal is a signal that switches back and forth between two states. The reference voltage does not switch back and forth and has a magnitude somewhere between the two states of the voltage signal. The reference voltage may have a substantially constant magnitude. The magnitude of the reference voltage may change to a certain extent due to, for example, noise or other non-ideal factors. Therefore, the reference voltage can be used to determine which state the voltage signal is currently in between the two states. The output 316 of the comparator 310 can therefore be an input voltage signal that switches back and forth between the two states.

[0056] The comparator 310 can operate with a reference voltage at the first input 312 or the second input 314. Likewise, the comparator 310 can operate with a voltage signal at the first input 312 or the second input 314. In one embodiment, during normal mode, a voltage signal is received at the first input 312, while the reference voltage is provided to the second input 314 by the control circuit 302. During normal mode, a voltage signal can be received at the I / O contact 308. The voltage signal received on the I / O contact 308 may be referred to herein as an "external voltage signal." The external voltage signal may be provided by the controller 122.

[0057] In one embodiment, during the test mode, the control circuit 302 provides a voltage signal to the second input 314 while receiving a reference voltage at the first input 312. During the test mode, the control circuit 302 may route the voltage signal from the output circuit 306 to the second input 314. The voltage signal routed from the output circuit 306 to the input circuit 304 may be referred to herein as an "internal voltage signal." In one embodiment of the test mode, the reference voltage is provided to the first input 312 via the I / O contact 308.

[0058] During normal mode, input circuit 304 inputs a voltage signal from I / O contact 308 under the control of control circuit 302. Therefore, during normal mode, the voltage signal is not routed from output circuit 306 to input circuit 304. In one embodiment, input circuit 304 inputs a data signal, which refers to a voltage signal containing data. For example, the data signal may contain data to be stored in a memory structure. However, input circuit 304 may input a voltage signal that is not a data signal. In one embodiment, input circuit 304 inputs a data strobe signal. The data strobe signal may be used as a clock type for the data signal. An example of a data strobe signal is a DQS signal, which is used in a plurality of different memory interfaces. For example, the Open NAND Flash Interface (ONFI) specification allows the use of a DQS signal.

[0059] During normal mode, output circuit 306 outputs a voltage signal through I / O contact 308 under the control of control circuit 302. Therefore, during normal mode, the voltage signal is not routed from output circuit 306 to input circuit 304. In one embodiment, output circuit 306 outputs a data voltage signal. For example, the data voltage signal may include data stored in a memory structure. However, output circuit 306 may output a voltage signal that is not a data signal.

[0060] Figure 4 One embodiment of a memory die 108 is depicted. Figure 4 The die shown is Figure 1An embodiment of a memory die 108 is shown. The built-in self-test circuit 134 has a data generation circuit 402 and a data comparison / status unit 404. The data generation circuit 402 generates test data, which is sent to a serializer / deserializer (SERDES) 406. In one embodiment, the SERDES 406 obtains the test data in parallel from the data generation circuit 402 and outputs the serial test data to the output circuit 306. The clock 408 outputs a clock signal that can be provided to various components on the memory die 108. The clock signal can be used to control the timing of data transfer within the memory die 108. In one embodiment, the clock 408 includes a phase-locked loop (PLL).

[0061] The control circuit 110 internally routes the serial test data from the output circuit 306 to the input circuit 304. The input circuit 304 sends the serial test data back to the SERDES 406, which converts the serial test data back into parallel test data. The parallel test data is provided from the SERDES 406 to the data comparison / state 404. The data comparison / state 404 also inputs the parallel test data generated by the data generation circuit 402. The data comparison / state 404 compares the two test data inputs and outputs a test result based on the comparison. For example, the test result may simply indicate whether the two test data inputs match.

[0062] The test results may be provided to the state machine 112 so that the test results may be sent outside the memory die 108. In some cases, the controller 122 may not be available when the memory die 108 is being tested. Therefore, the test results are not necessarily sent to the controller 122, but this is a possibility. In one embodiment, the test results are sent to a tester that tests many memory dies 108. For example, the tester may test many memory dies during die sorting (also known as wafer sorting). The tester may be any electronic device, such as, for example, a computer system having a processor that executes program instructions to test the memory die. In one embodiment, the tester instructs the memory die 108 to enter a test mode. Therefore, the built-in self-test circuit 134 may initiate a test mode in response to a command from a source external to the memory die 108.

[0063] In one embodiment, the SERDES 406 communicates with the read / write circuit 128. The SERDES 406 can transfer data from / to the read / write circuit 128 to allow reading and writing from / to the structure 126. In one embodiment, the read / write circuit 128 includes a buffer or latch for holding data to be written to or read from the structure 126. In one embodiment, the SERDES 406 provides the data to be written to the structure 126 to the buffer or latch in the read / write circuit 128. The data is received from the input circuit 304 from outside the memory die 108. The read / write circuit 128 then writes the data to the structure 126 under the control of the state machine 112. In one embodiment, the read / write circuit 128 reads the data from the structure 126 under the control of the state machine 112 and places the data in the buffer or latch in the read / write circuit 128. The SERDES 406 then accesses the data and sends it to the data output circuit 306 for transmission out of the memory die 108.

[0064] Figure 5 One embodiment of a portion of input / output circuitry connected to I / O contacts is depicted. The input / output circuitry can be located within input / output circuitry 136 on memory die 108. Figure 5 The output circuit 306 shown is Figure 3 One implementation of output circuit 306 is shown. Figure 5 The input circuit 304 is shown to be Figure 3 One implementation of input circuit 304 is shown. Figure 5 The output circuit 306 shown is Figure 4 One implementation of output circuit 306 is shown. Figure 5 The input circuit 304 is shown to be Figure 4 One implementation of input circuit 304 is shown.

[0065] Figure 5Two I / O contacts 308(1), 308(2) are shown. The I / O contacts 308 may include contact pads bonded to a semiconductor die (e.g., memory die 108). The I / O contacts 308 may include other conductive elements that provide electrical connections to the contact pads. In one embodiment, the semiconductor die may be placed into a package after testing the semiconductor die. However, it should be noted that during die sorting testing of the semiconductor die, the semiconductor die is typically not yet packaged. In one embodiment, two I / O contacts 308(1), 308(2) are used for data transmission. The semiconductor die may have additional I / O contacts 308 for data transmission. For example, there may be 8, 16, 32, or some other number of I / O contacts 308 for data transmission. In some embodiments, some of the I / O contacts 308 have functions other than data transmission. In one embodiment, two I / O contacts 308(1), 308(2) may be used for data strobe signals. For example, some devices have a DQS contact and a DQSn contact. As described above, the DQS signal can be used as a data strobe signal.

[0066] Figure 5 A portion of one section of an output circuit 306 connected to an I / O contact 308(1) is depicted. The output circuit 306 may have multiple sections, each of which is connected to a different I / O contact 308. The two stages 502, 504 of the output circuit 306 are Figure 5 . However, output circuit 306 may have more stages. Stage 502 has input 506 that receives a data output signal. The output of stage 502 is connected to the input of stage 504. Node 508 is located between the output of stage 502 and the input of stage 504. As used herein, the term "node" in a circuit is not limited to a single point in a circuit, but may refer to two points in a circuit. For example, briefly referring to Fig.10 , the node 508 includes a first point 508a and a second point 508b. In this case, the voltage between the two points 508a, 508b is the voltage at the node 508. In some cases, a node may refer to a single point in a circuit. Typically, in this case, the voltage at the node will be the voltage at that point relative to ground. Again referring to Figure 5 , stage 504 is the last stage whose output 510 is connected to I / O contact 308(1). Stage 504 may be referred to as an off-chip driver because stage 504 provides an output voltage signal to I / O contact 308(1). Stage 502 may be referred to as a pre-driver.

[0067] The input circuit 304 is associated with the I / O contact 308(2). The input circuit 304 may have multiple sections, each of which is connected to a different I / O contact 308. The input circuit 304 has a comparator 310, which has a first input 312, a second input 314, and an output 316. The first input 312 is connected to the I / O contact 308(2). Since the first input 312 is connected to the I / O contact 308(2), the first input 312 can be referred to as an "external input" because it allows input to be provided via the I / O contact 308. The second input 314 is connected to the switching logic element 512. The second input 314 can be referred to as an "internal input" because it is not connected to any I / O contact 308. The switching logic element 512 has a switch (SW1) that is capable of connecting the second input 314 to a reference voltage (Vref) or to a node 508 in the output circuit 306. Reference Figure 3 , the switch logic 512 can be considered as a part of the control circuit 302. Figure 1 and Figure 4 , the switching logic 512 can be considered as part of the control circuit 110 and can operate under the control of the state machine 112.

[0068] Fig. 6A Depicted Figure 5 308(1).

[0069] Figure 6B Depicted Figure 5 306, wherein the switch logic 512 is in a position that can be used during a test mode of operation. During the test mode, SW1 connects the node 508 in the output circuit 306 to the second input 314 of the comparator 310 in the input circuit 304. Therefore, the internal voltage signal is provided to the second input 314 of the comparator 310. A reference voltage can be received on the I / O contact 308(2). The voltage signal is provided to the first input 312 of the comparator 310. Therefore, the input voltage signal is based on the comparison of the internal voltage signal with the reference voltage.

[0070] Please note that Figure 6BThe configuration shown allows testing of substantially the entire I / O circuit while avoiding transmission of voltage signals through I / O contacts 308. For example, comparator 310 may be the first stage of input circuit 304. Stage 504 may be the last of multiple stages of output circuit 306. Thus, a majority of output circuit 306 may be tested. Additionally, other circuits in semiconductor die 300 other than input circuit 304 and output circuit 304 may also be tested.

[0071] In some embodiments, the semiconductor die operates in a test mode at one point in time and in a normal mode at another point in time. The test mode can be used to test I / O data paths in the semiconductor die. The normal mode can be used to input data to the semiconductor die and / or output data from the semiconductor die. Figure 7 A flow chart depicts one embodiment of a process 700 for operating input circuit 304 in two modes. When describing process 700, reference will be made to Fig. 6A and Figure 6B However, process 700 is not limited to Fig. 6A and Figure 6B In one embodiment, input circuit 304 is located on a memory die 108 having a memory structure 126 for storing data; however, input circuit 304 may be located on a semiconductor die that does not have a memory structure 126 for storing data.

[0072] Step 702 includes configuring the semiconductor die to operate in a test mode. In one embodiment, the semiconductor die receives a command from outside the semiconductor die that instructs the semiconductor die to operate in a test mode. Step 702 may include controlling switch logic 512 so that SW1 connects node 508 to second input 314 of comparator 310 in input circuit 304.

[0073] Step 704 includes operating input circuit 304 in a test mode in which control circuitry (e.g., control circuit 302, control circuit 110) provides an internal voltage signal from output circuit 306 to second input 314 of input circuit 304. In one embodiment of the test mode, input circuit 304 compares a reference voltage at first input 312 with an internal voltage signal from output circuit 306 at second input 314 to generate an input voltage signal at output 316. In one embodiment, first input 312 is connected to I / O contact 308(2) such that first input 312 receives a voltage present at I / O contact 308(2). Step 704 may include providing a reference voltage to I / O contact 308(2). For example, test logic may provide a reference voltage to I / O contact 308(2) during die sorting. However, step 704 is not limited to being performed during die sorting. Step 704 may be performed at any time. In one embodiment, the controller 122 provides a reference voltage to the I / O contact 308(2). In one embodiment, the built-in self-test circuit provides a reference voltage to the first input 312. For example, the switch logic 512 can be configured to provide a reference voltage to the first input 312.

[0074] Step 706 includes configuring the semiconductor die to operate in normal mode. The line between steps 704 and 706 is a dotted line to indicate that a considerable amount of time may pass between these two steps. The semiconductor die may be powered off and reconnected between steps 704 and 706, but this is not required. In one embodiment, by default, the semiconductor die enters normal mode when powered on. Therefore, there is not necessarily a special command to instruct the semiconductor die to enter normal mode. In one embodiment, the semiconductor die receives a command from outside the semiconductor die that instructs the semiconductor die to operate in normal mode. Step 706 may include controlling the switch logic 512 so that SW1 connects the reference voltage (Vref) to the second input 314 of the comparator 310 in the input circuit 304.

[0075] Step 708 includes operating the input circuit 304 in a normal mode in which the control circuit provides a reference voltage to the second input 314 of the input circuit 304. In one embodiment of the normal mode, the input circuit 304 compares the external voltage signal from the I / O contact 308(2) at the first input 312 to the reference voltage at the second input 314 to generate an input voltage signal at the output 316. Step 708 may include receiving the external voltage signal at the I / O contact 308(2) from the controller 122. Step 708 may include providing the reference voltage to the switch logic 512.

[0076] In some implementations, I / O circuits of the semiconductor die are tested during the test mode. Figure 8 A flow chart of one embodiment of a process 800 for controlling a semiconductor die during a test mode is depicted. The process 800 may be used to test, for example, I / O circuits in a semiconductor die. Figure 4 Process 800 is discussed with reference to memory die 108 in FIG. 1 . However, process 800 is not limited to memory die. Process 800 may be performed during step 704 of process 700. Thus, process 800 may be performed when a semiconductor die is in a test mode.

[0077] Step 802 includes providing an internal voltage signal to an output circuit 306 on a semiconductor die. The output circuit 306 has a driver 504 configured to drive an I / O contact 308(1) of the semiconductor die. Step 802 may include data generation circuit 402 generating a test voltage signal. In one embodiment, the test voltage signal is provided to SERDES 406. SERDES 406 may provide the test voltage signal to the output circuit 306.

[0078] Step 804 includes routing the internal voltage signal from the input of driver 504 to an input 314 of an input receiver (e.g., comparator 310) on the semiconductor die while receiving a reference voltage (e.g., Vref) at an input 312 of the input receiver via an input / output contact 308(2) to the semiconductor die.

[0079] Step 806 includes generating an input voltage signal based on a comparison of the internal voltage signal at input 314 with the reference voltage at input 312. Step 806 may be performed by comparator 310. The input voltage signal may be provided to SERDES 406, which may provide the input voltage signal to data compare / status 404.

[0080] Step 808 includes comparing the internal voltage signal provided to the output circuit with the input voltage signal generated at the input receiver. Step 808 may be performed by data compare / state 404.

[0081] Step 810 includes generating a test result based on the comparison. The test result may be provided to the state machine 112 from the data compare / state 404. The state machine 112 may provide the test result to a test external to the semiconductor die, for example.

[0082] As described above, the semiconductor die may operate in a normal mode.For example, the memory die 108 may operate in a normal mode in which data is written to and read from the memory structure 126. Fig. 9 A flow chart of one embodiment of a process 900 of controlling memory die 108 in normal mode is depicted. Process 900 is one embodiment of step 708 in process 700.

[0083] Step 902 includes providing a reference voltage to a second input 314 of an input receiver (eg, comparator 310). In one embodiment, state machine 112 operates switch logic 512 to connect SW1 to a reference voltage Vref.

[0084] Step 904 includes receiving an external voltage signal at the first input 312 of the input receiver from the input / output contact 308(2). In one embodiment, the controller 122 provides the external voltage signal to the input / output contact 308(2).

[0085] Step 906 includes comparing the external voltage signal at the first input 312 of the input receiver with the reference voltage at the second input 314 of the input receiver to generate an input voltage signal at the output 316 of the input receiver. Further details of one embodiment of an input receiver capable of performing such a comparison are described in Fig.11 middle.

[0086] Step 908 includes writing data to the memory structure 126 on the semiconductor die using the input voltage signal. Step 908 may be performed under the control of the state machine 112. The state machine 112 may cause the data from the input receiver to be transferred to the latch or buffer in the read / write circuit 128. The state machine 112 may control the read / write circuit 128 and the column decoder 132 to write the data to the target location in the memory structure 126.

[0087] Fig.10 is a schematic diagram of one embodiment of a portion of output circuit 306 . Fig.10 Depicted Figure 3 , Figure 4 , Figure 5 , Fig. 6A and / or Figure 6B One implementation of output circuit 306 is shown. Fig.10 Two stages 502, 504 of output circuit 306 are depicted in association with I / O contacts 308. Output circuit 306 may have additional stages. Stage 504 may be referred to as an off-chip driver. Stage 504 has a PMOS transistor 1002 and an NMOS transistor 1004 connected in series between a supply voltage (Vdd) and ground. An output 510 of stage 504 is located between PMOS transistor 1002 and NMOS transistor 1004.

[0088] Stage 502 has a PMOS transistor 1006, an NMOS transistor 1008, and an NMOS transistor 1010, which are connected in series between a supply voltage (Vdd) and ground. The gates of the PMOS transistor 1006 and the NMOS transistor 1008 are connected together at an input node 506a. Stage 502 has a PMOS transistor 1012, a PMOS transistor 1014, and an NMOS transistor 1016, which are connected in series between a supply voltage (Vdd) and ground. The gates of the PMOS transistor 1014 and the NMOS transistor 1016 are connected together at an input node 506b. The output circuit 306 may have additional stages, one of which is connected to the input node 506a and the input node 506b. The gate of the NMOS transistor 1010 is driven by a DEN, which can be used to bias the NMOS transistor 1010. The gate of the PMOS transistor 1012 is driven by a DENb, which can be used to bias the PMOS transistor 1012.

[0089] Nodes 506a and 506b together are Figure 5 1. In one embodiment, the data output signal is sampled between nodes 506a and 506b. During the test mode, the data output signal may be referred to as an internal voltage signal. Point 508a and point 508b together are Figure 5 One embodiment of node 508 is shown. In one embodiment, the internal voltage signal is sampled between points 508a and 508b and routed to the data input circuit.

[0090] Fig.11 for Figure 3 , Figure 4 , Figure 5 , Fig. 6A and / or Figure 6B A schematic diagram of one embodiment of a portion of input circuit 304 is shown. Input circuit 304 is connected to I / O contacts 308 and to switch logic 512, as previously described.

[0091] The gate of PMOS transistor 1102 is an embodiment of first input 312. The gate of PMOS transistor 1102 is connected to I / O contact 308. The gate of PMOS transistor 1102 can be referred to as external input. The gate of PMOS transistor 1104 is an embodiment of second input 314. The gate of PMOS transistor 1104 is connected to switch logic 512. The gate of PMOS transistor 1104 can be referred to as internal input. Herein, the gate of a transistor is an example of a control terminal. However, the term "control terminal" is not limited to the gate of a FET. The term control terminal can also refer to, for example, the base of a bipolar junction transistor.

[0092] Input circuit 304 has two output nodes 316a, 316b that are complementary to each other. That is, the input of inverter 1128 is connected to output node 316a, and its output is connected to output node 316b. In one embodiment, output node 316a is used in test mode. In one embodiment, output node 316b is used in normal mode. The two output nodes 316a, 316b are Figure 5 One implementation of output 316 is shown. The voltage at the output nodes 316a, 316b is based on a comparison of the voltages at the two inputs 312, 314.

[0093] Input circuit 304 has circuit elements that can be used to compare the voltage at the input and circuit elements that are used to provide output voltage signals. Comparison elements may include PMOS transistor 1102, PMOS transistor 1104, NMOS transistor 1106, NMOS transistor 1108, resistor 1112, resistor 1114, and current source 1116. Output elements may include PMOS transistor 1118, NMOS transistor 1120, PMOS transistor 1124, and NMOS transistor 1126. Node 1130 is connected to the gate of NMOS transistor 1120 so that the voltage at node 1130 is used as a comparison point. Node 1132 is connected to the gate of NMOS transistor 1126. The drain of NMOS transistor 1126 is connected to the gate of PMOS transistor 1118 so that the voltage at node 1132 can be used as another comparison point.

[0094] Many alternative forms of input circuit 304 are possible. For example, Fig.11 In one embodiment, PMOS transistors are used for transistors whose gates are inputs 312, 314. In another embodiment, NMOS transistors are used for transistors whose gates are inputs 312, 314. In one embodiment, input circuit 304 has two alternative input stages. One input stage has PMOS transistors at inputs 312, 314, such as Fig.11 , while the other input stage uses NMOS transistors at inputs 312, 314. In such a design, only one of the two alternative input stages is used at a given time.

[0095] A first embodiment disclosed herein includes a device including an input circuit associated with a first input / output (I / O) contact. The input circuit includes a first input and a second input. The first input communicates with the first I / O contact. The input circuit is configured to compare a voltage signal at one of the first input or the second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The device also includes an output circuit associated with the second I / O contact. The device also includes a control circuit configured to operate in a first mode, in which the control circuit provides a reference voltage to the second input of the input circuit. The control circuit is also configured to operate in a second mode, in which the control circuit provides an internal voltage signal from the output circuit to the second input of the input circuit.

[0096] In a second embodiment, to advance the first embodiment, in the first mode, the input circuit compares the external voltage signal from the first I / O contact at the first input with the reference voltage at the second input to generate a first input voltage signal. Additionally, in the second mode, the input circuit compares the reference voltage at the first input with the internal voltage signal from the output circuit at the second input to generate a second input voltage signal.

[0097] In a third embodiment, to advance the second embodiment, the control circuit is further configured to sample a first input voltage signal from a first output node of the input circuit when in the first mode. Similarly, the control circuit is further configured to sample a second input voltage signal from a second output node of the input circuit when in the second mode. The first input voltage signal at the first output node is complementary to the second input voltage signal at the second output node.

[0098] In a fourth embodiment, to advance any one of the first to third embodiments, the control circuit is further configured to provide an internal voltage signal to an output circuit in a second mode, the output circuit having a plurality of stages including a final stage configured to drive a second I / O contact. The control circuit is further configured to provide an internal voltage signal from a node at an output of a stage other than the final stage of the output circuit to a second input of the input circuit in the second mode.

[0099] In a fifth embodiment, to advance the fourth embodiment, the control circuit includes a switching logic element configured to connect the second input of the input circuit to a reference voltage when in a first mode, and to connect the second input of the input circuit to a node to provide an internal voltage signal when in a second mode.

[0100] In a sixth embodiment, to advance any one of the first to fifth embodiments, the input circuit includes a first transistor having a first control terminal and a second transistor having a second control terminal. The first control terminal is the first input, and the second control terminal is the second input. The first control terminal is connected to the first I / O contact.

[0101] In a seventh embodiment, to further the sixth embodiment, the first transistor and the second transistor are configured such that the input voltage signal is based on a comparison of respective voltages at the first control terminal and at the second control terminal.

[0102] In an eighth embodiment, to further any of the first to seventh embodiments, the control circuit includes a built-in self-test circuit that communicates with the input circuit and with the output circuit. The built-in self-test circuit is configured to provide an internal voltage signal to the output circuit during the second mode. The built-in self-test circuit is configured to receive the internal voltage signal from the input circuit during the second mode. The built-in self-test circuit is configured to compare the internal voltage signal received from the input circuit with the internal voltage signal provided to the output circuit, and output a test result based on the comparison.

[0103] In a ninth embodiment, in order to advance any one of the first to eighth embodiments, the device further comprises a non-volatile memory unit in communication with the input circuit and with the output circuit. The control circuit is further configured to control the input circuit so as to provide data from the first I / O contact to the non-volatile memory unit in the first mode, wherein the control circuit is further configured to control the output circuit so as to provide data from the non-volatile memory unit to the second I / O contact in the first mode.

[0104] In a tenth embodiment, to advance any one of the first to ninth embodiments, the apparatus further includes a clock and a data generation circuit configured to generate an internal voltage signal.

[0105] In an eleventh embodiment, to advance any one of the first to tenth embodiments, the first input is an external input connected to the first I / O contact, and the second input is an internal input not connected to any I / O contact.

[0106] One embodiment of the technology disclosed herein includes a method for controlling a semiconductor die. The method includes providing an internal voltage signal to an output circuit on the semiconductor die. The output circuit has a driver. The method includes routing the internal voltage signal from an input of the driver to a first input of an input receiver on the semiconductor die, while receiving a reference voltage at a second input of the input receiver via a first input / output contact to the semiconductor die. The driver is connected to a second input / output contact to the semiconductor die. The method includes generating an input voltage signal based on a comparison of the internal voltage signal at the first input with a reference voltage at the second input. The method includes comparing the internal voltage signal provided to the output circuit with the input voltage signal generated at the input receiver. The method includes generating a test result based on the comparison.

[0107] One embodiment of the technology disclosed herein includes a memory die, which includes a non-volatile memory cell, a plurality of input / output (I / O) contacts, an input receiver, an output circuit, and a control circuit. The input receiver includes a pair of transistors, the pair of transistors including a first transistor having a first control terminal and a second transistor having a second control terminal. The first control terminal is coupled to a first I / O contact in the I / O contacts. The output circuit has a plurality of stages, including an off-chip driver stage, the off-chip driver stage having an output configured to drive a second contact in the I / O contacts. The output circuit has an input configured to receive an output voltage signal at an input stage. The control circuit is configured to operate in a normal mode, in which the control circuit provides a reference voltage to the second control terminal. The input receiver compares an external voltage signal from a first I / O contact at the first control terminal with a reference voltage to generate a first input voltage signal for the control circuit to write data to the non-volatile memory cell. The control circuit is configured to operate in a test mode, in which the control circuit routes the output voltage signal from the output of the stage other than the off-chip driver stage of the output circuit to the second control terminal. The input receiver compares a reference voltage from the first I / O contact at the first terminal with the output voltage signal at the second control terminal to generate a second input voltage signal.

[0108] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0109] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0110] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0111] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0112] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0113] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device comprising: an input circuit associated with a first input / output contact, wherein the input circuit includes a first input and a second input, wherein the first input is in communication with the first input / output contact, wherein the input circuit is configured to compare a voltage signal at one of the first input or the second input to a reference voltage at the other of the first input or the second input to generate an input voltage signal; an output circuit associated with the second input / output contact; and A control circuit, wherein the control circuit is configured to operate in a first mode, in which the control circuit provides a reference voltage to the second input of the input circuit, and the control circuit is also configured to operate in a second mode, in which the control circuit provides an internal voltage signal from the output circuit to the second input of the input circuit.

2. The device according to claim 1, wherein: In the first mode, the input circuit compares the external voltage signal from the first input / output contact at the first input with the reference voltage at the second input to generate a first input voltage signal; as well as In the second mode, the input circuit compares the reference voltage at the first input with the internal voltage signal from the output circuit at the second input to generate a second input voltage signal.

3. The apparatus according to claim 2, wherein the control circuit is further configured to: sampling the first input voltage signal from a first output node of the input circuit when in the first mode; and When in the second mode, the second input voltage signal from a second output node of the input circuit is sampled, wherein the first input voltage signal at the first output node is complementary to the second input voltage signal at the second output node.

4. The apparatus according to claim 1, wherein the control circuit is further configured to: providing the internal voltage signal to the output circuit in the second mode, the output circuit having a plurality of stages including a final stage configured to drive the second input / output contact; and The internal voltage signal from a node at an output of a stage other than the final stage of the output circuit is supplied to the second input of the input circuit in the second mode.

5. The apparatus according to claim 4, wherein the control circuit comprises: A switch logic element is configured to connect the second input of the input circuit to the reference voltage when in the first mode, and to connect the second input of the input circuit to the node to provide the internal voltage signal when in the second mode.

6. The apparatus of claim 1, wherein the input circuit comprises: A first transistor having a first control terminal being the first input and a second transistor having a second control terminal being the second input, wherein the first control terminal is connected to the first input / output contact.

7. The device according to claim 6, wherein: The first transistor and the second transistor are configured such that the input voltage signal is based on a comparison of respective voltages at the first control terminal and at the second control terminal.

8. The apparatus of claim 1, wherein the control circuit comprises: a built-in self-test circuit, the built-in self-test circuit being in communication with the input circuit and with the output circuit, wherein the built-in self-test circuit is configured to provide the internal voltage signal to the output circuit during the second mode, wherein the built-in self-test circuit is configured to receive the internal voltage signal from the input circuit during the second mode, wherein the built-in self-test circuit is configured to compare the internal voltage signal received from the input circuit with the internal voltage signal provided to the output circuit and output a test result based on the comparison.

9. The device according to claim 1, further comprising: a non-volatile memory unit in communication with the input circuit and with the output circuit, wherein the control circuit is further configured to control the input circuit so as to provide data from the first input / output contact to the non-volatile memory unit in the first mode, wherein the control circuit is further configured to control the output circuit so as to provide data from the non-volatile memory unit to the second input / output contact in the first mode.

10. The device according to claim 1, further comprising: clock; and A data generating circuit is configured to generate the internal voltage signal.

11. The apparatus of claim 1, wherein the first input is an external input connected to the first input / output contact, and the second input is an internal input not connected to any input / output contact.

12. A method of controlling a semiconductor die, the method comprising: providing an internal voltage signal to an output circuit on the semiconductor die, the output circuit having a driver; routing the internal voltage signal from an input of the driver to a first input of an input receiver on the semiconductor die while receiving a reference voltage at a second input of the input receiver via a first input / output contact to the semiconductor die, wherein the driver is connected to a second input / output contact to the semiconductor die; generating an input voltage signal based on a comparison of the internal voltage signal at the first input and the reference voltage at the second input; comparing the internal voltage signal provided to the output circuit with the input voltage signal generated at the input receiver; as well as A test result is generated based on the comparison.

13. The method according to claim 12, further comprising: providing a reference voltage to the second input of the input receiver; receiving an external voltage signal at the first input of the input receiver from the first input / output contact; comparing the external voltage signal at the first input of the input receiver with the reference voltage at the second input of the input receiver to generate a second input voltage signal at an output of the input receiver; as well as The second input voltage signal is provided to a nonvolatile memory cell on the semiconductor die.

14. A memory die, comprising: a non-volatile memory unit; Multiple input / output contacts; an input receiver comprising a pair of transistors including a first transistor having a first control terminal and a second transistor having a second control terminal, wherein the first control terminal is coupled to a first one of the input / output contacts; an output circuit having a plurality of stages including an off-chip driver stage having an output configured to drive a second one of the input / output contacts, the output circuit having an input configured to receive an output voltage signal at an input stage; and a control circuit configured to operate in a normal mode in which the control circuit provides a reference voltage to the second control terminal, wherein the input receiver compares an external voltage signal from the first input / output contact at the first control terminal with the reference voltage to generate a first input voltage signal used by the control circuit to write data to the nonvolatile memory cell; and wherein the control circuit is configured to operate in a test mode in which the control circuit routes the output voltage signal from an output of a stage of the output circuit other than the off-chip driver stage to the second control terminal, wherein the input receiver compares a reference voltage from the first input / output contact at the first terminal with the output voltage signal at the second control terminal to generate a second input voltage signal.

15. The memory die of claim 14 wherein the control circuit comprises: A switch logic element is configured to provide the reference voltage to the second control terminal when in the normal mode, wherein the switch logic element is configured to provide the output voltage signal to the second control terminal when in the test mode.

16. The memory die of claim 14 wherein the control circuit comprises: a built-in self-test circuit in communication with the input receiver and with the output circuit, wherein the built-in self-test circuit is configured to provide the output voltage signal to the output circuit during the test mode, wherein the built-in self-test circuit is configured to receive the output voltage signal from the input receiver during the test mode, wherein the built-in self-test circuit is configured to compare the output voltage signal received from the input receiver with the output voltage signal provided to the output circuit and output a test result based on the comparison.

17. The memory die of claim 14, wherein the control circuit is further configured to: sampling the first input voltage signal from a first output node of the input receiver when in the normal mode; and When in the test mode, the second input voltage signal from the second output node of the input receiver is sampled, wherein the first input voltage signal at the first output node is complementary to the second input voltage signal at the second output node.

18. The memory die of claim 14, wherein the control circuit is configured to route the output voltage signal from an input of the off-chip driver to the second control terminal during the test mode.

19. The memory die of claim 14, wherein the first control terminal is an external input connected to the first input / output contact and the second control terminal is an internal input not connected to any input / output contact.

20. The memory die of claim 14, further comprising: A data generating circuit is configured to generate the output voltage signal.

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