Semiconductor substrate configuration structure

Abstract

A semiconductor substrate configuration includes a semiconductor substrate (10), the semiconductor substrate (10) including a dielectric insulating layer (11) and a first metallization layer (111) attached to the dielectric insulating layer (11), wherein the first metallization layer (111) is disposed on the dielectric insulating layer (11) in a vertical direction (z). The semiconductor substrate configuration further includes a conductive coating (20) disposed on the first metallization layer (111) in the vertical direction (z) such that the first metallization layer (111) is disposed between the conductive coating (20) and the dielectric insulating layer (11). In a horizontal plane (x-y) within a first distance (x1) from the outer periphery of the conductive coating (20), the first metallization layer (111) does not include any cavities or trenches (40), or includes only cavities or trenches (40) having a maximum width (w40) less than 10 μm in a horizontal direction (x, y) and a maximum depth (d40) less than 3 μm in a vertical direction (z).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate configuration structure, and more particularly to a semiconductor substrate configuration structure having a metal layer disposed thereon. Background Art

[0002] A power semiconductor module configuration structure typically includes at least one semiconductor substrate disposed in a housing. A semiconductor configuration structure including a plurality of semiconductor bodies (e.g., two IGBTs in a half-bridge configuration) is disposed on each of the at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. For example, the semiconductor bodies are mounted on the first metallization layer. The second metallization layer may optionally be attached to a substrate. The controllable semiconductor devices are typically mounted to the semiconductor substrate by soldering or sintering techniques. A metal layer may be disposed between the semiconductor body and the first metallization layer. For example, the metal layer forms a connection layer that mechanically and electrically couples the semiconductor body to the semiconductor substrate. Generally, a thin metal coating is disposed between such a metal connection layer and the first metallization layer. When the metal coating is formed on the semiconductor substrate, an undesired cavity typically appears in the first metallization layer adjacent to the metal coating. After the process of forming the metal coating has been completed, contaminants may remain in the undesired cavity. For example, these contaminants may be released during a subsequent sintering process of mounting the semiconductor body on the substrate and during subsequent process steps such as a cleaning step, and may cause an undesired oxidation of the metallization layer of the semiconductor substrate at the end of the production line. This may result in a loss of yield.

[0003] There is a need for a semiconductor substrate that reduces yield loss at the end of the production line. Summary of the Invention

[0004] A semiconductor substrate configuration structure includes: a semiconductor substrate including a dielectric insulating layer and a first metallization layer attached to the dielectric insulating layer, wherein the first metallization layer is disposed on the dielectric insulating layer in a vertical direction. The semiconductor substrate configuration structure further includes a conductive coating disposed on the first metallization layer in a vertical direction such that the first metallization layer is disposed between the conductive coating and the dielectric insulating layer. In a horizontal plane within a first distance from the outer periphery of the conductive coating, the first metallization layer does not include any cavities or trenches, or includes only cavities or trenches having a maximum width of less than 10 μm in a horizontal direction and a maximum depth of less than 3 μm in a vertical direction.

[0005] The present invention can be better understood with reference to the following drawings and description. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles of the present invention. Further, in the drawings, like or identical reference numerals designate corresponding parts in different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view of a semiconductor substrate configuration structure.

[0007] Figures 2A - 2C Schematically shows a conventional process for forming a semiconductor module configuration structure.

[0008] Figures 3A - 3D Schematically shows an exemplary method for forming a semiconductor substrate configuration structure.

[0009] Figure 4A and 4B show top views of the semiconductor substrate configuration structure before and after forming a metal coating when using a conventional plating process.

[0010] Figure 5A and 5B show top views of the semiconductor substrate configuration structure before and after forming a metal coating when using an exemplary plating process. DETAILED DESCRIPTION

[0011] In the following detailed description, reference is made to the drawings. The drawings show specific examples in which the present invention can be practiced. It should be understood that, unless otherwise specifically noted, the various features and principles described in connection with each example can be combined with each other. In the specification and the claims, certain elements are named "first element", "second element", "third element", etc. and should not be construed as an enumeration. Instead, such naming is merely used to refer to different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The semiconductor body described herein can be made of (doped) semiconductor material and can be a semiconductor chip or be included in a semiconductor chip. The semiconductor body has electrical connection pads and includes electrodes.

[0012] Referring to Figure 1 , a cross-sectional view of a semiconductor substrate configuration structure is schematically shown. The semiconductor substrate configuration structure includes a semiconductor substrate 10. The semiconductor substrate 10 includes a dielectric insulating layer 11, a first metallization layer 111 attached to the dielectric insulating layer 11, and a second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is disposed between the first and second metallization layers 111, 112. However, the semiconductor substrate 10 may also include only the first metallization layer 111 and omit the second metallization layer 112.

[0013] Each of the first and second metallization layers 111, 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during the operation of the semiconductor substrate configuration structure. The semiconductor substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic, such as a thin ceramic layer. The ceramic may be composed of or include one of the following materials: alumina; aluminum nitride; zirconia; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). For example, an insulated metal substrate typically includes such a dielectric insulating layer 11: the dielectric insulating layer 11 includes (filled) materials, such as epoxy resin or polyimide. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. Such particles may include, for example, Si2O, Al2O3, AlN, or BN, and may have a diameter between about 1 μm and about 50 μm. The substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may be composed of or include a cured resin.

[0014] Generally, one or more semiconductor bodies 22 may be disposed on the semiconductor substrate 10. Each of the semiconductor bodies disposed on the semiconductor substrate 10 may include an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), and / or any other suitable semiconductor element. One or more semiconductor bodies 22 may form a semiconductor configuration structure on the semiconductor substrate 10. In Figure 1 In the example shown, only one semiconductor body 22 is schematically shown.

[0015] Figure 1 the first metallization layer 111 and the second metallization layer 112 of the semiconductor substrate 10 therein are continuous layers. However, in Figure 1 the configuration structure shown, the first metallization layer 111 and / or the second metallization layer 112 can also be a structured layer. A "structured layer" means that the first or second metallization layer 111, 112 is not a continuous layer, but includes recesses between different sections of the layer. For example, different semiconductor bodies 22 can be mounted to the same or different sections of the first metallization layer 111. Different sections of the first metallization layer 111 may not have an electrical connection, or may be electrically connected to one or more other sections using an electrical connection structure (not specifically shown), such as bonding wires or bonding pads. For example, the electrical connection structure can also include connection plates or conductor rails, just to name a few examples here.

[0016] The semiconductor body 22 can be electrically and mechanically connected to the semiconductor substrate 10 by means of a conductive connection layer 21. For example, such a conductive connection layer 21 can be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as a sintered silver powder layer. Generally, an additional conductive coating 20 is arranged between the first metallization layer 111 and the conductive connection layer 21. The conductive coating 20 is generally a layer having a thickness of several (hundred) nanometers in the vertical direction z. The conductive coating 20 is generally a thin metal layer. For example, the conductive coating 20 can include a metal material such as silver. For example, the conductive coating 20 can also include other conductive materials, such as nickel or gold. The conductive coating 20 can also include a combination of two or more of silver, nickel, and gold. After the conductive coating 20 is applied, ion exchange occurs between the first metallization layer 111 and the conductive coating 20. For example, if the first metallization layer 111 is a copper layer and the conductive coating 20 is a thin silver layer, copper atoms can diffuse into the conductive coating 20, while silver ions can diffuse into the first metallization layer 111. This makes the boundary between the metallization layer 111 and the conductive coating 20 blurred. In other words, there is no longer a clear boundary between the first metallization layer 111 and the conductive coating 20. A transition region containing ions of two materials is formed.

[0017] Once the conductive coating 20 has been formed, the conductive connection layer 21 can be formed on the conductive coating 20 such that the conductive coating 20 is arranged between the conductive connection layer 21 and the first metallization layer 111. The conductive connection layer 21 generally has a greater thickness than the conductive coating 20 in the vertical direction z. In a further step, the semiconductor body 22 can be arranged on the conductive connection layer 21, and for example, a sintering process can be performed to mechanically and electrically couple the semiconductor body 22 to the semiconductor substrate 10. Then, the conductive connection layer 21 provides a permanent connection between the semiconductor body 22 and the semiconductor substrate 10.

[0018] Now refer toFigures 2A - 2C , schematically shows a conventional method for forming a semiconductor substrate configuration structure including a semiconductor substrate 10 with a conductive coating 20 arranged thereon. In a first step, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes at least a first metallization layer 111. As described above in conjunction with Figure 1 As described above, the first metallization layer 111 is arranged on the dielectric insulating layer 11. The mask 30 is arranged on the first metallization layer 111. The mask 30 generally has a varying thickness in the vertical direction z. The vertical direction z is a direction perpendicular to the top surface of the semiconductor substrate 10. For example, the first metallization layer 111 is arranged on the dielectric insulating layer 11 in the vertical direction z. The mask 30 is arranged on the first metallization layer 111 so that the first metallization layer 111 is arranged between the mask 30 and the dielectric insulating layer 11. The mask 30 has at least one opening. In other words, not all of the first metallization layer 111 is covered by the mask 30. The opening has a cross-section corresponding to the cross-section of the conductive coating 20 to be formed on the semiconductor substrate 10. For example, the cross-section may be a square cross-section or a rectangular cross-section ( Figures 2A - 2C The cross section is not visible in the sectional view of FIG.

[0019] If more than one conductive coating 20 is to be formed on semiconductor substrate 10 , mask 30 includes more than one opening. The number of openings in mask 30 corresponds to the number of conductive coatings 20 to be formed on semiconductor substrate 10 .

[0020] The mask 30 covers all portions of the semiconductor substrate 10 that are not covered by the conductive coating 20. As described above, when the mask 30 is applied to the semiconductor substrate 10, the thickness of the mask 30 in the vertical direction z is generally non-uniform. Typically, the thickness of the mask 30 adjacent to the opening is less than the thickness of the mask 30 away from the opening. In other words, the angle α formed between the top surface of the semiconductor substrate 10 and the edge of the mask 30 is, for example, between 130° and 170°. Figure 2B This typically results in the formation of undesirable cavities or trenches 40 in the first metallization layer 111 adjacent to the conductive coating 20, as schematically shown in FIG. The conductive coating 20 may be applied by any suitable process, such as screen printing, a plating process, or evaporative deposition. Figure 2B The undesired material removal of the first metallization layer 111 and the formation of cavities or trenches 40 during the step of applying the electrically conductive coating 20 are indicated in FIG.

[0021] Once the conductive coating 20 has been formed on the semiconductor substrate 10, the mask 30 may be removed. Figure 2C For example, in order to remove the mask 30, an etching process may be used. The thickness of the mask 30 in the vertical direction z is reduced by Figure 2Cis indicated by the dashed lines. Since the mask 30 has a varying thickness, the thickness of some portions (e.g., adjacent to the conductive coating 20) is reduced to zero earlier than that of other portions. Thus, the chemical substance used to remove the mask 30 can etch into the first metallization layer 111 in those portions of the mask 30 that have already been removed earlier. This can cause the existing cavities or trenches 40 to expand and new cavities or trenches 40 to form. Thus, once the mask 30 is completely removed from the semiconductor substrate 10, the cavities or trenches 40 typically have a maximum width w40 greater than 10 μm in the horizontal direction and a maximum depth d40 greater than 3 μm in the vertical direction z. The cavities or trenches 40 are typically arranged within a distance of 2 mm from the conductive coating 20.

[0022] After removing the mask 30, different kinds of contaminants may remain in the cavities or trenches 40. For example, residues of the chemical substance used to remove the mask 30 can remain in the cavities or trenches 40, such as alkali ions or other etching materials. When the semiconductor body 22 is subsequently mounted on the semiconductor substrate 10 such that the conductive coating 20 and the conductive connection layer 21 are arranged between the semiconductor body 22 and the semiconductor substrate 10, the contaminants react with the materials of different components of the semiconductor substrate 10, such as the material of the conductive coating 20. For example, this may cause an undesired rapid oxidation of the first metallization layer 111, which may significantly shorten the lifespan of the semiconductor substrate configuration structure.

[0023] To reduce or even prevent the formation of undesired cavities or trenches 40, the mask 30 is applied uniformly to the semiconductor substrate 10. According to another example, the thickness of the mask near its edge is even greater than the thickness away from its edge. In Figure 3A a mask 30 with a uniform thickness is schematically shown. In other words, the mask 30 has a substantially uniform thickness in the vertical direction z. In particular, the thickness d30 of the mask 30 near its edge can be the same as the thickness d32 of the mask 30 in a region further away from its edge. According to another example, the thickness d30 of the mask 30 near its edge can be even greater than the thickness d32 of the mask 30 in a region further away from its edge. The edge region of the mask 30 can be a region arranged within, for example, 2 mm or 4 mm from the edge of the mask 30. In other words, the width w30 of the edge region in the horizontal direction (e.g., the first horizontal direction x) can be at least 2 mm or at least 4 mm. For example, the angle α formed between the top surface of the semiconductor substrate 10 and the edge of the mask 30 can be between 90° and 130°. Figure 3B and 3C The subsequent steps of forming the conductive coating 20 and removing the mask 30 in Figure 2B and 2CThe steps described are similar. The resulting conductive coating 20 can have a thickness d1 of at least 300 nm to 1000 nm in the vertical direction z. Since the thickness d30, d32 of the mask 30 is uniform, the mask 30 is uniformly removed during the stripping process. Therefore, no cavities or grooves are formed adjacent to the conductive coating 20. The same applies to the case where d30>d32. In those cases, no cavities or grooves are formed adjacent to the conductive coating 20 either.

[0024] exist Figure 3D The resulting semiconductor substrate configuration is schematically shown in FIG. It can be seen that there are no cavities or grooves within the first distance x1 from the periphery of the conductive coating 20. For example, the first distance x1 may be 2 mm. However, due to process irregularities or anomalies, small cavities or grooves 40 may still be formed within the first distance x1 (in Figure 3D However, such a small groove or cavity 40 is more convenient than the above combination. Figures 2A - 2C The described cavities or grooves 40 are much smaller. In particular, any cavity or groove 40 within the first distance x1 from the periphery of the conductive coating 20 has a maximum width w40 of less than 10 μm in the horizontal direction x, y or horizontal plane and a maximum depth d40 of less than 3 μm in the vertical direction z. Such small cavities or grooves 40 can store fewer or even no contaminants. Therefore, the risk of rapid oxidation during subsequent processes is greatly reduced.

[0025] Problems may also arise if the outer edge of the mask 30 is not formed uniformly. Figures 4A - 4B The top view of FIG. Figure 4A , a mask 30 arranged on a semiconductor substrate 10, in particular on a first metallization layer 111, is schematically shown. Through the opening in the mask 30, the first metallization layer 111 is visible. However, the edge of the mask 30 is uneven. In other words, the edge of the mask does not form a straight line. When the conductive coating 20 is formed and the mask 30 is removed, this can also lead to undesirable cavities or trenches 40. Figure 4B The final state of the semiconductor substrate configuration is shown. The conductive coating 20 is arranged on the semiconductor substrate 10, and the mask 30 has been removed from the semiconductor substrate 10. In other words, the first metallization layer 111 is Figure 4A Those areas covered by mask 30 in Figure 4B is visible in the final state, which is similar to Figure 3A and 3D There are a plurality of cavities or trenches 40 in the first metallization layer 111 .

[0026] On the other hand, if the edge of the mask 30 is formed uniformly, as shown in FIG. Figure 5A As schematically shown inFigure 5B As shown, no cavity or trench 40 is formed in the first metallization layer 111, or only small cavities or trenches 40 are formed. The small cavities or trenches 40 also mean that the cavities or trenches 40 within the first distance x1 from the outer periphery of the conductive coating 20 have a maximum width w40 of less than 10 μm in the horizontal directions x, y or in the horizontal plane, and a maximum depth d40 of less than 3 μm in the vertical direction z. If the edges of the mask 30 are formed evenly, potential under-etching of the mask 30 can be prevented. If, for example, Figures 4A - 4B such under-etching occurs in the example of

[0027] the first metallization layer 111 may be damaged in the under-etched area, which can lead to unwanted cavities and trenches 40.

[0028] A method for forming a semiconductor substrate configuration structure may include forming a mask 30 on a semiconductor substrate 10, the semiconductor substrate 10 including a dielectric insulating layer 11 and a first metallization layer 111 disposed on the dielectric insulating layer 11. The mask 30 includes at least one opening. In other words, forming the mask 30 includes forming the mask 30 only on some regions of the first metallization layer 111, while at least one region of the first metallization layer 111 remains without the mask 30. The first metallization layer 111 is disposed between the mask 30 and the dielectric insulating layer. Forming the mask 30 includes applying a substantially uniform layer of material on the first metallization layer 111. Alternatively, the material of the mask 30 may be applied to the first metallization layer 111 such that the thickness d30 adjacent to the edge of the mask 30 is greater than the thickness d32 of the mask 30 further away from the edge. Optionally, the material may then be hardened in a subsequent step (e.g., by performing a drying or heating process to remove liquid from the material). Then at least one conductive coating 20 is formed on the first metallization layer 111. The at least one conductive coating 20 is formed on those regions of the first metallization layer 111 that are not covered by the mask 30. Once the at least one conductive coating 20 is formed, the mask 30 is removed from the semiconductor substrate 10 in a subsequent step. This obtains a semiconductor substrate configuration structure including the semiconductor substrate 10, the semiconductor substrate 10 including a dielectric insulating layer 11 and a first metallization layer 111 attached to the dielectric insulating layer 11, wherein the first metallization layer 111 is disposed on the dielectric insulating layer 11 in the vertical direction z. The resulting semiconductor substrate configuration structure further includes a conductive coating 20 disposed on the first metallization layer 111 in the vertical direction z such that the first metallization layer 111 is disposed between the conductive coating 20 and the dielectric insulating layer 11. In the horizontal plane x-y within a distance of 2 mm from the outer periphery of the conductive coating 20, the first metallization layer 111 does not include any cavities or trenches 40, or includes only cavities or trenches 40 having a width w40 less than 10 μm in the horizontal directions x, y and a depth d40 less than 3 μm in the vertical direction z.

Claims

1. A method for forming a semiconductor substrate configuration structure, the method comprising: A mask (30) is formed on a semiconductor substrate (10) which includes a dielectric insulating layer (11) and a first metallization layer (111) disposed on the dielectric insulating layer (11), the mask (30) including at least one opening, wherein the first metallization layer (111) is disposed between the mask (30) and the dielectric insulating layer (11); A conductive coating (20) is formed on the first metallization layer (111), wherein the conductive coating (20) is formed in the at least one opening on those regions of the first metallization layer (111) not covered by the mask (30); and After forming the conductive coating (20), the mask (30) is removed from the semiconductor substrate (10), wherein forming the mask (30) includes either applying a layer of homogeneous material on the first metallization layer (111) such that the thickness (d30) of the mask (30) in a region adjacent to the edge of the mask (30) in the vertical direction (z) is equal to the thickness (d32) of the mask (30) in a region further away from the edge in the vertical direction (z), or applying the material of the mask (30) on the first metallization layer (111) such that the thickness (d30) of the mask (30) in a region adjacent to the edge of the mask (30) is greater than the thickness (d32) of the mask (30) in a region further away from the edge, wherein the vertical direction (z) is perpendicular to the top surface of the semiconductor substrate (10), wherein the region adjacent to the edge of the mask (30) is a region disposed within 2 mm or 4 mm from the edge of the mask (30); and wherein the mask (30) is formed such that the angle (α) between the top surface of the semiconductor substrate (10) and the edge of the mask (30) is between 90° and 130°.

2. The method according to claim 1, wherein, The method further includes hardening the material of the mask (30) before forming the conductive coating (20).

3. The method according to claim 2, wherein, Hardening the material of the mask (30) includes removing liquid from the material by performing a drying or heating process.

4. The method according to any one of claims 1 to 3, wherein, The conductive coating (20) is formed to have a thickness (d1) of at least 300 to 1000 nm in the vertical direction (z).

5. The method according to any one of claims 1 to 3, wherein, Removing the mask (30) includes an etching process.

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