Methods of processing semiconductor wafers, semiconductor wafers, clamps, and semiconductor devices

Abstract

A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first major surface and a second major surface. A defect is created inside the semiconductor wafer to define a detachment plane parallel to the first major surface. The first major surface is processed to define a plurality of electronic semiconductor components. A glass structure is provided, the glass structure including a plurality of openings. The glass structure is attached to the processed first major surface, each of the plurality of openings leaving a respective region of the plurality of electronic semiconductor components uncovered, respectively. A polymer layer is applied to the second major surface, and the semiconductor wafer is split along the detachment plane into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer below its glass transition temperature. The semiconductor slice includes the plurality of electronic semiconductor components.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a method for processing a semiconductor wafer. The invention also relates to a semiconductor wafer and a semiconductor device. The present disclosure also relates to a clip for electrically connecting pads arranged on a semiconductor wafer. BACKGROUND

[0002] To improve the properties of a semiconductor device, the final thickness of the semiconductor material in the device is often reduced. Especially for vertical power devices, the final thickness influences the electrical properties.

[0003] A semiconductor wafer can be thinned by etching, lapping, sawing, etc. These removal processes can be time consuming or resource intensive. Another method of thinning can be to split the wafer.

[0004] The handling of thin wafers is complex. Brittle semiconductor material is prone to breaking once it is thinned. Semiconductor wafers to be thinned and already thinned semiconductor wafers can be mounted on carriers for safe handling.

[0005] In case a thinned semiconductor wafer is arranged on a carrier, it is not possible to electrically contact both sides of the wafer. It is then not possible to measure the electrical properties of a vertical device with electrical contacts on both sides on wafer level.

[0006] The lateral dimensions of semiconductor devices also tend to decrease. The smaller the lateral dimensions, the smaller the pads have to be that have to be electrically connected. On the other hand, electrical connectors that connect power devices can need a sufficiently large cross section to allow a high current to flow. SUMMARY

[0007] One example relates to a method for processing a semiconductor wafer. The method provides a semiconductor wafer having a first main surface and a second main surface opposite the first main surface. A defect is created inside the semiconductor wafer. The defect defines a detachment plane parallel to the first main surface. According to the method, the first main surface is processed to define a plurality of electronic semiconductor components. The method further provides a glass structure. The glass structure has a plurality of openings. The glass structure is attached to the processed first main surface. Each of the plurality of openings leaves a respective area of the plurality of electronic semiconductor components uncovered, respectively. A polymer layer is applied to the second main surface. The method splits the semiconductor wafer into semiconductor slices and a remaining semiconductor wafer by cooling the polymer layer below its glass transition temperature. The semiconductor slices extend between the first main surface and the detachment plane. The semiconductor slices comprise the plurality of electronic semiconductor components.

[0008] One example relates to a semiconductor wafer. The semiconductor wafer has a first major surface and a second major surface opposite the first major surface. A detachment plane defined by a defect is located inside the semiconductor wafer. The detachment plane is parallel to the first major surface. A plurality of electronic semiconductor components are formed at the first major surface and between the first major surface and the detachment plane. A glass structure is attached to the first major surface. The glass structure includes a plurality of openings. Each of the plurality of openings respectively leaves a respective region of the plurality of electronic semiconductor components uncovered.

[0009] One example relates to a clip for electrically connecting a pad disposed on a bottom of an opening in a glass structure. The clip includes a rivet forming a first portion of the clip or a single piece of sheet metal bent to form the first portion and a second portion, the rivet riveted to the second portion of the clip. The second portion is configured to extend to a terminal. The first portion has a width that is about half or more of a width of the opening. The first portion is configured to extend straight through to the bottom of the opening.

[0010] One example relates to a semiconductor device. The semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface. The first major surface includes a pad and a glass structure. The glass structure includes an opening. An edge of the opening surrounds the pad. An aspect ratio between a thickness of the glass structure surrounding the opening and a width of the opening is equal to one to three or more. The semiconductor device includes a carrier on which the semiconductor die is mounted. The second major surface of the semiconductor die faces the carrier. An adhesive is on a bottom of the opening. A clip electrically connects the pad. The clip includes a rivet forming a first portion of the clip or a single piece bent to form the first portion and a second portion, the rivet riveted to the second portion of the clip. The second portion is configured to extend to a terminal on the carrier. The first portion has a width that is about half or more of a width of the opening. The first portion is configured to extend straight through to the bottom of the opening. The first portion of the clip is electrically connected to the pad by way of the adhesive. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings illustrate examples and, together with the description, serve to explain the principles of the disclosure. Other examples and many of the intended advantages of the present disclosure will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like or similar designations can represent like or similar parts throughout the several views.

[0012] Figures 1A-1H is a conceptual diagram illustrating an example method for processing a semiconductor wafer, according to one example.

[0013] Figure 2 is a flowchart of an example method for processing a semiconductor wafer, according to one example.

[0014] Figure 3 is a conceptual top-down view of a semiconductor wafer according to one example.

[0015] Figure 4A and 4B is a conceptual cross-sectional view along line A-A' of Figure 3

[0016] Figure 5 is a conceptual cross-sectional view of a semiconductor device according to one example.

[0017] Figure 6A is a conceptual perspective view of a clip including a rivet according to one example.

[0018] Figure 6B is a conceptual cross-sectional view of a clip including a rivet according to one example.

[0019] Figure 7A is a conceptual perspective view of a curved clip according to one example.

[0020] Figure 7B is a conceptual perspective view of a curved clip according to one example.

[0021] Figure 7C is a conceptual cross-sectional view of a curved clip attached to an example semiconductor device according to one example. DETAILED DESCRIPTION

[0022] In the following description, numerous specific details are set forth to provide a thorough understanding of one or more aspects of the examples. However, it will be apparent to one skilled in the art that one or more aspects of the examples can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the examples.

[0023] ​Various aspects generali zed can be implemented in various forms. The following description descnbes and illustrates various combinations and configurations. It is understood that the described aspects and / or examples are merely examples, and that other aspects and / or examples can be utilized, and structural and functional modifications can be made without departing from the scope of the present disclosure. Additionally, while an example can be disclosed employing a particular feature or aspect, this feature or aspect can be utilized in combination with any other feature or aspect disclosed herein, and in any combination. Further, to the extent that the terms "includes," "including," "has," "having," or the like are used in the detailed description and / or claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open term with the most possible scope. Additionally, the term "exemplary" is used herein merely for the purpose of providing an example and is not intended to convey an indication of a preferred or ideal implementation.

[0024] Examples described herein can relate to a semiconductor wafer. The semiconductor wafer can include any kind of semiconductor material. The semiconductor wafer can include a particular semiconductor material such as Si, SiC, SiGe, GaAs, GaN, or any other semiconductor material. The semiconductor wafer can have a circular form. The diameter of the circular semiconductor wafer can be about 110 mm, 150 mm, 200 mm, 300 mm, or 450 mm. The diameter of the circular semiconductor wafer can have any other value. The semiconductor wafer can have a rectangular form. The semiconductor wafer can have a square form. The semiconductor wafer can be made of SiC and have a diameter of 150 mm. The thickness of the semiconductor wafer can be between about 200 pm and about 700 pm. The thickness of the semiconductor wafer can be about 350 pm or about 500 pm.

[0025] Aspects of the described examples can include generating a defect within a semiconductor wafer. The defect can be generated with the aid of at least one radiation source. The radiation source can be a laser. The radiation source can be a femtosecond laser. The defect generated within the semiconductor wafer can determine an out-of-plane parallel to a surface of the semiconductor wafer. The out-of-plane or defect layer can govern or guide crack propagation. Stress applied to the semiconductor wafer can cause crack propagation. Exposing the wafer to the radiation source can generate a type of perforation within the semiconductor wafer in a first step, crack propagation along the perforation in a second step. Forming the defect layer and starting crack propagation can allow for splitting a thin slice from the semiconductor wafer. In other words: the defect layer can be introduced, e.g. by a laser process, in order to weaken the substrate at a desired depth, and a subsequent process is used to split the substrate along the defect layer. This can be achieved by applying a thermal (cold / thermal gradient) force or a mechanical (e.g. ultrasonic) force. The thickness of the split slice can be less than 200 pm or less than 100 pm or less than 80 pm or less than 60 pm or less than 40 pm or less than 20 pm. In multiple examples, the thickness of the slice can be comprised between about 30 and 50 pm.

[0026] Examples described herein can include an electronic semiconductor component processed on a surface of a semiconductor wafer. The electronic semiconductor component can be a semiconductor device processed at least partially. The electronic semiconductor component can be processed or partially processed in and on the semiconductor wafer. Partial processing can indicate that the semiconductor device is not fully completed. Further processes, e.g. forming doped regions, contact regions, metallization or dicing, can still be required to obtain an operable semiconductor device. The semiconductor device can be at least a two-terminal device, e.g. a diode. The semiconductor device can also be a three-terminal device, e.g. a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET) and a thyristor, etc. The semiconductor device can also comprise more than three terminals. The semiconductor device can be a vertical device. The electronic component formed on the semiconductor wafer can be separated by a cut line.

[0027] Examples disclosed herein can include a glass structure. The thickness of the glass structure can be comprised between about 100 pm and 700 pm or between about 400 pm and 600 pm. The thickness of the bars can be about 500 pm. The thickness of the bars can be comprised between about 150 pm and 190 pm. The glass structure can comprise any suitable glass material, such as pure silica or any type of float glass. The glass structure can have a plurality of openings. The lateral dimension of the plurality of openings or of one of the openings can be adapted to the lateral dimension of the semiconductor device or semiconductor component. The lateral dimension of the plurality of openings or of one of the openings can be adapted to the lateral dimension of the contact pads on the surface of the semiconductor component or semiconductor device. The lateral width of the openings can be less than 2 mm, or less than 1.5 mm or less than 1 mm. The lateral width of the openings can be about 1 mm. The lateral width of the openings can be about 1.2 mm. The area of the openings can be less than 3 mm 2 or less than 2.5 mm 2 or less than 2 mm 2 or less than 1.5 mm 2 The area of the openings can be 1.1 x 1.2 mm 2 The openings can be rectangular. The glass structure can be a glass grid. The glass grid can be a regular glass grid. The openings of the glass grid can be separated by bars. The lateral width of the bars can be comprised between about 100 pm and 200 pm. The lateral width of the bars can be about 155 pm. The bars can form a rim around the openings. The distance of the bars can be adapted to the distance of the scribe lines on the semiconductor wafer. The thickness of the bars can be comprised between about 300 pm and 700 pm or between about 400 pm and 600 pm. The thickness of the bars can be about 500 pm. The aspect ratio between the thickness of the glass structure, i.e. the bars, and the width of the openings can be about 1 :3 or about 1 :2.5 or 1 :2 or more, with the aspect ratio reaching 1 : 1 or even more as the thickness of the glass structure is greater than the width of the openings. The thickness of the bars can be about 500 pm while the width of the openings can be between about 1 mm and 1.2 mm.

[0028] The glass structures described herein can be formed by an etching process, which can be a wet etching process. The etching process can comprise forming a mask on both sides of the glass wafer using photolithography techniques. Once the mask is formed on the surface of the glass wafer, the glass wafer can be etched from both surfaces to a depth of about half of the glass wafer from each side to obtain the openings. The glass structures described herein can be formed by a laser-induced deep etching (LIDE) process. In the LIDE process, the openings are formed in a two-step process. First, the glass surface is irradiated by laser pulses, which creates a linear modification across the entire glass thickness. Subsequently, a wet etching is performed to enlarge the laser pulse-induced micro-perforations.

[0029] The glass structure described above can be attached to the processed first major surface of the semiconductor wafer. The glass structure can be permanently or in other words irreversibly attached to the semiconductor wafer. The glass structure can be attached using a polymer adhesive. The glass structure can be attached using an epoxy. The glass structure can be attached using a ceramic adhesive. The glass structure can be attached using a glass solder. The glass structure can be attached using anodic bonding, glass paste bonding, or fusion bonding. The glass structure can be attached using any other method that provides a permanent connection to the semiconductor wafer. The permanent connection can accommodate a wide temperature range. The permanent connection can withstand temperatures as high as 300°C or even higher and as low as -170°C or even lower.

[0030] The glass structure can be arranged relative to the semiconductor wafer such that the plurality of openings in the glass structure respectively leave each region of the plurality of electronic semiconductor components uncovered. The glass structure can be arranged relative to the semiconductor wafer such that the strip of the glass structure covers the scribe line of the semiconductor wafer. The glass structure can include two or more openings for each semiconductor component. The two openings per semiconductor component can allow the semiconductor component to have an uncovered control pad and a power pad. The control pad can provide an electrical connection to the gate of a field effect transistor or to the base of a bipolar transistor. The power pad can provide an electrical connection to the source or drain of a field effect transistor or to the emitter or collector of a bipolar transistor. The openings can be sized to be smaller than the size of the final semiconductor die.

[0031] Examples described herein can include applying a polymer layer to the second major surface of the semiconductor wafer. The polymer layer can be adapted to induce stress to the semiconductor wafer upon cooling. Examples can include applying a sacrificial layer to the second major surface of the semiconductor wafer prior to applying the polymer layer. Examples described herein can include applying the polymer layer to the first major surface of the semiconductor wafer with or without an intermediate sacrificial layer. Examples described herein can include cooling the polymer layer below its glass transition temperature. The cooling can include rapid cooling. Cooling the polymer layer can induce stress to the semiconductor wafer and cause the semiconductor dies to be split from the semiconductor wafer along a predefined detachment layer.

[0032] Examples disclosed herein can include cutting the semiconductor dies permanently attached with the glass structure along the scribe line into semiconductor chips. The singulation or cutting can be achieved by scribe-and-break, laser cutting, sawing, or any other method as is commonly done. In the case where a strip of the glass structure is arranged along the scribe line, the glass structure can be cut simultaneously. The strip of the glass structure can be large enough to leave a rim around the opening on each semiconductor chip. The rim can provide stability to the thin semiconductor chip. The rim can provide high voltage protection.

[0033] Examples described herein can include a clip for electrically connecting a pad disposed on a bottom of an opening in a glass structure. The clip can provide a cross section large enough to conduct high current handled by a semiconductor device. The high current to be conducted can be higher than 5 A, higher than 6 A, or higher than 7 A or more. The current required can be approximately 6.9 A. The cross sectional area required can be greater than 800 pm 2 , 900 pm 2 , or 1000 pm 2 or more.

[0034] The clip described herein can include copper. The clip described herein can be of any other electrically conductive material. The clip can include a first portion that extends to a bottom of an opening of a glass structure. The first portion can be formed of a rivet. The rivet can have a circular cross section. The diameter of the rivet can be greater than 200 pm, greater than 300 pm, greater than 500 pm, or more. The diameter of the rivet can be approximately 500 pm to 700 pm. The rivet can have a diameter approximately half or more of a width of the opening. The rivet can be configured to extend straight to the bottom of the opening. The rivet can be riveted to a second portion of the clip. The second portion can extend to a terminal. The second portion can be formed of a sheet of metal. The second portion can have a rectangular cross section. The second portion can have a cross sectional area corresponding to a cross sectional area of the rivet.

[0035] The clip described herein can include a first portion integrally formed with a second portion. The first portion and the second portion can be formed of a sheet of metal, which can be a sheet of copper. The clip can be bent such that the first portion and the second portion are approximately at right angles to each other. The clip can have a rectangular cross section. The first portion can have a square cross section. The width of the first portion can be approximately 200 pm, greater than 300 pm, greater than 500 pm, or more. The width of the first portion can be approximately 500 pm to 700 pm. The first portion can have a width approximately half or more of a width of the opening. The first portion can be configured to extend straight to the bottom of the opening. The second portion can extend to a terminal. The second portion can have a rectangular cross section. The second portion can have a cross sectional area corresponding to a cross sectional area of the first portion. The second portion can have a varying cross section.

[0036] Examples disclosed herein can include a semiconductor device having a clip. A first portion of the clip can extend into an opening. The opening can include a conductive adhesive at a bottom. The adhesive can attach the clip to the bottom. The adhesive can provide an electrical connection between a pad disposed at the bottom of the opening and the clip. The adhesive can be solder. The adhesive can be conductive paste.

[0037] It should be understood that all the details given above can be applied to the examples discussed below with reference to the accompanying drawings, and any example dimensions or materials given below should be understood as merely examples that do not limit this disclosure.

[0038] Figures 1A-1H This is a conceptual diagram illustrating an example method for processing a semiconductor wafer, based on an example.

[0039] Figure 1A A cross-section of a semiconductor wafer 10 is shown. The semiconductor wafer 10 according to this example may be a SiC (silicon carbide) wafer. The wafer 10 includes a first main surface 12 and a second main surface 14 opposite to the first main surface 12. The SiC wafer according to this example may be a 6-inch wafer with a diameter of 150 mm. The wafer may have a thickness of approximately 500 μm between the first main surface 12 and the second main surface 14. w .

[0040] Figure 1B A semiconductor wafer 10 and a radiation source 16 disposed above a first main surface 12 are shown. According to this example, the radiation source 16 exposes the wafer 10 to a laser beam 18. The laser beam 18 can be configured to produce defects within the semiconductor wafer 10 at a well-defined depth. The well-defined depth takes into account subsequent splitting losses. The laser beam 18 can be focused to produce defects at the well-defined depth. Defects produced at the same depth can define a breakaway plane 20. The breakaway plane 20 is generally parallel to the first main surface 12. The distance t between the first main surface 12 and the breakaway plane 20 is... S It can be between approximately 50 μm and 100 μm. The distance t between the first primary surface 12 and the detachment plane 20. S It can be approximately 50 μm.

[0041] Figure 1C The diagram illustrates a process performed at the first main surface 12 of wafer 10 to form a semiconductor component 22. This process can include any front-end processes required to form the semiconductor component 22. This can include deposition, etching, implantation, growth, doping, diffusion, etc. Although Figure 1C Only four components are shown, but it should be understood that wafer 10 may include many more components 22. A portion of semiconductor component 22 may extend above the first main surface 12. A portion of semiconductor component 22 may extend within the semiconductor body between the first main surface 12 and the detachment plane 20. Semiconductor component 22 may be made of Figure 1C The notched lines are separated. Semiconductor component 22 may include contact pads on the first main surface 12.

[0042] Figure 1DA schematic cross-section of the glass structure 24 is shown. The glass structure 24 can be a glass grid. The glass structure 24 can comprise glass strips 26 with openings 28 therebetween. In the present example, the thickness t of the glass structure 24 can be about 500 pm. In the present example, the width of the openings 28 can be between about 1 mm and 1.5 mm. g

[0043] Figure 1E The glass structure 24 is shown irreversibly attached to the wafer 10 by an adhesive 30. The glass structure 24 can be aligned with the processed wafer 10 so that the semiconductor components 22 are not covered. In other words, the openings 28 can be over at least a portion of the semiconductor components 22. The openings 28 can leave the contact pads of the semiconductor components 22 uncovered. The strips 26 can be arranged on top of and along the cut lines for separating the semiconductor components 22. Each semiconductor component can have more than one opening 28. For example, in case the semiconductor components 22 comprise two contact pads on the first main surface of the wafer 10, each contact pad can have a separate opening 28.

[0044] Figure 1F A prepared state for splitting the processed semiconductor dies from the wafer is shown. A polymer layer 32 is applied to the second main surface 14 of the wafer 10. The polymer layer can have a thermal coefficient that is about two orders of magnitude higher than the semiconductor wafer. In one example, a further polymer layer (not shown) can be applied to the first main surface 12. The assembly comprising the wafer 10, the glass structure 24 and the polymer layer can then be cooled. The cooling can be down to a temperature below the glass transition temperature of the polymer layer. The cooling can be down to a temperature below 0°C. The cooling can be down to below -10°C, below -100°C, below -150°C, below -170°C or even lower. The cooling can be achieved by means of liquid nitrogen, for example. The glass transition changes the physical properties of the polymer layer and exerts a stress on the wafer. The use of the glass transition allows to achieve a relatively high elastic modulus so that a sufficiently large stress can be generated. This stress causes a crack to propagate in the release layer and subsequently causes the dies 34 to split off the wafer. The glass structure 24 stabilizes the dies 34 during the splitting off. An optional additional polymer layer on the glass structure 24 can further act as a stabilizer during the splitting off. An optional additional polymer layer on the glass structure 24 can further enhance the crack propagation during the splitting off. The dies extend between the first main surface 12 and the release layer 20. The semiconductor dies 34 comprise the processed semiconductor portions of the wafer 10.

[0045] Figure 1G ​The semiconductor slice 34 is shown split off from the remaining semiconductor wafer 36. The polymer layer 32 can be detached from the remaining semiconductor wafer 36. This can be achieved, for example, by etching. The remaining semiconductor wafer can still be thick enough, for example, with a starting wafer thickness of 350 μm and a slice thickness of 50 μm, so that the method as explained with reference to 1A-1G can be restarted with the remaining wafer 36 as semiconductor wafer 10. Thus, with the same wafer, multiple processed semiconductor slices can be produced. The sawing loss can be minimized. The backside 38 of the semiconductor slice 34 can be ground, etched or processed in any other form to release any residual damage originating from the splitting process. The permanently attached glass grid 24 stabilizes the thin semiconductor slice 34. The thickness tgof the glass structure 24 can be at least four times the thickness t of the semiconductor slice 34. g The thickness tgof the glass structure 24 can be ten times the thickness t of the semiconductor slice 34. S The thickness tgof the glass structure 24 can be ten times the thickness t of the semiconductor slice 34. S The thickness tgof the glass structure 24 can be ten times the thickness t of the semiconductor slice 34. S The thickness tgof the glass structure 24 can be ten times the thickness t of the semiconductor slice 34.

[0046] Figure 1H The assembly comprising the glass structure 24 and the semiconductor slice 34 is shown rotated by 180° compared to Figure 1G Figure 1H Further backside processing steps for completing the semiconductor component 22 are shown. The backside processing can include an implantation process to form doped example regions 40. The backside processing can include any annealing steps. The backside processing can include forming metallization structures 42, for example, contact pads, connection lines, etc. The glass structure 24 can be thinned after the splitting. At this stage, i.e., after splitting the slice from the wafer, metallization structures 44 can also be formed on the front side 12 of the semiconductor slice 34, i.e., inside the opening 28. The metallization structures 44 can also be formed at an earlier stage. The metallization structures 44 can be formed during the front side processing. When both the front side 12 and the backside 38 are provided with contact pads 42, 44, the semiconductor component 22 can be electrically tested. Thus, electrical measurements can be performed at wafer level. The glass structure 24 stabilizes the wafer during testing, but makes the contact pads 44 accessible. No additional carrier is needed. After testing, the semiconductor slice 34 and the glass structure 24 together can be separated into individual semiconductor dies. The singulation can be achieved by sawing along the cut line 46. Any other cutting method can be used.

[0047] Figure 2 ​is a flowchart of an example method for processing a semiconductor wafer according to an example. At S1, a semiconductor wafer is provided. At S2, a defect is created by means of a laser, preferably a femtosecond laser with pulses of less than 500 fs. The defect is created inside the semiconductor wafer. The defect is located in a plane that defines a detachment plane parallel to a surface of the semiconductor wafer. At S3, a first major surface of the wafer is processed to define a plurality of electronic semiconductor components. At S4, a glass structure is provided. The glass structure comprises a plurality of openings extending from a first surface of the glass structure to a second surface of the glass structure opposite the first surface. The glass structure can comprise one opening for each semiconductor component or more than one opening for each semiconductor component. At S5, the glass structure is permanently attached to the processed first major surface of the semiconductor wafer. The attachment is performed to withstand temperatures of about 300°C - 170°C. At S6, a polymer layer is applied to a second major surface of the wafer opposite the first major surface. The polymer can have a glass transition temperature. At S7, the semiconductor wafer is split into semiconductor dies comprising the processed first surface of the semiconductor wafer and a remaining semiconductor wafer. The splitting is achieved by cooling the assembly below the glass transition temperature to achieve cold splitting.

[0048] Figure 3 is a conceptual top-down view of a semiconductor wafer 10 or a semiconductor die 34 with a glass structure 24 attached. The top-down view does not change after splitting. It shows a grid formed by the regular glass structure 24 that bounds the openings 28. At the bottom of the openings are the uncovered semiconductor components 22. The entire uncovered surface of one semiconductor component 22 can form a contact pad. On the uncovered surface of one semiconductor component 22, more than one contact pad can be formed (not shown). In the middle of the bars 26 that form the grid 24, there are cut-out lines 46.

[0049] Figure 4A is a conceptual cross-sectional view along the line A-A’ in Figure 3 According to an example. On the semiconductor die 34, two bars 26 of the glass structure 24 are shown. Between the two bars 26, a contact pad 44 is shown. The bars 26 show two concave surfaces 26a, 26b. These surfaces arise when etching the openings 28 into the glass structure starting from both surfaces using a lithographic mask as described above. The wet etch undercuts the mask and creates the concave surfaces. The two concave surfaces limit the aspect ratio width / depth of the openings 28. If the opening width is sufficiently larger than the depth of the opening, they are tolerable. The resulting openings can be calculated by adding twice the etch depth to the initial opening.

[0050] Figure 4B is a conceptual cross-sectional view along the line A-A’ in Figure 3conceptual cross-sectional view of the line A-A' in Fig. 3. On the semiconductor slice 34, two strips 26 of the glass structure 24 are shown. Between the two strips 26, a contact pad 44 is shown. The strips 26 show straight vertical surfaces. In the present example, the openings 28 have been etched using the LIDE process described above. A smaller aspect ratio width / depth of the openings 28 can be achieved, i.e. for the same height (equal to the depth of the opening) of the glass structure, compared to the use of a wet etching process as shown in Fig. 2. Figure 4A The openings can achieve a smaller width compared to the wet etching process shown.

[0051] Figure 5 is a conceptual cross-sectional view of a semiconductor device 48 according to one example. The semiconductor device 48 comprises a die obtained by dicing the semiconductor slice 34. The die can comprise one electronic component 22. In the shown example, the electronic component 22 can be a diode. A contact pad 44 can be arranged on top of the electronic component 22 at the bottom of the opening 28 and a metallization structure 42 can be arranged at the backside. The cross-sectional view shows strips 26 of the glass structure 24 at the left and right side of the contact pad 44. From the view of the Figure 3 It can be understood from the view that the glass structure 24 forms a rim completely surrounding the contact pad 44 arranged at the bottom of the opening 28. The semiconductor device 48 further comprises a carrier 50 which can be a lead frame. The carrier 50 comprises a die pad 50a and terminals 50b.

[0052] The metallization structure 42 of the die electrically and mechanically connects the die pad 50a, e.g. by solder or conductive paste. The schematically shown clip 52 has a first part 52a and a second part 52b. The first part 52a can have a length which is larger than the thickness of the glass structure 24. A first end 54 of the first part 52a is electrically connected to the contact pad 44 by means of an adhesive 56 at the bottom of the opening 28. The adhesive can be solder or conductive paste. The second part 52b can be configured to extend to the terminals 50b. The structure of the second part 52b can be related to the carrier used. For example, the carrier can have terminals on another level than the die pad.

[0053] Figure 6Ais a conceptual perspective view of a clip 58 including a rivet according to one example. The clip 58 can include a first portion 58a and a second portion 58b. The first portion 58a can be formed from a rivet that is riveted to the second portion 58b. The clip 58 can be made of copper. The diameter of the rivet 58a can be scalable to conform to a contact pad to be contacted. For example, the contact pad can be a source contact. The diameter of the rivet 58a can be scalable to conform to current through the clip. The second portion 58b can be stamped from a metal sheet. The second portion 58b can have a scalable top surface area related to current through the clip. The second portion 58b can have a scalable top surface area related to on-resistance requirements. On-resistance is the resistance value between the source and the drain of a MOSFET transistor. The second portion 58b can be bent to fit to a carrier terminal. The second portion 58b can include an opening through which the rivet 58a passes.

[0054] Figure 6B is a conceptual cross-sectional view of a clip 58 connected to a pad 44 of an example semiconductor device. The semiconductor device includes a semiconductor component 22 with a glass structure 24 surrounding an opening 28. A rivet 58a passes straight into the opening 28. The rivet 58a is not bent. To secure the rivet 58a, the opening 28 can be partially filled with an adhesive 56. The adhesive 56 can be a conductive paste. The adhesive 56 can be solder. The rivet 58a can extend into the adhesive. When attached to the pad 44, it can not be necessary to bend the clip or apply any force to the clip. The diameter d can be about 500 to 700 μιη. The distance between the surface of the pad 44 and the top surface of the second portion 58b can be about 1.25 mm to 1.3 mm. The clip 58 combines a long vertical dimension for small contacts with a wide clip surface area. By riveting a vertical first portion 58a to a large second portion 58b, the clip can be inserted into a small bond pad opening 28 surrounded by a tall glass structure or tall rim. If the depth / width aspect ratio of the opening 28 is too large, it can not be possible to contact the pad 44 with a bond wire. The clip 58 can easily accommodate current, on-resistance, and package design requirements.

[0055] Figure 7A is a conceptual perspective view of a bent clip 60 according to one example. The clip 60 can include a first portion 60a and a second portion 60b. The first and second portions can be integrally formed from a metal sheet. The metal sheet can be a copper sheet. The length dl and width d2 of the cross-section of the first portion 60a can fit to the surface of a pad to be contacted. The length dl and width d2 can be about 500 to 700 μιη. The cross-section dl x d2 can correspond to the surface pl x p2 of the pad. The cross-section of the first portion 60a can be the same as the cross-section of the second portion 60b. The first portion 60a can combine a long vertical dimension with a small source contact.

[0056] Figure 7B is a conceptual perspective view of a curved clip 62 according to an example. The clip 62 differs from the clip 60 in that the cross section of the first portion 62a can be different from the cross section of the second portion 62b. The second portion 62b can include a portion 62b.1 having the same cross section as the first portion 62a. The portion 62b.1 can be connected to a terminal. The second portion 62b can include a portion 62b.2 that can be larger than the first portion 62a and larger than the portion 62b.1. The portion 62b.2 can be a scalable surface area. The scalable surface area can be achieved, for example, by stamping or etching. The area is not limited to another method.

[0057] Figure 7C is a conceptual cross-sectional view of a clip 60 or clip 62 connected to a pad 44 of an example semiconductor device. The semiconductor device includes a semiconductor component 22 with a glass structure 24 surrounding an opening 28. The first portion 62a (or 60a) passes into the opening 28. To secure the first portion 60a, 62a, the opening 28 can be partially filled with an adhesive 56. The adhesive 56 can be a conductive paste. The adhesive 56 can be solder. The first portion 60a, 62a can extend into the adhesive. When attached to the pad 44, it can not be necessary to bend the clip 60, 62 or apply any force to the clip 60, 62. The clip 60, 62 combines a long vertical dimension for small contact with a wide clip surface area. The clip can be inserted into a small bond pad opening 28 surrounded by a tall glass structure or tall rim. The clip 60, 62 can easily adapt to current, on-resistance, and package design requirements.

[0058] Example

[0059] In the following, a method for processing a semiconductor wafer as well as a semiconductor wafer, a semiconductor device, and a clip are further described using specific examples.

[0060] Example 1 is a method for processing a semiconductor wafer, the method comprising: providing a semiconductor wafer comprising a first major surface and a second major surface opposite the first major surface; creating a defect within the semiconductor wafer, the defect defining a detachment plane parallel to the first major surface; processing the first major surface to define a plurality of electronic semiconductor components; providing a glass structure comprising a plurality of openings; attaching the glass structure to the processed first major surface, each of the plurality of openings leaving a respective region of the plurality of electronic semiconductor components uncovered, respectively; applying a polymer layer to the second major surface; splitting the semiconductor wafer into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer to below its glass transition temperature, the semiconductor slice extending between the first major surface and the detachment surface and comprising the plurality of electronic semiconductor components.

[0061] Example 2 is the method of Example 1, wherein the method further comprises applying an additional polymer layer to the first major surface prior to singulating the semiconductor die from the semiconductor wafer.

[0062] Example 3 is the method of Example 1, wherein the semiconductor die has a thickness of about 100 pm or less, preferably about 50 pm or less.

[0063] Example 4 is the method of Example 1, wherein the glass structure has a thickness that is at least four times the thickness of the semiconductor die.

[0064] Example 5 is the method of Example 1, wherein the plurality of electronic components are separated by a scribe line, the scribe line being covered by the glass structure.

[0065] Example 6 is the method of Example 5, wherein the method further comprises singulating the semiconductor die with the attached glass structure along the scribe line into semiconductor chips.

[0066] Example 7 is the method of Example 1, wherein the method further comprises connecting a clip to a pad, the pad being disposed in a respective area of the first major surface that is not covered by the glass structure.

[0067] Example 8 is the method of Example 7, the clip comprising a first portion having a length that is greater than a thickness of the glass structure connected to the pad; and a second portion configured to extend to a terminal.

[0068] Example 9 is the method of Example 8, the clip comprising at least one of a rivet forming a rivet to the first portion of the second portion and a single piece that is bent to form the first portion and the second portion.

[0069] Example 10 is the method of Example 7, wherein connecting the clip to the pad comprises filling an adhesive into a respective opening of the glass structure.

[0070] Example 11 is the method of Example 1, wherein the method further comprises restarting the method with a remaining semiconductor wafer as the semiconductor wafer.

[0071] Example 12 is a semiconductor wafer comprising: a first major surface and a second major surface opposite the first major surface; a detachment plane within the semiconductor wafer interior parallel to the first major surface, the detachment plane being defined by a defect; a plurality of electronic semiconductor components formed at the first major surface and between the first major surface and the detachment plane; a glass structure attached to the first major surface, the glass structure comprising a plurality of openings, each of the plurality of openings respectively leaving a respective area of the plurality of electronic semiconductor components uncovered.

[0072] Example 13 is a clip for electrically connecting a pad disposed on a bottom of an opening in a glass structure, the clip comprising at least one of a rivet forming a first portion of the clip and a single piece of sheet metal bent to form the first portion and a second portion, the rivet riveted to the second portion of the clip, wherein the second portion is configured to extend to a terminal, the first portion having a width that is about half or more of a width of the opening and configured to extend straight through to the bottom of the opening.

[0073] Example 14 is a semiconductor device comprising: a semiconductor chip having a first major surface and a second major surface opposite the first major surface, the first major surface including a pad and a glass structure, the glass structure including an opening, a rim of the opening surrounding the pad, wherein an aspect ratio between a thickness of the glass structure surrounding the opening and a width of the opening is one to three or more; a carrier, the semiconductor chip mounted on the carrier with the second major surface facing the carrier; an adhesive on a bottom of the opening; a clip electrically connecting the pad, the clip comprising at least one of a rivet forming a first portion of the clip and a single piece bent to form the first portion and a second portion, the rivet riveted to the second portion of the clip, wherein the second portion is configured to extend to a terminal on the carrier and the first portion is configured to extend straight through to the bottom of the opening, the first portion having a width that is about half or more of a width of the opening and electrically connected to the pad by way of the adhesive.

[0074] Example 15 is the semiconductor device of Example 14, wherein the semiconductor chip is a vertical power component.

[0075] While the present disclosure has been illustrated and described in relation to one or more implementations, various changes and / or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions described above as being performed by the means or structural components (assemblies, devices, circuits, systems, etc.) disclosed above, the terminology used is intended to be in the nature of words of description and not of limitation, unless specifically stated otherwise. For example, the term "means" is intended to refer to any structure or combination of structures that performs the function described in the claims, even if the structure is not explicitly described in the specification.

Claims

1. A method for processing a semiconductor wafer, the method comprising: providing a semiconductor wafer comprising a first main surface and a second main surface opposite the first main surface; creating a defect inside the semiconductor wafer, the defect defining a detachment plane parallel to the first main surface; processing the first main surface to define a plurality of electronic semiconductor components; applying a polymer layer; splitting the semiconductor wafer into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer below its glass transition temperature, the semiconductor slice extending between the first main surface and the detachment plane and comprising the plurality of electronic semiconductor components, characterized in that the method further comprises: providing a glass structure comprising a plurality of openings; attaching the glass structure to the processed first main surface prior to splitting the semiconductor wafer, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered, respectively; wherein the polymer layer is applied to the second main surface; wherein the plurality of electronic semiconductor components are separated by a cut line, the cut line being covered by the glass structure; dividing the semiconductor slice with the attached glass structure along the cut line into semiconductor dies; and connecting a clip to a pad, the pad being arranged in a respective area of the first main surface left uncovered by the glass structure, the clip comprising: a first portion having a length greater than a thickness of the glass structure connected to the pad; and a second portion configured to extend to a terminal.

2. The method of claim 1, wherein, The method further comprises applying a further polymer layer to the first main surface prior to splitting the semiconductor slice from the semiconductor wafer.

3. The method according to any of the preceding claims, wherein, The semiconductor slice has a thickness of or less than 100 pm.

4. The method of claim 3, wherein, The semiconductor slice has a thickness of or less than 50 pm.

5. The method of any one of claims 1, 2, 4, wherein, The glass structure has a thickness that is at least four times the thickness of the semiconductor slice.

6. The method of any one of claims 1, 2, 4, wherein, The clip comprises at least one of: a rivet forming the first portion riveted to the second portion; a single piece that is bent to form the first portion and the second portion.

7. The method of any one of claims 1, 2, 4, wherein, Connecting the clip to the pad comprises filling an adhesive into the respective opening of the glass structure.

8. The method of any one of claims 1, 2, 4, wherein, The method further comprises restarting the method with the remaining semiconductor wafer as a semiconductor wafer.

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