Manufacturing method of an IGBT structure with a special-shaped groove isolation grid

Abstract

The present invention provides a special-shaped groove isolated gate IGBT structure and a manufacturing method thereof, relating to the technical field of IGBT structures. An n-type substrate is arranged above the collector. Regularly arranged vertical grooves are provided inside the n-type substrate. There are oxide layers and polycrystalline layers in the grooves. P-type wells are arranged between adjacent grooves. An n+ emitter region and a p+ short-circuit region are arranged in the p-type wells. The n+ emitter region is located at the upper edge of the p-type well, and the p+ short-circuit region is located in the middle of the n+ emitter region. A protective oxide layer and an emitter metal are provided at the top of the groove. A metal layer is arranged in the protective oxide layer to form an emitter and a gate. Compared with the prior art, the beneficial effects of the present invention are as follows: In the IGBT device, the isolated gate adopts an up-and-down structure. Through a unique two-time etching groove process, the internal structure of the produced IGBT device is compact and seamless, which can reduce the Miller capacitance of the IGBT device, improve the switching speed of the IGBT, and effectively reduce the switching loss.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT structures, and in particular to a special-shaped groove separated gate IGBT structure and a manufacturing method thereof. Background Art

[0002] As a new type of power semiconductor field-controlled self-shutoff device, the insulated gate transistor (IGBT) combines the high-speed performance of power MOSFET with the low resistance of bipolar devices. It has the characteristics of high input impedance, low power consumption of voltage control, simple control circuit, high voltage resistance, and large current bearing, and is widely used in various power conversions. As the application power continues to increase, the IGBT switching loss also increases. The special-shaped slot split-gate IGBT significantly reduces the IGBT switching loss through the unique split-gate design. Summary of the invention

[0003] The present invention provides a special-shaped groove separated gate IGBT structure, which forms an upper and lower structure separated gate through a unique two-time groove etching process, reduces the Miller capacitance of the IGBT device, and effectively reduces the switching loss.

[0004] The specific technical scheme is a special-shaped groove separated gate IGBT structure, including a collector, an n-type substrate is arranged above the collector, and vertical grooves arranged regularly are arranged inside the n-type substrate, and the vertical grooves include connected upper grooves and lower grooves, and the lower groove is located below the upper groove, and there is a lower groove emitter thick gate oxide layer on the inner side wall and bottom wall of the lower groove, and there is a lower groove emitter polycrystalline layer inside the lower groove emitter thick gate oxide layer, and there is an isolation oxide layer on the top of the lower groove emitter polycrystalline layer. layer, an upper trench gate oxide layer is arranged on the inner side wall of the upper trench, an upper trench gate polycrystalline layer is arranged inside the upper trench gate oxide layer and above the isolation oxide layer, a p-type well is arranged between adjacent trenches, an n+ emitter region and a p+ type short-circuit region are built in the p-type well, the n+ emitter region is located at the upper edge of the p-type well, the p+ type short-circuit region is located in the middle of the n+ emitter region, a protective oxide layer and an emitter metal are arranged on the top of the trench, and a metal layer is arranged in the protective oxide layer to form an emitter and a gate.

[0005] Furthermore, the groove is bottle-shaped, the width of the lower groove is greater than the width of the upper groove, and the height of the lower groove is lower than the height of the upper groove.

[0006] Furthermore, the height of the p-type well is lower than the height of the upper trench.

[0007] Furthermore, the collector includes: a collector metal and a p+ collector, and the p+ collector is located between the collector metal and the n-type substrate.

[0008] The method for manufacturing the special-shaped trench split-gate IGBT structure described in the present application comprises the following steps:

[0009] S1, depositing a 7000A dense oxide layer on the surface of the n-type substrate as a hard mask,

[0010] S2, first photolithography, photolithography a first trench etching window on the top of the hard mask through photolithography and etching process,

[0011] S3, first trench etching, high temperature sacrificial oxidation, sacrificial oxidation removal, etching downward from the top of the n-type substrate to form the upper trench, and growing the upper trench gate oxide layer on the inner wall of the upper trench,

[0012] S4, depositing the silicon nitride barrier layer on the inner surface of the upper trench gate oxide layer formed in step S3,

[0013] S5, a second trench etching, etching downward from the bottom of the silicon nitride barrier layer in step S4 to form the lower trench,

[0014] S6, high temperature sacrificial oxidation, sacrificial oxidation removal, growing the lower trench emitter thick gate oxide layer on the inner wall of the lower trench,

[0015] S7, removing the silicon nitride barrier layer formed in step S4 in the upper trench, depositing the lower trench emitter polycrystalline layer in the lower trench emitter thick gate oxide layer and etching back the lower trench emitter polycrystalline layer, depositing the isolation oxide layer on top of the lower trench emitter polycrystalline layer and etching back the isolation oxide layer,

[0016] S8, depositing the upper trench gate polycrystalline layer inside the upper trench gate oxide layer and above the isolation oxide layer, and etching back the upper trench gate polycrystalline layer,

[0017] S9, third photolithography, first photolithography a p-type well injection window between adjacent grooves, perform BODY injection, and anneal to form the p-type well,

[0018] S10, fourth photolithography, photolithography to form an n+ type emitter injection window at the upper edge of the p-type well, perform n+ ion implantation to form the n+ emitter region, and chemically vapor deposit an oxide layer,

[0019] S11, fifth photolithography, etching an emitter contact hole in the middle of the n+ emitter region, performing p+ ion implantation, annealing at 875° C. in a nitrogen atmosphere for 30 minutes to form the p+ type short circuit region,

[0020] S12, setting a contact window, setting the emitter metal and the protective oxide layer on the top of the completed part of the structure respectively, and setting a metal layer in the protective oxide layer to form an emitter and a gate respectively, then removing the back side of the n-type substrate, performing p+ back side injection by ion implantation, annealing at 400°C, and setting a metal material layer to form a collector.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: the separation gate in the IGBT device adopts an upper and lower structure with an exquisite design. Through a unique double-etching groove process, the internal structure of the IGBT device produced is compact and seamless, which can reduce the Miller capacitance of the IGBT device, increase the IGBT switching speed, effectively reduce the switching loss, and be safe and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 A schematic diagram of a structure corresponding to the implementation of step S1 disclosed in an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a structure corresponding to the implementation of step S2 disclosed in an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of a structure corresponding to the implementation of step S3 disclosed in an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a structure corresponding to the implementation of step S4 disclosed in an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of a structure corresponding to the implementation of step S5 disclosed in an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of a structure corresponding to the implementation of step S6 disclosed in an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of a structure corresponding to the implementation of step S7 disclosed in an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of a structure corresponding to the implementation of step S8 disclosed in an embodiment of the present invention;

[0031] Fig. 9 A schematic diagram of a structure corresponding to the implementation of step S9 disclosed in an embodiment of the present invention;

[0032] Fig.10A schematic diagram of a structure corresponding to the implementation of step S10 disclosed in an embodiment of the present invention;

[0033] Fig.11 A schematic diagram of a structure corresponding to the implementation of step S11 disclosed in an embodiment of the present invention;

[0034] Fig.12 This is a schematic diagram of a corresponding structure after the step S12 disclosed in the embodiment of the present invention is implemented.

[0035] Among them: 1. Collector metal, 2. p+ collector, 3. n-type substrate, 4. hard mask, 5. upper trench gate oxide layer, 6. silicon nitride barrier layer, 7. trench bottom, 8. lower trench emitter thick gate oxide layer, 9. lower trench emitter polycrystalline layer, 10. isolation oxide layer, 11. upper trench gate polycrystalline layer, 12. p-type well, 13. n+ emitter region, 14. p+ short circuit region, 15. protective oxide layer, 16. emitter metal, 17. first trench etching window. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0037] In the description of the present invention, it should be noted that the terms "inside", "outside", "left" and "right" indicate directions or positional relationships based on the positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention.

[0038] The following is combined with Figure 1-12 Description of the present invention:

[0039] Embodiment: A special-shaped groove separated gate IGBT structure, including a collector, an n-type substrate 3 is arranged above the collector, and a vertical groove arranged regularly is arranged inside the n-type substrate 3, and the vertical groove includes an upper groove and a lower groove connected, and the lower groove is located below the upper groove, and a lower groove emitter thick gate oxide layer 8 is provided on the inner side wall and bottom wall of the lower groove, and a lower groove emitter polycrystalline layer 9 is provided inside the lower groove emitter thick gate oxide layer 8, and an isolation oxide layer 10 is provided on the top of the lower groove emitter polycrystalline layer 9, and an isolation oxide layer 10 is provided on the inner side wall of the upper groove. An upper trench gate oxide layer 5 is provided on the upper trench gate, an upper trench gate polycrystalline layer 11 is provided inside the upper trench gate oxide layer 5 and above the isolation oxide layer 10, a p-type well 12 is provided between adjacent trenches, the p-type well 12 has an n+ emitter region 13 and a p+ short-circuit region 14 built therein, the n+ emitter region 13 is located at the upper edge of the p-type well 12, the p+ short-circuit region 14 is located in the middle of the n+ emitter region 13, a protective oxide layer 15 and an emitter metal 16 are provided on the top of the trench, a metal layer is provided in the protective oxide layer 15 to form an emitter and a gate.

[0040] Furthermore, the groove is bottle-shaped, the width of the lower groove is greater than the width of the upper groove, and the height of the lower groove is lower than the height of the upper groove.

[0041] Furthermore, the height of the p-type well 12 is lower than the height of the upper trench.

[0042] Furthermore, the collector includes: a collector metal 1 and a p+ collector 2 , and the p+ collector 2 is located between the collector metal 1 and the n-type substrate 3 .

[0043] The method for manufacturing the special-shaped trench split-gate IGBT structure described in the present application comprises the following steps:

[0044] S1, depositing a 7000A dense oxide layer on the surface of the n-type substrate 3 as a hard mask 4,

[0045] S2, first photolithography, photolithography a first trench etching window 17 on the top of the hard mask 4 through photolithography and etching process,

[0046] S3, the first trench etching is 3.5um, high temperature sacrificial oxidation, sacrificial oxidation removal, etching from the top of the n-type substrate 3 downward to form an upper trench, at this time the bottom of the upper trench is the trench bottom 7, the upper trench gate oxide layer 5 is grown on the inner wall of the upper trench,

[0047] S4, depositing the silicon nitride barrier layer 6 on the inner surface of the upper trench gate oxide layer 5 formed in step S3,

[0048] S5, second trench etching 2.5um, etching downward from the bottom of the silicon nitride barrier layer 6 in step S4 to form a lower trench, at which the bottom of the lower trench is the trench bottom 7, and the position of the trench bottom 7 has changed compared to step S3.

[0049] S6, high temperature sacrificial oxidation, sacrificial oxidation removal, growing the lower trench emitter thick gate oxide layer 8 on the inner wall of the lower trench, relative to step S5, the position of the trench bottom 7 has changed, the bottom of the lower trench emitter thick gate oxide layer 8 is the trench bottom 7,

[0050] S7, removing the silicon nitride barrier layer 6 formed in step S4 in the upper trench, depositing the lower trench emitter polycrystalline layer 9 in the lower trench emitter thick gate oxide layer 8 and etching back the lower trench emitter polycrystalline layer 9, depositing the isolation oxide layer 10 on the top of the lower trench emitter polycrystalline layer 9 and etching back the isolation oxide layer 10,

[0051] S8, depositing the upper trench gate polycrystalline layer 11 inside the upper trench gate oxide layer 5 and above the isolation oxide layer 10, and etching back the upper trench gate polycrystalline layer 11,

[0052] S9, third photolithography, first photolithography a p-type well injection window between adjacent grooves, perform BODY injection, and anneal to form the p-type well 12,

[0053] S10, fourth photolithography, photolithography to form an n+ type emitter injection window at the upper edge of the p-type well 12, perform n+ ion implantation to form the n+ emitter region 13, and chemically vapor deposit an oxide layer,

[0054] S11, fifth photolithography, etching an emitter contact hole in the middle of the n+ emitter region 13, performing p+ ion implantation, annealing at 875° C. in a nitrogen atmosphere for 30 minutes to form the p+ type short circuit region 14,

[0055] S12, setting a contact window, setting the emitter metal 16 and the protective oxide layer 15 on the top of the completed part of the structure, and setting a metal layer in the protective oxide layer 15 to form an emitter and a gate respectively, then removing the back side of the n-type substrate 3, performing p+ back side implantation by ion implantation, annealing at 400°C, and setting a metal material layer to form a collector.

[0056] The method used in the present application etches the groove twice and gradually forms it. For example, the lower trench emitter polycrystalline layer 9 is first deposited in the lower trench emitter thick gate oxide layer 8, and then the lower trench emitter polycrystalline layer 9 is etched back. The formed lower trench emitter polycrystalline layer 9 is well bonded with the lower trench emitter thick gate oxide layer 8, and the lower trench emitter polycrystalline layer 9 itself is uniform and dense. Using the above process, the internal structure of the IGBT device produced is compact and seamless, which can reduce the Miller capacitance of the IGBT device, improve the IGBT switching speed, effectively reduce the switching loss, and is safe and reliable.

[0057] The above is only the preferred embodiment of the present invention, and does not limit the present invention in other forms. Any technician familiar with the profession may use the above disclosed technical content to change or modify it into an equivalent embodiment with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the technical solution of the present invention still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a special-shaped groove separated gate IGBT structure, the special-shaped groove separated gate IGBT structure comprising a collector, an n-type substrate (3) is arranged above the collector, and vertical grooves arranged regularly are arranged inside the n-type substrate (3), the vertical grooves comprising an upper groove and a lower groove connected to each other, the lower groove is located below the upper groove, a lower groove emitter thick gate oxide layer (8) is provided on the inner side wall and bottom wall of the lower groove, a lower groove emitter polycrystalline layer (9) is provided inside the lower groove emitter thick gate oxide layer (8), an isolation oxide layer (10) is provided on the top of the lower groove emitter polycrystalline layer (9), and an isolation oxide layer (10) is provided on the inner side wall of the upper groove. An upper trench gate oxide layer (5) is provided on the upper trench gate oxide layer (5), an upper trench gate polycrystalline layer (11) is provided inside the upper trench gate oxide layer (5) and above the isolation oxide layer (10), a p-type well (12) is provided between adjacent trenches, an n+ emitter region (13) and a p+ short-circuit region (14) are built into the p-type well (12), the n+ emitter region (13) is located at the upper edge of the p-type well (12), the p+ short-circuit region (14) is located in the middle of the n+ emitter region (13), a protective oxide layer (15) and an emitter metal (16) are provided on the top of the trench, and a metal layer is provided in the protective oxide layer (15) to form an emitter and a gate; The groove is bottle-shaped, the width of the lower groove is greater than the width of the upper groove, and the height of the lower groove is lower than the height of the upper groove; The height of the p-type well (12) is lower than the height of the upper trench; The collector comprises: a collector metal (1) and a p+ collector (2), wherein the p+ collector (2) is located between the collector metal (1) and the n-type substrate (3); It is characterized by comprising the following steps: S1, depositing a 7000A dense oxide layer on the surface of the n-type substrate (3) as a hard mask (4), S2, first photolithography, photolithography a first trench etching window (17) on the top of the hard mask (4) through photolithography and etching processes, S3, first trench etching, high temperature sacrificial oxidation, sacrificial oxidation removal, etching downward from the top of the n-type substrate (3) to form the upper trench, and growing the upper trench gate oxide layer (5) on the inner wall of the upper trench, S4, depositing a silicon nitride barrier layer (6) on the inner surface of the upper trench gate oxide layer (5) formed in step S3, S5, a second trench etching, etching downward from the bottom of the silicon nitride barrier layer (6) in step S4 to form the lower trench, S6, high temperature sacrificial oxidation, sacrificial oxidation removal, growing the lower trench emitter thick gate oxide layer (8) on the inner wall of the lower trench, S7, removing the silicon nitride barrier layer (6) formed in step S4 in the upper trench, depositing the lower trench emitter polycrystalline layer (9) in the lower trench emitter thick gate oxide layer (8) and etching back the lower trench emitter polycrystalline layer (9), depositing the isolation oxide layer (10) on the top of the lower trench emitter polycrystalline layer (9) and etching back the isolation oxide layer (10), S8, depositing the upper trench gate polycrystalline layer (11) inside the upper trench gate oxide layer (5) and above the isolation oxide layer (10), and etching back the upper trench gate polycrystalline layer (11), S9, third photolithography, first photolithography a p-type well injection window between adjacent grooves, perform BODY injection, and anneal to form the p-type well (12), S10, fourth photolithography, photolithography to form an n+ type emitter injection window at the upper edge of the p-type well (12), perform n+ ion implantation to form the n+ emitter region (13), and chemically vapor deposit an oxide layer, S11, a fifth photolithography, etching an emitter contact hole in the middle of the n+ emitter region (13), performing p+ ion implantation, and annealing at 875° C. in a nitrogen atmosphere for 30 minutes to form the p+ type short circuit region (14), S12, setting a contact window, setting the emitter metal (16) and the protective oxide layer (15) on the top of the completed structure, and setting a metal layer in the protective oxide layer (15) to form an emitter and a gate respectively, then removing the back side of the n-type substrate (3), performing p+ back side implantation by ion implantation, annealing at 400° C., and setting a metal material layer to form a collector.

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