Photodetector with adjacent anode-cathode pairs

Abstract

The present invention relates to a photodetector having an adjacent anode-cathode pair, and discloses a structure for a photodetector and a method for manufacturing the structure for a photodetector. The structure comprises a light absorbing region having a side, an anode adjacent to the side of the light absorbing region, and a cathode adjacent to the side of the light absorbing region.

Description

Technical Field

[0001] The present invention relates to a photonics chip, and more particularly, to a structure for a photodetector and a method for manufacturing the structure for a photodetector. Background Art

[0002] Photonic chips are used in many applications and systems, such as data communication systems and data computing systems. Photonic chips integrate optical components (such as waveguides and optical switches) and electronic components (such as field effect transistors) into a unified platform. Among other factors, layout area, cost, and operating overhead can be reduced through the integration of the two types of components.

[0003] Photonic chips include detectors that convert modulated light into electrical signals. Common detectors are photodetectors made of materials such as germanium, which are characterized by high absorption in the infrared wavelength range. When photons of electromagnetic radiation are absorbed by germanium, the germanium photodetector converts the modulated light pulses into an electric current.

[0004] There is a need for improved structures for photodetectors and methods of making structures for photodetectors. Summary of the invention

[0005] In one embodiment of the present invention, a structure for a photodetector is provided, which includes a light absorbing region having a side, an anode adjacent to the side of the light absorbing region, and a cathode adjacent to the side of the light absorbing region.

[0006] In one embodiment of the present invention, a method for forming a structure for a photodetector is provided, wherein the method includes forming a light absorbing region, forming an anode adjacent to the side of the light absorbing region, and forming a cathode adjacent to the side of the light absorbing region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals refer to like features in the various views.

[0008] Figure 1 FIG. 1 is a top view of a structure in an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0009] Figure 2 for Figure 1 Cross-sectional view along line 2-2.

[0010] Figure 3 For Figure 1A top view of the structure at a manufacturing stage following a processing method.

[0011] Figure 4 For along Figure 3 A cross-sectional view shown on line 4-4.

[0012] Figure 5 For Figure 3 A top view of the structure at a manufacturing stage following a processing method.

[0013] Figure 6 For along Figure 5 A cross-sectional view shown on line 6-6.

[0014] Figure 7 For Figure 5 A top view of the structure at a manufacturing stage following a processing method.

[0015] Figure 8 For along Figure 7 A cross-sectional view shown on line 8-8.

[0016] Fig. 8A For along Figure 7 A cross-sectional view shown along line 8A-8A.

[0017] Fig. 9 For Figure 7 A top view of the structure at a manufacturing stage following a processing method.

[0018] Fig.10 For along Fig. 9 A cross-sectional view shown along line 10-10.

[0019] Fig. 10A For along Fig. 9 A cross-sectional view shown along line 10A-10A.

[0020] Fig.11 For Fig. 9 A top view of the structure at a manufacturing stage following a processing method.

[0021] Fig.12 and Fig.13 is a top view of a structure according to an alternative embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 10 substrate

[0024] 11 Top

[0025] 12 Equipment Layer

[0026] 14. Buried insulation layer

[0027] 16 Wafer Processing

[0028] 17,17a,17b Shallow trench isolation area

[0029] 18,18a,18b Shallow trench isolation area

[0030] 20 Dielectric layer

[0031] 21 Opening

[0032] 22 Groove

[0033] 24th floor

[0034] 25 Side

[0035] 26, 26a Doped region

[0036] 27 Side

[0037] 28, 28a Doping region

[0038] 30 Implantation Mask

[0039] 32, 32a Doping region

[0040] 34, 34a Doping region

[0041] 35 Opening

[0042] 36 Implantation Mask

[0043] 37 Opening

[0044] 38 Waveguide

[0045] 40 Contacts

[0046] 42 contacts. DETAILED DESCRIPTION

[0047] refer to Figure 1 , Figure 2 According to an embodiment of the present invention, a substrate 10 in a representative form of a semiconductor-on-insulator (SOI) substrate includes a device layer 12 defining a semiconductor layer, a buried insulating layer 14, and a handle wafer 16. The device layer 12 is separated from the handle wafer 16 by the intermediate buried insulating layer 14 and can be much thinner than the handle wafer 16. The device layer 12 and the handle wafer 16 can be composed of a single crystal semiconductor material (e.g., single crystal silicon) and can be lightly doped to have, for example, p-type conductivity. The buried insulating layer 14 can be composed of a dielectric material such as silicon dioxide. The device layer 12 is electrically isolated from the handle wafer 16 by the buried insulating layer 14.

[0048] The shallow trench isolation regions 17 , 18 may be formed by etching trenches in the device layer 12 , depositing a dielectric material (eg, silicon dioxide) in the trenches, and planarizing using chemical mechanical polishing. The shallow trench isolation regions 17 , 18 may pass completely through the device layer 12 to the buried insulating layer 14 .

[0049] refer to Figure 3 , Figure 4 , where the same reference numerals denote Figure 1 , Figure 2 . In a subsequent manufacturing stage, a dielectric layer 20 is deposited on the top surface 11 of the substrate 10 and patterned by photolithography and etching processes to define a window or opening 21. The dielectric layer 20 may be composed of a dielectric material such as silicon nitride. The opening 21 that completely penetrates the dielectric layer 20 to the device layer 12 exposes an area on the top surface 11 of the device layer 12. The opening 21 in the dielectric layer 20 may be laterally located between the shallow trench isolation region 17 and the shallow trench isolation region 18.

[0050] A trench 22 is formed partially through the device layer 12 in the device layer 12. The trench 22 may be formed by an etching process, such as a reactive ion etching process. The patterned dielectric layer 20 acts as an etching mask during the etching process, and the opening 21 in the patterned dielectric layer 20 defines the location of the trench 22 in the device layer 12. The surface of the device layer 12 borders the trench 22.

[0051] refer to Figure 5 , Figure 6 , where the same reference numerals denote Figure 3 , Figure 4 . In a subsequent manufacturing stage, a layer 24 containing a light absorbing material is deposited within the trench 22 and defines a light absorbing region of the photodetector. In one embodiment, the layer 24 may have a composition including germanium. In one embodiment, the layer 24 may consist of elemental germanium. In one embodiment, the trench 22 and the layer 24 within the trench 22 may extend from the shallow trench isolation region 17 to the shallow trench isolation region 18. The layer 24 includes opposing sides 25, 27 that define the width of the light absorbing region and ends connecting the sides 25, 27. The shallow trench isolation region 17 terminates at the side 25 of the layer 24, and the shallow trench isolation region 18 terminates at the side 27 of the layer 24.

[0052] In one embodiment, layer 24 may be selectively deposited so that material is not deposited on the dielectric material of dielectric layer 20. In one embodiment, the surface of device layer 12 bordering trench 22 may be subjected to a surface treatment process and then subjected to chemical vapor deposition of germanium, with germanium growing only at locations where the semiconductor surface of device layer 12 is exposed, resulting in selective deposition and minimization of threading dislocation density.

[0053] refer to Figure 7 , Figure 8 , Fig. 8A , where the same reference numerals denote Figure 5 , Figure 6 . In subsequent manufacturing stages, doped regions 26 and doped regions 28 are formed in respective portions of device layer 12. In one embodiment, doped regions 26, 28 may extend through the entire thickness of device layer 12 to buried insulating layer 14. Specifically, doped regions 26, 28 may extend from a top surface of device layer 12 completely through device layer 12 to an interface between device layer 12 and buried insulating layer 14. Layer 24 may be laterally disposed at sides 25, 27 between doped regions 26 and doped regions 28. Shallow trench isolation regions 17, 18 define respective boundaries for doped regions 26, 28 along directions parallel to sides 25, 27 of layer 24.

[0054] The doped regions 26, 28 may be formed, for example, by ion implantation, with an implantation mask 30 covering the region on the device layer 12 to define the implantation region of the device layer 12 for the doped regions 26, 28. The implantation mask 30 may include a layer of photosensitive material (e.g., photoresist) formed by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define openings 35. The openings 35 in the implantation mask 30 are disposed above the region of the device layer 12 to be implanted, and each opening 35 in the implantation mask 30 may overlap with the shallow trench isolation region 17, 18 on one side. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical characteristics and physical properties of the doped regions 26, 28. The implantation mask 30 may be stripped after the doped regions 26, 28 are formed.

[0055] In one embodiment, portions of layer 24 may be implanted so that portions of doped regions 26, 28 are located in layer 24, such as Figure 8 , Fig. 8A27. The simultaneous implantation of layer 24 may be provided by slightly overlapping each opening 35 in implant mask 30 with layer 24 at its inner edge so that opening 35 extends inwardly beyond sides 25, 27 of layer 24. In one embodiment, the semiconductor material of doped regions 26, 28 may be doped with a p-type dopant (e.g., boron) that provides p-type conductivity. In one embodiment, doped regions 26, 28 may be moderately doped to contain a p-type conductivity of about 1x10 17 atoms / cm 3 To about 5x10 18 atoms / cm 3 The doping concentration is within the range of .

[0056] refer to Fig. 9 , Fig.10 , Fig. 10A , where the same reference numerals denote Figure 7 , Figure 8 , Fig. 8A 1 . In a subsequent manufacturing stage, doped regions 32 and doped regions 34 are formed in respective portions of device layer 12 that are not aligned with the portion of device layer 12 containing doped regions 26, 28. In an embodiment, doped regions 32, 34 may extend through the entire thickness of device layer 12 to buried insulating layer 14. Specifically, doped regions 32, 34 may extend from a top surface of device layer 12 completely through device layer 12 to an interface between device layer 12 and buried insulating layer 14. Shallow trench isolation regions 17, 18 define respective boundaries of doped regions 32, 34 in a direction parallel to sides 25, 27 of layer 24.

[0057] The doped regions 32, 34 may be formed, for example, by ion implantation, with an implantation mask 36 covering the area above the device layer 12 to define the implantation area of ​​the device layer 12 for the doped regions 32, 34. The implantation mask 36 may include a layer of photosensitive material, such as a photoresist, performed by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define openings 37. The openings 37 in the implantation mask 36 are disposed on the area of ​​the device layer 12 to be implanted, and each opening 37 in the implantation mask 36 may overlap with the shallow trench isolation region 17, 18 on one side. The implantation mask 36 covers a portion of the device layer 12 containing the doped regions 26, 28. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical characteristics and physical properties of the doped regions 32, 34. After the doped regions 32, 34 are formed, the implantation mask 36 may be stripped.

[0058] In one embodiment, implantation may be performed in various portions of layer 24 so that portions of doped regions 32, 34 may be located in layer 24, such as Fig.10 , Fig. 10A 24. The simultaneous implantation of layer 24 may be provided by slightly overlapping each opening 37 in implant mask 36 at the inner edge with layer 24 so that the openings 37 extend inwardly beyond the sides 25, 27 of layer 24. Doped regions 32, 34 are doped to have a conductivity type opposite to that of doped regions 26, 28. In one embodiment, the semiconductor material of doped regions 32, 34 may be doped with an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. In one embodiment, the doped regions 32, 34 may be moderately doped to contain an amount of about 1x10 17 atoms / cm 3 To about 5x10 18 atoms / cm 3 The doping concentration is within the range of .

[0059] Doped region 26 is located along side 25 of layer 24 on a side of shallow trench isolation region 17 opposite doped region 32. Doped region 28 is located along side 27 of layer 24 on a side of shallow trench isolation region 18 opposite doped region 34. Layer 24 may be positioned laterally between doped regions 26, 32 and doped regions 28, 34. Side 25 of layer 24 is adjacent to doped regions 26, 32 and shallow trench isolation region 17, and side 27 of layer 24 is adjacent to doped regions 26, 32 and shallow trench isolation region 18.

[0060] refer to Fig.11 , where the same reference numerals denote Fig. 9 , Fig.10 and Fig. 10A , and in a subsequent manufacturing stage, forms a waveguide 38 coupled to layer 24. Waveguide 38 guides light to layer 24 for conversion into an electrical signal. Waveguide 38 may be formed by patterning device layer 12 using photolithography and etching processes.

[0061] The middle-of-line (MOL) and back-end-of-line (BEOL) processes are then performed, which include the formation of silicide, contacts, vias, and wiring for interconnect structures coupled to the photodetectors. In particular, contacts 40 to doped regions 26, 28 and contacts 42 to doped regions 32, 34 are schematically shown in dashed lines. Heavily doped regions (not shown) may be provided in doped regions 26, 28 and doped regions 32, 34, and may reduce contact resistance. Layer 24 does not contact the contacts of the interconnect structures.

[0062] The completed photodetector includes doped regions 26, 28 as cathodes, doped regions 32, 34 as anodes, and layer 24 as a light absorbing region. Shallow trench isolation region 17 is laterally located between the cathode represented by doped region 26 and the anode represented by doped region 32. Shallow trench isolation region 18 is laterally located between the cathode represented by doped region 28 and the anode represented by doped region 34. Layer 24 is laterally located between doped regions 26, 32 representing an anode-cathode pair and doped regions 28, 34 also representing an anode-cathode pair.

[0063] In use, laser light is guided by waveguide 38 to layer 24 where it absorbs photons. The biased anode provides a proliferation region of high electric field. The junction extends to layer 24 near shallow trench isolation regions 17, 18 and an avalanche effect occurs at these locations, characterized by high electric fields.

[0064] Providing an anode-cathode pair along opposite sides of the light absorption region can reduce the operating voltage of the photodetector, increase the gain of the photodetector, reduce the capacitance of the photodetector, and increase the bandwidth of the photodetector. The breakdown voltage of the photodetector can be reduced by not placing contacts on the light absorption region. The structure of the photodetector is easy to integrate with low voltage CMOS technology. The structure of the photodetector can exhibit high avalanche gain at low operating voltages. The additional electric field near the shallow trench isolation regions 17, 18 can accelerate charge carriers, thereby widening the light absorption region without reducing the carrier transit time, which can improve quantum efficiency and can improve responsivity.

[0065] refer to Fig.12 , where similar numbers represent Fig.11 , and according to an alternative embodiment, the photodetector can be modified to increase the number of anode-cathode pairs by adding additional doped regions 26a, 28a and additional doped regions 32a, 34a. Additional shallow trench isolation regions 17a, 17b and 18a, 18b are also located in the device layer 12 to provide electrical isolation of additional anodes and cathodes of the photodetector. In a representative embodiment, the doped regions 26, 26a, 32, 32a have uniform spacing, and the doped regions 28, 28a, 34, 34a also have uniform spacing. In an alternative embodiment, the doped regions 26, 26a, 32, 32a have non-uniform spacing, and the doped regions 28, 28a, 34, 34a also have non-uniform spacing, so that the anode and cathode can have shapes of different sizes. The shallow trench isolation regions 17 , 17 a , 17 b terminate at the side 25 of the layer 24 , and the shallow trench isolation regions 18 , 18 a , 18 b terminate at the side 27 of the layer 24 .

[0066] refer to Fig.13 , where similar numbers represent Fig.11 , and according to an alternative embodiment, the photodetector may be modified to add a region 44 positioned laterally between the cathode and layer 24 defined by doped regions 26, 28. Region 44 may be composed of semiconductor material of lightly doped device layer 12 having a conductivity type (e.g., p-type conductivity) opposite to that of doped regions 26, 28. Region 44 may be used to further increase the gain of the photodetector. In an alternative embodiment, Fig.12 The photodetector may have regions similar to region 44 , with each of these regions being located between a cathode and layer 24 .

[0067] The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), bare chip form, or packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0068] Terms modified by approximate language, such as "about," "approximately," and "substantially," as used herein, are not limited to the exact value specified. Approximate language may correspond to the precision of the instrument used to measure the value and may represent + / -10% of the stated value unless the precision of the instrument specifies otherwise.

[0069] The terms "vertical", "horizontal", etc. mentioned herein are used to establish a reference frame by way of example and not limitation. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to a direction perpendicular to the horizontal, as previously defined. The term "lateral" refers to a direction within the horizontal plane.

[0070] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there are at least one intervening feature. A feature that is "on" or "contacting" another feature may be directly on or directly contacting the other feature, or one or more intervening features may be present. A feature may be "directly on" or "directly contacting" another feature if there are no intervening features. A feature may be "indirectly on" or "indirectly contacting" another feature if there are at least one intervening feature.

[0071] The description of various embodiments of the present invention is presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is intended to best explain the principles of the embodiments, the practical application or technical improvement of technologies found on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photodetector, characterized in that: The structure includes: a light absorbing region including a first side edge; a semiconductor layer comprising a first doped region and a second doped region, the first doped region defining a first anode adjacent to the first side of the light absorbing region, and the second doped region defining a first cathode adjacent to the first side of the light absorbing region; a dielectric layer disposed below the semiconductor layer; and a first shallow trench isolation region, which is laterally located in the semiconductor layer between the first doped region and the second doped region, and the first shallow trench isolation region passes through the semiconductor layer to the dielectric layer, The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.

2. The structure according to claim 1, wherein: The first shallow trench isolation region terminates at the first side.

3. The structure according to claim 1, wherein: The semiconductor layer includes a trench, the light absorption region is a layer located in the trench, and the layer includes germanium.

4. The structure according to claim 1, wherein: The light absorbing region is a layer composed of the element germanium.

5. The structure according to claim 1, wherein: The light absorption region includes a second side opposite to the first side, and the semiconductor layer includes a third doped region and a fourth doped region, the third doped region defines a second anode adjacent to the second side of the light absorption region, and the fourth doped region defines a second cathode adjacent to the second side of the light absorption region, the third doped region has the first conductivity type, and the fourth doped region has the second conductivity type.

6. The structure according to claim 5, further comprising: A second shallow trench isolation region is laterally located in the semiconductor layer between the third doped region and the fourth doped region, The first shallow trench isolation region terminates at the first side, and the second shallow trench isolation region terminates at the second side.

7. The structure according to claim 6, wherein: The second shallow trench isolation region passes through the semiconductor layer and reaches the dielectric layer.

8. The structure according to claim 1, wherein: The semiconductor layer includes a fifth doping region and a sixth doping region, the fifth doping region defines a third anode adjacent to the first side, and the sixth doping region defines a third cathode adjacent to the first side.

9. The structure according to claim 8, further comprising: A third shallow trench isolation region, located between the first doped region and the sixth doped region; as well as a fourth shallow trench isolation region, which is located between the second doped region and the fifth doped region, The first shallow trench isolation region, the third shallow trench isolation region, and the fourth shallow trench isolation region terminate at the first side.

10. A structure for a photodetector, characterized in that: The structure includes: a light absorbing region including side edges; A semiconductor layer, comprising a first doped region, a second doped region and a third doped region in the semiconductor layer, the third doped region being laterally located between the second doped region and the side of the light absorbing region, the first doped region defining an anode adjacent to the side of the light absorbing region, and the second doped region defining a cathode adjacent to the side of the light absorbing region, The first doped region has a first conductivity type, the second doped region has a second conductivity type opposite to the first conductivity type, and the third doped region has the first conductivity type.

11. The structure according to claim 10, wherein: The semiconductor layer includes a trench, the light absorption region is a layer located in the trench, and the layer includes germanium.

12. The structure according to claim 10, wherein: The light absorbing region is a layer composed of the element germanium.

13. A method of forming a structure for a photodetector, characterized in that The method includes: forming a light absorbing region; Forming a first doped region in the semiconductor layer, wherein the first doped region has a first conductivity type, the first doped region defines a first anode adjacent to a first side of the light absorbing region, and a dielectric layer is located below the semiconductor layer; forming a second doped region in the semiconductor layer, wherein the second doped region has a second conductivity type opposite to the first conductivity type, and the second doped region defines a first cathode adjacent to the first side of the light absorbing region; and A shallow trench isolation region is formed, which is laterally located in the semiconductor layer between the first doped region and the second doped region, wherein the shallow trench isolation region passes through the semiconductor layer to the dielectric layer.

14. The method according to claim 13, wherein: The light absorbing region includes a second side opposite to the first side, and the method further includes: forming a third doped region in the semiconductor layer, wherein the third doped region has the first conductivity type and defines a second anode adjacent to the second side of the light absorbing region; and A fourth doped region is formed in the semiconductor layer, wherein the fourth doped region has the second conductivity type and defines a second cathode adjacent to the second side of the light absorbing region.

15. The method according to claim 13, wherein: The first doped region is formed by a first ion implantation process, and the second doped region is formed by a second ion implantation process.

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