Memory device, integrated circuit, data processing device, and manufacturing method thereof

Abstract

The present invention discloses a memory device, an integrated circuit, a data processing device and a manufacturing method thereof. The memory device has a phase change material in which a specific silicon oxide (SiO x ) is doped into a particularly germanium-rich Ge x Sb y Te z material. An integrated circuit using this phase change material as a memory element in a memory array can exhibit good setting speed and good 10-year data retention characteristics through the bonding standard described in the present invention. The storage cell described in the present invention includes a first electrode and a second electrode; and a memory element electrically connected in series between the first electrode and the second electrode. This memory element includes a Ge x Sb y Te z phase change material and a silicon oxide additive, including a combination of multiple elements having germanium (Ge) in the range of 28 to 36 at%, antimony (Sb) in the range of 10 to 20 at%, tellurium (Te) in the range of 25 to 40 at%, silicon (Si) in the range of 5 to 10 at%, and oxygen (O) in the range of 12 to 23 at%.

Description

Technical Field

[0001] The present invention relates to the field of phase change memory technology, including a phase change memory applicable to an integrated circuit memory and used as an embedded memory, and particularly relates to a memory device, an integrated circuit, a data processing device and a manufacturing method thereof. Background Art

[0002] Phase change based memory materials, such as chalcogenide-based materials and the like, can cause a phase change between an amorphous phase and a crystalline phase by the application of a current level applicable to integrated circuits. Generally, the amorphous phase has the characteristic of higher resistance compared to the general crystalline phase, and can be readily sensed to indicate data. These properties have generated an interest in using programmable resistive materials to form non-volatile memory circuits that can be read and written by random access.

[0003] The change from the amorphous phase to the crystalline phase, which defines the setting of the present invention, generally involves lower current operation. Generally, a current pulse for a set operation has a magnitude that is insufficient to melt the active region of a cell, but heats the active region to a transition temperature at which the amorphous phase change material tends to change to a crystalline solid phase. The change from the crystalline phase to the amorphous phase, which defines the reset of the present invention, generally involves higher current operation, including pulses of short high-density current to melt or breakdown the crystalline structure. The reset pulse generally has a short duration and a fast fall time to rapidly quench the phase change material, inhibiting the phase change process and allowing at least a portion of the phase change material to stabilize in an amorphous solid phase. The required current intensity for reset can be reduced by decreasing the size of the phase change material element in the cell and / or the contact area between the electrodes and the phase change material, such that a higher current density is achieved with a small absolute current value through the phase change material element.

[0004] A limitation in the application of phase change memories results from heat-induced phase transitions. Thus, heat in the environment in which the chip is deployed can cause loss of data and loss of reliability.

[0005] In addition, this limitation of not exposing the chip to the hot operating environment creates another limitation in technology applications. Specifically, in a surface mount operation or other mounting process that includes a thermal cycle, the chip can be mounted onto and electrically connected to the circuitry in a patterned circuit substrate (such as a packaging substrate or a printed circuit board). For example, a surface mount operation typically includes a solder reflow procedure that requires components (including the chip) to be heated to a temperature near the melting point (or eutectic point) of the alloy that constitutes the solder. Other mounting procedures also subject the chip to high-temperature thermal cycles. This can cause a change in the resistance of the materials in these cells such that the cells are no longer read as programmed.

[0006] Typical phase change materials are based on the germanium-antimony-tellurium (Ge-Sb-Te) material system inherited from optical disk memory. These materials exhibit fast speeds but poor data retention. In addition, these materials cannot pass the solder bonding thermal cycling criteria, which is specified as the ability to withstand a temperature of 260 °C for 30 seconds.

[0007] Therefore, prior art phase change memory chips that can retain a data set (referred to as pre-coded data) stored prior to the mounting process are not available. Thus, after the components of a circuit board or after the components of a system that includes the circuit board, the board manufacturer is required to store any necessary codes on any chips. This makes the phase change memory device less desirable compared to other types of non-volatile memory for many applications.

[0008] It is desirable to provide a phase change memory chip that can be used in an extreme operating environment and an integrated circuit having an embedded phase change memory. It is desirable to provide a phase change memory chip that can be encoded before being mounted on a circuit board, using a process that retains data during the thermal cycling encountered during the manufacture of the board or components.

[0009] It is desirable to provide materials for use as phase change memory elements in such devices. Summary of the Invention

[0010] A class of phase change materials having silicon oxide (SiO x ) doped in a Ge-rich Ge x Sb y Te z material is described. An integrated circuit using this phase change material as a memory element in a memory array can meet the above solder bonding criteria, exhibit good set speeds, and show good 10-year data retention characteristics.

[0011] The memory cell described in the present invention includes a first electrode and a second electrode; and a memory element electrically connected in series between the first electrode and the second electrode. This memory element includes a Ge x Sb y Te z phase change material and a silicon oxide additive, including a combination of elements having germanium (Ge) in the range of 28 to 36 at%, antimony (Sb) in the range of 10 to 20 at%, tellurium (Te) in the range of 25 to 40 at%, silicon (Si) in the range of 5 to 10 at%, and oxygen (O) in the range of 12 to 23 at%.

[0012] Examples of materials for memory elements with germanium (Ge) content in the range of 29 to 32 at% are described, including examples with germanium (Ge) content in the range of 29 to 32 at%, antimony (Sb) content in the range of 15 to 16 at%, and tellurium (Te) content in the range of 27 to 31 at%.

[0013] The combination of multiple elements in the phase change material has the concentrations of germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O), and the quantitative relationship of the concentrations of germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) effectively enables the memory device to have a crystallization transition temperature exceeding 250 °C and a setting speed less than 1000 nanoseconds (ns).

[0014] An integrated circuit including an array of memory cells having the above-described memory elements is described, wherein the combination of multiple elements in the phase change material has the concentrations of germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O), and the quantity of the concentrations of germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) effectively passes the solder bonding standard during testing (exposed to 260 °C for 30 seconds). Before the integrated circuit is installed as a component in a system, data can be written to the memory array, and the memory array using the memory elements of the present invention can be pre-coded.

[0015] The integrated circuit can mainly be a memory device. In addition, the memory array in the integrated circuit can be an embedded memory, wherein the integrated circuit includes logic that is operably connected to the memory array to use the memory array through an intra-chip connection.

[0016] The integrated circuit can be a component of a data processing system, wherein the integrated circuit is coupled (e.g., by solder bonding) to a patterned circuit substrate (e.g., a printed circuit board or a multichip substrate) to be connected to other components of the data processing system.

[0017] A method of manufacturing a data processing device includes:

[0018] Storing data in an array of memory cells on an integrated circuit, the array of memory cells having memory elements, the memory elements including a Ge x Sb y Te zA phase change material and a silicon oxide additive, comprising a combination of multiple elements having germanium (Ge) in the range of 28 to 36 at%, antimony (Sb) in the range of 10 to 20 at%, tellurium (Te) in the range of 25 to 40 at%, silicon (Si) in the range of 5 to 10 at%, and oxygen (O) in the range of 12 to 23 at%; and

[0019] After storing this data, the integrated circuit is bonded to a patterned circuit substrate by welding.

[0020] Other aspects and advantages of the present invention can be seen by reading the following drawings, detailed description, and the scope of the claims. Description of the Drawings

[0021] Figure 1 Illustrates the structure of a mushroom-type memory element including a memory element, which memory element includes silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z material.

[0022] Figure 2 Illustrates the structure of a via-active type memory element including a memory element, which memory element includes silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z material.

[0023] Figure 3 Illustrates the structure of a cross-point memory cell including a memory element, which memory element includes silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z material.

[0024] Figure 4 Illustrates the structure of a pore-type memory element including a memory element, which memory element includes silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z material.

[0025] Figure 5 Illustrates the stages of an embodiment of constructing a semiconductor chip element including a pre-coded chip on a circuit board or other substrate.

[0026] Figure 6A and Figure 6B illustrate stages in surface mounting operations suitable for the integrated circuits described in the present invention.

[0027] Figure 7 illustrate examples of reflow heating profiles for conventional solder (broken line graph) and lead-free tin-silver (SnAg) solder.

[0028] Figure 8 is a graph of temperature versus resistance showing the crystallization transition temperatures of materials A - D.

[0029] Figure 9 is a graph of bake time versus failure rate at various temperatures for material A.

[0030] Figure 10 is a graph showing the results of the durability test of material A.

[0031] Figure 11 is a graph of bake time versus failure rate at various temperatures for material C.

[0032] Figure 12 is a graph showing the results of the durability test of material C.

[0033] Figure 13 and Figure 14 is a graph of the resistance distribution in the memory array on the integrated circuit before and after baking according to the solder joint standard test for material A.

[0034] Figure 15 and Figure 16 is a graph of the resistance distribution in the memory array on the integrated circuit before and after baking according to the solder joint standard test for material C.

[0035] Figure 17 is a simplified block diagram of an integrated circuit memory device including a phase change memory cell described in the present invention.

[0036] Figure 18 is a simplified flow chart of the process described in the present invention.

[0037] Figure 19 is a schematic diagram of an array of one transistor / one memory element memory cells including a buffer layer described in the present invention.

[0038]

Symbol Explanation

[0039] 11: Arrow

[0040] 12: Microcontroller Unit MCU

[0041] 13: Arrow

[0042] 14: PCM

[0043] 15: Circuit board

[0044] 16: Random Access Memory RAM

[0045] 18: Input / Output I / O device

[0046] 100, 110: Memory element

[0047] 111: Buffer layer

[0048] 120: First electrode

[0049] 122: Contact area

[0050] 130: Dielectric

[0051] 140: Second electrode

[0052] 141: Contact area

[0053] 210: Memory element

[0054] 211: Second electrode

[0055] 212: First electrode

[0056] 215: Buffer layer

[0057] 301: Bottom electrode layer

[0058] 302: Buffer layer

[0059] 303: OTS switch layer

[0060] 304: Buffer layer

[0061] 305: Memory element

[0062] 306: Buffer layer

[0063] 310: First access line

[0064] 320: Second access line

[0065] 325: Memory cell

[0066] 414: Buffer layer

[0067] 416: Memory element

[0068] 420: First electrode

[0069] 440: Second electrode

[0070] 600: Lead frame package

[0071] 612: Lead bonding

[0072] 613: Interconnection pad

[0073] 614: Semiconductor die

[0074] 615: Bonding finger

[0075] 616: Conductor wire

[0076] 617: Foot

[0077] 619: Protection package

[0078] 623: Bonding site

[0079] 624: Circuit board

[0080] 625: Solder paste

[0081] 645: Foot

[0082] 705: Bonding pad

[0083] 706: Substrate

[0084] 707: Zone

[0085] 712: Conductive ball or bump

[0086] 713: Interconnection pad

[0087] 714: Die

[0088] 716: Solder ball

[0089] 719: Underfill

[0090] 720: Package

[0091] 723: Bonding site

[0092] 725: Solder paste

[0093] 765: Ball

[0094] 1800: Integrated circuit

[0095] 1802: Array

[0096] 1804: Column / layer decoder

[0097] 1806: Word line

[0098] 1808: Row / layer decoder

[0099] 1810: Bit line

[0100] 1812: Bus

[0101] 1814: Module

[0102] 1816: Data bus

[0103] 1818: Data input line

[0104] 1820: Other circuits

[0105] 1822: Data output line

[0106] 1824: Controller

[0107] 1826: Bias circuit voltage source and current source

[0108] 1900, 1910, 1920, 1930, 1940, 1950, 1960: Steps

[0109] 2014: Word line decoder

[0110] 2018: Bit line decoder

[0111] 2024: Sense amplifier and data input circuit

[0112] 2030, 2032, 2034, 2036: Memory cells

[0113] 2040, 2042, 2044, 2046: Memory elements

[0114] 2054: Access line

[0115] 2055: Source line terminal circuit

[0116] 2056, 2058: Word lines

[0117] 2060, 2062: Bit lines Detailed implementation manners

[0118] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further describes the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0119] The detailed description of the embodiments of the present invention refers to Figures 1 to 19 provided. A new class of phase change materials is described, including a germanium-rich GST doped with silicon oxide. The term "doped" as used in the present invention means an additive combined with GST, and the amount of the additive combined with GST effectively achieves the desired change in the characteristics of GST excluding the additive.

[0120] Representative materials of this class include Materials A - D, as shown in Table 1 below.

[0121] [Ge] at.% [Sb] at.% [Te] at.% [Si] at.% [O] at.% Material A 30.1±0.5 15.8±5 30.7±5 8.4±0.5 15.0±2 Material B 30.7±0.5 14.7±5 26.5±5 7.7±0.5 20.4±2 Material C 31.4±0.5 15.1±5 27.9±5 8.9±0.5 16.7±2 Material D 34.9±0.5 14.0±5 26.3±5 7.6±0.5 17.2±2

[0122] Table 1

[0123] The material of this new category is a Ge with a silicon oxide additive x Sb y Te z A phase change material, comprising a combination of multiple elements, having germanium (Ge) in the range of 28 to 36 at%, antimony (Sb) in the range of 10 to 20 at%, tellurium (Te) in the range of 25 to 40 at%, silicon (Si) in the range of 5 to 10 at%, and oxygen (O) in the range of 12 to 23 at%.

[0124] Examples of materials for memory elements are described, with germanium (Ge) in the range of 29 to 32 at%. Multiple examples are also described, with germanium (Ge) in the range of 29 to 32 at%, antimony (Sb) in the range of 15 to 16 at%, and tellurium (Te) in the range of 27 to 31 at%.

[0125] Figure 1Illustrates a "mushroom"-type memory element 100 having a first electrode 120 extending through a dielectric 130, and including a memory element 110 of silicon oxide-doped and germanium-rich GST phase change material, a buffer layer 111 in the form of a continuous layer (in this embodiment, contacting the memory element 110), and a second electrode 140 on the memory element 110. The first electrode 120 contacts the memory element of the phase change material on a first contact region 122, and the second electrode contacts a carbon deposit on a second contact region 141. Among mushroom-type memory elements, as shown, the first contact region 122 is smaller than the second contact region 141, for example, at least less than 50%. In some embodiments, the first contact region 122 is at least 90% smaller than the second contact region 141. The first electrode 120 is coupled to a terminal of an access device (not shown), such as a diode or a switch, while the second electrode 140 is coupled to a bit line and can be part of the bit line (not shown). The small first contact region 122 between the memory element of the phase change material and the first electrode 120, and the relatively large second contact region 141 between the buffer layer (carbon deposit) 111 and the second electrode 140 result in a higher current density and a small absolute current value in an active region of the memory element 110 proximal to the first electrode 120. In one embodiment structure, the first electrode 120 has a first contact region 122 on the order of 15 to 30 square nanometers, while the second electrode can have a contact region 141 that is continuous along a conductive line that serves as a bit line or a local bit line. The memory element of the phase change material is formed such that the bottom side of the conductive line is continuous along a length of the bottom side of the conductive line. The first electrodes of multiple mushroom memory elements (such as the first electrode 120) contact the memory elements distributed along that length.

[0126] The buffer layer 111 can be a sputter deposited formation having a thickness less than 15 nm, such as about 10 nm, and contacts the memory element of the phase change material. The buffer layer can include carbon, carbon silicide, titanium nitride, or other suitable buffer layer materials.

[0127] The memory element of the phase change material may have a thickness among the regions of the first contact region 122, which is selected according to the operating characteristics of a specific material, for example, it can be approximately 50 nm. The thickness of the phase change material depends on the design of the cell structure and the operating condition.

[0128] The first electrode 120 and the second electrode 140 may include, for example, titanium nitride (TiN) or tantalum nitride (TaN). Alternatively, the first electrode 120 and the second electrode 140 can each be tungsten (W), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN). In a further embodiment, the first electrode 120 and the second electrode 140 can each include one or more elements selected from the group consisting of doped silicon (doped-Si), silicon (Si), carbon (C), germanium (Ge), chromium (Cr), titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni), nitrogen (N), oxygen (O), ruthenium (Ru), and combinations thereof.

[0129] In the illustrated embodiment, the dielectric 130 includes silicon nitride. Alternatively, other dielectric materials, such as silicon oxide, can be used.

[0130] The contact region 122 located between the first electrode 120 and the memory element 110 of the phase change material has a width (in some embodiments, a diameter), which is less than the width of the contact region 141 located between the memory element 110 of the phase change material and the second electrode 140. Therefore, the current is concentrated in a portion of the memory element 110 adjacent to or adjacent to the first electrode 120, resulting in the phase change kinetics of the active region being confined during operation.

[0131] The first electrode 120 extends through the dielectric 130 to the underlying access circuitry (not shown). The underlying access circuitry can be formed by standard processes known in the art, and the structure of the various elements of the access circuitry depends on the array structure in which the memory cells of the present invention are implemented. Generally, the access circuitry can include an access device switch, such as an Ovonic threshold switch, a field effect transistor (FET transistor), or a bipolar transistor. Additionally, access devices, such as diodes, can be utilized. Other elements of the access circuitry include word lines, source lines, conductive plugs, and doped regions that serve as conductors within a semiconductor substrate.

[0132] Figure 2 A cross-sectional view of a pillar-shaped memory element having an "active in via" structure is shown. The memory element includes a memory element 210 of a phase change material located between a first electrode 212 and a second electrode 211, and a buffer layer 215 formed between the memory element 210 of the silicon oxide-doped and germanium-rich GST phase change material and the second electrode 211. In this embodiment, the memory element has a width substantially the same as the widths of the first electrode 212 and the second electrode 211 to define a multi-layer pillar surrounded by a dielectric (not shown). During operation, current passes through the buffer layer (carbon deposition) 215 and the memory element 210 located between the first electrode 212 and the second electrode 211.

[0133] Figure 3 An embodiment of a memory cell 325 is shown, including a multi-layer pillar disposed at the intersection of a first access line 310 and a second access line 320.

[0134] The pillar of this embodiment includes a bottom electrode layer 301 over the first access line 310, such as a metal, metal nitride, a doped semiconductor, or the like.

[0135] A buffer layer 302 is disposed over the bottom electrode layer 301. In some embodiments, the buffer layer 302 can be a composition, such as carbon, or a combination of silicon and carbon. The buffer layer 302 can be, for example, 15 to 30 nm thick.

[0136] An OTS switching layer 303 is disposed above the buffer layer 302. For example, the OTS switching layer 303 may include an OTS material such as arsenic selenium germanium silicon (AsSeGeSi), arsenic selenium germanium silicon carbon (AsSeGeSiC), arsenic selenium germanium silicon nitrogen (AsSeGeSiN), arsenic selenium germanium silicon tellurium (AsSeGeSiTe), arsenic selenium germanium silicon tellurium sulfur (AsSeGeSiTeS), arsenic tellurium germanium silicon (AsTeGeSi), arsenic tellurium germanium silicon nitrogen (AsTeGeSiN), and other available OTS materials. The OTS switching layer may be, for example, 15 to 45 nm thick, preferably less than 50 nm thick.

[0137] A buffer layer 304 is disposed above the OTS switching layer 303 and may be referred to as a capping layer of the OTS material. The buffer layer 304 may be a barrier layer including a composition of silicon and carbon. The buffer layer 304 may be, for example, 15 to 30 nm thick.

[0138] A memory element 305 is disposed above the buffer layer 304. The material of the memory element includes a GST phase change memory material doped with silicon oxide and rich in germanium.

[0139] The memory element 305 may be a layer having a thickness selected according to a specific embodiment.

[0140] A buffer layer 306 is disposed above a top surface of the memory element 305. The buffer layer 306 may be, for example, a continuous layer of carbon or other material and 5 to 15 nm thick.

[0141] The first access line (bit line) and the second access line (word line) may include various metals, metalloid materials, doped semiconductors, or combinations thereof. Embodiments of the first access line and the second access line may be implemented using one or more material layers, such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), titanium nitride / tungsten / titanium nitride (TiN / W / TiN), and other materials. For example, the thickness of the first access line and the second access line may range from 10 to 100 nm. In other embodiments, the first access line and the second access line may be very thin or very thick. In this embodiment, the selected material of the second access line is preferably selected to be compatible with the buffer layer (carbon deposition) 306 or the memory cell 325. Similarly, the selected material of the first access line is preferably selected to be compatible with the electrode material of the bottom electrode layer 301 or the memory cell 325.

[0142] In another embodiment, compared to the surface of the switching layer, such as Figure 1The bottom electrode layer shown has a small contact surface. Therefore, an increased current density can be achieved.

[0143] Figure 4 A cross-sectional view of a fourth memory element having a pore-type structure is shown. The memory element 416 is a body of silicon oxide doped and germanium-rich GST phase change material, which is surrounded by a dielectric (not shown). The body is electrically connected in series between the top surface of the first electrode 420 and the bottom surface of the second electrode 440. A buffer layer 414 is formed on top of a top surface of the memory element 416 of the phase change material as discussed above. The memory element 416 of the phase change material may have a width adjacent to the second electrode (top electrode) 440 that is greater than the width adjacent to the first electrode 420.

[0144] Figure 5Illustrates multiple stages of constructing an element of a semiconductor chip on a circuit board or other substrate in one embodiment. In this embodiment, the desired selection of chips, such as a microcontroller unit MCU 12, a germanium-rich GST phase change memory PCM 14 doped with silicon oxide, at least a portion of which can be used to store encoded or other data sets, a random access memory RAM 16, and an input / output I / O device 18 are "designed into" an electronic product including a circuit board. The non-volatile memory in one or more selected chips can be programmed by a manufacturer as shown by arrow 11, for example, using a step and test system before or after packaging of the individual chips. In this embodiment, the PCM 14 is programmed using a pre-mounting coding process to produce a pre-coded PCM 14'. Additionally, any coding in other chips can also be performed at this stage to produce a collection of pre-coded chips of the PCM 14', suitable for a specific use in the art. The pre-coded chips are then mounted on a circuit board 15 (e.g., a motherboard) or other substrate as shown by arrow 13. During the step of mounting the chips on the substrate, a thermal cycle of heating the chips may be required during the period when the storage cells in the coded PCM are raised to a temperature above a transition temperature to change the solid phase of a typical phase change memory material. Additionally, in some embodiments of known system-on-a-chip SOC devices, including a single chip with an embedded memory, this embedded memory includes a germanium-rich GST phase change memory array doped with silicon oxide and other circuits, and can be replaced using Figure 5 the four devices shown.

[0145] A representative mounting step including a thermal process, which may interfere with prior art phase change memory cells, is discussed with reference to Figure 6A , Figure 6B and Figure 7 . Multiple stages in a surface mount operation are illustrated in Figure 6A and Figure 6BAmong these embodiments shown in the drawings, a lead frame package 600 and a flip-chip package 720 are mounted on and electrically connected to bond sites 623, 723, and the bond sites 623, 723 are exposed on a package mount surface of a circuit board 624.

[0146] The lead frame package 600 in this embodiment includes a semiconductor die 614 that can be pre-coded as described in the present invention. The active side of the semiconductor die 614 is mounted upward, and the semiconductor die 614 is located above a wire 616. Interconnect pads 613 in the die are electrically connected to a bond site above a bond finger 615 on the wire 616 through a wire bond 612. The die, wire bond, and bond finger are enclosed in a protective package 619 to form a package body from leads projecting. The wire 616 has a dogleg shape, so that feet 617 are located below the package body. When the feet 617 of the wire rest on the bond site 623, some clearance is provided between the lower surface of the package body and the upper surface of the circuit board.

[0147] The flip-chip package 720 in this embodiment includes a die 714 that can be pre-coded as described in the present invention. The die 714 is mounted on a package substrate 706 in a flip-chip manner and electrically connected to a circuit on the package substrate 706. Conductive balls or bumps 712 (typically metal, such as gold or solder) are mounted on interconnect pads 713 on the die. Bond pads 705 connected to the circuit in the substrate 706 are exposed on the die attach surface of the substrate to provide attachment of the interconnect balls or bumps and the bond site. A second layer of interconnect land 707 on the opposite side of the substrate is connected to the bond pad 705 through the circuit in the substrate. An underfill 719 fills the space between the active side of the die and the die mount side of the package substrate to complete the package. Solder balls 716 are mounted on the land 707 to provide an electrical connection of the package 720 to the bond site 723 on the circuit board.

[0148] The second-level interconnection of the lead frame package 600 and the flip-chip package 720 is formed by soldering the feet 617 and the second-level interconnect solder balls 716 onto the bonding sites 623, 723. Typically, before installing this package, the circuit board is prepared by depositing a small amount of solder or solder paste (e.g., by plating or printing) onto the bonding sites (the solder or solder paste may be optionally omitted for flip-chip interconnection). Then, the package can be oriented so that the feet 617 and the solder balls 716 are aligned with the corresponding bonding sites 623, 723 on the circuit board, and the package is moved toward the circuit board so that the feet 617 and the solder balls 716 rest on the solder or solder paste 625, 725.

[0149] Thereafter, the solder or solder paste (or the second-level interconnect solder balls) is heated to reflow the solder and complete this electrical connection. Typically, where the solder or solder paste is provided, the feet or balls are wetted by reflowing the solder so that the solder flows on the surfaces of the bonding sites 623, 723 and flows onto the lower surfaces of the feet 645 and the balls 765 as Figure 6B shown.

[0150] The heating of the reflow solder or solder paste, typically by passing the components through a reflow oven, requires the temperature of the components to be raised according to a time / temperature schedule appropriate for the particular solder.

[0151] Figure 7An example of the reflow heating profile of a conventional solder (broken line) and a lead-free SnAg solder is shown. The lead-free solder has a higher melting point and reflows more slowly, so components with lead-free solder must be brought to a higher temperature and held for a longer time compared to components with conventional solder. In particular, for a typical lead-free solder, during the pre-heat phase with a cycle from about 150 °C to about 180 °C and about 60 to 120 seconds, the temperature is raised; then, during the reflow phase lasting more than 30 seconds, the temperature rises more rapidly to a peak temperature close to about 240 °C, holds for a period of about 10 to 20 seconds or longer, and then is allowed to drop; the temperature throughout the reflow phase exceeds about 220 °C. In particular, for a conventional solder, during the pre-heat phase with a cycle from about 140 °C to about 170 °C and about 60 to 120 seconds, the temperature is raised; then, during the reflow phase lasting more than 30 seconds, the temperature rises more rapidly to a peak temperature close to about 225 °C and holds for a period of about 5 seconds or longer; the temperature throughout the reflow phase exceeds about 200 °C. The industry specification for solder bonding qualification calls for the ability to withstand a temperature of 260 °C for 30 seconds or longer.

[0152] Figure 8 It is a chart of the thermal cycling results for establishing a crystallization transition temperature (generally 800), where the resistance decreases as the temperature rises, and when the temperature exceeds a certain threshold temperature, the resistance suddenly drops sharply, and this temperature is the crystallization temperature. The crystallization temperatures of materials A - D are approximately 250 °C or higher. In addition, this chart shows that the resistance in the crystalline phase increases slightly with the increase in the germanium (Ge) concentration.

[0153] Table 2 below shows the characteristics of Material A and Material C.

[0154]

[0155] Table 2

[0156] It can be seen that Material A and Material C each exhibit a resistance window with a set state of approximately 100 kiloohms (K ohms) and a reset state of 500 K ohms. Thus, the resistance in the reset state is five times that in the set state. For the test with a set current of 300 μA, the set speed of Material A is approximately 2 μs. For Material C, the set speed is approximately 800 ns. The measured endurance of Material A is approximately 10 K cycles, while that of Material C is approximately 100 K cycles. Both Material A and Material C pass the three - solder joint standard, which extends from 30 seconds at 260 °C to 90 seconds at 260 °C. Additionally, Material A shows a 10 - year data retention temperature of 145 °C. Material C shows a 10 - year Data storage temperature.

[0157] Figure 9 is a graph showing the failure rate versus baking time for two samples of Material A. Figure 10 is a graph plotting the lifetime of two samples versus temperature (1 / K B T). This test shows an activation energy Ea of approximately 2.7 electron volts for Material A (as in the Arrhenius equation), passing the 10 - year 145 °C data retention criterion.

[0158] Figure 11 is a graph showing the failure rate versus baking time for two samples of Material C. Figure 12 is a graph showing the lifetime of two samples versus temperature (1 / K B T). This test shows an activation energy Ea of approximately 3.2 electron volts for Material C, passing the 10 - year 140 °C data retention criterion. However, Material C has a faster set speed at 800 ns and can pass the solder joint standard.

[0159] Figure 13Shown is the resistance distribution of a memory array of memory elements including material A in a memory with an array of set and reset memory cells, using 3 different set pulse currents. The results shown are based on tests after 10 set / reset cycles on the memory cells. The three different set pulse characteristics include 150 μA for 960 ns, 200 μA for 960 ns, and 300 μA for 960 ns. The set pulses with higher current result in a tighter and lower resistance distribution. The reset pulse in this embodiment is 400 μA for 40 ns. In this test, the same number of memory cells are exposed to each of four conditions, including three set conditions and one reset condition.

[0160] Figure 14 Shown is the measured distribution after exposing the integrated circuit to a ramp up to 260 °C for 90 seconds to verify the solder bonding criterion. It can be seen that the integrated circuit passes the criterion, which is that the resistance in the reset condition of a set pulse current of 200 μA remains above 500 K ohms and the resistance in the set condition of a set pulse current of 300 μA remains below 100 K ohms.

[0161] Figure 15 Shown is the resistance distribution of a memory array of memory elements including material C in a memory with an array of set and reset memory cells, using 3 different set pulse currents. The results shown are based on tests after 10 set / reset cycles on the memory cells. The three different set pulse characteristics include 300 μA for 800 ns, 300 μA for 960 ns, and 200 μA for 960 ns. The longer set pulses result in a tighter and lower resistance distribution. The reset pulse in this embodiment is 400 μA for 40 ns. In this test, the same number of memory cells are exposed to each of four conditions, including three set conditions and one reset condition.

[0162] Figure 16 Shown is the measured distribution after exposing the integrated circuit to a ramp up to 260 °C for 90 seconds to verify the solder bonding criterion. It can be seen that both set pulses of 300 μs can pass the solder bonding criterion, with a yield loss of less than 0.5% for the 90 - second exposure, where passing the criterion requires the resistance in the reset condition to remain above 500 K ohms and the resistance in the set condition to remain below 100 K ohms.

[0163] Other tests of Materials A - D show that at least Material A and Material C among this new class of materials can be set using a pulse length substantially less than 1000 ns.

[0164] Silicon oxide (SiO x ) doped, germanium-rich Ge x Sb y Te z Tests of examples of this new class of materials show that a combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) can be used. The combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) effectively enables the memory device to have a set speed of less than 1000 ns, and as low as 640 ns. In addition, this test shows that within the new class of phase change materials, a combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) can be used. The combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) effectively has a crystallization transition temperature greater than 250 °C. In addition, this test shows that for a memory array on an integrated circuit using this new class of phase change materials, a combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) can be used. The combination of the elements germanium (Ge), antimony (Sb), tellurium (Te), silicon (Si), and oxygen (O) effectively passes the soldering bond standard.

[0165] Figure 17 is a simplified block diagram of an integrated circuit 1800 that is an embedded phase change memory array 1802 including a plurality of memory cells, and these memory cells have germanium (Ge) that is doped with silicon oxide (SiO x ) and is germanium-rich x Sb y Te zMemory elements formed of the material. A row / level decoder 1804 having read, set, and reset modes is coupled and in electrical communication with a plurality of word lines 1806, which are arranged along multiple levels and multiple columns in the array 1802. A column / level decoder 1808 is in electrical communication with a plurality of bit lines 1810, and the column / level decoder 1808 is used to read, set, and reset memory cells in the array 1802, and these bit lines 1810 are arranged along multiple levels and multiple rows in the array 1802. An address on a bus 1812 is supplied to the column / level decoder 1804 and the row / level decoder 1808. A sense circuitry (sense amplifier) and a data-in structure in a module 1814 including voltage sources and / or current sources for read, set, and reset modes are coupled to the row / level decoder 1808 via a data bus 1816. Data is supplied to the data-in structure in the module 1814 via a data-in line 1818 from an input / output port above the integrated circuit 1800 or from other data sources inside or outside the integrated circuit 1800.

[0166] Other circuits 1820 may be included above the integrated circuit 1800, such as a general-purpose processor or special-purpose application circuitry, or a combination of multiple modules providing system-on-a-chip functionality supported by the array 1802, and the array is used as an embedded memory accessed via on-chip connections. Data is supplied from the sense amplifier in the module 1814 to an input / output port above the integrated circuit 1800 or to other data destinations inside or outside the integrated circuit 1800 used for inter-chip communication via a data-out line 1822.

[0167] A controller 1824 implemented using this embodiment of a bias arrangement state machine controls the application of a bias circuitry voltage source and current source 1826 for the application of a bias arrangement, including rapidly reading, setting, resetting, and verifying the voltage and / or current of word lines and bit lines. During a read operation or other operation of accessing a selected memory cell, by applying a voltage to a selected memory cell to make the voltage on the switch in the selected memory cell higher than a threshold, and by applying a voltage to an unselected memory cell to make the voltage on the switch in the unselected memory cell lower than the threshold, the controller includes control circuitry for a switching layer that has a threshold voltage depending on the structure and composition of the memory cell.

[0168] The controller 1824 can be implemented using special-purpose logic circuitry known in the art. In an alternative embodiment, the controller 1824 includes a general-purpose processor that can be implemented on the same integrated circuit to execute a computer program to control the operation of the device. In other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor can be used in the implementation of the controller 1824.

[0169] Among the operations, each of the multiple memory cells in the array 1802 stores data according to the resistance of the corresponding memory element. The data value can be determined, for example, by comparing the current on a bit line of a selected memory cell with the current of a suitable reference current of a sense amplifier of the sense circuit (module 1814). The reference current can be established such that a predetermined range of current corresponds to logic '0', and different ranges of current correspond to logic '1'. In some embodiments, multiple bits of each cell can be stored.

[0170] In some embodiments, before installing the integrated circuit in a data processing system, the memory array 1802 is pre-coded with data, such as a computer program. This can be implemented using factory programming during a process before or after packaging and before shipping to the user.

[0171] Reading or writing to a memory cell of array 1802 can thus be achieved by applying an appropriate voltage to the bit lines using a voltage source, to cause current to flow through the selected memory cell.

[0172] Figure 18 A process flow diagram illustrating a process for fabricating an integrated circuit using a pre-coded array of memory cells, the plurality of memory cells having memory elements including silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z material.

[0173] In step 1900, a first electrode 120 having a contact region 122 is formed, the first electrode 120 extending through the dielectric 130. In the illustrated embodiment, the first electrode 120 includes titanium nitride (TiN) and the dielectric 130 includes silicon nitride (SiN). In some embodiments, the contact region 122 of the first electrode 120 has a sub-lithographic width or diameter.

[0174] The first electrode 120 and the dielectric 130 can be formed by several processes. For example, a layer of electrode material can be formed over the top surface of the access circuit (not shown), and then a photoresist layer over the electrode layer is patterned using standard photolithographic techniques to form a mask of photoresist overlying the location of the first electrode 120. The photoresist mask is then trimmed using, for example, an oxygen plasma to form a mask structure having sub-lithographic dimensions overlying the location of the first electrode 120. The electrode material layer is then etched using the trimmed photoresist mask to form the first electrode 120 having a sub-lithographic diameter. The dielectric 130 is then formed and planarized.

[0175] In step 1910, silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Tez The host system of the phase change material of the material category is deposited on the first electrode 120 and the dielectric 130. Germanium-rich Ge x Sb y Te z and the deposition of silicon oxide can be performed by co-sputtering a Ge-Sb-Te target and a silicon dioxide target (SiO2 target) in an argon atmosphere. Alternatively, germanium-rich Ge x Sb y Te z and the deposition of silicon oxide can be performed by an oxygen reactive process using a sputtered single composite Ge x Sb y Te z and a silicon target. Other processes suitable for a particular phase change material and memory cell structure can be used.

[0176] An optional annealing (not shown) can be performed to crystallize the phase change material. In the illustrated embodiment, the annealing step is performed in a nitrogen ambient at 300 °C for 100 seconds. Alternatively, in some embodiments, since the subsequent back-end-of-line processes performed to complete the device may include high temperature cycles and / or a thermal annealing step according to the manufacturing techniques used to complete the device, annealing can be achieved by the following processes and no separate annealing step is added to the manufacturing line.

[0177] Next, in step 1920, a second electrode 140 is formed, resulting in Figure 1 the structure shown. In the illustrated embodiment, the second electrode 140 includes titanium nitride (TiN).

[0178] Next, in step 1930, back-end-of-line (BEOL) processing is performed to complete the semiconductor processing steps of the chip. The back-end process can be a standard process known in the art, and the processes performed depend on the configuration of the chip in which the memory cells are implemented. Generally, the structures formed by the back-end process may include contacts, inter-layer dielectrics, and various metal layers on the chip for interconnection. This chip includes circuitry for coupling the memory cells to the peripheral circuitry. These back-end processes may include the deposition of dielectric materials at elevated temperatures, such as depositing silicon nitride (SiN) at 400 °C, or performing high density plasma HDP oxide deposition at 500 °C or higher temperatures. Due to these processes, Figure 17 the control circuit and biasing circuit shown are formed on a device including circuitry for setting the operation and reset operations.

[0179] By forming multiple layers of the memory array circuit, this process can be extended to 3D memory arrays.

[0180] After the back-end process, the chip is packaged into a single-chip or multi-chip package according to a specific requirement (step 1940). Additionally, the chip can be pre-coded with data, such as but not limited to a computer program or a control parameter (step 1950). The pre-coding can be performed before or after the packaging step 1940.

[0181] The pre-coded chip can then be soldered and mounted on a patterned circuit substrate, such as a printed circuit board, without significant loss of the pre-coded data (step 1960). In this context, significant loss of the pre-coded data can include using the available error correction on the integrated circuit rather than a recoverable loss of data volume, or can include a loss of data volume that interferes with the functionality of the integrated circuit in its mission function.

[0182] Figure 19 Among them, four one-transistor, one memory element (1T / 1R) storage cells 2030, 2032, 2034, 2036 with memory elements 2040, 2042, 2044, 2046 represent a small section of an array. The memory elements 2040, 2042, 2044, 2046 are silicon oxide (SiO x ) doped and germanium-rich Ge x Sb y Te z The main body of the phase change material. An array of this type can be used on a memory device and used as the embedded memory discussed above.

[0183] The sources of the respective access transistors of the storage cells 2030, 2032, 2034, 2036 are commonly connected to a first type of access line 2054 (i.e., the source line), which terminates at a source line termination of circuit 2055, such as a ground terminal. In another embodiment, the source lines of the access devices are not shared among adjacent cells but are independently controllable. The source line termination circuit 2055 may include a biasing circuit, such as a voltage source and a current source. In some embodiments, the source line termination circuit 2055 may include a decoding circuit for applying a bias configuration to the access line 2054 other than ground.

[0184] A plurality of second type access lines including word lines 2056, 2058 extend along a direction parallel to a first direction. The word lines 2056, 2058 are electrically connected to the word line decoder 2014. The gates of the access transistors of the storage cells 2030, 2034 are connected to the word line 2056, and the gates of the access transistors of the storage cells 2032, 2036 are commonly connected to the word line 2058.

[0185] Multiple third - type access lines including bit lines 2060, 2062 extend in a direction parallel to a second direction and are electrically connected to the bit - line decoder 2018, sense amplifiers, and data - in circuit 2024. In the illustrated embodiment, respective memory elements are arranged between the drain of the corresponding access device and the corresponding bit line. Alternatively, the memory elements can be located above the source side of the corresponding access device. The control circuit and the bias circuit (see Figure 8 ) are coupled to the array and provide means for applying set and reset operations to the memory cells.

[0186] Alternatively, the memory cells can be organized in a cross - point architecture. The first electrode can be an access line, such as a word line and / or a bit line. In this architecture, access devices, such as diodes or OTS switches, are arranged between the memory elements and the access lines.

[0187] A method of manufacturing a circuit including an integrated - circuit phase - change memory having a memory element of a SiO x - doped and Ge - rich Ge x Sb y Te z material, the manufacturing method includes:

[0188] Precoding a data set in the integrated - circuit phase - change memory by inducing a lower - resistance state in some of the cells in the memory and a higher - resistance state in other cells in the memory; and

[0189] After encoding, using a step including thermal cycling, such as inducing a soldering bond at a temperature between 200 °C and 260 °C, mounting the integrated - circuit phase - change memory on a substrate.

[0190] The described new class of phase - change memory materials is characterized by high data retention and the capability of the thermal budget of the soldering bond. This new class of phase - change materials is used in embedded memories and memory arrays in high - density large - scale memory integrated circuits.

[0191] The specific embodiments described above further elaborate on the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A memory device, comprising: A first electrode and a second electrode; And A memory element electrically connected in series between the first electrode and the second electrode, the memory element comprising a Ge x Sb y Te z phase change material and a silicon oxide additive, comprising a combination of elements having germanium in the range of 28 to 36 at%, antimony in the range of 10 to 20 at%, tellurium in the range of 25 to 40 at%, silicon in the range of 5 to 10 at%, and oxygen in the range of 12 to 23 at%; A buffer layer disposed between the second electrode and the memory element, the material of the buffer layer comprising carbon, carbon silicide, or titanium nitride; Another buffer layer disposed on the first electrode; An OTS switching layer disposed on the another buffer layer; Yet another buffer layer disposed on the OTS switching layer, and the memory element is disposed on the yet another buffer layer.

2. The memory device according to claim 1, wherein the combination of the plurality of elements comprises germanium, antimony, tellurium, silicon, and oxygen, or germanium, antimony, tellurium, silicon, and oxygen, and the amount of the combination of the plurality of elements is such that the memory device has a crystallization transition temperature exceeding 250 °C or a setting speed less than 1000 nanoseconds.

3. The memory device according to claim 1, wherein the germanium content ranges from 29 to 32 at%, the antimony content ranges from 15 to 16 at%, and the tellurium content ranges from 27 to 31 at%.

4. An integrated circuit, comprising: A memory cell array having a first electrode, a second electrode, a buffer layer, and a plurality of memory elements, one of the memory elements being electrically connected in series between the first electrode and the second electrode, the memory elements including a Ge x Sb y Te z phase change material and a silicon oxide additive, comprising a combination of elements including germanium in the range of 28 to 36 at%, antimony in the range of 10 to 20 at%, tellurium in the range of 25 to 40 at%, silicon in the range of 5 to 10 at%, and oxygen in the range of 12 to 23 at%; Wherein, the buffer layer is disposed between the second electrode and the memory element, and the material of the buffer layer comprises carbon, carbon silicide, or titanium nitride; The memory cell array further comprises: Another buffer layer disposed on the first electrode; An OTS switching layer disposed on the another buffer layer; Yet another buffer layer disposed on the OTS switching layer, and the memory element is disposed on the yet another buffer layer.

5. The integrated circuit according to claim 4, wherein the combination of the plurality of elements comprises germanium, antimony, tellurium, silicon, and oxygen, or germanium, antimony, tellurium, silicon, and oxygen, and the amount of the combination of the plurality of elements is such that the integrated circuit has a crystallization transition temperature exceeding 250 °C or a setting speed less than 1000 nanoseconds.

6. The integrated circuit according to claim 4, wherein the combination of the plurality of elements comprises germanium, antimony, tellurium, silicon, and oxygen, and after being exposed to a temperature of 260 °C for 30 seconds, the amounts of germanium, antimony, tellurium, silicon, and oxygen are such that the data stored in the memory elements of the memory cell array is retained.

7. The integrated circuit according to claim 4, wherein the germanium content ranges from 29 to 32 at%, the antimony content ranges from 15 to 16 at%, and the tellurium content ranges from 27 to 31 at%.

8. A data processing device, comprising: An integrated circuit is bonded to a patterned circuit substrate by soldering, wherein the integrated circuit includes an array of memory cells, the array of memory cells having a first electrode, a second electrode, a buffer layer, and a plurality of memory elements, one of the memory elements being electrically connected in series between the first electrode and the second electrode, the memory elements including a Ge x Sb y Te z phase change material and a silicon oxide additive, including a combination of elements having germanium in the range of 28 to 36 at%, antimony in the range of 10 to 20 at%, tellurium in the range of 25 to 40 at%, silicon in the range of 5 to 10 at%, and oxygen in the range of 12 to 23 at%; Wherein, the buffer layer is disposed between the second electrode and the memory element, and the material of the buffer layer comprises carbon, carbon silicide, or titanium nitride; The memory cell array further comprises: Another buffer layer disposed on the first electrode; An OTS switching layer disposed on the another buffer layer; Yet another buffer layer disposed on the OTS switching layer, and the memory element is disposed on the yet another buffer layer.

9. The data processing device according to claim 8, wherein the combination of the plurality of elements comprises germanium, antimony, tellurium, silicon, and oxygen, or germanium, antimony, tellurium, silicon, and oxygen, and the amount of the combination of the plurality of elements is such that the data processing device has a setting speed less than 1000 nanoseconds.

10. The data processing device according to claim 8, wherein the germanium content ranges from 29 to 32 at%, the antimony content ranges from 15 to 16 at%, and the tellurium content ranges from 27 to 31 at%.

11. A method for manufacturing a data processing device, comprising: Store data in a memory cell array on an integrated circuit, the memory cell array having a first electrode, a second electrode, a buffer layer, and a plurality of memory elements, one of the memory elements being electrically connected in series between the first electrode and the second electrode, the memory elements including a Ge x Sb y Te z phase change material and a silicon oxide additive, including a combination of elements having germanium in the range of 28 to 36 at%, antimony in the range of 10 to 20 at%, tellurium in the range of 25 to 40 at%, silicon in the range of 5 to 10 at%, and oxygen in the range of 12 to 23 at%; and after storing the data, welding and bonding the integrated circuit to a patterned circuit substrate; wherein, the buffer layer is disposed between the second electrode and the memory element, and the material of the buffer layer includes carbon, carbon silicide or titanium nitride; The memory cell array further includes: another buffer layer disposed on the first electrode; an OTS switching layer disposed on the another buffer layer; yet another buffer layer disposed on the OTS switching layer, and the memory element is disposed on the yet another buffer layer.

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