Resistive random access memory device, method for forming the same, and integrated chip

Abstract

Various embodiments of the present invention are directed to a resistive random access memory device, a method for forming the same, and an integrated chip, wherein the resistive random access memory device includes a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure includes a dielectric material doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant.

Description

Technical Field

[0001] The embodiments of the present invention relate to a resistive random access memory device, a method for forming the same, and an integrated chip. Background Art

[0002] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be either volatile memory or nonvolatile memory. Volatile memory stores data when it is powered, while nonvolatile memory is able to retain data when power is removed. Resistive random access memory (RRAM) is a promising candidate for the next generation of nonvolatile memory technology due to its simple structure and compatibility with complementary metal-oxide semiconductor (CMOS) logic processes. An RRAM cell contains a dielectric data storage structure with a variable resistance, which is placed between two conductive structures. Summary of the invention

[0003] An embodiment of the present invention provides a memory device, comprising: a substrate; a bottom electrode covering the substrate; a top electrode covering the bottom electrode; and a data storage structure arranged between the top electrode and the bottom electrode, wherein the data storage structure comprises a dielectric material doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant.

[0004] An embodiment of the present invention provides an integrated chip, comprising: a substrate; and a resistive random access memory (RRAM) cell overlying the substrate, wherein the RRAM cell comprises a top electrode, a bottom electrode, and a data storage structure arranged between the top electrode and the bottom electrode, wherein the data storage structure comprises a first high-κ dielectric material and a plurality of dopants, wherein the plurality of dopants comprise a first dopant, a second dopant, and a third dopant that are different from each other.

[0005] An embodiment of the present invention provides a method for forming a memory device, the method comprising: depositing a bottom electrode above a substrate; depositing a data storage structure above the bottom electrode so that the data storage structure includes a dielectric material doped with a first dopant, a second dopant, and a third dopant; depositing a top electrode above the data storage structure; and patterning the bottom electrode, the data storage structure, and the top electrode, thereby forming a memory cell above the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Schematic diagrams illustrating some embodiments of memory devices including memory cells having low formation voltages.

[0008] Figure 2 Cross-sectional views illustrating some embodiments of memory devices including memory cells having multi-doped data storage structures.

[0009] Figures 3 to 5 Cross-sectional views illustrating some embodiments of operating a memory cell including a multi-doped data storage structure.

[0010] Figure 6 and Figure 7 illustrate Figure 2 Cross-sectional views of some alternative embodiments of memory devices.

[0011] Figure 8 and Fig. 9 Cross-sectional diagrams illustrating some embodiments of an integrated chip having memory cells disposed above a substrate, wherein the memory cells have a low formation voltage.

[0012] Figure 10 to Figure 14 Cross-sectional views illustrating some embodiments of methods for forming a memory cell having a data storage structure multi-doped with a first dopant, a second dopant, and / or a third dopant.

[0013] Fig.15 A flow chart is illustrated according to some embodiments of a method for forming a memory cell having a data storage structure multi-doped with a first dopant, a second dopant, and / or a third dopant.

[0014] Fig.16 Flowcharts illustrating some embodiments of methods for forming an integrated chip including a front-end-of-line resistive memory cell having a data storage structure multi-doped with a first dopant, a second dopant, and / or a third dopant.

[0015] Description of Figure Numbers

[0016] 100, 200, 600, 700: memory devices;

[0017] 102: Transistor;

[0018] 104: memory unit;

[0019] 106: bottom electrode;

[0020] 108: data storage structure;

[0021] 110: roof layer;

[0022] 110a: metal layer;

[0023] 110b: metal oxide layer;

[0024] 112: top electrode;

[0025] 114: Region;

[0026] 126p: peripheral area;

[0027] 202: substrate;

[0028] 204: source / drain region;

[0029] 206: gate dielectric layer;

[0030] 208: gate electrode;

[0031] 210: sidewall spacer structure;

[0032] 212: lower internal communication hole;

[0033] 214: lower internal connecting wire;

[0034] 216, 816: Inner connection dielectric structure;

[0035] 218: bottom electrode through hole;

[0036] 220: top electrode through hole;

[0037] 222: upper internal communication hole;

[0038] 224: upper internal connecting wire;

[0039] 226: oxygen vacancy;

[0040] 228: conductive path;

[0041] 300: first state;

[0042] 400: second state;

[0043] 402: lower area;

[0044] 404: middle area;

[0045] 406: upper area;

[0046] 500: third state;

[0047] 602: multi-doped data storage layer;

[0048] 604: data storage layer;

[0049] 702: first data storage layer;

[0050] 704: second data storage layer;

[0051] 706: third data storage layer;

[0052] 800: integrated chip;

[0053] 802: Isolation structure;

[0054] 804a: first source / drain region;

[0055] 804b: second source / drain region;

[0056] 806: Semiconductor devices;

[0057] 808: gate dielectric layer;

[0058] 810: Conductive wire / gate electrode;

[0059] 812: internal connection structure;

[0060] 814: conductive contact;

[0061] 818: Conductive wire;

[0062] 818bl, BL: bit line;

[0063] 818sl, SL: source line;

[0064] 818wl, WL: word line;

[0065] 820: via;

[0066] 902: Device gate stack;

[0067] 1000, 1100, 1200, 1300, 1400: cross-sectional views;

[0068] 1002: lower interlayer dielectric layer;

[0069] 1202: memory cell layer stacking;

[0070] 1204: mask layer;

[0071] 1402: upper interlayer dielectric layer;

[0072] 1500, 1600: Methods;

[0073] 1502, 1504, 1506, 1508, 1510, 1512, 1602, 1604, 1606, 1608, 1610, 1612, 1614: action;

[0074] h1: height. DETAILED DESCRIPTION

[0075] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0076] Additionally, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0077] A resistive random access memory (RRAM) cell includes a data storage structure (e.g., one or more oxide layers) disposed between a top electrode and a bottom electrode. The RRAM cell is disposed above a semiconductor substrate. The variable resistance of the data storage structure represents a data cell, such as a data bit. Depending on the voltage applied between the top electrode and the bottom electrode, the variable resistance undergoes a reversible change between a high resistance state and a low resistance state corresponding to a data state of the data cell. The high resistance state is high where the variable resistance exceeds a threshold, and the low resistance state is low where the variable resistance is below a threshold.

[0078] Before the RRAM cell can be used to store data, an initial conductive path (i.e., a conductive filament) is typically formed across the data storage structure. The formation of the initial conductive path makes subsequent write operations (which form the conductive path) easier to perform. To form the initial conductive path, a forming voltage is applied across the top electrode and the bottom electrode at the end of the RRAM manufacturing process. In some types of RRAM cells, the conductive path may include vacancies (e.g., oxygen vacancies). In such devices, the forming voltage can knock out oxygen atoms of the lattice of the data storage structure, thereby forming local oxygen vacancies. These local oxygen vacancies tend to align to form a conductive path extending through the data storage structure. Thereafter, a set voltage or a reset voltage may be applied across the top electrode and the bottom electrode to change the resistivity of the data storage structure between a high resistance state and a low resistance state. Typically, the forming voltage is greater than the set voltage. Typically, one or more transistors (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) disposed on / above the semiconductor substrate provide voltages to the RRAM cell so that a forming voltage, a set voltage, and a reset voltage may be applied across the top electrode and the bottom electrode.

[0079] In some embodiments where the conductive filament is formed before storing data using the RRAM cell, the data storage structure may be or include an undoped metal oxide structure (e.g., undoped aluminum oxide (AlO x )). In such embodiments, the forming voltage may be relatively high. To improve device density and device performance, the feature size of one or more transistors and / or RRAM cells is continuously scaled down. However, as the feature size of one or more transistors is scaled down, the relatively high forming voltage becomes problematic (e.g., due to the reduced feature size of one or more transistors, thereby reducing the breakdown voltage). The relatively high forming voltage may be greater than the safe output voltage of the one or more transistors. Therefore, if one or more transistors are operated to output the relatively high forming voltage, the one or more transistors may be damaged and / or destroyed.

[0080] In some embodiments, the present application is directed to a RRAM cell with a low formation voltage. The RRAM cell includes a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode. The data storage structure includes a dielectric material (e.g., aluminum oxide (AlO)) doped with multiple dopants. x)). For example, the plurality of dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and / or a third dopant (e.g., hafnium). Because the data storage structure is doped with the first dopant, the second dopant, and / or the third dopant, the formation voltage of the RRAM cell may be improved (e.g., reduced) while maintaining good reliability of the RRAM cell. For example, doping the data storage structure with the first dopant may reduce or eliminate the formation voltage of the RRAM cell, doping the data storage structure with the second dopant may improve or maintain the reliability of the RRAM cell (e.g., good retention performance), and doping the data storage structure with the third dopant may reduce the current leakage path of the RRAM cell (e.g., good endurance performance). Therefore, an integrated chip including an RRAM cell may have one or more transistors with a scaled-down feature size, which safely provides a low formation voltage for the RRAM cell. This in turn helps to reduce the feature size of the RRAM cell and the one or more transistors and / or reduce the power consumption of the integrated chip while reducing damage to the RRAM cell and / or the one or more transistors.

[0081] Figure 1 Schematic diagram illustrating some embodiments of a memory device 100 including a memory cell 104 having a data storage structure 108 that is heavily doped and has a low formation voltage.

[0082] The memory device 100 includes a memory cell 104 electrically coupled to a transistor 102 so that the memory device 100 is in a one transistor-one resistive memory cell (1T1R) configuration. In some embodiments, the transistor 102 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET). The memory cell 104 includes a bottom electrode 106, a top electrode 112, a cap layer 110, and a data storage structure 108 disposed between the bottom electrode 106 and the top electrode 112. In some embodiments, the bottom electrode 106 is referred to as a lower conductive structure, and the top electrode 112 is referred to as an upper conductive structure. A bit line (BL) is electrically coupled to one end of the data storage structure 108 through the top electrode 112, and a source line (SL) is electrically coupled to the opposite end of the data storage structure 108 through the transistor 102. A word line (WL) is electrically coupled to the gate electrode of the transistor 102. Therefore, a suitable WL voltage is applied to the gate electrode of the transistor 102 to couple the memory cell 104 between BL and SL. Thus, in some embodiments, by providing appropriate bias conditions, the memory cell 104 can be switched between two states of resistance (a low resistance state and a high resistance state) to store data.

[0083] In some embodiments, the data storage structure 108 includes a dielectric material (eg, aluminum oxide (AlO) multi-doped with multiple dopants). x )). For example, the plurality of dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and / or a third dopant (e.g., hafnium). In some embodiments, the dielectric material may be a metal oxide. Thus, in various embodiments, the data storage structure 108 may include aluminum oxide, nitrogen, tantalum, and hafnium, and / or may have a thickness in a range of approximately 10 angstroms to 60 angstroms. In other embodiments, between approximately 5% and 10% of the chemical composition of the data storage structure 108 is the first dopant (e.g., nitrogen). In yet other embodiments, between approximately 12% and 18% of the chemical composition of the data storage structure 108 is the second dopant (e.g., tantalum). In some embodiments, between approximately 15% and 22% of the chemical composition of the data storage structure 108 is the third dopant (e.g., hafnium). In yet other embodiments, the data storage structure 108 may be referred to as a multi-dopant switching layer (MDSL). In some embodiments, the memory cell 104 may be configured as a resistive random access memory (RRAM) cell such that the data storage structure 108 includes a material having a variable resistance configured to undergo a reversible phase change between a high resistance state and a low resistance state.

[0084] In some embodiments, before the memory cell 104 can be used to store data, an initial conductive path (i.e., a conductive filament) is typically formed within the region 114 across the data storage structure 108. The formation of the initial conductive path makes subsequent write operations (which form the conductive path) easier to perform. In other embodiments, to form the initial conductive path, a forming voltage is applied across the top electrode 112 and the bottom electrode 106 through the transistor 102 and the BL. The initial conductive path may include vacancies (e.g., oxygen vacancies). In such embodiments, the forming voltage may knock out oxygen atoms of the lattice of the data storage structure 108, thereby forming local oxygen vacancies. These local vacancies tend to align with the region 114 to form an initial conductive path extending from the bottom electrode 106 to the cap layer 110 within the data storage structure 108. Thereafter, a set voltage or a reset voltage may be applied across the bottom electrode 106 and the top electrode 112 through the transistor 102 and the BL to change the resistivity of the data storage structure 108 between the high resistance state and the low resistance state.

[0085] In various embodiments, with the data storage structure 108 including a first dopant (e.g., nitrogen), the formation voltage may be reduced and / or eliminated. For example, in some embodiments, the formation of the initial conductive path may not be performed prior to the set operation of the memory cell 104 so that the formation voltage is not applied across the data storage structure 108 and / or the transistor 102. This in turn helps to reduce the feature size of the memory cell 104 and / or the transistor 102 while reducing damage to the memory cell 104 and / or the transistor 102. In some embodiments, the formation voltage may be equal to the set voltage. In other embodiments, with the data storage structure 108 including a second dopant (e.g., tantalum), the data retention of the memory cell 104 may be improved. In such embodiments, the second dopant has a strong bond with the oxygen atoms within the data storage structure 108, so that heat applied to the data storage structure 108 during the formation and / or operation of the data storage structure 108 may not destroy the strong bond between the second dopant and the oxygen atoms. In various embodiments, data retention of the memory cell 104 may be further improved with the data storage structure 108 including a first dopant (e.g., nitrogen) and a second dopant (e.g., tantalum). In yet further embodiments, endurance of the memory cell 104 may be improved with the data storage structure 108 including a third dopant (e.g., hafnium). In such embodiments, the third dopant is configured to reduce current leakage paths in the RRAM cell. In various embodiments, current leakage paths in the memory cell 104 are further reduced with the data storage structure 108 including a first dopant (e.g., nitrogen) and a third dopant (e.g., hafnium). Therefore, because the data storage structure 108 is multi-doped with the first dopant, the second dopant, and / or the third dopant, the formation voltage of the memory cell 104 may be improved (e.g., reduced or eliminated) while maintaining good data retention and good endurance of the memory cell 104.

[0086] Figure 2 Cross-sectional diagrams illustrating some embodiments of a memory device 200 including a memory cell 104 having a data storage structure 108 including a first dopant, a second dopant, and / or a third dopant.

[0087] In some embodiments, the memory device 200 includes an interconnect dielectric structure 216 and a substrate 202. In some embodiments, the substrate 202 may be, for example, or include a semiconductor body such as a single crystal silicon / CMOS bulk, silicon-germanium (SiGe), silicon-on-insulator (SOI), or another suitable semiconductor substrate material, and / or the substrate 202 may include a first doping type (e.g., p-type). The transistor 102 is disposed on / in the substrate 202. In some embodiments, the transistor 102 may be, for example, or include a metal oxide semiconductor field effect transistor (MOSFET), a high voltage transistor, a bipolar junction transistor (BTJ), an n-channel metal oxide semiconductor (nMOS) transistor, a p-channel metal oxide semiconductor (pMOS) transistor, or another suitable transistor. It should be understood that the transistor 102 configured as another semiconductor device is also within the scope of the present invention. In other embodiments, the transistor 102 may be configured, for example, as a gate-all-around FET (GAAFET), a gate-all-around FET, a multi-bridge channel FET (MBCFET), a nanowire FET, a nanoring FET, a nanosheet field-effect transistor (NSFET), or the like. In other embodiments, the transistor 102 may include source / drain regions 204, a gate dielectric layer 206, a gate electrode 208, and / or a sidewall spacer structure 210. The source / drain regions 204 may be disposed within the substrate 202 and / or may include a second doping type (e.g., n-type) opposite to the first doping type.

[0088] The lower inner connecting via 212 is disposed in the inner connecting dielectric structure 216 and overlies the source / drain region 204 of the transistor 102. In some embodiments, the inner connecting dielectric structure 216 may be, for example, or include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may be, for example, or include silicon oxide, a low-κ dielectric material, an extremely low-κ dielectric material, another suitable dielectric material, or any combination of the foregoing. As used herein, the low-κ dielectric material may be, for example, or include a dielectric material having a dielectric constant of less than about 3.9, 3, 2, or 1.5. The lower inner connecting wire 214 overlies the lower inner connecting via 212. In some embodiments, the lower inner connecting via 212 and the lower inner connecting wire 214 may be, for example, or include copper, aluminum, tungsten, ruthenium, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing. The bottom electrode via 218 is disposed in the interconnect dielectric structure 216 and overlies the lower interconnect wire 214. The top electrode via 220 overlies the bottom electrode via 218. The memory cell 104 is disposed in the interconnect dielectric structure 216 between the bottom electrode via 218 and the top electrode via 220. The upper interconnect via 222 is disposed on the top electrode via 220, and the upper interconnect wire 224 overlies the upper interconnect via 222.

[0089] In some embodiments, the memory cell 104 includes a bottom electrode 106, a cap layer 110, a top electrode 112, and a data storage structure 108 disposed between the bottom electrode 106 and the top electrode 112. During operation, the memory cell 104 relies on a redox reaction to form and release a conductive path 228 in a region 114 of the data storage structure 108 between the bottom electrode 106 and the cap layer 110. The presence of the conductive path 228 in the region 114 between the bottom electrode 106 and the cap layer 110 produces a low resistance state, while the absence of the conductive path 228 in the region 114 causes a high resistance state. Thus, the memory cell 104 can be switched between a high resistance state and a low resistance state by applying an appropriate bias to the memory cell 104 to create or release the conductive path 228 in the region 114. In further embodiments, the conductive path 228 may, for example, include an oxygen vacancy 226 disposed within the region 114 and extending between the bottom electrode 106 and the cap layer 110.

[0090] In some embodiments, the data storage structure 108 may include a multi-doped dielectric material such that the data storage structure 108 includes a dielectric material, a first dopant, a second dopant, and a third dopant. In some embodiments, the dielectric material may be, for example, or include a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), another dielectric material, or any combination of the foregoing. As used herein, a high-κ dielectric material may be, for example, or include a dielectric material having a dielectric constant greater than about 3.9, 9.34, 9.9, or 11.54. In some embodiments, the first dopant may be, for example, or include nitrogen, silicon, fluorine, or the like. It should be understood that first dopants including other elements are also within the scope of the present invention. In other embodiments, the second dopant may be, for example, or include tantalum, cerium, or the like. It should be understood that second dopants including other elements are also within the scope of the present invention. In yet other embodiments, the third dopant may be, for example, or include hafnium, zirconium, or the like. It should be understood that third dopants including other elements are also within the scope of the present invention. Therefore, in some embodiments, the data storage structure 108 may be, for example, or include aluminum oxide (e.g., Al2O3) doped with a first dopant, a second dopant, and a third dopant, wherein the first dopant, the second dopant, and the third dopant are each different from each other. In various embodiments, the first dopant may be configured to reduce the formation voltage of the data storage structure 108, the second dopant may be configured to improve the data retention of the data storage structure 108, and the third dopant is configured to improve the durability of the data storage structure 108, thereby improving the performance of the memory device 200.

[0091] In various embodiments, between about 5% and 10% of the chemical composition of the data storage structure 108 is the first dopant (e.g., nitrogen, silicon, fluorine, etc.). It should be understood that data storage structures 108 that include other chemical composition percentages of the first dopant are also within the scope of the present invention. In some embodiments, if the first dopant comprises a relatively small percentage of the chemical composition of the data storage structure 108 (e.g., less than about 5%), then the formation voltage of the memory cell 104 may not be reduced. In other embodiments, if the first dopant comprises a relatively large percentage of the chemical composition of the data storage structure 108 (e.g., greater than about 10%), then the endurance of the memory cell 104 may be reduced, thereby reducing the number of set operations and / or reset operations that can be performed on the data storage structure 108.

[0092] Additionally, in some embodiments, between about 12% and 18% of the chemical composition of the data storage structure 108 is the second dopant (e.g., tantalum, cerium, etc.). It should be appreciated that data storage structures 108 that include other chemical composition percentages of the second dopant are also within the scope of the present invention. In some embodiments, if the second dopant comprises a relatively small percentage of the chemical composition of the data storage structure 108 (e.g., less than about 12%), then the data retention of the memory cell 104 may not be improved. In other embodiments, if the second dopant comprises a relatively large percentage of the chemical composition of the data storage structure 108 (e.g., greater than about 18%), then the number of set operations and / or reset operations that can be performed on the data storage structure 108 is reduced.

[0093] In other embodiments, between about 15% and 22% of the chemical composition of the data storage structure 108 is the third dopant (e.g., hafnium, zirconium, etc.). It should be understood that data storage structures 108 including other chemical composition percentages of the third dopant are also within the scope of the present invention. In some embodiments, if the third dopant accounts for a relatively small percentage of the chemical composition of the data storage structure 108 (e.g., less than about 15%), then the endurance of the memory cell 104 may not be improved. In other embodiments, if the third dopant accounts for a relatively large percentage of the chemical composition of the data storage structure 108 (e.g., greater than about 22%), then the formation voltage of the data storage structure 108 may be increased.

[0094] Furthermore, in various embodiments, the chemical composition of the data storage structure 108 is between about 7% and 15% aluminum. It should be appreciated that data storage structures 108 including other chemical composition percentages of aluminum are also within the scope of the present invention. In some embodiments, the chemical composition of the data storage structure 108 is between about 38% and 48% oxygen. It should be appreciated that data storage structures 108 including other chemical composition percentages of oxygen are also within the scope of the present invention. In some embodiments, the data storage structure 108 includes a first atomic percentage of a first dopant, a second atomic percentage of a second dopant, a third atomic percentage of a third dopant, a fourth atomic percentage of aluminum, and a fifth atomic percentage of oxygen. In other embodiments, the first atomic percentage is less than the second atomic percentage and the second atomic percentage is less than the third atomic percentage. In yet other embodiments, the first atomic percentage may be in the range of about 5% to 10%, the second atomic percentage may be in the range of about 12% to 18%, the third atomic percentage may be in the range of about 15% to 22%, the fourth atomic percentage may be in the range of about 7% to 15%, and / or the fifth atomic percentage may be in the range of about 38% to 48%. It should be appreciated that the first atomic percentage to the fifth atomic percentage, including other values, respectively, are within the scope of the present invention. In various embodiments, the thickness of the data storage structure 108 is in the range of about 10 angstroms to 60 angstroms. It should be appreciated that the thickness of the data storage structure 108 having other values ​​is within the scope of the present invention. In other embodiments, if the thickness of the data storage structure 108 is relatively small (e.g., less than about 10 angstroms), high current leakage may occur between the bottom electrode 106 and the cap layer 110. In yet other embodiments, if the thickness of the data storage structure 108 is relatively large (e.g., greater than about 60 angstroms), the formation voltage of the memory cell 104 may increase. In various embodiments, the data storage structure 108 may, for example, consist of or consist essentially of a dielectric material, a compound of a first dopant, and a second dopant (e.g., AlTaON); a dielectric material, a compound of a first dopant, and a third dopant (e.g., AlHfON); a dielectric material, a compound of a first dopant, a second dopant, and a third dopant (e.g., AlTaHfON); or another suitable material.

[0095] In some embodiments, the bottom electrode via 218 and / or the top electrode via 220 may be, for example, copper, aluminum, tungsten, another suitable conductive material, or any combination of the foregoing. In some embodiments, the cap layer 110 may be, for example, tantalum, titanium, tantalum nitride, titanium nitride, any combination of the foregoing, or the like. In other embodiments, the bottom electrode 106 and / or the top electrode 112 may be, for example, titanium nitride, tantalum nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material, or any combination of the foregoing. Thus, in some embodiments, the cap layer 110 may include a first dopant (e.g., nitrogen) and / or a second dopant (e.g., tantalum). In other embodiments, the top electrode 112 and the bottom electrode 106 may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and / or a third dopant (e.g., hafnium), respectively.

[0096] Figures 3 to 5 illustrate Figure 1 and / or Figure 2 1 and 2. In some embodiments, the memory cell 104 is a cross-sectional view of some embodiments of different states of the memory cell 104 during operation of the memory cell 104. Figure 3 A first state 300 is illustrated in which the memory cell 104 is in a low resistance state (eg, storing logic "1"). In another embodiment, Figure 4 The second state 400 is illustrated, wherein the memory cell 104 is in a high resistance state (eg, storing a logic "0"). In yet another embodiment, Figure 5 A third state 500 is illustrated in which the memory cell 104 is in a low resistance state (eg, storing logic "1").

[0097] although Figures 3 to 5 The memory cells are described as having conductive paths formed by oxygen vacancies, but it should be understood that the disclosed data storage structures are not limited to memory cells having such paths. For example, in some embodiments, the data storage structures can be used in memory devices having conductive paths formed by conductive ions and oxygen vacancies or by conductive ions but not oxygen vacancies.

[0098] Figure 3 One embodiment of a first state 300 of a memory cell 104 is illustrated, wherein a forming operation is performed on the memory cell 104. The memory cell 104 includes a data storage structure 108, a bottom electrode 106, a top electrode 112, and a cap layer 110 (e.g., Figure 1 and / or Figure 2). In some embodiments, the cap layer 110 may include a metal layer 110a (e.g., including a metal material such as tantalum, tantalum nitride, titanium, titanium nitride, or the like) overlying a metal oxide layer 110b (e.g., including an oxide of a metal material). In some embodiments, during a forming operation, a forming voltage is applied across the bottom electrode 106 and the top electrode 112. In such embodiments, the forming voltage is configured to knock out oxygen atoms of the lattice of the data storage structure 108, and the metal oxide layer 110b is configured to receive oxygen atoms, thereby forming oxygen vacancies 226 in the data storage structure 108. The oxygen vacancies 226 tend to align within the region 114 of the data storage structure 108 to form a conductive path 228 (e.g., an initial conductive path) extending through the data storage structure 108. In some embodiments, the oxygen vacancies 226 are offset from a peripheral region 126p of the data storage structure 108, wherein the peripheral region 126p laterally surrounds the region 114. Therefore, after the forming operation, the memory cell 104 is in a low resistance state (e.g., storing logic "1"). In some embodiments, the formation voltage can be reduced and / or eliminated by including the first dopant (e.g., nitrogen) in the data storage structure 108. For example, in some embodiments, the formation voltage can be approximately equal to the set voltage of the memory cell 104 (e.g., see Figure 5 ) in order to eliminate the formation process and perform a set operation on the memory cell 104 to reach the first state 300. This in turn helps to reduce the feature size of the memory cell 104 while reducing damage to the memory cell 104.

[0099] Figure 4 One embodiment of a second state 400 of the memory cell 104 is illustrated, wherein a reset operation is performed on the memory cell 104. In some embodiments, during the reset operation, a reset voltage is applied across the bottom electrode 106 and the top electrode 112. In such embodiments, the reset voltage is configured to knock oxygen atoms from the metal oxide layer 110b to the middle region 404 of the data storage structure 108, thereby releasing the conductive path ( Figure 3The data storage structure 108 may be configured to store at least a portion of the conductive path 228 of the memory cell 104 so that the memory cell 104 is in a high resistance state (e.g., storing logic "0"). In another embodiment, the data storage structure 108 includes a lower region 402, an upper region 406, and an intermediate region 404 vertically disposed between the lower region 402 and the upper region 406. In various embodiments, after a reset operation is performed, the oxygen vacancies 226 may remain in the lower region 402 and the upper region 406, and at least most of the oxygen vacancies 226 may be removed from the intermediate region 404. With the data storage structure 108 including the first dopant (e.g., nitrogen), the second dopant (e.g., tantalum), and / or the third dopant (e.g., hafnium), the height h1 of the intermediate region 404 may be reduced, thereby reducing the set voltage and / or reset voltage and improving the switching efficiency of the memory cell 104. In further embodiments, the third dopant (e.g., hafnium) is configured to reduce current leakage paths in the data storage structure 108 when in the high resistance state, thereby improving discrete data states and endurance of the memory cell 104. For example, the third dopant may increase the energy level of oxygen vacancies within the data storage structure 108 so that oxygen atoms may more easily recombine in the data storage structure 108 during a reset operation, thereby reducing current leakage paths in the memory cell 104 when in the high resistance state.

[0100] Figure 5 An embodiment of a third state 500 of the memory cell 104 is illustrated, wherein a set operation is performed on the memory cell 104. In some embodiments, during the set operation, a set voltage is applied across the bottom electrode 106 and the top electrode 112. In further embodiments, the set voltage is configured to knock oxygen atoms from the middle region 404 of the data storage structure 108 to the metal oxide layer 110b, thereby forming a conductive path 228 in the region 114 of the data storage structure. As a result, the memory cell 104 is in a low resistance state (e.g., storing logic "1"). With the data storage structure 108 including the first dopant, the second dopant, and / or the third dopant, data retention and switching efficiency of the memory cell 104 can be improved.

[0101] In some embodiments, the data storage structure 108 including the first dopant (eg, nitrogen) and the second dopant (eg, tantalum) can significantly reduce the time required to complete the data storage structure. Figure 3The energy of the forming operation is such that the forming voltage is substantially equal to the set voltage. In such embodiments, the forming operation may be omitted and the set operation may be performed in place of the forming operation. In yet other embodiments, the forming voltage may be in a range of about 0% to 25% greater than the set voltage. In some embodiments, if the set voltage is about 2 volts (V), the forming voltage is less than about 2.5V. In some embodiments, the first dopant (e.g., nitrogen) may, for example, reduce the energy required to form oxygen vacancies 226 within the data storage structure 108, thereby improving the ability to form localized oxygen vacancies within the region 114. In further embodiments, data retention of the memory cell 104 may be improved by means of a data storage structure 108 including a second dopant (e.g., tantalum). In such embodiments, the second dopant has a strong bond with oxygen atoms within the data storage structure 108, such that the strong bond may not be destroyed by high heat (e.g., greater than about 250° C.) applied to the memory cell 104 during formation and / or operation of the memory cell 104. In some embodiments, the strong bonding between the second dopant and the oxygen atom may be greater than about 600 kilojoules per mole (kJ / mol). For example, if the second dopant is tantalum, the strong bonding between tantalum and oxygen may be in the range of about 800 kJ / mol to 845 kJ / mol. In further embodiments, the strong bonding between the second dopant (e.g., tantalum) and oxygen is greater than the bonding between the first dopant (e.g., nitrogen) and oxygen, and the bonding between the first dopant and oxygen is greater than the bonding between aluminum and oxygen. In some embodiments, the strong bonding between the second dopant and oxygen is greater than the bonding between the third dopant (e.g., hafnium) and oxygen. For example, the bonding between the third dopant and oxygen may be in the range of about 550 kJ / mol to 700 kJ / mol. Therefore, because the data storage structure 108 is multi-doped with the first dopant, the second dopant, and the third dopant, the formation voltage of the memory cell 104 can be improved (e.g., reduced or eliminated) while maintaining good data retention of the memory cell 104 and improving the switching performance of the memory cell 104.

[0102] Figure 6 Description corresponds to Figure 2 200, wherein the data storage structure 108 includes a data storage layer 604 overlying a multi-doped data storage layer 602. In addition, the conductive path (e.g., Figure 2The conductive path 228 of the multi-doped data storage layer 602 can be selectively generated or released in the region 114, wherein the region 114 extends continuously across the multi-doped data storage layer 602 and the data storage layer 604. In some embodiments, the data storage layer 604 can be, for example, or include undoped hafnium oxide, undoped tantalum oxide, another dielectric material, or any combination of the foregoing. In yet another embodiment, the multi-doped data storage layer 602 includes a dielectric material (e.g., aluminum oxide (AlO)) that is multi-doped with multiple dopants. x )). For example, the plurality of dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and a third dopant (e.g., hafnium). In various embodiments, the multi-doped data storage layer 602 may be, for example, or include: a dielectric material, a compound of a first dopant, and a second dopant (e.g., AlTaON); a dielectric material, a compound of a first dopant, and a third dopant (e.g., AlHfON); a dielectric material, a compound of a first dopant, a second dopant, and a third dopant (e.g., AlTaHfON); or another suitable material. Thus, in some embodiments, the multi-doped data storage layer 602 may include, for example, Figure 1 and / or Figure 2 The data storage layer 604 may be a dielectric material having the same chemical composition and / or multiple doping materials as described for the data storage structure 108 of FIG. 1 . In yet other embodiments, the data storage layer 604 may be, for example, or include, undoped hafnium oxide, undoped tantalum oxide, another dielectric material, or any combination thereof. In some embodiments, the data storage layer 604 may be free of the first dopant (e.g., nitrogen).

[0103] Figure 7 Description corresponds to Figure 2 1 and 1 , wherein the data storage structure 108 includes a first data storage layer 702, a second data storage layer 704, and a third data storage layer 706. In some embodiments, the first data storage layer 702 includes a first dielectric material (e.g., aluminum oxide) doped with a first dopant (e.g., nitrogen), the second data storage layer 704 includes a second dielectric material (e.g., hafnium oxide) doped with the first dopant, and / or the third data storage layer 706 includes a third dielectric material (e.g., tantalum oxide) doped with the first dopant. In other embodiments, the first dielectric material, the second dielectric material, and the third dielectric material each include a high-κ dielectric material (e.g., aluminum oxide, hafnium oxide, tantalum oxide, etc.) that is different from each other.

[0104] Figure 8 A cross-sectional view of some embodiments of an integrated chip 800 having a memory cell 104 disposed within an interconnect structure 812 overlying a substrate 202 is illustrated. In some embodiments, Figure 8The memory cell 104 is configured as Figure 1 , Figure 2 , Figure 6 or Figure 7 It should be appreciated that in some embodiments, the integrated chip 800 may include a plurality of memory cells 104 disposed in a memory array.

[0105] The integrated chip 800 includes a semiconductor device 806 disposed on a substrate 202. In some embodiments, the semiconductor device 806 may be a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BTJ), a high-electric-mobility transistor (HEMT), or any other front-end semiconductor device. In other embodiments, the semiconductor device 806 may include a gate dielectric layer 808, a gate electrode 810 overlying the gate dielectric layer 808, and a source / drain region pair 804a-b. The isolation structure 802 is disposed in the substrate 202 and is configured to electrically isolate the semiconductor device 806 from other devices (not shown) disposed in and / or on the substrate 202.

[0106] The interconnect structure 812 is disposed above the substrate 202 and the semiconductor device 806. In some embodiments, the interconnect structure 812 includes an interconnect dielectric structure 816, a plurality of conductive contacts 814, a plurality of conductive lines 818 (e.g., metal lines), and a plurality of vias 820 (e.g., metal through-holes). The plurality of conductive contacts 814, the plurality of conductive lines 818, and the plurality of vias 820 are electrically coupled in a predefined manner and configured to provide electrical connections between various devices disposed throughout the integrated chip 800. In other embodiments, the plurality of conductive contacts 814, the plurality of conductive lines 818, and / or the plurality of conductive wires 810 may be, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, another conductive material, or any combination thereof. In yet other embodiments, the interconnect dielectric structure 816 may include one or more ILD layers, which may include a low-κ dielectric material, an oxide (e.g., silicon dioxide), another dielectric material, or any combination thereof. In another embodiment, the memory cell 104 is disposed in an upper region of the interconnect structure 812 such that the memory cell 104 is directly above the plurality of conductive contacts 814 and / or directly above one or more layers of the conductive lines 818 and the vias 820. The memory cell 104 includes a bottom electrode 106, a data storage structure 108 multi-doped with a plurality of dopants, a cap layer 110, and a top electrode 112.

[0107] The first of the plurality of conductive lines 818 is denoted as 818wl and may be referred to as a word line. In some embodiments, the word line 818wl may be electrically coupled to the gate electrode 810 of the semiconductor device 806 via the interconnect structure 812. The second of the plurality of conductive lines 818 is denoted as 818sl and may be referred to as a source line. In other embodiments, the source line 818sl may be electrically coupled to the first source / drain region 804a of the semiconductor device 806 via the interconnect structure 812. The third of the plurality of conductive lines 818 is denoted as 818bl and may be referred to as a bit line. In yet other embodiments, the bit line 818bl may be electrically coupled to the top electrode 112 of the memory cell 104, and the bottom electrode 106 may be electrically coupled to the second source / drain region 804b of the semiconductor device 806 via the interconnect structure 812.

[0108] In some embodiments, the memory cell 104 is electrically coupled to the second source / drain region 804b of the semiconductor device 806 via the interconnect structure 812. Therefore, in some embodiments, applying a suitable word line voltage to the word line 818wl can electrically couple the memory cell 104 between the bit line 818bl and the source line 818sl. Therefore, by providing suitable bias conditions, the memory cell 104 can be switched between two data states.

[0109] Fig. 9 A cross-sectional view of some embodiments of an integrated chip 900 having a device gate stack 902 overlying a substrate 202 is illustrated. In some embodiments, the device gate stack 902 includes a memory cell 104 such that Fig. 9 The memory cell 104 may be referred to as a front-end resistive memory cell.

[0110] The device gate stack 902 is disposed on the substrate 202 and is laterally spaced between a pair of source / drain regions 804a-804b. In some embodiments, the device gate stack 902 includes a gate dielectric layer 808, a gate electrode 810, a data storage structure 108, and a top electrode 112. Thus, in various embodiments, the device gate stack 902 may include a memory cell 104 directly overlying the gate electrode 810. In some embodiments, the gate electrode 810 may be referred to as a bottom electrode. In some embodiments, the memory cell 104 includes a top electrode 112 and a data storage structure 108, wherein the data storage structure 108 includes a multi-doped data storage layer 602 and a data storage layer 604. In yet another embodiment, Fig. 9 The memory cell 104 is configured as Figure 1 , Figure 2 , Figure 6 or Figure 7 In yet another embodiment, the cap layer ( Figure 1The top cap layer 110 is disposed between the top electrode 112 and the data storage structure 108 (not shown). In some embodiments, the word line 818wl can be electrically coupled to the data storage structure 108 via the interconnect structure 812. Therefore, by providing appropriate bias conditions for the word line 818wl, the bit line 818bl and / or the source line 818sl, the data storage structure 108 can be switched between two data states.

[0111] In some embodiments, the gate dielectric layer 808 may be, for example, or include a high-κ dielectric material, an oxide (e.g., silicon dioxide), another dielectric material, or any combination thereof, and / or may have a thickness in the range of about 1,000 angstroms to 1,100 angstroms, or another suitable thickness value. In other embodiments, the gate electrode 810 may be, for example, or include ruthenium, aluminum, titanium nitride, tantalum nitride, another conductive material, or any combination thereof, and / or may have a thickness in the range of about 150 angstroms to 250 angstroms, or another suitable thickness value. In yet other embodiments, the multi-doped data storage layer 602 may be, for example, or include a dielectric material (e.g., aluminum oxide) multi-doped with a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and a third dopant (e.g., hafnium), and / or may have a thickness of about 13 angstroms, a thickness in the range of about 10 angstroms to 15 angstroms, or another suitable thickness value. In various embodiments, the data storage layer 604 may be, for example, or include hafnium oxide, tantalum oxide, hafnium and tantalum oxide, another high-κ dielectric material, or any combination thereof, and / or may have a thickness of about 30 angstroms, a thickness in the range of about 20 to 40 angstroms, or another suitable thickness value. In some embodiments, the multi-doped data storage layer 602 may include Al 0.10 Ta 0.17 Hf 0.20 O 0.46 N 0.06 , such that the atomic percentage of aluminum is about 10%, the atomic percentage of oxygen is about 46%, the atomic percentage of the first dopant (e.g., nitrogen) is about 6%, the atomic percentage of the second dopant (e.g., tantalum) is about 17%, and the atomic percentage of the third dopant (e.g., hafnium) is about 20%. It should be understood that the multi-doped data storage layer 602 including other atomic percentages of the aforementioned elements and / or dopants is also within the scope of the present invention.

[0112] The isolation structure 802 may be configured as a shallow trench isolation (STI) structure or another suitable isolation structure. In other embodiments, the isolation structure 802 may be, for example, or include silicon dioxide, silicon nitride, silicon carbide, another dielectric material, or any combination thereof. In some embodiments, the substrate 202 includes a first doping type (e.g., p-type), and the pair of source / drain regions 804a-804b includes a second doping type (e.g., n-type) opposite to the first doping type.

[0113] Figure 10 to Figure 14 Cross-sectional views 1000 to 1400 illustrate some embodiments of a method for forming a memory cell according to the present invention, the memory cell having a data storage structure multi-doped with a first dopant, a second dopant, and / or a third dopant. Figure 10 to Figure 14 1000 to 1400, but it should be understood that Figure 10 to Figure 14 The structure shown in FIG. 1 is not limited to the method but can be independent of the method. Figure 10 to Figure 14 Described as a series of actions, it should be understood that these actions are not limiting, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted completely or partially.

[0114] like Fig.101000, a lower interlayer dielectric (ILD) layer 1002 is formed above a substrate 202, and a lower interconnect 214 is formed in the lower ILD layer 1002. In some embodiments, the lower ILD layer 1002 may be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. In other embodiments, the lower interconnect 214 may be formed by a single damascene process, a dual damascene process, or another suitable formation process. In some embodiments, the substrate 202 may be, for example, or include a semiconductor body, such as a single crystal silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), or another suitable semiconductor substrate material, and / or the substrate 202 may include a first doping type (e.g., p-type). In various embodiments, the lower interconnect 214 may be, for example, or include aluminum, copper, ruthenium, titanium nitride, tantalum nitride, another conductive material, or any combination thereof. In some embodiments, the lower ILD layer 1002 may be, for example, or include a low-κ dielectric material, an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination thereof.

[0115] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , the bottom electrode 106 is formed above the lower interconnect 214 and the data storage structure 108 is formed above the bottom electrode 106. In some embodiments, the bottom electrode 106 and / or the data storage structure 108 may be formed by, for example, CVD, PVD, ALD, sputtering, co-sputtering, electroless plating, electroplating, or another suitable growth or deposition process.

[0116] In some embodiments, the data storage structure 108 is formed in a manner such that the data storage structure 108 includes a dielectric material (e.g., aluminum oxide (e.g., Al2O3)) that is multi-doped with a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and / or a third dopant (e.g., hafnium). In some embodiments, the dielectric material may, for example, be or include a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide, hafnium oxide, another suitable dielectric material, or any combination of the foregoing. In some embodiments, the first dopant may, for example, be or include nitrogen, silicon, fluorine, or the like. In other embodiments, the second dopant may, for example, be or include tantalum, cerium, or the like. In yet other embodiments, the third dopant may, for example, be or include hafnium, zirconium, or the like. In addition, the data storage structure 108 may, for example, be formed such that the data storage structure 108 includes a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, a third atomic percentage of the third dopant, a fourth atomic percentage of aluminum, and a fifth atomic percentage of oxygen. In yet other embodiments, the first atomic percentage may be in the range of approximately 5% to 10%, the second atomic percentage may be in the range of approximately 12% to 18%, the third atomic percentage may be in the range of approximately 15% to 22%, the fourth atomic percentage may be in the range of approximately 7% to 15%, and / or the fifth atomic percentage may be in the range of approximately 38% to 48%.

[0117] In addition, a process for forming the data storage structure 108 may include: depositing a compound (e.g., the compound includes a dielectric material (e.g., aluminum oxide), a second dopant (e.g., tantalum), and a third dopant (e.g., hafnium)) by a deposition process (e.g., CVD, PVD, ALD, sputtering, co-sputtering, etc.), while exposing the compound to a first dopant (e.g., nitrogen) so that the data storage structure 108 includes a multi-doped dielectric material (e.g., aluminum oxide multi-doped with a first dopant, a second dopant, and a third dopant). In yet another embodiment, the data storage structure 108 may be formed in a processing chamber, wherein the processing chamber is heated to a temperature of about 250° C. to 300° C. during the formation of the data storage structure 108. In yet another embodiment, the data storage structure 108 is formed at a thickness in a range of about 10 angstroms to 60 angstroms. In various embodiments, the data storage structure 108 may be formed, for example, so that it includes a compound of a dielectric material, a first dopant, and a second dopant (e.g., AlTaON); a compound of a dielectric material, a first dopant, and a third dopant (e.g., AlHfON); a compound of a dielectric material, a first dopant, a second dopant, and a third dopant (e.g., AlTaHfON); or another suitable material.

[0118] Additionally, another process for forming the data storage structure 108 may include performing a co-sputtering process to deposit a compound including aluminum oxide, a second dopant, and a third dopant (e.g., co-sputtering aluminum oxide, tantalum oxide, and hafnium dioxide) in a plasma environment, wherein the plasma includes, for example, nitrogen (e.g., N2). In further embodiments, a process for forming the data storage structure 108 may include performing a CVD process or an ALD process to deposit a compound including aluminum oxide, tantalum oxide, and hafnium dioxide in a plasma environment, wherein the plasma includes N2 or NH3. In yet further embodiments, a process for forming the data storage structure 108 may include performing a CVD process or an ALD process to form a material (e.g., aluminum oxide) in a chamber using a first precursor, a second precursor, and / or a third precursor, wherein the first precursor ensures that the material is doped with a first dopant, the second precursor ensures that the material is doped with a second dopant, and the third precursor ensures that the material is doped with a third dopant. In some embodiments, the first precursor may be, for example, or include (NH4)OH or another suitable precursor. In other embodiments, the second precursor may be, for example, or include TaCl5, Ta(OC2H5)5, or another suitable precursor. In yet other embodiments, the third precursor may be, for example, or include HfCl4 or another suitable precursor.

[0119] like Fig.12 As illustrated in the cross-sectional view 1200 of FIG. 1 , a cap layer 110 is formed over the data storage structure 108 and a top electrode 112 is formed over the cap layer 110, thereby forming a memory cell layer stack 1202 over the lower interconnect wire 214. In some embodiments, the memory cell layer stack 1202 includes a bottom electrode 106, a data storage structure 108, a cap layer 110, and a top electrode 112. In other embodiments, the cap layer 110 and / or the top electrode 112 may be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, electroplating, or another suitable deposition or growth process, respectively. Subsequently, a mask layer 1204 is formed over the memory cell layer stack 1202. In some embodiments, the mask layer 1204 covers the middle region of the memory cell layer stack 1202 and exposes the peripheral region of the memory cell layer stack 1202.

[0120] like Fig.13 As shown in the cross-sectional view 1300, according to the mask layer ( Fig.12 1204) in the memory cell layer stack ( Fig.12 1202), thereby forming the memory cell 104. In some embodiments, the patterning process may include: stacking the memory cell layer ( Fig.121202) unmasked area is exposed to one or more etchants; and a removal process (not shown) is performed to remove the mask layer ( Fig.12 1204).

[0121] like Fig.14 As illustrated in the cross-sectional view 1400 of FIG. 1 , an upper ILD layer 1402 is formed above and around the memory cell 104, an upper interconnecting via 222 is formed above the memory cell 104, and an upper interconnecting wire 224 is formed above the upper interconnecting via 222. In some embodiments, the upper ILD layer 1402 may be formed, for example, by PVD, CVD, ALD, or another suitable deposition or growth process. In other embodiments, the upper interconnecting via 222 and / or the upper interconnecting wire 224 may be formed, for example, by a single damascene process, a dual damascene process, or another suitable formation process, respectively. In some embodiments, the upper ILD layer 1402 may be, for example, or include a low-κ dielectric material, an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination thereof. In various embodiments, the upper interconnecting via 222 and the upper interconnecting wire 224 may be, for example, or include aluminum, copper, ruthenium, titanium nitride, tantalum nitride, another conductive material, or any combination thereof, respectively.

[0122] Fig.15 A method 1500 for forming a memory cell according to the present invention is described, wherein the memory cell has a data storage structure that is multi-doped with a first dopant, a second dopant, and / or a third dopant. Although method 1500 is described and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions described. Therefore, in some embodiments, the actions may be performed in a different order than described, and / or may be performed simultaneously. In addition, in some embodiments, the described actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the described actions or events may be omitted, and other undescribed actions or events may be included.

[0123] At act 1502, a lower conductive wire is formed over a substrate. Fig.10 Cross-sectional diagram 1000 is illustrated corresponding to some embodiments of act 1502 .

[0124] At act 1504, a bottom electrode is formed over the lower conductive wire. Fig.11 Cross-sectional view 1100 is illustrated corresponding to some embodiments of act 1504 .

[0125] At act 1506, a data storage structure is formed over the bottom electrode, wherein the data storage structure includes a multi-doped dielectric material including a first dopant, a second dopant, and / or a third dopant. Fig.11 Cross-sectional view 1100 is illustrated corresponding to some embodiments of act 1506 .

[0126] At act 1508, a cap layer is formed over the data storage structure and a top electrode is formed over the cap layer. Fig.12 Cross-sectional view 1200 is illustrated corresponding to some embodiments of act 1508 .

[0127] At act 1510, the top electrode, the cap layer, the data storage structure, and the bottom electrode are patterned, thereby forming a memory cell. Fig.13 Cross-sectional view 1300 is illustrated corresponding to some embodiments of act 1510 .

[0128] At act 1512, an upper via and an upper conductive wire are formed over the memory cell. Fig.14 Cross-sectional view 1400 is illustrated corresponding to some embodiments of act 1512 .

[0129] Fig.16 A method 1600 for forming an integrated chip according to the present invention is described, wherein the integrated chip includes a front-end process resistive memory cell having a data storage structure that is multi-doped with a first dopant, a second dopant, and / or a third dopant. Although method 1600 is described and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions described. Therefore, in some embodiments, the actions may be performed in a different order than described, and / or may be performed simultaneously. In addition, in some embodiments, the described actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the described actions or events may be omitted, and other undescribed actions or events may be included.

[0130] At act 1602, an isolation structure is formed in a substrate.

[0131] In some embodiments, the isolation structure may be substantially Fig. 9 In another embodiment, a process for forming an isolation structure may include: patterning Fig. 9 The method comprises depositing a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, or the like) in the isolation structure opening (e.g., by PVD, CVD, ALD, etc.); and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the dielectric material to define an isolation structure.

[0132] At act 1604, a gate dielectric layer is formed over the substrate and a gate electrode is formed over the gate dielectric layer.

[0133] In some embodiments, the gate dielectric layer may be substantially Fig. 9 The gate dielectric layer 808 is similar to that of FIG. 8 , and the gate electrode may be substantially the same as Fig. 9 The gate electrode 810 is similar to the gate electrode 810. In other embodiments, the gate dielectric layer and the gate electrode may be deposited by CVD, PVD, ALD, electroplating, electroless plating or another suitable deposition or growth process, respectively.

[0134] At act 1606, a data storage structure is formed over the gate electrode, wherein the data storage structure includes a multi-doped dielectric material including a first dopant, a second dopant, and / or a third dopant.

[0135] In some embodiments, the data storage structure may be substantially similar to Fig. 9 108, wherein the data storage structure includes a multi-doped data storage layer 602 and a data storage layer 604. In another embodiment, a process for forming a data storage structure may include depositing a multi-doped data storage layer over a gate electrode, and depositing a data storage layer over the multi-doped data storage layer. In some embodiments, the multi-doped data storage layer may be deposited substantially as described above with respect to Fig.11 The data storage structure 108 is formed over the gate electrode by a process similar to the process of forming the data storage structure 108. In other embodiments, the data storage layer can be formed over the multi-doped data storage layer by, for example, CVD, PVD, ALD, co-sputtering, or another suitable deposition or growth process.

[0136] At action 1608, a cap layer is formed over the data storage structure, and a top electrode is formed over the cap layer. In some embodiments, the cap layer and the top electrode may be formed substantially as described above with respect to Fig.12 The top cap layer 110 and the top electrode 112 are formed by a similar process to that formed over the data storage structure.

[0137] At act 1610, a top electrode, a cap layer, a data storage structure, a gate electrode, and a gate dielectric layer are patterned, thereby forming a device gate stack over the substrate.

[0138] In some embodiments, the device gate stack may be substantially similar to Fig. 9 In another embodiment, the device gate stack 902 can be substantially the same as described above. Fig.13 The device gate stack is patterned using a process similar to the patterning process.

[0139] At act 1612, a pair of source / drain regions are formed in the substrate and on opposite sides of the gate dielectric layer.

[0140] In some embodiments, a pair of source / drain regions may be substantially Fig. 9 In other embodiments, a process for forming a pair of source / drain regions may include selectively doping the substrate with a second doping type (eg, n-type).

[0141] At act 1614, an interconnect structure is formed over the substrate.

[0142] In some embodiments, the interconnect structure may be substantially similar to Fig. 9 In such embodiments, the interconnect dielectric structure 816 may be formed by one or more deposition processes (e.g., CVD, PVD, ALD, etc.), and the conductive contacts 814, the conductive lines 818, and / or the vias 820 may be formed by a single damascene process, a dual damascene process, or another suitable formation process, respectively.

[0143] Therefore, in some embodiments, the present invention relates to a memory cell, which includes a top electrode, a bottom electrode, and a data storage structure arranged between the top electrode and the bottom electrode, wherein the data storage structure includes a dielectric material multi-doped with a first dopant, a second dopant and / or a third dopant.

[0144] In some embodiments, the present application provides a memory device comprising: a substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a dielectric material doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant.

[0145] In some embodiments, the dielectric material further includes a third dopant different from the first dopant and the second dopant. In some embodiments, the dielectric material includes aluminum oxide, the first dopant includes nitrogen, the second dopant includes tantalum, and the third dopant includes hafnium. In some embodiments, the dielectric material includes a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, and a third atomic percentage of the third dopant, wherein the first atomic percentage is less than the second atomic percentage, and the second atomic percentage is less than the third atomic percentage. In some embodiments, the first atomic percentage is in a range of about 5% to 10%, the second atomic percentage is in a range of about 12% to 18%, and the third atomic percentage is in a range of about 15% to 22%. In some embodiments, the data storage structure includes a data storage layer and a multi-doped data storage layer, wherein the multi-doped data storage layer includes the dielectric material doped with the first dopant and the second dopant, and wherein the data storage layer includes an undoped metal oxide. In some embodiments, the data storage layer does not contain the first dopant. In some embodiments, the memory device further comprises: a gate dielectric layer overlying the substrate; and a pair of source / drain regions disposed in the substrate and on opposite sides of the gate dielectric layer; wherein the bottom electrode is disposed between the gate dielectric layer and the data storage structure, wherein opposite sidewalls of the gate dielectric layer are aligned with opposite sidewalls of the data storage structure. In some embodiments, the top electrode comprises the first dopant and / or the second dopant.

[0146] In some embodiments, the present application provides an integrated chip comprising a substrate and a resistive random access memory (RRAM) cell overlying the substrate, wherein the RRAM cell comprises a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a first high-κ dielectric material and a plurality of dopants, wherein the plurality of dopants comprise a first dopant, a second dopant, and a third dopant that are respectively different from each other.

[0147] In some embodiments, the data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer, wherein the first data storage layer includes the first high-κ dielectric material doped with the first dopant, the second data storage layer includes the second high-κ dielectric material doped with the first dopant, and the third data storage layer includes the third high-κ dielectric material doped with the first dopant. In some embodiments, the second high-κ dielectric material includes the second dopant, and the third high-κ dielectric material includes the third dopant. In some embodiments, the data storage structure includes a data storage layer and a multi-doped data storage layer, wherein the multi-doped data storage layer includes the first high-κ dielectric material doped with the plurality of dopants, and wherein the data storage layer includes the second high-κ dielectric material. In some embodiments, the thickness of the multi-doped data storage layer is less than the thickness of the data storage layer. In some embodiments, the integrated chip further includes: a cap layer disposed between the top electrode and the data storage structure, wherein the cap layer includes the first dopant and / or the second dopant. In some embodiments, the opposite sidewalls of the top electrode, the opposite sidewalls of the data storage structure, and the opposite sidewalls of the bottom electrode are aligned, respectively.

[0148] In some embodiments, the present application provides a method for forming a memory device, the method comprising: depositing a bottom electrode above a substrate; depositing a data storage structure above the bottom electrode so that the data storage structure includes a dielectric material doped with a first dopant, a second dopant, and a third dopant; depositing a top electrode above the data storage structure; and patterning the bottom electrode, the data storage structure, and the top electrode, thereby forming a memory cell above the substrate.

[0149] In some embodiments, the data storage structure includes a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, and a third atomic percentage of the third dopant, wherein the first atomic percentage is less than the second atomic percentage and the second atomic percentage is less than the third atomic percentage. In some embodiments, the method for forming a memory device further includes: forming a gate dielectric layer above the substrate, wherein the gate dielectric layer is disposed between the bottom electrode and the substrate, wherein opposite sidewalls of the gate dielectric layer are aligned with opposite sidewalls of the data storage structure; and forming a pair of source / drain regions in the substrate and on opposite sides of the gate dielectric layer. In some embodiments, the dielectric material includes aluminum oxide, the first dopant includes nitrogen, the second dopant includes tantalum, and the third dopant includes hafnium.

[0150] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A resistive random access memory device, comprising: substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; as well as A data storage structure is disposed between the top electrode and the bottom electrode, in, The data storage structure includes a dielectric material doped with a first dopant and a second dopant, the first dopant being different from the second dopant, the first dopant being selected from any one of the group consisting of nitrogen, silicon, and fluorine, and the second dopant being selected from any one of the group consisting of tantalum and cerium, The dielectric material includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, the first atomic percentage being in a range of 5% to 10% and the second atomic percentage being in a range of 12% to 18%, and The top electrode includes the first dopant and / or the second dopant. 2 . The RRAM device of claim 1 , wherein the dielectric material further comprises a third dopant different from the first dopant and the second dopant, the third dopant being selected from any one of the group consisting of hafnium and zirconium. 3 . The RRAM device of claim 2 , wherein the dielectric material comprises aluminum oxide, the first dopant comprises nitrogen, the second dopant comprises tantalum, and the third dopant comprises hafnium. 4 . The RRAM device of claim 2 , wherein the dielectric material comprises a third atomic percentage of the third dopant, wherein the second atomic percentage is less than the third atomic percentage. 5 . The RRAM device of claim 4 , wherein the third atomic percentage is in a range of 15% to 22%.

6. A resistive random access memory device according to claim 1, wherein the data storage structure includes a data storage layer and a multi-doped data storage layer, wherein the multi-doped data storage layer includes the dielectric material doped with the first dopant and the second dopant, and wherein the data storage layer includes an undoped metal oxide. 7 . The RRAM device according to claim 6 , wherein the data storage layer does not contain the first dopant. 8 . The RRAM device of claim 6 , wherein opposite sidewalls of the multi-doped data storage layer, opposite sidewalls of the data storage layer, and opposite sidewalls of the top electrode are aligned, respectively.

9. The resistance random access memory device according to claim 1, further comprising: a gate dielectric layer overlying the substrate; as well as a pair of source / drain regions disposed in the substrate and on opposite sides of the gate dielectric layer; The bottom electrode is disposed between the gate dielectric layer and the data storage structure, wherein opposite sidewalls of the gate dielectric layer are aligned with opposite sidewalls of the data storage structure.

10. An integrated chip, comprising: substrate; as well as a resistive random access memory cell overlying the substrate, in, The resistance random access memory cell includes a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode. The data storage structure includes a first high-κ dielectric material and a plurality of dopants, The plurality of dopants include a first dopant, a second dopant, and a third dopant that are different from each other, the first dopant is selected from any one of the group consisting of nitrogen, silicon, and fluorine, the second dopant is selected from any one of the group consisting of tantalum and cerium, and the third dopant is selected from any one of the group consisting of hafnium and zirconium, A first concentration of the first dopant, a second concentration of the second dopant, and a third concentration of the third dopant in the first high-κ dielectric material are respectively different from each other, the first concentration is in a range of 5% to 10%, the second concentration is in a range of 12% to 18%, and the third concentration is in a range of 15% to 22%, and The top electrode includes the first dopant and / or the second dopant.

11. An integrated chip according to claim 10, wherein the data storage structure comprises a first data storage layer, a second data storage layer and a third data storage layer, wherein the first data storage layer comprises the first high-κ dielectric material doped with the first dopant, the second data storage layer comprises the second high-κ dielectric material doped with the first dopant, and the third data storage layer comprises the third high-κ dielectric material doped with the first dopant. 12 . The integrated chip of claim 11 , wherein the second high-κ dielectric material comprises the second dopant, and the third high-κ dielectric material comprises the third dopant.

13. The integrated chip of claim 10, wherein the data storage structure comprises a dielectric switching layer and a multi-doped data storage layer, wherein the multi-doped data storage layer comprises the first high-κ dielectric material doped with the plurality of dopants, and wherein the dielectric switching layer comprises a second high-κ dielectric material.

14. The integrated chip according to claim 13, wherein a thickness of the multi-doped data storage layer is smaller than a thickness of the dielectric switching layer.

15. The integrated chip of claim 13, wherein the multi-doped data storage layer directly contacts the bottom electrode, and wherein the dielectric switching layer directly contacts a top surface of the multi-doped data storage layer.

16. The integrated chip according to claim 10, further comprising: A cap layer is disposed between the top electrode and the data storage structure, wherein the cap layer includes the first dopant and / or the second dopant. 17 . The integrated chip according to claim 10 , wherein opposite sidewalls of the top electrode, opposite sidewalls of the data storage structure, and opposite sidewalls of the bottom electrode are respectively aligned.

18. A method for forming a resistive random access memory device, the method comprising: depositing a bottom electrode over the substrate; depositing a data storage structure over the bottom electrode such that the data storage structure includes a dielectric material doped with a first dopant, a second dopant, and a third dopant; depositing a top electrode over the data storage structure; as well as performing a patterning process on the bottom electrode, the data storage structure, and the top electrode, thereby forming a memory cell above the substrate, in, The first dopant is selected from any one of the group consisting of nitrogen, silicon and fluorine, the second dopant is selected from any one of the group consisting of tantalum and cerium, and the third dopant is selected from any one of the group consisting of hafnium and zirconium, The data storage structure includes a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, and a third atomic percentage of the third dopant, the first atomic percentage is in a range of 5% to 10%, the second atomic percentage is in a range of 12% to 18%, and the third atomic percentage is in a range of 15% to 22%, and The top electrode includes the first dopant and / or the second dopant.

19. The method for forming a resistive random access memory device according to claim 18, wherein the second atomic percentage is less than the third atomic percentage.

20. The method for forming a resistive random access memory device according to claim 18, further comprising: forming a gate dielectric layer over the substrate, wherein the gate dielectric layer is disposed between the bottom electrode and the substrate, wherein opposite sidewalls of the gate dielectric layer are aligned with opposite sidewalls of the data storage structure; and A pair of source / drain regions are formed in the substrate and on opposite sides of the gate dielectric layer.

21. The method for forming a resistive random access memory device of claim 18, wherein the dielectric material comprises aluminum oxide, the first dopant comprises nitrogen, the second dopant comprises tantalum, and the third dopant comprises hafnium.

22. An integrated chip, comprising: a bottom electrode overlying a substrate; a top electrode overlying the bottom electrode; A data storage layer disposed between the top electrode and the bottom electrode; as well as a multi-doped data storage layer disposed between the bottom electrode and the data storage layer, in, The multi-doped data storage layer includes a dielectric material doped with a first dopant and a second dopant, the first dopant being selected from any one of the group consisting of nitrogen, silicon, and fluorine, and the second dopant being selected from any one of the group consisting of tantalum and cerium, The dielectric material includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, the first atomic percentage is in a range of 5% to 10%, and the second atomic percentage is in a range of 12% to 18%, The top electrode includes the first dopant and / or the second dopant, and The conductive path is selectively engenderable and at least partially de-engenderable in a region extending continuously from the bottom surface of the multi-doped data storage layer to the top surface of the data storage layer.

23. The integrated chip of claim 22, wherein when the conductive path is at least partially released, a portion of the conductive path remains along a bottom surface of the multi-doped data storage layer and remains along a top surface of the data storage layer.

24. The integrated chip according to claim 22, further comprising: A cap layer is disposed between the data storage layer and the top electrode.

25. The integrated chip of claim 24, wherein the multi-doped data storage layer directly contacts the bottom electrode, and wherein the data storage layer directly contacts the cap layer.

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