Socket for semiconductor package and semiconductor package

Abstract

The present invention provides a socket for a semiconductor package having a metal block shaped to be integrally formed with a via ring. It has: a via ring; a first metal block integrally formed with the via ring and protruding on the upper surface of the via ring, and being substantially U-shaped when viewed from the normal direction of the upper surface of the via ring; a first lead penetrating the via ring from the upper surface side to the lower surface side and hermetically joined in a first through hole; a first substrate having a surface formed with a first signal pattern electrically connected to the first lead and a back surface opposite to the surface, and the back surface side being fixed to a first end surface of the first metal block; a second lead penetrating the via ring from the upper surface side to the lower surface side and hermetically joined in a second through hole; and a second substrate having a surface formed with a second signal pattern electrically connected to the second lead and a back surface opposite to the surface, and the back surface side being fixed to a second end surface of the first metal block.

Description

Technical Field

[0001] The present invention relates to a socket for semiconductor packaging and a semiconductor package. Background Art

[0002] There are various types of light-emitting elements. For example, electro-absorption modulator integrated with DFB laser (EML) and directly modulated laser (DML) are known. These light-emitting elements are used, for example, in optical communication.

[0003] In these light-emitting elements, in order to stabilize the oscillation wavelength, a Peltier element as a temperature regulator is sometimes mounted in the package. In this case, since the Peltier element is mounted, the length of the transmission line in the package becomes long, and thus a relay substrate considering transmission loss and a metal block for holding the relay substrate are required, and these components are arranged on the via ring.

[0004] <Prior Art Documents>

[0005] <Patent Documents>

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2011-108939 Summary of the Invention

[0007] <Problems to be Solved by the Invention>

[0008] The metal block for holding the relay substrate can be separately manufactured from the via ring and joined to the via ring by solder or the like, but from the viewpoint of improving productivity and the like, it is preferably integrally formed with the via ring by stamping or the like. However, since the above metal block protrudes above the via ring, it is sometimes difficult to integrally form the metal block with the via ring by stamping or the like depending on the shape of the metal block.

[0009] The present invention has been made in view of the above points, and an object thereof is to provide a socket for semiconductor packaging having a metal block with a shape capable of being integrally formed with a via ring.

[0010] <Means for Solving the Problems>

[0011] The socket for semiconductor packaging has: a hole ring; a first metal block, which is integrally formed with the above hole ring and protrudes on the upper surface of the above hole ring, and is substantially U-shaped when viewed from the normal direction of the upper surface of the above hole ring; a first lead, which penetrates the above hole ring from the upper surface side to the lower surface side and is hermetically joined in the first through hole; a first substrate, which has a surface formed with a first signal pattern electrically connected to the above first lead and a back surface opposite to the above surface, and the back surface side is fixed to the first end surface of the above first metal block; a second lead, which penetrates the above hole ring from the upper surface side to the lower surface side and is hermetically joined in the second through hole; and a second substrate, which has a surface formed with a second signal pattern electrically connected to the above second lead and a back surface opposite to the above surface, and the back surface side is fixed to the second end surface of the above first metal block.

[0012] <Effects of the Invention>

[0013] According to the disclosed technology, it is possible to provide a socket for semiconductor packaging having a metal block with a shape that can be integrally formed with a hole ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. is a perspective view (one) of a socket for semiconductor packaging showing a first embodiment by way of example.

[0015] Figure 2 FIG. is a perspective view (two) of a socket for semiconductor packaging showing a first embodiment by way of example.

[0016] Figure 3 FIG. is a top view of a socket for semiconductor packaging showing a first embodiment by way of example.

[0017] Figure 4 FIG. is a perspective view (one) of a semiconductor package showing a first embodiment by way of example.

[0018] Figure 5 FIG. is a perspective view (two) of a semiconductor package showing a first embodiment by way of example.

[0019] Figure 6 FIG. is a top view of a semiconductor package showing a first embodiment by way of example.

[0020] Figure 7 FIG. is a perspective view of a socket for semiconductor packaging showing a comparative example by way of example.

[0021] Figure 8 FIG. is a perspective view of a socket for semiconductor packaging showing a first modification example 1 by way of example.

[0022] Figure 9 FIG. is a perspective view of a semiconductor package showing a first modification example 1 by way of example.

[0023] Figure 10 It is a top view of a semiconductor package showing a modification 1 of the first embodiment by way of example.

[0024] Description of reference numerals:

[0025] 1, 1A Socket for semiconductor package

[0026] 2, 2A Semiconductor package

[0027] 10 Hole ring

[0028] 10a Upper surface

[0029] 10b Lower surface

[0030] 21, 21M First metal block

[0031] 21a, 21b, 22a Substrate fixing surface

[0032] 22, 22M Second metal block

[0033] 31 First substrate

[0034] 31G, 32G, 33G Ground pattern

[0035] 31S, 32S, 33S1, 33S2 Signal pattern

[0036] 32 Second substrate

[0037] 33 Third substrate

[0038] 41 First lead

[0039] 42 Second lead

[0040] 43 Third lead

[0041] 44 Fourth lead

[0042] 45 Fifth lead

[0043] 46 Sixth lead

[0044] 50 Sealing portion

[0045] 60 Light-emitting element

[0046] 70 Peltier element

[0047] 80 Linear component

[0048] 100 Cover

[0049] 110 Transparent component

[0050] Side wall portions 211, 212

[0051] Connecting portion 213

[0052] Recessed portion 214 Detailed implementation mode

[0053] Hereinafter, a mode for implementing the invention will be described with reference to the accompanying drawings. It should be noted that in the respective drawings, the same reference numerals are given to the same components, and repeated descriptions may sometimes be omitted.

[0054] (First Embodiment)

[0055] Figure 1 FIG. 1 is a perspective view (one) of a socket for a semiconductor package showing a first embodiment, and is a view of the socket for a semiconductor package as viewed from the surface side of the first substrate and the second substrate. Figure 2 FIG. 2 is a perspective view (two) of a socket for a semiconductor package showing a first embodiment, and is a view of the socket for a semiconductor package as viewed from the back side of the first substrate and the second substrate. Figure 3 FIG. 3 is a top view of a socket for a semiconductor package showing a first embodiment.

[0056] Refer to Figures 1 to 3 , the socket 1 for a semiconductor package according to the first embodiment includes: a hole ring 10; a first metal block 21; a second metal block 22; a first substrate 31; a second substrate 32; a first lead 41; a second lead 42; a third lead 43; a fourth lead 44; a fifth lead 45; a sixth lead 46; and a sealing portion 50. The socket 1 for a semiconductor package can be used, for example, as a socket for a directly modulated laser (DML).

[0057] The hole ring 10 is a disk-shaped component. The diameter of the hole ring 10 is not particularly limited and can be appropriately determined according to the purpose. For example, it can be φ3.8 mm, φ5.6 mm, etc. The thickness of the hole ring 10 is not particularly limited and can be appropriately determined according to the purpose. For example, it can be about 1.0 to 1.5 mm. The hole ring 10 can be formed of a metal material such as iron that can be stamped.

[0058] It should be noted that in the present application, "disk-shaped" means that the top view shape is substantially circular and has a specified thickness. The size of the thickness relative to the diameter is not limited. In addition, being partially formed with recesses, protrusions, through holes, etc. is also included. In addition, in the present application, "top view" means observing the object from the normal direction of the upper surface 10a of the hole ring 10, and the top view shape means the shape of the object observed from the normal direction of the upper surface 10a of the hole ring 10.

[0059] On the outer edge portion of the hole ring 10, in a plan view, one or more notch portions having a concave shape can be formed from the outer peripheral side toward the center side. The notch portion is, for example, a recess having a substantially triangular or substantially quadrilateral shape in a plan view. The notch portion can be used, for example, for positioning the element mounting surface when mounting a semiconductor element on the socket 1 for semiconductor packaging, etc. In addition, the notch portion can be used, for example, for positioning the rotation direction of the socket 1 for semiconductor packaging, etc.

[0060] The first metal block 21 is a member integrally formed with the hole ring 10 and protruding from the upper surface 10a of the hole ring 10. The first metal block 21 can be made of a metal material such as iron, and integrally formed with the hole ring 10 by cold forging stamping or the like. The first metal block 21 has side wall portions 211 and 212 arranged in parallel at a predetermined interval, and a connecting portion 213 connecting the ends of the same side of the side wall portions 211 and 212. At the side wall portion 211, the side wall portion 212, and the connecting portion 213, a concave portion 214 recessed from the first lead 41 and the second lead 42 sides toward the outer peripheral direction of the hole ring 10 is formed.

[0061] That is, the first metal block 21 is substantially U-shaped when viewed in the normal direction of the upper surface 10a of the hole ring 10. Here, the substantially U-shape means that as long as it has two side wall portions arranged in parallel at a predetermined interval, and a connecting portion connecting the ends of the same side of each side wall portion, and a concave portion structure capable of surrounding a predetermined component from three directions through each side wall portion and the connecting portion, the detailed shape is not limited.

[0062] For example, in a plan view, the concave portion 214 can be rectangular, semi-circular, or semi-elliptical. In addition, there is no need for a specific relationship between the lengths and widths of the respective side wall portions and the connecting portion. In addition, although the widths of the respective side wall portions and the connecting portion are substantially constant even when the height from the upper surface 10a of the hole ring 10 changes, strictly speaking, they may not be constant.

[0063] The first end surface of the first metal block 21 facing the first lead 41 side is a substrate fixing surface 21a for fixing the first substrate 31. The second end surface of the first metal block 21 facing the second lead 42 side is a substrate fixing surface 21b for fixing the second substrate 32. The substrate fixing surface 21a and the substrate fixing surface 21b are provided to be substantially perpendicular to the upper surface 10a of the hole ring 10, for example. The substrate fixing surface 21a and the substrate fixing surface 21b face the same side and are, for example, located on the same plane.

[0064] It should be noted that although the substrate fixing surface 21a and the substrate fixing surface 21b are required to be flat enough to fix the substrate, the inner wall surface of the recess 214 of the first metal block 21 can be a rough surface with bumps and depressions because the substrate is not fixed.

[0065] The first substrate 31 is fixed to the substrate fixing surface 21a. A signal pattern 31S and a ground pattern 31G are provided on the front surface of the first substrate 31 (the surface facing the first lead 41). A ground pattern 31G is provided across the entire surface of the back surface of the first substrate 31 (the surface facing the first metal block 21). The ground pattern 31G on the front and back surfaces of the first substrate 31 are electrically connected via through-holes extending through the first substrate 31.

[0066] The second substrate 32 is fixed to the substrate fixing surface 21b. A signal pattern 32S and a ground pattern 32G are provided on the front surface of the second substrate 32 (the surface facing the second lead 42). A ground pattern 32G is provided across the entire back surface of the second substrate 32 (the surface facing the first metal block 21). The ground pattern 32G on the front surface and the ground pattern 32G on the back surface of the second substrate 32 are electrically connected via through-holes extending through the second substrate 32.

[0067] The back side of the first substrate 31 is fixed to the substrate-fixing surface 21a using a conductive material such as solder (e.g., a gold-tin alloy), and the back side of the second substrate 32 is fixed to the substrate-fixing surface 21b using a conductive material such as solder (e.g., a gold-tin alloy). As a result, the ground pattern 31G on the back side of the first substrate 31 and the ground pattern 32G on the back side of the second substrate 32 are electrically connected to the first metal block 21, and the first metal block 21 is at the GND potential (reference potential).

[0068] The height of the first metal block 21 is substantially the same as the height of the first substrate 31 and the second substrate 32 relative to the upper surface 10a of the eyelet 10. The height of the first metal block 21, the first substrate 31, and the second substrate 32 relative to the upper surface 10a of the eyelet 10 is, for example, 2 mm.

[0069] The first substrate 31 and the second substrate 32 are made of aluminum oxide or aluminum nitride. The signal patterns 31S, 32S, and the ground patterns 31G, 32G can be formed of, for example, tungsten, titanium, or gold. The surfaces of the signal patterns 31S, 32S, and the ground patterns 31G, 32G can be plated with gold or the like.

[0070] The first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are hermetically joined in the through-holes of the through-hole ring 10 from the upper surface 10a side to the lower surface 10b side in such a manner that the length direction faces the thickness direction of the hole ring 10. That is, the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are sealed by a sealing portion 50 around them in each through-hole.

[0071] Portions of the first lead 41 and the second lead 42 protrude upward from the upper surface 10a of the hole ring 10. The protrusion amount is, for example, about 0 to 0.3 mm. Portions of the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 protrude upward from the upper surface 10a of the hole ring 10. The protrusion amount of the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 from the upper surface 10a of the hole ring 10 is, for example, about 0 to 2 mm.

[0072] In addition, portions of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 protrude downward from the lower surface 10b of the hole ring 10. The protrusion amount of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 from the lower surface 10b of the hole ring 10 is, for example, about 6 to 10 mm.

[0073] The first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are made of a metal such as iron-nickel alloy or Kovar alloy, and the sealing portion 50 is made of an insulating material such as a glass material. Gold plating or the like can be formed on the surfaces of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46.

[0074] The portion of the first lead 41 that protrudes upward from the upper surface 10a of the hole ring 10 is electrically connected to the signal pattern 31S of the first substrate 31 through a solder (such as gold-tin alloy) or the like. In addition, the portion of the second lead 42 that protrudes upward from the upper surface 10a of the hole ring 10 is electrically connected to the signal pattern 32S of the second substrate 32 through a solder (such as gold-tin alloy) or the like.

[0075] The first lead 41 and the second lead 42 serve as paths through which differential signals that are electrically connected to the light-emitting element mounted on the semiconductor package socket 1 via the signal pattern 31S and the signal pattern 32S pass. The third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 serve as paths through which signals, for example, that are electrically connected to GND and the Peltier element mounted on the semiconductor package socket 1 pass, and paths through which signals that are electrically connected to the temperature sensor mounted on the semiconductor package socket 1 pass. It should be noted that the number of leads is not limited and can be increased or decreased as needed.

[0076] Figure 4 FIG. 4 is a perspective view (one) of the semiconductor package according to the first embodiment, and is a view of the semiconductor package observed from the surface side of the first substrate and the second substrate. Figure 5 FIG. 6 is a perspective view (two) of the semiconductor package according to the first embodiment, and is a view of the semiconductor package observed from the back side of the first substrate and the second substrate. Figure 6 FIG. 8 is a top view of the semiconductor package according to the first embodiment. It should be noted that, Figure 4 for convenience, the cover 100 is illustrated as transparent in FIGS. 8, Figure 5 and Figure 6 the illustration of the cover 100 and the transparent member 110 is omitted in FIGS. 11 and 13.

[0077] Refer to Figures 4 to 6 , the semiconductor package 2 of the first embodiment includes a semiconductor package socket 1 (refer to Figures 1 to 3 ), a second metal block 22, a third substrate 33, a light-emitting element 60, a Peltier element 70, a cover 100, and a transparent member 110.

[0078] As Figure 4 shown, in the semiconductor package 2, the cover 100 integrated with the transparent member 110 such as a lens or a window for extracting the emitted light L of the light-emitting element 60 is fixed to the semiconductor package socket 1 by resistance welding or the like. The cover 100 is formed of a metal such as stainless steel, for example, and the main components such as the light-emitting element 60 of the semiconductor package socket 1 are hermetically sealed inside.

[0079] The Peltier element 70 is disposed on the upper surface 10a of the hole ring 10. A part of the Peltier element 70 enters the recess 214 in a manner not in contact with the recess 214, and the other part of the Peltier element 70 protrudes from the recess 214 toward the fourth lead 44 and the fifth lead 45.

[0080] The second metal block 22 is a substantially L-shaped component and is fixed on the Peltier element 70. A part of the second metal block 22 (the part with a higher height) enters the recess 214 in a manner not contacting the recess 214, and the other part of the second metal block 22 (the part with a lower height) protrudes from inside the recess 214 toward the fourth lead 44 and the fifth lead 45 side. That is, the second metal block 22 is arranged separately from the first metal block 21.

[0081] The side surface of the second metal block 22 toward the fourth lead 44 and the fifth lead 45 side is a substrate fixing surface 22a for fixing the third substrate 33. The substrate fixing surface 22a is provided, for example, in a manner substantially perpendicular to the upper surface 10a of the via hole ring 10. The substrate fixing surface 22a faces the same side as the substrate fixing surfaces 21a and 21b, and the substrate fixing surface 22a and the substrate fixing surfaces 21a and 21b are, for example, located on the same plane.

[0082] The second metal block 22 can be formed of a metal material such as stainless steel, etc. The second metal block 22 is fixed on the Peltier element 70 through, for example, an adhesive with high thermal conductivity, etc. The second metal block 22 is, for example, substantially L-shaped, but can be of any shape.

[0083] The third substrate 33 is fixed on the substrate fixing surface 22a. Signal patterns 33S1, 33S2, and a ground pattern 33G are provided on the surface of the third substrate 33 (the surface facing the fourth lead 44 and the fifth lead 45 side). A ground pattern 33G is provided over the entire surface on the back surface of the third substrate 33 (the surface facing the second metal block 22 side). The ground pattern 33G on the surface of the third substrate 33 and the ground pattern 33G on the back surface are electrically connected through the side surface of the third substrate 33.

[0084] The third substrate 33 is made of, for example, aluminum nitride. The signal patterns 33S1, 33S2, and the ground pattern 33G can be formed of, for example, tungsten, titanium, gold, etc. Gold plating, etc. can be formed on the surfaces of the signal patterns 33S1, 33S2, and the ground pattern 33G.

[0085] On the surface side of the third substrate 33, the signal pattern 33S1 is electrically connected to the signal pattern 31S through the linear member 80. Further, on the surface side of the third substrate 33, the signal pattern 33S2 is electrically connected to the signal pattern 32S through the linear member 80. Further, on the surface side of the third substrate 33, the ground pattern 33G is electrically connected to the ground pattern 31G and the ground pattern 32G through the linear member 80. The number of the linear members 80 connecting the respective parts can be set to any number of one or more. As the linear member 80, for example, a bonding wire can be cited, and as long as it is a linear member, it is not particularly limited. As another example of the linear member 80, a strip can be cited. Further, a metal wire or the like can be joined using solder.

[0086] The signal pattern 33S1 and the signal pattern 33S2 are electrically connected to the terminals of the light-emitting element 60 mounted on the surface of the third substrate 33. In order to correspond to the differential driving circuit for driving the light-emitting element 60, two systems of the signal pattern 33S1 and the signal pattern 33S2 are required for the input lines of the driving signals. The normal-phase signal is input to one of the signal pattern 33S1 and the signal pattern 33S2, and the inverted signal obtained by inverting the normal-phase signal is input to the other. It should be noted that the light-emitting element 60 is, for example, a semiconductor laser chip having a wavelength of 1310 nm or the like.

[0087] The back side of the third substrate 33 is fixed to the substrate fixing surface 22a by a conductive material such as solder (e.g., gold-tin alloy). Thereby, the ground pattern 33G on the back side of the third substrate 33 is conducted to the second metal block 22, and the second metal block 22 becomes the GND potential (reference potential).

[0088] Figure 7 It is a perspective view of a socket for a semiconductor package showing a comparative example. Refer to Figure 7 , the socket 1X for a semiconductor package of the comparative example is different from the socket 1 for a semiconductor package (refer to Figures 1 to 3 etc.) in that the first metal block 21 is separated into the metal block 21X and the metal block 21Y.

[0089] In order to integrally stamp the via ring 10 with the metal blocks 21X and 21Y, it is necessary to adjust the inflow amount of the metal material into the mold relative to each of the metal blocks 21X and 21Y. However, since the stamping speed is high, that is, the plastic deformation speed of the metal material is high, it is almost impossible to adjust the inflow amount of the metal material into the mold. For example, if the filling of the metal material into one of the metal blocks 21X and 21Y is satisfied, the other of the metal blocks 21X and 21Y becomes insufficiently filled with the metal material or overfilled, and in the case of overfilling, the mold may be damaged.

[0090] Thus, it is extremely difficult to integrally stamp the two metal blocks 21X and 21Y that protrude separately above the hole ring 10 with the hole ring 10 by stamping molding.

[0091] In contrast, in the socket 1 for semiconductor package, the first substrate 31 and the second substrate 32 are fixed to the substrate fixing surfaces 21a and 22a of a first metal block 21. That is, the metal block integrally stamped with the hole ring 10 is only the first metal block 21, so that it is not necessary to adjust the inflow amount of the metal material into the mold as described above, and the first metal block 21 has a shape that can be integrally stamped with the hole ring 10. As a result, the socket 1 for semiconductor package can be supplied at low cost.

[0092] (Modification Example 1 of the First Embodiment)

[0093] In Modification Example 1 of the First Embodiment, an example of a socket for semiconductor package having a structure different from that of the First Embodiment is shown. It should be noted that in Modification Example 1 of the First Embodiment, the description of the constituent parts that are the same as those of the already described embodiment may be omitted.

[0094] Figure 8 FIG. is a perspective view of the socket for semiconductor package according to Modification Example 1 of the First Embodiment, and is a view of the socket for semiconductor package observed from the back side of the first substrate and the second substrate.

[0095] Refer to Figure 8 , the socket for semiconductor package 1A according to Modification Example 1 of the First Embodiment is different from the socket for semiconductor package 1 (refer to Figures 1 to 3 etc.) in that the first metal block 21 is replaced with the first metal block 21M.

[0096] Based on the upper surface 10a of the hole ring 10, the height of the first metal block 21M is lower than the height of the first metal block 21. That is, based on the upper surface 10a of the hole ring 10, the height of the first metal block 21M is lower than the heights of the first substrate 31 and the second substrate 32. Therefore, at least a part of the ground pattern 31G on the back surface of the first substrate 31 and at least a part of the ground pattern 32G on the back surface of the second substrate 32 are exposed from the first metal block 21M, so that wire bonding etc. can be performed from the rear on the exposed portions.

[0097] It should be noted that considering the ease of installation of the first substrate 31 and the second substrate 32, it is preferable that the height of the first metal block 21M based on the upper surface 10a of the hole ring 10 is 1 / 2 or more of the heights of the first substrate 31 and the second substrate 32. For example, when the heights of the first substrate 31 and the second substrate 32 based on the upper surface 10a of the hole ring 10 are 2 mm, it is preferable to set the height of the first metal block 21M to 1 mm or more.

[0098] In this way, the height of the first metal block 21M of the socket 1A for semiconductor packaging with respect to the upper surface 10a of the via ring 10 is lower than that of the first metal block 21 of the socket 1 for semiconductor packaging, making it easier to integrally stamp and form with the via ring 10.

[0099] Figure 9 FIG. 5 is a perspective view of a semiconductor package showing a modification 1 of the first embodiment, and is a view of the semiconductor package observed from the back side of the first substrate and the second substrate. Figure 10 FIG. 6 is a top view of a semiconductor package showing a modification 1 of the first embodiment. It should be noted that, Figure 9 and Figure 10 there are the same cover member 100 and transparent member 110 as in Figure 4 etc., but illustration thereof is omitted.

[0100] Referring to Figure 9 and Figure 10 , the semiconductor package 2A of the modification 1 of the first embodiment is different from the semiconductor package 2 (refer to Figures 4 to 6 etc.) in that the first metal block 21 is replaced with the first metal block 21M and the second metal block 22 is replaced with the second metal block 22M.

[0101] Different from the second metal block 22, the second metal block 22M is formed such that the width of the substrate fixing surface 22a is narrower than the width of the third substrate 33, and the third substrate 33 is fixed to the substrate fixing surface 22a in such a manner that both sides of the back surface (the first substrate 31 side and the second substrate 32 side) protrude from both sides of the second metal block 22M. Therefore, at least a part of the ground pattern 33G on the back surface of the third substrate 33 is exposed from the first substrate 31 side and the second substrate 32 side of the second metal block 22M.

[0102] The ground pattern 33G on the back surface of the third substrate 33 that is exposed from the first substrate 31 side of the second metal block 22M is electrically connected to the ground pattern 31G on the back surface of the first substrate 31 that is exposed from the first metal block 21M by a linear member 80. The number of the linear members 80 connecting the ground pattern 33G and the ground pattern 31G on the back surface sides of the third substrate 33 and the first substrate 31 can be set to any number of one or more, but preferably two or more from the viewpoint of the stability of the GND potential.

[0103] However, preferably, the number of the linear members 80 connecting the ground pattern 33G and the ground pattern 31G on the back surface sides of the third substrate 33 and the first substrate 31 is ten or less. This is to prevent the heat generated by the operation of the light-emitting element 60 that moves due to the Peltier element 70 from returning to the light-emitting element 60 via the first substrate 31 and the third substrate 33.

[0104] A ground pattern 33G formed on the back surface of the third substrate 33 and exposed from the second substrate 32 side of the second metal block 22M is electrically connected to a ground pattern 32G formed on the back surface of the second substrate 32 and exposed from the first metal block 21M by a linear member 80. The number of the linear members 80 connecting the ground pattern 33G and the ground pattern 32G on the back surface sides of the third substrate 33 and the second substrate 32 can be set to any number of one or more, but from the viewpoint of the stability of the GND potential, it is preferably two or more.

[0105] However, the number of the linear members 80 connecting the ground pattern 33G and the ground pattern 32G on the back surface sides of the third substrate 33 and the second substrate 32 is preferably ten or less. This is to prevent the heat generated by the operation of the light-emitting element 60, which is moved by the Peltier element 70, from returning to the light-emitting element 60 via the first substrate 32 and the third substrate 33.

[0106] In this way, in the semiconductor package 2A, at least a part of the ground pattern 31G on the back surface of the first substrate 31 and at least a part of the ground pattern 32G on the back surface of the second substrate 32 are exposed from the first metal block 21M. In addition, at least a part of the ground pattern 33G on the back surface of the third substrate 33 is exposed from the first substrate 31 side and the second substrate 32 side of the second metal block 22M.

[0107] Moreover, the ground pattern 31G on the back surface of the first substrate 31 exposed from the first metal block 21M is electrically connected to the ground pattern 33G on the back surface of the third substrate 33 exposed from the first substrate 31 side of the second metal block 22M by a linear member 80. In addition, the ground pattern 32G on the back surface of the second substrate 32 exposed from the first metal block 21M is electrically connected to the ground pattern 33G on the back surface of the third substrate 33 exposed from the second substrate 32 side of the second metal block 22M by a linear member 80.

[0108] That is to say, unlike the prior art where the back surface sides of the metal blocks are electrically connected by a linear member, the ground pattern 31G on the back surface of the first substrate 31 and the ground pattern 32G on the back surface of the second substrate 32 are electrically connected to the ground pattern 33G on the back surface of the third substrate 33 by a linear member. Thereby, the ground patterns of different substrates can be connected to each other in the shortest way without passing through the metal block, and the electrical characteristics can be further improved.

[0109] In addition, for the connection between the ground pattern 31G on the back surface of the first substrate 31 and the ground pattern 33G on the back surface of the third substrate 33, an improvement effect in electrical characteristics can be obtained even by using, for example, a bonding wire with a diameter of 25 μm. Similarly, for the connection between the ground pattern 32G on the back surface of the second substrate 32 and the ground pattern 33G on the back surface of the third substrate 33, an improvement effect in electrical characteristics can be obtained even by using, for example, a bonding wire with a diameter of 25 μm.

[0110] Therefore, it is not necessary to arbitrarily increase the number of metal wires added on the back side of each substrate, and heat can be suppressed from returning to the light-emitting element through the linear members added on the back side of each substrate. However, if the required specifications of the semiconductor package can be satisfied, multiple linear members can be used to connect the ground patterns of different substrates to each other. In this case, further improvement in electrical characteristics is expected.

[0111] In addition, it is preferable that the first substrate 31 and the second substrate 32 are formed of a material having a lower thermal conductivity than the third substrate 33. Thereby, it is possible to further prevent heat generated due to the operation of the light-emitting element 60 and transferred by the Peltier element 70 from returning to the light-emitting element 60 via the first substrate 31 and the second substrate 32. To obtain such an effect, for example, the first substrate 31 and the second substrate 32 can be made of alumina, and the third substrate 33 can be made of aluminum nitride.

[0112] It should be noted that when a bonding wire is used as the linear member 80, if the bonding wire is set to be thicker, the electrical characteristics are improved, but heat return is likely to occur. Considering the improvement of electrical characteristics and heat return, it is preferable to set the diameter of the bonding wire to about 25 μm.

[0113] As described above, the preferred embodiments have been described in detail, but the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope described in the claims.

Claims

1. A socket for semiconductor packaging, comprising: A hole ring; A first metal block, which is integrally formed with the above-mentioned hole ring and protrudes from the upper surface of the above-mentioned hole ring, and is U-shaped when viewed from the normal direction of the upper surface of the above-mentioned hole ring; A first lead, which is hermetically joined inside a first through-hole that penetrates the above-mentioned hole ring from the upper surface side to the lower surface side; A first substrate, which has a surface formed with a first signal pattern electrically connected to the above-mentioned first lead, and a back surface that is the opposite surface of the above-mentioned surface, and the back surface side is fixed to the first end surface of the above-mentioned first metal block; A second lead, which is hermetically joined inside a second through-hole that penetrates the above-mentioned hole ring from the upper surface side to the lower surface side; and A second substrate, which has a surface formed with a second signal pattern electrically connected to the above-mentioned second lead, and a back surface that is the opposite surface of the above-mentioned surface, and the back surface side is fixed to the second end surface of the above-mentioned first metal block, A first part that is a part of the back surface of the above-mentioned first substrate and a second part that is a part of the back surface of the above-mentioned second substrate protrude from the above-mentioned first metal block, A ground pattern is formed on the first part of the above-mentioned first substrate and the second part of the above-mentioned second substrate.

2. The socket for semiconductor packaging according to claim 1, wherein, The first end surface and the second end surface are located on the same plane.

3. The socket for semiconductor packaging according to claim 1 or 2, wherein, Based on the upper surface of the above-mentioned hole ring, the height of the above-mentioned first metal block is lower than the heights of the above-mentioned first substrate and the above-mentioned second substrate.

4. A semiconductor package, comprising: The socket for semiconductor packaging according to any one of claims 1 to 3; A Peltier element, which is arranged on the upper surface of the above-mentioned hole ring in such a way that at least a part of it enters the inside of the U-shape of the above-mentioned first metal block and is separated from the above-mentioned first metal block; A second metal block, which is arranged on the above-mentioned Peltier element in such a way that at least a part of it enters the inside of the U-shape of the above-mentioned first metal block and is separated from the above-mentioned first metal block, and the second metal block has a side surface facing the same direction as the above-mentioned first end surface and the above-mentioned second end surface; and A third substrate, which has a surface on which a light-emitting element is mounted, and a back surface that is the opposite surface of the above-mentioned surface, and the back surface side is fixed to the above-mentioned side surface of the above-mentioned second metal block.

5. The semiconductor package according to claim 4, wherein, A third part that is a part of the back surface of the above-mentioned third substrate protrudes from the above-mentioned second metal block, A ground pattern is formed on the third part of the above-mentioned third substrate, The ground pattern formed on the first part of the above-mentioned first substrate and the ground pattern formed on the second part of the above-mentioned second substrate are electrically connected to the ground pattern formed on the third part of the above-mentioned third substrate through a linear component.

6. The semiconductor package according to claim 5, wherein, The ground pattern formed on the first portion of the first substrate and the ground pattern formed on the second portion of the second substrate are electrically connected to the ground pattern formed on the third portion of the third substrate through a plurality of linear members.

7. The semiconductor package according to any one of claims 4 to 6, wherein the first substrate and the second substrate are formed of a material having a lower thermal conductivity than the third substrate.

8. The semiconductor package according to claim 7, wherein the first substrate and the second substrate are made of alumina, and the third substrate is made of aluminum nitride.

Images