Socket for semiconductor package and semiconductor package

Abstract

The present invention provides a socket for a semiconductor package and a semiconductor package that can further improve electrical characteristics. The socket for a semiconductor package has: a via ring; a first metal block that protrudes on the upper surface of the via ring; a first lead that is hermetically joined in a first through hole that penetrates the via ring from the upper surface side to the lower surface side; and a first substrate that has a surface formed with a first signal pattern electrically connected to the first lead and a back surface that is the opposite surface of the surface, and the back surface side is fixed to the first side surface of the first metal block, and a first portion that is a part of the back surface of the first substrate protrudes from the first metal block, and a ground pattern is formed on the first portion of the first substrate.

Description

Technical Field

[0001] The present invention relates to a socket for semiconductor packaging and a semiconductor package. Background Art

[0002] There are various types of light-emitting elements, for example, an electro-absorption modulator integrated with a DFB laser (EML) and a directly modulated laser (DML) are known. These light-emitting elements are used for optical communication, for example.

[0003] Among these light-emitting elements, in order to stabilize the oscillation wavelength, a Peltier element as a temperature regulator is sometimes mounted in the package. In this case, since the Peltier element is mounted, the length of the transmission line in the package becomes long, and thus a relay substrate considering transmission loss and a metal block for holding the relay substrate are required, and these components are arranged above the via ring.

[0004] However, since the Peltier element is a semiconductor type heat transfer device, electrical conduction in the vertical direction is not achieved. Therefore, for example, when an element mounting substrate on which a light-emitting element is mounted is arranged above the Peltier element, the element mounting substrate becomes in an electrically floating state with respect to the via ring, which is not preferable for processing high-frequency signals.

[0005] Then, for example, research is being conducted to connect the GND on the surface side of the relay substrate and the GND on the surface side of the element mounting substrate with a metal wire, and to connect the metal block on the back side for holding the relay substrate and the metal block on the back side for holding the element mounting substrate with a metal wire, thereby improving the electrical characteristics.

[0006] <Prior Art Documents>

[0007] <Patent Documents>

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-108939 Summary of the Invention

[0009] <Problems to be Solved by the Invention>

[0010] However, in the case of adding a metal wire between the metal blocks, it is necessary to consider not allowing the heat of the light-emitting element that does not move due to the Peltier element to return to the light-emitting element again via the relay substrate or the like. That is, although increasing the number of additional metal wires improves the electrical characteristics, since heat easily returns to the light-emitting element via the metal wire, it is not preferable to arbitrarily increase the number of metal wires. Therefore, further improvement of the electrical characteristics using fewer metal wires is desired.

[0011] The present invention has been made in view of the above points, and an object thereof is to provide a socket for a semiconductor package that can further improve electrical characteristics.

[0012] <Means for Solving the Problem>

[0013] The socket for a semiconductor package includes: a via ring; a first metal block protruding from the upper surface of the via ring; a first lead hermetically bonded in a first through hole that penetrates the via ring from the upper surface side to the lower surface side; and a first substrate having a surface formed with a first signal pattern electrically connected to the first lead and a back surface that is the opposite surface of the surface, and the back surface side is fixed to a first side surface of the first metal block, a first portion that is a part of the back surface of the first substrate protrudes from the first metal block, and a ground pattern is formed on the first portion of the first substrate.

[0014] <Effects of the Invention>

[0015] According to the disclosed technology, it is possible to provide a socket for a semiconductor package that can further improve electrical characteristics. Description of the Drawings

[0016] Figure 1 FIG. 1 is a perspective view (one) of a socket for a semiconductor package illustrating a first embodiment.

[0017] Figure 2 FIG. 2 is a perspective view (two) of a socket for a semiconductor package illustrating a first embodiment.

[0018] Figure 3 FIG. 3 is a top view of a socket for a semiconductor package illustrating a first embodiment.

[0019] Figure 4 FIG. 4 is a perspective view (one) of a semiconductor package illustrating a first embodiment.

[0020] Figure 5 FIG. 5 is a perspective view (two) of a semiconductor package illustrating a first embodiment.

[0021] Figure 6 FIG. 6 is a top view of a semiconductor package illustrating a first embodiment.

[0022] Figure 7 FIG. 7 is a perspective view of a socket for a semiconductor package illustrating a first modification.

[0023] Figure 8 FIG. 8 is a diagram (one) for explaining the simulation.

[0024] Figure 9 FIG. 9 is a diagram (one) for explaining the result of the simulation.

[0025] Figure 10 Figure for explaining the simulation (Part II).

[0026] Figure 11 Figure for explaining the result of the simulation (Part II).

[0027] Figure 12 Figure for explaining the result of the simulation (Part III).

[0028] Figure 13 Figure for explaining the simulation (Part III).

[0029] Figure 14 Figure for explaining the result of the simulation (Part IV).

[0030] Figure 15 Figure for explaining the simulation (Part IV).

[0031] Figure 16 Figure for explaining the result of the simulation (Part V).

[0032] Figure 17 Figure for explaining the simulation (Part V).

[0033] Figure 18 Figure for explaining the result of the simulation (Part VI).

[0034] Explanation of reference numerals:

[0035] 1, 1A Socket for semiconductor package

[0036] 2 Semiconductor package

[0037] 10 Hole ring

[0038] 10a Upper surface

[0039] 10b Lower surface

[0040] 21 First metal block

[0041] 21a, 22a, 23a Substrate fixing surface

[0042] 22 Second metal block

[0043] 23 Third metal block

[0044] 31 First substrate

[0045] 31G, 32G, 33G Ground pattern

[0046] 31S, 32S, 33S1, 33S2 Signal pattern

[0047] 32 Second substrate

[0048] 33rd third substrate

[0049] 41st first lead

[0050] 42nd second lead

[0051] 43rd third lead

[0052] 44th fourth lead

[0053] 45th fifth lead

[0054] 46th sixth lead

[0055] 50 Sealing portion

[0056] 60 Light-emitting element

[0057] 70 Peltier element

[0058] 80 Linear component

[0059] 100 Cover

[0060] 110 Transparent component Detailed implementation mode

[0061] Hereinafter, a mode for implementing the invention will be described with reference to the accompanying drawings. It should be noted that in each of the drawings, the same reference numerals are given to the same components, and redundant descriptions may be omitted sometimes.

[0062] (First embodiment)

[0063] Figure 1 FIG. is a perspective view (one) of a socket for a semiconductor package according to the first embodiment, and is a view of the socket for a semiconductor package observed from the surface sides of the first substrate and the second substrate. Figure 2 FIG. is a perspective view (two) of a socket for a semiconductor package according to the first embodiment, and is a view of the socket for a semiconductor package observed from the back sides of the first substrate and the second substrate. Figure 3 FIG. is a top view of a socket for a semiconductor package according to the first embodiment.

[0064] Refer to Figures 1 to 3 , the socket 1 for a semiconductor package according to the first embodiment has: a hole ring 10; a first metal block 21; a second metal block 22; a first substrate 31; a second substrate 32; a first lead 41; a second lead 42; a third lead 43; a fourth lead 44; a fifth lead 45; a sixth lead 46; and a sealing portion 50. The socket 1 for a semiconductor package can be used, for example, as a socket for a directly modulated laser (DML).

[0065] The hole ring 10 is a disc-shaped component. The diameter of the hole ring 10 is not particularly limited and can be appropriately determined according to the purpose. For example, it can be φ3.8 mm, φ5.6 mm, etc. The thickness of the hole ring 10 is not particularly limited and can be appropriately determined according to the purpose. For example, it can be about 1.0 - 1.5 mm. The hole ring 10 can be formed of a metal material such as iron. The hole ring 10 can also be formed of a metal material (such as a so-called clad material) in which multiple metal layers (copper layer, iron layer, etc.) are laminated. Gold plating or the like can be applied to the surface of the hole ring 10.

[0066] It should be noted that in this application, "disc-shaped" means that the top view shape is approximately circular and has a specified thickness. The size of the thickness relative to the diameter is not limited. In addition, cases where concave portions, convex portions, through holes, etc. are partially formed are also included. In addition, in this application, "top view" means observing the object from the normal direction of the upper surface 10a of the hole ring 10, and the top view shape means the shape of the object observed from the normal direction of the upper surface 10a of the hole ring 10.

[0067] At the outer edge portion of the hole ring 10, in the top view, one or more notch portions having a recessed shape can be formed from the outer peripheral side toward the center side. The notch portion is, for example, a recess having a top view shape that is approximately triangular or approximately quadrilateral. The notch portion can be used, for example, for positioning the element mounting surface when mounting a semiconductor element on the semiconductor package socket 1. In addition, the notch portion can be used, for example, for positioning the rotation direction of the semiconductor package socket 1.

[0068] The first metal block 21 and the second metal block 22 are columnar components protruding from the upper surface 10a of the hole ring 10 and are arranged separately from each other on the upper surface 10a of the hole ring 10. The side surface of the first metal block 21 facing the first lead 41 side is a substrate fixing surface 21a for fixing the first substrate 31.

[0069] Similarly, the side surface of the second metal block 22 facing the second lead 42 side is a substrate fixing surface 22a for fixing the second substrate 32. The substrate fixing surface 21a and the substrate fixing surface 22a are, for example, disposed substantially perpendicular to the upper surface 10a of the hole ring 10. The substrate fixing surface 21a and the substrate fixing surface 22a face the same side, for example, and are located on the same plane.

[0070] The first metal block 21 and the second metal block 22 are formed of a metal material such as iron, for example. The first metal block 21 and the second metal block 22 are joined to the hole ring 10 through a conductive material such as solder, for example. The first metal block 21 and the second metal block 22 can also be integrally formed with the hole ring 10 by, for example, cold forging stamping or the like. The first metal block 21 and the second metal block 22 are, for example, rectangular parallelepiped-shaped, but as long as they are shapes that can expose a part of the back surfaces of the first substrate 31 and the second substrate 32 respectively, they can be set to any shape.

[0071] The first substrate 31 is fixed to the substrate fixing surface 21a. A signal pattern 31S and a ground pattern 31G are provided on the surface of the first substrate 31 (the surface facing the first lead 41). A ground pattern 31G is provided over the entire surface on the back surface of the first substrate 31 (the surface facing the first metal block 21). The ground pattern 31G on the surface of the first substrate 31 and the ground pattern 31G on the back surface are electrically connected through a through hole penetrating the first substrate 31.

[0072] The back side of the first substrate 31 is fixed to the substrate fixing surface 21a through a conductive material such as solder (e.g., gold-tin alloy). Thereby, the ground pattern 31G on the back surface of the first substrate 31 is conducted to the first metal block 21, and the first metal block 21 becomes the GND potential (reference potential).

[0073] Based on the upper surface 10a of the via pad 10, the height of the first metal block 21 is lower than the height of the first substrate 31. Therefore, at least a part of the ground pattern 31G on the back surface of the first substrate 31 is exposed from the first metal block 21, and wire bonding or the like can be performed from the back surface on the exposed part.

[0074] It should be noted that considering the ease of mounting of the first substrate 31, it is preferable that the height of the first metal block 21 based on the upper surface 10a of the via pad 10 is 1 / 2 or more of the height of the first substrate 31. For example, when the height of the first substrate 31 based on the upper surface 10a of the via pad 10 is 2 mm, it is preferable to set the height of the first metal block 21 to 1 mm or more.

[0075] The second substrate 32 is fixed to the substrate fixing surface 22a. A signal pattern 32S and a ground pattern 32G are provided on the surface of the second substrate 32 (the surface facing the second lead 42). A ground pattern 32G is provided over the entire surface on the back surface of the second substrate 32 (the surface facing the second metal block 22). The ground pattern 32G on the surface of the second substrate 32 and the ground pattern 32G on the back surface are electrically connected through a through hole penetrating the second substrate 32.

[0076] The back side of the second substrate 32 is fixed to the substrate fixing surface 22a through a conductive material such as solder (e.g., gold-tin alloy). Thereby, the ground pattern 32G on the back surface of the second substrate 32 is conducted to the second metal block 22, and the second metal block 22 becomes the GND potential (reference potential).

[0077] Based on the upper surface 10a of the via pad 10, the height of the second metal block 22 is lower than the height of the second substrate 32. Therefore, at least a part of the ground pattern 32G on the back surface of the second substrate 32 is exposed from the second metal block 22, and wire bonding or the like can be performed from the back surface on the exposed part.

[0078] It should be noted that, considering the ease of mounting the second substrate 32, it is preferable that the height of the second metal block 22 based on the upper surface 10a of the hole ring 10 is 1 / 2 or more of the height of the second substrate 32. For example, when the height of the second substrate 32 based on the upper surface 10a of the hole ring 10 is 2 mm, it is preferable to set the height of the second metal block 22 to 1 mm or more.

[0079] The first substrate 31 and the second substrate 32 are made of, for example, alumina or aluminum nitride. In particular, alumina with relatively low thermal conductivity is preferable. The signal patterns 31S, 32S and the ground patterns 31G, 32G can be formed of, for example, tungsten, titanium, gold, etc. Gold plating or the like can be formed on the surfaces of the signal patterns 31S, 32S and the ground patterns 31G, 32G.

[0080] The first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are hermetically joined in the through holes that penetrate the hole ring 10 from the upper surface 10a side to the lower surface 10b side, with their longitudinal directions facing the thickness direction of the hole ring 10. That is, the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are sealed by the sealing portion 50 around them in each through hole.

[0081] A part of the first lead 41 and the second lead 42 protrudes upward from the upper surface 10a of the hole ring 10. The protruding amount is, for example, about 0 to 0.3 mm. A part of the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 protrudes upward from the upper surface 10a of the hole ring 10. The protruding amount of the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 from the upper surface 10a of the hole ring 10 is, for example, about 0 to 2 mm.

[0082] In addition, a part of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 protrudes downward from the lower surface 10b of the hole ring 10. The protruding amount of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 from the lower surface 10b of the hole ring 10 is, for example, about 6 to 10 mm.

[0083] The first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 are made of a metal such as iron-nickel alloy or Kovar alloy, and the sealing portion 50 is made of an insulating material such as a glass material. Gold plating or the like can be formed on the surfaces of the first lead 41, the second lead 42, the third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46.

[0084] The portion of the first lead 41 protruding upward from the upper surface 10a of the hole ring 10 is electrically connected to the signal pattern 31S of the first substrate 31 by a solder (such as a gold-tin alloy) or the like. In addition, the portion of the second lead 42 protruding upward from the upper surface 10a of the hole ring 10 is electrically connected to the signal pattern 32S of the second substrate 32 by a solder (such as a gold-tin alloy) or the like.

[0085] The first lead 41 and the second lead 42 serve as paths through which differential signals that are electrically connected to the light-emitting element mounted on the semiconductor package socket 1 via the signal pattern 31S and the signal pattern 32S pass. The third lead 43, the fourth lead 44, the fifth lead 45, and the sixth lead 46 serve as paths through which signals, for example, electrically connected to GND, the Peltier element mounted on the semiconductor package socket 1, and the temperature sensor mounted on the semiconductor package socket 1 pass. It should be noted that the number of leads is not limited and can be increased or decreased as needed.

[0086] Figure 4 FIG. 8 is a perspective view (one) of the semiconductor package according to the first embodiment, and is a view of the semiconductor package observed from the surface side of the first substrate and the second substrate. Figure 5 FIG. 10 is a perspective view (two) of the semiconductor package according to the first embodiment, and is a view of the semiconductor package observed from the back side of the first substrate and the second substrate. Figure 6 FIG. 12 is a top view of the semiconductor package according to the first embodiment. It should be noted that in Figure 4 , for convenience, the cover 100 is illustrated as transparent, and the illustration of the cover 100 and the transparent member 110 is omitted in Figure 5 and Figure 6 .

[0087] Referring to Figures 4 to 6 , the semiconductor package 2 according to the first embodiment includes a semiconductor package socket 1 (refer to Figures 1 to 3 ), a third metal block 23, a third substrate 33, a light-emitting element 60, a Peltier element 70, a cover 100, and a transparent member 110.

[0088] As shown in Figure 4 , in the semiconductor package 2, the cover 100 integrated with the transparent member 110, which is a lens, a window, etc. for extracting the emitted light L of the light-emitting element 60, is fixed to the semiconductor package socket 1 by resistance welding or the like. The cover 100 is formed of a metal such as stainless steel, and the main components such as the light-emitting element 60 of the semiconductor package socket 1 are hermetically sealed inside.

[0089] The third metal block 23 is a component in a substantially L shape, which is fixed on the Peltier element 70 disposed on the upper surface 10a of the hole ring 10. The third metal block 23 is disposed between the first metal block 21 and the second metal block 22 in a manner that does not contact either of them. That is to say, the third metal block 23 is disposed separately from the first metal block 21 and the second metal block 22.

[0090] The surface of the third metal block 23 facing the fourth lead 44 and the fifth lead 45 is a substrate fixing surface 23a for fixing the third substrate 33. The substrate fixing surface 23a is set to be substantially perpendicular to the upper surface 10a of the hole ring 10, for example. The substrate fixing surface 23a faces the same side as the substrate fixing surfaces 21a and 22a. For example, the substrate fixing surface 23a and the substrate fixing surfaces 21a and 22a are on the same plane.

[0091] Considering heat dissipation and the coefficient of thermal expansion, the third metal block 23 can be formed of a metal material such as copper tungsten, etc. The third metal block 23 is fixed on the Peltier element 70 through an adhesive with relatively high thermal conductivity, etc. The third metal block 23 is, for example, in a substantially L shape, and can be of any shape as long as it can expose a part of the back surface of the third substrate 33.

[0092] The third substrate 33 is fixed on the substrate fixing surface 23a. Signal patterns 33S1, signal patterns 33S2, and a ground pattern 33G are provided on the surface of the third substrate 33 (the surface facing the fourth lead 44 and the fifth lead 45). A ground pattern 33G is provided over the entire surface on the back surface of the third substrate 33 (the surface facing the third metal block 23). The ground pattern 33G on the surface of the third substrate 33 and the ground pattern 33G on the back surface are electrically connected through the side surface of the third substrate 33.

[0093] Considering thermal conductivity, the third substrate 33 is made of, for example, aluminum nitride. The signal patterns 33S1, the signal patterns 33S2, and the ground pattern 33G can be formed of, for example, tungsten, titanium, gold, etc. Gold plating, etc. can be formed on the surfaces of the signal patterns 33S1, the signal patterns 33S2, and the ground pattern 33G.

[0094] On the surface side of the third substrate 33, the signal pattern 33S1 is electrically connected to the signal pattern 31S through one or more linear members 80. The linear member 80 is a conductive element such as a wire. Further, on the surface side of the third substrate 33, the signal pattern 33S2 is electrically connected to the signal pattern 32S through one or more linear members 80. Further, on the surface side of the third substrate 33, the ground pattern 33G is electrically connected to the ground pattern 31G and the ground pattern 32G through one or more linear members 80. The number of the linear members 80 connecting the respective parts can be set to any number of one or more. As the linear member 80, for example, a bonding wire can be cited, and any linear member can be used without particular limitation. As another example of the linear member 80, a strip can be cited. Further, a metal wire or the like can be joined using solder.

[0095] The signal pattern 33S1 and the signal pattern 33S2 are electrically connected to the terminals of the light-emitting element 60 mounted on the surface of the third substrate 33. In order to correspond to a differential driving circuit for driving the light-emitting element 60, two systems of the signal pattern 33S1 and the signal pattern 33S2 are required for the input lines of the driving signals. A positive-phase signal is input to one of the signal pattern 33S1 and the signal pattern 33S2, and an inverted signal obtained by inverting the positive-phase signal is input to the other. It should be noted that the light-emitting element 60 is, for example, a semiconductor laser chip having a wavelength of 1310 nm or the like.

[0096] The back side of the third substrate 33 is fixed to the substrate fixing surface 23a by a conductive material such as solder (e.g., gold-tin alloy). Thereby, the ground pattern 33G on the back side of the third substrate 33 is conducted to the third metal block 23, and the third metal block 23 becomes a GND potential (reference potential).

[0097] It should be noted that the width of the substrate fixing surface 23a of the third metal block 23 is formed to be narrower than the width of the third substrate 33, and the third substrate 33 is fixed to the substrate fixing surface 23a such that both sides of the back side (the first substrate 31 side and the second substrate 32 side) protrude from both sides of the third metal block 23. Thereby, at least a part of the ground pattern 33G on the back side of the third substrate 33 is exposed from the first substrate 31 side and the second substrate 32 side of the third metal block 23.

[0098] The ground pattern 33G formed on the back side of the third substrate 33 and exposed from the first substrate 31 side of the third metal block 23 is electrically connected to the ground pattern 31G formed on the back side of the first substrate 31 and exposed from the first metal block 21 through the linear member 80. The number of the linear members 80 connecting the ground pattern 33G and the ground pattern 31G on the back side of the third substrate 33 and the first substrate 31 can be set to any number of one or more, but is preferably set to two or more from the viewpoint of the stability of the GND potential.

[0099] However, preferably, the number of linear members 80 that connect the ground pattern 33G and the ground pattern 31G on the back side of the third substrate 33 and the first substrate 31 is ten or less. This is to prevent the heat generated by the operation of the light-emitting element 60 that is moved by the Peltier element 70 from returning to the light-emitting element 60 via the first substrate 31 and the third substrate 33.

[0100] The ground pattern 33G formed on the back surface of the third substrate 33 that is exposed from the second substrate 32 side of the third metal block 23 and the ground pattern 32G formed on the back surface of the second substrate 32 that is exposed from the second metal block 22 are electrically connected by the linear member 80. The number of linear members 80 that connect the ground pattern 33G and the ground pattern 32G on the back side of the third substrate 33 and the second substrate 32 can be set to any number of one or more, but preferably two or more from the viewpoint of the stability of the GND potential.

[0101] However, preferably, the number of linear members 80 that connect the ground pattern 33G and the ground pattern 32G on the back side of the third substrate 33 and the second substrate 32 is ten or less. This is to prevent the heat generated by the operation of the light-emitting element 60 that is moved by the Peltier element 70 from returning to the light-emitting element 60 via the second substrate 32 and the third substrate 33.

[0102] In this way, in the semiconductor package 2, at least a part of the ground pattern 31G on the back surface of the first substrate 31 is exposed from the first metal block 21, and at least a part of the ground pattern 32G on the back surface of the second substrate 32 is exposed from the second metal block 22. In addition, at least a part of the ground pattern 33G on the back surface of the third substrate 33 is exposed from the first substrate 31 side and the second substrate 32 side of the third metal block 23.

[0103] Moreover, the ground pattern 31G on the back surface of the first substrate 31 that is exposed from the first metal block 21 and the ground pattern 33G on the back surface of the third substrate 33 that is exposed from the first substrate 31 side of the third metal block 23 are electrically connected by the linear member 80. In addition, the ground pattern 32G on the back surface of the second substrate 32 that is exposed from the second metal block 22 and the ground pattern 33G on the back surface of the third substrate 33 that is exposed from the second substrate 32 side of the third metal block 23 are electrically connected by the linear member 80.

[0104] That is to say, unlike in the past where the back sides of the metal blocks were electrically connected by linear members, the ground pattern 31G on the back surface of the first substrate 31 and the ground pattern 32G on the back surface of the second substrate 32 are electrically connected to the ground pattern 33G on the back surface of the third substrate 33 by linear members. Thereby, the ground patterns of different substrates can be connected to each other in the shortest path without passing through the metal blocks, and the electrical characteristics can be further improved.

[0105] In addition, regarding the connection between the ground pattern 31G on the back surface of the first substrate 31 and the ground pattern 33G on the back surface of the third substrate 33, even by using, for example, a bonding wire with a diameter of 25 μm, an improvement effect in electrical characteristics can be obtained. Similarly, regarding the connection between the ground pattern 32G on the back surface of the second substrate 32 and the ground pattern 33G on the back surface of the third substrate 33, even by using, for example, a bonding wire with a diameter of 25 μm, an improvement effect in electrical characteristics can be obtained (refer to the simulation results described later).

[0106] Therefore, it is not necessary to arbitrarily increase the number of metal wires added on the back surface side of each substrate, and heat can be suppressed from returning to the light-emitting element through the linear members added on the back surface side of each substrate. However, if the required specifications of the semiconductor package can be satisfied, multiple linear members can be used to connect the ground patterns of different substrates to each other. In this case, further improvement in electrical characteristics is expected.

[0107] In addition, it is preferable that the first substrate 31 and the second substrate 32 are formed of a material having a lower thermal conductivity than the third substrate 33. Thereby, heat due to the operation of the light-emitting element 60 that moves through the Peltier element 70 can be further prevented from returning to the light-emitting element 60 via the first substrate 31 and the second substrate 32. To obtain such an effect, for example, the first substrate 31 and the second substrate 32 can be made of alumina, and the third substrate 33 can be made of aluminum nitride.

[0108] It should be noted that when a bonding wire is used as the linear member 80, if the bonding wire is set to be thicker, the electrical characteristics are improved, but heat return is likely to occur. Considering the improvement of electrical characteristics and heat return, it is preferable to set the diameter of the bonding wire to about 25 μm.

[0109] (Modification Example 1 of the First Embodiment)

[0110] In Modification Example 1 of the first embodiment, an example of a socket for a semiconductor package having a configuration different from that of the first embodiment is shown. It should be noted that in Modification Example 1 of the first embodiment, the description of the components that are the same as those of the already described embodiment may sometimes be omitted.

[0111] Figure 7 is a perspective view of the socket for a semiconductor package according to Modification Example 1 of the first embodiment, and is a view of the socket for a semiconductor package observed from the surface side of the first substrate. Refer to Figure 7 , the socket for a semiconductor package 1A according to Modification Example 1 of the first embodiment is different from the socket for a semiconductor package 1 in that the second metal block 22, the second substrate 32, and the second lead 42 are removed (refer to Figures 1 to 3 etc.).

[0112] The socket 1 for semiconductor packaging in the first embodiment corresponds to a differential-mode drive circuit, and the socket 1A for semiconductor packaging corresponds to a single-ended mode drive circuit. Therefore, only one system of the signal pattern 31S is required for the input line of the drive signal, and thus the second metal block 22, the second substrate 32, and the second lead 42 are not needed.

[0113] On the socket 1A for semiconductor packaging, a third metal block 23, a third substrate 33, a light-emitting element 60, a Peltier element 70, a cover 100, and a transparent member 110 can be provided in the same manner as the socket 1 for semiconductor packaging, so as to form a semiconductor package. At this time, the signal pattern and the ground pattern of the third substrate 33 can be appropriately designed according to the single-ended mode drive circuit.

[0114] In the socket 1A for semiconductor packaging corresponding to the single-ended mode drive circuit, at least a part of the ground pattern 31G on the back surface of the first substrate 31 is also exposed from the first metal block 21 in the same manner as the socket 1 for semiconductor packaging. Thus, when manufacturing a semiconductor package using the socket 1A for semiconductor packaging, the ground pattern 31G on the back surface of the first substrate 31 exposed from the first metal block 21 can be electrically connected to the ground pattern 33G on the back surface of the third substrate 33 exposed from the first substrate 31 side of the third metal block 23 by the linear member 80. As a result, the same effect as the first embodiment is achieved.

[0115] (Simulation)

[0116] Next, the results of the simulation of connecting the ground patterns to each other on the back sides of the first substrate 31, the second substrate 32, and the third substrate 33 will be described in detail. In the simulation, the analysis software ANSYS Electromagnetics Suite 2019R3 was used. As the linear member 80, a gold bonding wire with a diameter of 25 μm was assumed. It should be noted that the simulation results are only shown for the first substrate 31 side, and the same results are obtained for the second substrate 32 side which is symmetric left and right.

[0117] (Simulation 1)

[0118] In Simulation 1, the number of the linear members 80 connecting the ground patterns to each other on the back sides of the first substrate 31 and the third substrate 33 was set to two, and the characteristic difference based on the position in the height direction of the connecting linear members 80 was simulated. In addition, as a comparative example, the case where the linear members 80 are not connected was also simulated.

[0119] Specifically, for the case (comparative example) where the linear members 80 are not connected as shown in (a) of Figure 8 , and as shown in Figure 8The case where two linear components 80 are connected one by one on the upper and lower sides as shown in (b) of, such as Figure 8 The case where two linear components 80 are only connected on the upper side as shown in (c) of, and Figure 8 The case where two linear components 80 are only connected on the lower side as shown in (d) of, the reflection loss (dB) and insertion loss (dB) were obtained.

[0120] The simulation results are shown in Figure 9 . In Figure 9 , the characteristics shown by the dotted line are the differential-mode reflection loss (SDD11), and the characteristics shown by the solid line are the differential-mode insertion loss (SDD21). In Figure 9 , a1 and a2 are Figure 8 the characteristics of the case of (a), b1 and b2 are Figure 8 the characteristics of the case of (b), c1 and c2 are Figure 8 the characteristics of the case of (c), d1 and d2 are Figure 8 the characteristics of the case of (d).

[0121] According to Figure 9 a1, b1, c1, d1, it can be confirmed that Figure 8 in the cases of (b) to Figure 8 (d) where two linear components 80 are connected, compared with the case of (a) in Figure 8 where no linear component 80 is connected, the reflection loss (SDD11) improves as the frequency increases. In addition, according to Figure 9 a2, b2, c2, d2, it can be confirmed that Figure 8 in the cases of (b) to Figure 8 (d) where two linear components 80 are connected, compared with the case of (a) in Figure 8 where no linear component 80 is connected, the insertion loss (SDD21) improves as the frequency increases.

[0122] However, in Figure 9 , the characteristics of b1 to d1 and b2 to d2 overlap with each other and basically appear as one line, without significant differences. Therefore, it can be said that connecting the linear component 80 is important, and the position of the connected linear component 80 is not important.

[0123] It should be noted that through additional research by the inventors, when there is one linear component 80, it becomes Figure 9 approximately in the middle of the characteristics of a1 and b1 to d1 and the characteristics of a2 and b2 to d2 as shown. It was confirmed that even connecting one linear component 80 can achieve certain effects.

[0124] (Simulation 2)

[0125] In Simulation 2, simulations were performed with the number of wire-like members 80 set to two and eight for the case of changing the height of the first metal block 21.

[0126] Specifically, for the case where the height of the first metal block 21 is low as shown in (a) of Figure 10 and only two wire-like members 80 are connected to the upper side, for the case where the height of the first metal block 21 is high as shown in (b) of Figure 10 and only two wire-like members 80 are connected to the upper side, for the case where the height of the first metal block 21 is low as shown in (c) of Figure 10 and eight wire-like members 80 are connected over substantially the entire height direction, and for the case where the height of the first metal block 21 is high as shown in (d) of Figure 10 and eight wire-like members 80 are connected over substantially the entire height direction, the reflection loss (dB) and insertion loss (dB) were obtained.

[0127] Regarding Figure 10 (a) and Figure 10 (b), the simulation results are shown in Figure 11 . Regarding Figure 10 (c) and Figure 10 (d), the simulation results are shown in Figure 12 . In Figure 11 and Figure 12 , the characteristics indicated by the dashed line are the differential-mode reflection loss (SDD11), and the characteristics indicated by the solid line are the differential-mode insertion loss (SDD21). In Figure 11 , a1 and a2 are the characteristics of the case of Figure 10 (a), and b1 and b2 are the characteristics of the case of Figure 10 (b). Additionally, in Figure 12 , c1 and c2 are the characteristics of the case of Figure 10 (c), and d1 and d2 are the characteristics of the case of Figure 10 (d).

[0128] Based on Figure 11 and Figure 12 , the characteristics of the case of connecting two wire-like members 80 and the case of connecting eight overlap with each other, and the influence of the height of the first metal block 21 cannot be confirmed. Additionally, comparing Figure 11 and Figure 12 , the reflection loss (SDD11) and insertion loss (SDD21) are improved in the case of connecting eight wire-like members 80 compared to the case of connecting two wire-like members 80.

[0129] (Simulation 3-1)

[0130] In Simulation 3-1, a simulation was conducted in which the height of the first metal block 21 was set to be constant and the number of wire-like members 80 was changed.

[0131] Specifically, based on the case of connecting ten wire-like members 80, for the case where two in the center were removed as shown in Figure 13 (a) to become eight, the case where two at the lower side were removed as shown in Figure 13 (b) to become eight, and the case where two at the upper side were removed as shown in Figure 13 (c) to become eight, the reflection loss (dB) and the insertion loss (dB) were obtained.

[0132] The simulation results including the case of connecting ten wire-like members 80 from Figure 13 (a) to Figure 13 (c) are shown in Figure 14 . In Figure 14 , the characteristics shown by the dashed line are the differential-mode reflection loss (SDD11), and the characteristics shown by the solid line are the differential-mode insertion loss (SDD21). In Figure 14 , a1 and a2 are the characteristics of the case of connecting ten wire-like members 80, and b1 and b2 are the characteristics of the case of Figure 13 (a), c1 and c2 are the characteristics of the case of Figure 13 (b), and d1 and d2 are the characteristics of the case of Figure 13 (c).

[0133] According to Figure 14 , the characteristics of the case of connecting ten wire-like members 80 and the case of connecting eight overlap with each other, and the influence of reducing the number of wire-like members 80 from ten to eight and the significant difference in the reduction position cannot be confirmed.

[0134] (Simulation 3-2)

[0135] In Simulation 3-2, a simulation was conducted in which the height of the first metal block 21 was set to be constant and the number of wire-like members 80 was changed.

[0136] Specifically, based on the case of connecting ten wire-like members 80, for the case where six in the center were removed as shown in Figure 15 (a) to be set to four, the case where six at the lower side were removed as shown in Figure 15 (b) to be set to four, and the case where six at the upper side were removed as shown in Figure 15 (c) to be set to four, the reflection loss (dB) and the insertion loss (dB) were obtained.

[0137] The Figure 15 including the case of connecting ten wire-like members 80 from Figure 15The simulation results of (c) are shown in Figure 16 . In Figure 16 , the characteristic shown by the dashed line is the differential-mode return loss (SDD11), and the characteristic shown by the solid line is the differential-mode insertion loss (SDD21). In Figure 16 , a1 and a2 are the characteristics of the case where ten linear members 80 are connected, and b1 and b2 are the characteristics of the case of Figure 15 (a), c1 and c2 are the characteristics of the case of Figure 15 (b), and d1 and d2 are the characteristics of the case of Figure 15 (c).

[0138] According to Figure 16 , if the number of linear members 80 is reduced from ten to four, there is a tendency for the characteristic to deteriorate as the frequency increases. However, no significant difference can be confirmed for the position where the linear members 80 are reduced.

[0139] (Simulation 3-3)

[0140] In Simulation 3-3, a simulation was conducted in which the height of the first metal block 21 was set constant and the number of linear members 80 was changed.

[0141] Specifically, based on the case where ten linear members 80 are connected, for the case where eight in the center are removed to become two as shown in Figure 17 (a), the case where eight at the lower side are removed to become two as shown in Figure 17 (b), and the case where eight at the upper side are removed to become two as shown in Figure 17 (c), the return loss (dB) and the insertion loss (dB) were obtained.

[0142] The simulation results of (a) to Figure 17 including the case where ten linear members 80 are connected to Figure 17 (c) are shown in Figure 18 . In Figure 18 , the characteristic shown by the dashed line is the differential-mode return loss (SDD11), and the characteristic shown by the solid line is the differential-mode insertion loss (SDD21). In Figure 18 , a1 and a2 are the characteristics of the case where ten linear members 80 are connected, and b1 and b2 are the characteristics of the case of Figure 17 (a), c1 and c2 are the characteristics of the case of Figure 17 (b), and d1 and d2 are the characteristics of the case of Figure 17 (c).

[0143] According to Figure 18 , the influence of reducing the number of linear members 80 from ten to two is greater than the influence of reducing it to four or eight. However, no significant difference can be confirmed for the position where the linear members 80 are reduced.

[0144] As described above, summarizing the results of Simulations 1 to 3-3, the following conclusions can be drawn. When the ground patterns are connected to each other on the back side of the first substrate 31, the second substrate 32, and the third substrate 33, a certain effect can be obtained even by connecting only one linear member 80. However, considering reflection loss and insertion loss, it is preferable to connect two or more. In addition, if three or more linear members 80 are connected, the reflection loss and insertion loss are further improved, but no further improvement is expected if there are more than eight. Further, no significant difference was found in the heights of the first metal block 21 and the second metal block 22 and the position in the height direction of the connecting linear member 80.

[0145] That is, when considering the improvement of electrical characteristics and the return of heat, for the linear member 80 connecting the first substrate 31 and the third substrate 33 and connecting the second substrate 32 and the third substrate 33 on the back side, it is preferable to select within the range of one or more and eight or less within the range that satisfies the required specifications of the semiconductor package.

[0146] As described above, the preferred embodiments have been described in detail. However, without being limited to the above embodiments, various modifications and substitutions can be made to the above embodiments without exceeding the scope described in the claims.

Claims

1. A socket for a semiconductor package, having: A via ring; A first metal block protruding from the upper surface of the via ring; A first lead hermetically bonded within a first through-hole that penetrates the via ring from the upper surface side of the via ring to the lower surface side of the via ring; A first substrate having a surface formed with a first signal pattern electrically connected to the first lead and a back surface opposite to the surface, and the back surface side is fixed to a first side surface of the first metal block; A second metal block protruding from the upper surface of the via ring, having a second side surface facing the same side as the first side surface, and being separated from the first metal block; A second lead hermetically bonded within a second through-hole that penetrates the via ring from the upper surface side of the via ring to the lower surface side of the via ring; And A second substrate having a surface formed with a second signal pattern electrically connected to the second lead and a back surface opposite to the surface, and the back surface side is fixed to the second side surface of the second metal block, A first portion that is part of the back surface of the first substrate is exposed from the first metal block, A ground pattern is formed on the first portion of the first substrate, A second portion that is part of the back surface of the second substrate is exposed from the second metal block, A ground pattern is formed on the second portion of the second substrate.

2. The socket for a semiconductor package according to claim 1, wherein Based on the upper surface of the via ring, the height of the first metal block is lower than the height of the first substrate.

3. The socket for a semiconductor package according to claim 1 or 2, wherein Based on the upper surface of the via ring, the height of the second metal block is lower than the height of the second substrate.

4. The socket for a semiconductor package according to claim 1 or 2, wherein The first side surface and the second side surface are on the same plane.

5. A semiconductor package, having: The socket for a semiconductor package according to any one of claims 1 to 4; A Peltier element disposed on the upper surface of the via ring; A third metal block disposed above the Peltier element and having a third side surface facing the same side as the first side surface and the second side surface; and A third substrate having a surface on which a light-emitting element is mounted and a back surface opposite to the surface, and the back surface side is fixed to the third side surface of the third metal block, A third portion that is part of the back surface of the third substrate is exposed from the first substrate side of the third metal block, A fourth portion that is part of the back surface of the third substrate is exposed from the second substrate side of the third metal block, Ground patterns are formed on the third portion and the fourth portion of the third substrate, The first metal block and the third metal block are separated, and the second metal block and the third metal block are separated, The ground pattern formed on the first portion of the first substrate and the ground pattern formed on the third portion of the third substrate are electrically connected by a linear component, The ground pattern formed in the second portion of the second substrate is electrically connected to the ground pattern formed in the fourth portion of the third substrate through a linear member.

6. The semiconductor package according to claim 5, wherein the ground pattern formed in the first portion of the first substrate is electrically connected to the ground pattern formed in the third portion of the third substrate through a plurality of linear members, the ground pattern formed in the second portion of the second substrate is electrically connected to the ground pattern formed in the fourth portion of the third substrate through a plurality of linear members.

7. The semiconductor package according to claim 5 or 6, wherein the first substrate and the second substrate are formed of a material having a lower thermal conductivity than the third substrate.

8. The semiconductor package according to claim 7, wherein the first substrate and the second substrate are made of alumina, and the third substrate is made of aluminum nitride.

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