Slew rate control circuit for image sensor

Abstract

A conversion rate control circuit for an image sensor is disclosed. The image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulation voltages at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistors coupled to first and second storage capacitors, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rail. The third transistor is configured to limit a conversion rate of a current flowing between a control terminal of the second transistor and the first or second voltage rail to a first conversion rate when the image sensor operates in a global shutter mode, and to limit a conversion rate of a current flowing between a control terminal of the second transistor and the first or second voltage rail to a second conversion rate when the image sensor operates in a rolling mode, wherein the first conversion rate is less than the second conversion rate.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods and, in particular embodiments, to a slew rate control circuit for an image sensor. Background Art

[0002] The image sensor detects and transmits the information of the image. The image sensor can be implemented by a CMOS sensor. Conventional CMOS sensors include multiple CMOS active pixel sensor (APS) structures, which can be implemented by clamping photodiodes. For example, Figure 1 As shown, the CMOS APS pixel 100 may be implemented with a clamped photodiode 102, a reset transistor 104, a select transistor 108, and a source follower transistor 106. The clamped photodiode 102 may be enabled or disabled by applying a voltage to a control terminal (not shown) of the clamped photodiode 102.

[0003] During normal operation, reset transistor 104 is reset to set the voltage at the gate of transistor 106 to V RST (Wherein, V RST Can be used with V DD The same), thereby clearing the integrated charge of the photodiode 102. When the reset transistor 104 is turned off, the voltage of the photodiode based on the intensity of the light received by the photodiode 102 is buffered by the source follower transistor 106 and can be read in the column bus COL when the select transistor 108 is turned on.

[0004] Some image sensors can operate in a rolling shutter mode, in which an image is captured by scanning a scene row by row or column by column and also by reading the captured scene row by column or column by column. In other words, the row (or column) integrates and samples the image sequentially. In contrast to the rolling shutter mode, some image sensors can operate in a global shutter mode, in which all pixels of the image sensor are integrated and sampled simultaneously, thereby capturing the entire image at the same time, and during the readout phase, image recovery still operates in a row by row or column by column scanning mode. Summary of the invention

[0005] According to an embodiment, an image sensor includes: a first voltage rail and a second voltage rail; a first regulator having an output coupled to the first voltage rail and configured to generate a first regulated voltage; a second regulator having an output coupled to the second voltage rail and configured to generate a second regulated voltage lower than the first regulated voltage; and a plurality of pixels coupled to the first voltage rail and the second voltage rail. Each of the plurality of pixels includes: a first storage capacitor and a second storage capacitor; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between a control terminal of the first transistor and the first voltage rail or the second voltage rail. The third transistor is configured to limit a slew rate of a current flowing between a control terminal of the second transistor and the first voltage rail or the second voltage rail to a first slew rate when the image sensor operates in a global shutter mode, and to limit a slew rate of a current flowing between a control terminal of the second transistor and the first voltage rail or the second voltage rail to a second slew rate when the image sensor operates in a rolling mode, the first slew rate being less than the second slew rate.

[0006] According to an embodiment, a method includes: generating a first voltage at a first voltage rail coupled to a plurality of pixels of an image sensor; generating a second voltage at a second voltage rail coupled to the plurality of pixels, wherein the second voltage is different from the first voltage; transitioning a first signal at a control terminal of a first transistor from the first voltage to a second voltage, wherein the first transistor has a current path coupled to a first storage capacitor; after transitioning the first signal from the first voltage to the second voltage, transitioning a second signal at a control terminal of a second transistor from the first voltage to the second voltage, wherein the second transistor has a current path coupled to a second storage capacitor; after transitioning the second signal from the first voltage to the second voltage, transitioning the second signal from the second voltage to the first voltage; and during the transition of the second signal from the second voltage to the first voltage, when the image sensor is in a global shutter mode, limiting a slew rate of a current flowing between a control terminal of the first transistor or the second transistor and the first voltage rail to a first slew rate, and, when the image sensor is in a rolling mode, limiting a slew rate of a current flowing between a control terminal of the first transistor or the second transistor and the first voltage rail to a second slew rate, wherein the first slew rate is less than the second slew rate.

[0007] According to an embodiment, an integrated circuit includes: a first internal low dropout linear regulator (LDO) configured to generate a first regulated voltage at a first voltage rail, wherein the first internal LDO is not coupled to a compensation capacitor external to the integrated circuit; a second internal LDO configured to generate a second regulated voltage at a second voltage rail, wherein the second internal LDO is not coupled to a compensation capacitor external to the integrated circuit, and wherein the second regulated voltage is lower than the first regulated voltage; and an image sensor including a plurality of image sensor pixels arranged in rows and columns and coupled to the first voltage rail and the second voltage rail, wherein each of the plurality of image sensor pixels includes : a first storage capacitor and a second storage capacitor; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between a control terminal of the first transistor and a second voltage rail, wherein the third transistor is configured to limit a conversion rate of a current flowing between the control terminal of the first transistor and the second voltage rail to a first conversion rate when the image sensor operates in a global shutter mode, and to limit a conversion rate of a current flowing between the control terminal of the first transistor and the second voltage rail to a second conversion rate when the image sensor operates in a rolling mode, the first conversion rate being less than the second conversion rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 shows a schematic diagram of an exemplary CMOS sensor pixel;

[0010] Figure 2A and Figure 2B Schematic diagrams of a CMOS image sensor and a pixel of the CMOS image sensor according to an embodiment of the present invention are respectively shown;

[0011] Figure 3 The embodiment according to the present invention is shown Figure 2B The signal waveform of the pixel;

[0012] Figure 4 The embodiment according to the present invention is shown Figure 2B Possible implementation of gate drivers;

[0013] Figure 5 Shows no restriction Figure 4 In the case of gate driver current, Figure 2A and Figure 2B The voltage rails of the pixels of a CMOS sensor and possible waveforms of the signals;

[0014] Figure 6 The embodiment according to the present invention is shown Figure 4 possible implementations of at least a portion of a controller;

[0015] Figure 7 The embodiment according to the present invention is shown Figure 4 possible implementations of at least a portion of a controller of ; and

[0016] Figure 8 FIG. 1 shows a method for performing a global shutter mode according to an embodiment of the present invention. Figure 7 The implementation shown Figure 2A and Figure 2B Voltage rails and signal waveforms of a CMOS sensor pixel.

[0017] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0018] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the present invention, and do not limit the scope of the present invention.

[0019] The following description shows various specific details to provide a deep understanding of several exemplary embodiments according to the description. The embodiments can be obtained without one or more specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. Reference to "embodiment" in this specification indicates that the specific configuration, structure, or feature described in the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this description do not necessarily refer to the same embodiment completely. In addition, in one or more embodiments, specific formations, structures, or features can be combined in any appropriate manner.

[0020] Embodiments of the present invention will be described in the specific context of a slew rate control circuit for a CMOS image sensor operating in a global shutter mode and a rolling mode and having a shared regulator. Some embodiments may be used in other circuits that may benefit from a combined regulator, for example. For example, some embodiments may be used in imaging applications such as photography, facial recognition, and automotive applications.

[0021] In an embodiment of the present invention, a first internal regulator generating a high voltage rail and a second internal regulator generating a low voltage rail are shared across all pixels of a CMOS image sensor. Spikes that may be generated in the high voltage rail or the low voltage rail are suppressed by a slew rate control circuit that is configurable based on whether the CMOS image sensor is operating in a global shutter mode or in a rolling mode.

[0022] Figure 2A and Figure 2B Schematic diagrams of a CMOS image sensor 250 and a pixel 200 according to an embodiment of the present invention are shown respectively. Figure 2A As shown, the CMOS image sensor 250 includes a CMOS sensor array 252, which includes a plurality of CMOS pixels 200 arranged in rows and columns. The CMOS image sensor 250 also includes internal regulators 220 and 222. As will be described in more detail later, the internal regulators 220 and 222 are shared across all pixels 200 of the CMOS image sensor 250. In some embodiments, the CMOS image sensor 250 may be implemented in a single substrate within an integrated circuit (IC).

[0023] like Figure 2B As shown, each pixel 200 includes a pinned photodiode 102, a reset transistor 202, a select transistor 218, a source follower transistor 204, storage control transistors 206, 208 and 210, storage capacitors 212 and 214, and gate drivers 232 and 234. The pinned photodiode 102 can be enabled or disabled by applying a voltage to a control terminal (not shown) of the pinned photodiode 102.

[0024] During normal operation, reset transistor 104 is reset to set the voltage at the gate of transistor 204 to V RST (Wherein, V RST For example, with V DD When reset transistor 104 is turned off and photodiode 102 is enabled, the voltage at node FD based on the intensity of light received by photodiode 102 (integrated over time) is buffered to node V by source follower transistor 204. 204 By switching storage control transistors 208 and 210, node V 204 , so that the voltage V 204 is stored in storage capacitors 212 and 214. When the pixel is selected for readout at column bus COL (by turning on transistor 218), the stored voltage V 214 The voltage is transmitted to V through source follower 216. out Reading the output voltage V is performed in a known manner.out , and thereby read the intensity of light received by the photodiode 102.

[0025] Gate drivers 232 and 234 generate signals S 208 and S 210 , to control the storage control transistors 208 and 210. Figure 2B As shown, the signal S 208 and S 210 Can have low voltage V L Or high voltage V H As a non-limiting example, in some embodiments, the low voltage V L and high voltage V H Respectively, for example, 0.4 V and 3.3 V. Other voltages may be used.

[0026] In some embodiments, Figure 2B As shown, gate drivers 232 and 234 can operate as inverters. In other embodiments, gate drivers 232 and 234 can operate as buffers or level shifters.

[0027] Voltage V H and V L , respectively, are generated by shared internal regulators 220 and 222. The internal regulators 220 and 222 may be implemented as, for example, LDOs without external compensation capacitors (outside the IC of the CMOS image sensor 250).

[0028] In some image sensors, it may be advantageous to limit the number of LDOs, for example, to reduce power consumption. In some embodiments, sharing regulators 220 and 222 across gate drivers 232 and 234 of all pixels of CMOS image sensor 250 advantageously minimizes power consumption of the CMOS image sensor, compared to using two dedicated regulators for all gate drivers 232 and two additional dedicated regulators for all gate drivers 234.

[0029] Figure 3 shows a signal S of the pixel 200 according to an embodiment of the present invention. 208 and S 210 waveform. Figure 4 A possible implementation of gate drivers 232 and 234 according to an embodiment of the present invention is shown. Figure 4 Parasitic capacitances 402 , 404 , 406 , and 408 are also shown.

[0030] In some embodiments, internal regulators 220 and 222 have no external capacitors (external to the IC of CMOS image sensor 250). Capacitors 406 and 408 (which may be a combination of parasitic capacitors and actual internal capacitors, or just parasitic capacitors) may be relatively small. For example, in some embodiments, capacitors 406 and 408 may be on the order of pF, such as 50 pF.

[0031] In rolling mode, a subset (eg, a row) of all pixels 200 of the CMOS image sensor 250 are simultaneously activated. The capacitances 402 and 404 of the activated pixels 200 may be in the order of pF, such as 1 pF to 3 pF.

[0032] In global shutter mode, all pixels 200 of CMOS image sensor 250 are activated simultaneously. Depending on the number of rows in global mode, the capacitances 402 and 404 of pixels 200 activated during global shutter mode may be greater than 100 times (such as greater than 1000 times) the capacitances 402 and 404 of pixels 200 during rolling mode. For example, in some embodiments, the capacitances 402 and 404 may be in the order of nF, such as 2.4 nF.

[0033] In some embodiments, aggregate capacitances 402 and 404 of activated pixel 200 are at least 50 times higher than capacitances 406 and 408 .

[0034] The inventors have noticed that during the global shutter mode, if the current I 224 ,I 226 ,I 228 and I 230 If not limited or controlled (e.g., due to charge transfer between capacitors 402 and 404 and capacitors 406 and 408, where capacitors 402 and 404 are larger than capacitors 406 and 408), then during the switching period of storage control transistors 208 and 210, the voltage rail V H and V L For example, Figure 5 shows that during global shutter mode and without limiting the current I 224 ,I 226 ,I 228 and I 230 The high voltage rail V H , low voltage rail V L and signal S 210 and S 208 Possible waveforms. Figure 5 In the example shown, the voltage rail V H and V L The target values ​​are 3.3V and 0.4V respectively.

[0035] In some embodiments, LDO 220 and LDO 222 may be sized to independently drive S 208 or S 210 , and also be able to drive them simultaneously. In some embodiments, the LDO size may be constrained by power consumption and silicon area. 208 and / or S 210 Some embodiments advantageously avoid the problem of the slew rate of the current flowing into the output of LDO 220 and / or LDO 222 by controlling the slew rate of the current flowing into the output of LDO 220 and / or LDO 222. 208 and S 210 The independent control period may be controlled by LDO 220 and LDO 222 with signal S 208 and S 210 Artifacts caused by interference caused by interactions between them.

[0036] like Figure 5 As shown, when the signal S 210 At time t 4 When changing from high to low (eg, by current I flowing from capacitor 404 from all pixels 200), 230 ) Low voltage rail V L The spike in is generated into capacitor 408. The low voltage rail V L This voltage spike in the signal can be high enough to boost the signal S 208 At an unexpected time (e.g., at time t 4 ) turns on or partially turns on the storage control transistor 208.

[0037] In an embodiment of the present invention, a gate driver coupled to a voltage rail controls a gate of a storage control transistor and controls or limits a slew rate of current flowing from the gate of the storage control transistor into the voltage rail via the gate driver during a slew of the storage control transistor, for example, to reduce voltage spikes in the voltage rail.

[0038] In some embodiments, the slew rate of current flowing into or out of the voltage rail is controlled by adjusting the rdson of a transistor coupled between the gate driver and the voltage rail. Figure 4 As shown, the controller 450 uses the signal S 412 and S 416 The rdson of transistors 412 and 416 (i.e., the on-resistance of the current path of the transistors) is controlled to limit the current flowing into the low voltage rail V L In some embodiments, the current flowing into or out of the low voltage rail V L The initial current is related to the difference between the high voltage rail and the low voltage rail (V H -V L ) and inversely proportional to the rdson of transistors 412 and 416.

[0039] In some embodiments, the current slew rate is limited based on the output capability of the regulator. For example, if the regulator 222 has an I 220 The maximum driving current of the capacitor 408 is limited in conversion rate, so that the conversion rate of the current flowing into the capacitor 408 is No more than I 220 .

[0040] The controller 450 may use the signal S 410 and S 414 The rdson of control transistors 410 and 414 is similarly limited to flow into or out of the high voltage rail V H of current.

[0041] In some embodiments, the controller 450 is implemented inside each gate driver 232 and 234. The controller 450 may also be implemented outside the gate drivers 232 and 234.

[0042] In some embodiments, the controller 450 only generates a 208 and S 210 414 and 416 during the transition period, and fully turn on transistors 410, 412, 414 and 416 during the rest of the time. Controller 450 regulates the flow of current into or out of the voltage rail V L and V H The switching time of the switching rate of the current may have a duration in the order of μs, such as 3 μs to 5 μs. Different durations may also be used.

[0043] In some embodiments, slew rate control advantageously allows sharing of regulators for multiple control switches, which may advantageously reduce power consumption and / or silicon area.

[0044] Figure 6 A possible implementation of a controller 450 for controlling the slew rate of transistor 416 is shown in accordance with an embodiment of the present invention. It should be understood that controller 450 may also implement similar circuits for controlling the slew rates of transistors 410, 412, and 414.

[0045] During normal operation, the reference current I ref Can be set to the first value I ref1 (which fully turns on transistor 416). 210 and / or S 208 During the conversion period, the reference current I ref can be set to limit the current I 230 The second value I ref2 The second value Iref2 Can be based on the voltage rail V H and V L and the capacitances 402, 404, 406 and 408. It should be understood that the first value I ref1 and the second value I ref2 It may also be based on the ratio of the current mirror 610 .

[0046] In some embodiments, the current I ref1 and I ref2 Can be generated by a single current source (eg, by adjusting the magnitude of the current). In other embodiments, the current I ref1 and I ref2 Each of the currents I is generated by a dedicated current source that is multiplexed based on the current to be injected into transistor 602. ref1 and I ref2 can be generated by varying the ratio of current mirror 610. Other implementations are also possible.

[0047] The inventors note that in embodiments that implement both a global shutter mode (e.g., for image acquisition) and a rolling mode (e.g., for image recovery), slew rate control that prevents spikes in the voltage rails during global shutter mode can slow down operation during rolling mode, which can result in readout data errors.

[0048] In some embodiments, slew rate control allows reducing regulator drive capability and consumption, and independently controlling timing sequences for global shutter mode and rolling mode.

[0049] In an embodiment of the present invention, the slew rate control is based on the operating mode of the CMOS image sensor (e.g., global shutter mode or rolling mode). For example, in some embodiments, the ratio of the current mirror 610 is 1:1 during the rolling mode and M:1 during the global mode, where M is higher than 1, such as 100. Other values ​​(greater than 100 or less than 100) may also be used. In some embodiments, the value of M is based on the ratio of the capacitors 402 and 404 during the global shutter mode, and the ratio of the capacitors 402 and 404 during the rolling mode.

[0050] Figure 7 A possible implementation of a controller 450 for controlling the slew rate of transistor 416 is shown in accordance with an embodiment of the present invention. It should be understood that controller 450 may also implement similar circuits for controlling the slew rates of transistors 410, 412, and 414.

[0051] During the global shutter mode, the signal GLB_EN is asserted (eg, high) and the signal ROL_EN is deasserted (eg, low). During the rolling mode, the signal GLB_EN is deasserted (eg, low) and the signal ROL_EN is asserted (eg, high).

[0052] like Figure 7 As shown, during the global shutter mode, current mirror 710 is enabled (switch 704 is open and switch 706 is closed), while current mirror 760 is disabled (switch 754 is closed and switch 756 is open).

[0053] In global shutter mode, the reference current I 702 The value of M, the number of transistors activated from the plurality of transistors 708 (eg, using switch 709), and the value of M generate the current I 602a To control the current I 230 slew rate, for example, to avoid low voltage rails V L The peak in the.

[0054] In rolling mode, the reference current I 752 The value of N, the number of transistors activated from the plurality of transistors 758 (eg, using switch 759), and the value of N generate the current I 602b To control the current I 230 The switching rate may be increased, for example, to avoid readout data errors (e.g., by allowing more current and, therefore, making the circuit faster when compared to a global shutter mode).

[0055] In some embodiments, N is equal to 1. In some embodiments, the current I 702 Can be greater than the current I 752 In some embodiments, switches 709 and 759 may be avoided. In some embodiments, switches 706 and 756 may be avoided (eg, by enabling / disabling transistors 708 and 758 in another manner).

[0056] Switches 704, 706, 709, 754, 756, and 759 may be implemented in any manner known in the art, such as by using MOSFETs.

[0057] like Figure 7As shown, by having dedicated slew rate control circuits for global shutter mode (e.g., circuit 701) and rolling mode (e.g., 751), some embodiments advantageously avoid spikes in the voltage rails during global shutter mode and avoid readout data errors during rolling mode, while optimizing power consumption by sharing internal regulators (e.g., 220 and 222). Some embodiments allow the use of internal regulators (e.g., 220 and 222) without external compensation capacitors (regulators without output capacitors), thereby advantageously reducing the number of pins of the image sensor and / or the occupied area in the PCB.

[0058] Figure 8 shows the high voltage rail V during global shutter mode according to an embodiment of the present invention. H , low voltage rail V L and signal S 210 and S 208 waveform. Figure 8 The waveform corresponds to a Figure 7 Waveforms for pixel 200 of controller 450 implemented as shown.

[0059] like Figure 8 As shown, in some embodiments, the controller 450 only operates at time Δt 1 and Δt 2 (via transistors 410 and / or 414) and time Δt 3 and Δt 4 (via transistors 412 and / or 416) during which slew rate control is applied. In some embodiments, time Δt 1 Equal to time Δt 2 , and time Δt 3 Equal to time Δt 4 .

[0060] like Figure 8 As shown, at time Δt 4 During this period, the low voltage rail V L The low-frequency component of the peak (can be coupled to the signal S 208 frequency component) does not exceed 50mV (with Figure 5 ) and the spike to signal S 208 The corresponding coupling of is advantageously less than the turn-on threshold of transistor 208 (which may be, for example, 0.5V to 0.6V) and does not cause transistor 208 to turn on. Figure 8 As shown, at time Δt 2 During this period, the high voltage rail V H The low frequency component of the peak does not exceed 50mV (with Figure 5 compared to about 2.5V in ).

[0061] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the overall description and claims submitted herein.

[0062] Example 1: An image sensor includes: a first voltage rail and a second voltage rail; a first regulator having an output coupled to the first voltage rail and configured to generate a first regulated voltage; a second regulator having an output coupled to the second voltage rail and configured to generate a second regulated voltage lower than the first regulated voltage; and a plurality of pixels coupled to the first voltage rail and the second voltage rail, wherein each of the plurality of pixels includes: a first storage capacitor and a second storage capacitor; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between a control terminal of the first transistor and the first voltage rail or the second voltage rail, wherein the third transistor is configured to limit a slew rate of a current flowing between the control terminal of the second transistor and the first voltage rail or the second voltage rail to a first slew rate when the image sensor is operated in a global shutter mode (e.g., for image acquisition), and to limit a slew rate of a current flowing between the control terminal of the second transistor and the first voltage rail or the second voltage rail to a second slew rate when the image sensor is operated in a rolling mode (e.g., for image readout), the first slew rate being less than the second slew rate.

[0063] Example 2: An image sensor according to Example 1, wherein the third transistor is configured to limit a conversion rate of a current between a control terminal of the second transistor and the first voltage rail or the second voltage rail to a first conversion rate only during a conversion of the first transistor or the second transistor from a first state to a second state.

[0064] Example 3: The image sensor of one of Examples 1 or 2, wherein the first state is high and corresponds to a first regulated voltage, and wherein the second state is low and corresponds to a second regulated voltage.

[0065] Example 4: The image sensor of one of Examples 1 to 3, wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail.

[0066] Example 5: An image sensor according to one of Examples 1 to 4, wherein each pixel further includes a fourth transistor coupled between a control terminal of the first transistor and the first voltage rail or the second voltage rail, wherein the fourth transistor is configured to limit a conversion rate of a current flowing between the control terminal of the first transistor and the first voltage rail or the second voltage rail to a first conversion rate when the image sensor operates in a global shutter mode, and to limit a conversion rate of a current flowing between the control terminal of the first transistor and the first voltage rail or the second voltage rail to a second conversion rate when the image sensor operates in a rolling mode, the first conversion rate being less than the second conversion rate.

[0067] Example 6: An image sensor according to one of Examples 1 to 5, wherein the aggregate capacitance of the control terminal of each second transistor of an activated pixel in the plurality of pixels is at least 100 times greater during a global shutter mode than during a rolling mode.

[0068] Example 7: An image sensor according to one of Examples 1 to 6, wherein, during a global shutter mode, an aggregate capacitance at a control terminal of each second transistor of an activated pixel in a plurality of pixels is at least 50 times greater than a capacitance associated with the first voltage rail or the second voltage rail.

[0069] Example 8: The image sensor of one of Examples 1 to 7, wherein each pixel further comprises a first current mirror comprising a third transistor and a fourth transistor.

[0070] Example 9: The image sensor of one of Examples 1 to 8, wherein the first current mirror has a ratio of M:1, wherein M is a positive integer greater than 1.

[0071] Example 10: An image sensor according to one of Examples 1 to 9, wherein M is 100.

[0072] Example 11: An image sensor according to one of Examples 1 to 10, each pixel also includes a second current mirror coupled between a control terminal of the second transistor and the first voltage rail or the second voltage rail, wherein the first current mirror is disabled during the rolling mode, and wherein the second current mirror is disabled during the global shutter mode.

[0073] Example 12: The image sensor of one of Examples 1 to 11, wherein the second current mirror has a ratio of 1:1.

[0074] Example 13: An image sensor according to one of Examples 1 to 12, wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail, and wherein each pixel further includes: a first switch coupled between the second voltage rail and the control terminal of the third transistor; and a second switch coupled between the second voltage rail and the second current mirror, wherein the first switch is configured to be turned on during the rolling mode, and wherein the second switch is configured to be turned on during the global shutter mode.

[0075] Example 14: An image sensor according to one of Examples 1 to 13, wherein each pixel further comprises a clamped photodiode.

[0076] Example 15: An image sensor according to one of Examples 1 to 14, wherein each pixel further includes: a fourth transistor having a control terminal coupled to the clamped photodiode; and a current patch coupled to the current path of the first transistor.

[0077] Example 16: A method comprising: generating a first voltage at a first voltage rail coupled to a plurality of pixels of an image sensor; generating a second voltage at a second voltage rail coupled to the plurality of pixels, wherein the second voltage is different from the first voltage; transitioning a first signal at a control terminal of a first transistor from the first voltage to a second voltage, wherein the first transistor has a current path coupled to a first storage capacitor; after transitioning the first signal from the first voltage to the second voltage, transitioning a second signal at a control terminal of a second transistor from the first voltage to the second voltage, wherein the second transistor has a current path coupled to a second storage capacitor; after transitioning the second signal from the first voltage to the second voltage, transitioning the second signal from the second voltage to the first voltage; and during the transition of the second signal from the second voltage to the first voltage, when the image sensor is in a global shutter mode, limiting a slew rate of a current flowing between a control terminal of the first transistor or the second transistor and the first voltage rail to a first slew rate, and when the image sensor is in a rolling mode, limiting a slew rate of a current flowing between a control terminal of the first transistor or the second transistor and the first voltage rail to a second slew rate, wherein the first slew rate is less than the second slew rate.

[0078] Example 17: The method of Example 16, wherein the first voltage is approximately 0.4V and the second voltage is approximately 3.3V.

[0079] Example 18: The method according to one of Examples 16 or 17, further comprising: after converting the second signal from the second voltage to the first voltage, converting the first signal from the second voltage to the first voltage.

[0080] Example 19: An integrated circuit comprising: a first internal LDO configured to generate a first regulated voltage at a first voltage rail, wherein the first internal LDO is not coupled to a compensation capacitor external to the integrated circuit; a second internal LDO configured to generate a second regulated voltage at a second voltage rail, wherein the second internal LDO is not coupled to a compensation capacitor external to the integrated circuit, and wherein the second regulated voltage is lower than the first regulated voltage; and an image sensor comprising a plurality of image sensor pixels arranged in rows and columns and coupled to the first voltage rail and the second voltage rail, wherein each of the plurality of image sensor pixels comprises: a first storage voltage; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between a control terminal of the first transistor and a second voltage rail, wherein the third transistor is configured to limit a slew rate of current flowing between the control terminal of the first transistor and the second voltage rail to a first slew rate when the image sensor is operated in a global shutter mode, and to limit a slew rate of current flowing between the control terminal of the first transistor and the second voltage rail to a second slew rate when the image sensor is operated in a rolling mode, the first slew rate being less than the second slew rate.

[0081] Example 20: An integrated circuit according to Example 19, wherein the third transistor is configured to limit the conversion rate of the current between the control terminal of the second transistor and the second voltage rail to a first conversion rate only during the transition of the second transistor from a first state to a second state, wherein the first state corresponds to a first regulation voltage, and wherein the second state corresponds to a second regulation voltage.

[0082] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An image sensor, include: a first voltage rail and a second voltage rail; a first regulator having an output coupled to the first voltage rail and configured to generate a first regulated voltage; a second regulator having an output coupled to the second voltage rail and configured to generate a second regulated voltage lower than the first regulated voltage; as well as a plurality of pixels coupled to the first voltage rail and the second voltage rail, wherein each pixel of the plurality of pixels comprises: a first storage capacitor and a second storage capacitor; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between the control terminal of the first transistor and the first voltage rail or the second voltage rail, wherein the third transistor is configured to: when the image sensor operates in a global shutter mode, limit a slew rate of a current flowing between the control terminal of the second transistor and the first voltage rail or the second voltage rail to a first slew rate, and when the image sensor operates in a rolling mode, limit a slew rate of a current flowing between the control terminal of the second transistor and the first voltage rail or the second voltage rail to a second slew rate, the first slew rate being less than the second slew rate.

2. The image sensor of claim 1 , wherein the third transistor is configured to limit the slew rate of the current between the control terminal of the second transistor and the first voltage rail or the second voltage rail to the first slew rate only during a transition of the first transistor or the second transistor from a first state to a second state. 3 . The image sensor of claim 2 , wherein the first state is high and corresponds to the first regulation voltage, and wherein the second state is low and corresponds to the second regulation voltage. 4 . The image sensor of claim 1 , wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail.

5. The image sensor of claim 1 , wherein each pixel further comprises a fourth transistor coupled between a control terminal of the first transistor and the first voltage rail or the second voltage rail, wherein the fourth transistor is configured to: when the image sensor operates in a global shutter mode, limit a slew rate of a current flowing between the control terminal of the first transistor and the first voltage rail or the second voltage rail to the first slew rate, and when the image sensor operates in a rolling mode, limit a slew rate of a current flowing between the control terminal of the first transistor and the first voltage rail or the second voltage rail to the second slew rate, the first slew rate being less than the second slew rate.

6. The image sensor of claim 1, wherein an aggregate capacitance of a control terminal of each of the second transistors of an activated pixel of the plurality of pixels is at least 100 times greater during a global shutter mode than during a rolling mode.

7. The image sensor of claim 1 , wherein during a global shutter mode, an aggregate capacitance at a control terminal of each of the second transistors of an activated pixel of the plurality of pixels is at least 50 times greater than a capacitance associated with the first voltage rail or the second voltage rail. 8 . The image sensor of claim 1 , wherein each pixel further comprises a first current mirror, the first current mirror comprising the third transistor and the fourth transistor. 9 . The image sensor of claim 8 , wherein the first current mirror has a ratio of M:1, wherein M is a positive integer greater than 1. 10 . The image sensor according to claim 9 , wherein M is 100.

11. The image sensor of claim 8 , each pixel further comprising a second current mirror coupled between the control terminal of the second transistor and the first voltage rail or the second voltage rail, wherein the first current mirror is disabled during a rolling mode, and wherein the second current mirror is disabled during a global shutter mode. 12 . The image sensor of claim 11 , wherein the second current mirror has a ratio of 1:

1.

13. The image sensor of claim 11 , wherein the third transistor is coupled between the control terminal of the second transistor and the second voltage rail, and wherein each pixel further comprises a include: a first switch coupled between the second voltage rail and a control terminal of the third transistor; as well as A second switch is coupled between the second voltage rail and the second current mirror, wherein the first switch is configured to be turned on during a rolling mode, and wherein the second switch is configured to be turned on during a global shutter mode.

14. The image sensor of claim 1, wherein each pixel further comprises a clamped photodiode.

15. The image sensor according to claim 14, wherein each pixel further include: a fourth transistor having a control terminal coupled to the clamped photodiode; and a current patch coupled to the current path of the first transistor.

16. A conversion rate control method for an image sensor, include: generating a first voltage at a first voltage rail, the first voltage rail being coupled to a plurality of pixels of an image sensor; generating a second voltage at a second voltage rail, the second voltage rail being coupled to the plurality of pixels, wherein the second voltage is different from the first voltage; converting a first signal at a control terminal of a first transistor from the first voltage to the second voltage, wherein the first transistor has a current path coupled to a first storage capacitor; after changing the first signal from the first voltage to the second voltage, changing a second signal at a control terminal of a second transistor from the first voltage to the second voltage, wherein the second transistor has a current path coupled to a second storage capacitor; After converting the second signal from the first voltage to the second voltage, converting the second signal from the second voltage to the first voltage; as well as During a transition of the second signal from the second voltage to the first voltage, a slew rate of a current flowing between the control terminal of the first transistor or the second transistor and the first voltage rail is limited to a first slew rate when the image sensor is in a global shutter mode, and a slew rate of a current flowing between the control terminal of the first transistor or the second transistor and the first voltage rail is limited to a second slew rate when the image sensor is in a rolling mode, wherein the first slew rate is less than the second slew rate. The method of claim 16 , wherein the first voltage is 0.4V, and the second voltage is 3.3V.

18. The method according to claim 16, further comprising: include: After the second signal is converted from the second voltage to the first voltage, the first signal is converted from the second voltage to the first voltage.

19. An integrated circuit, include: a first internal LDO configured to generate a first regulated voltage at a first voltage rail, wherein the first internal LDO is not coupled to a compensation capacitor external to the integrated circuit; a second internal LDO configured to generate a second regulated voltage at a second voltage rail, wherein the second internal LDO is not coupled to a compensation capacitor external to the integrated circuit, and wherein the second regulated voltage is lower than the first regulated voltage; as well as An image sensor comprising a plurality of image sensor pixels arranged in rows and columns and coupled to the first voltage rail and the second voltage rail, wherein each image sensor pixel of the plurality of image sensor pixels comprises: a first storage capacitor and a second storage capacitor; a first transistor having a current path coupled to the first storage capacitor; a second transistor having a current path coupled to the second storage capacitor; and a third transistor coupled between the control terminal of the first transistor and the second voltage rail, wherein the third transistor is configured to: limit a slew rate of a current flowing between the control terminal of the first transistor and the second voltage rail to a first slew rate when the image sensor operates in a global shutter mode, and to limit a slew rate of a current flowing between the control terminal of the first transistor and the second voltage rail to a second slew rate when the image sensor operates in a rolling mode, the first slew rate being less than the second slew rate.

20. The integrated circuit of claim 19, wherein the third transistor is configured to limit the slew rate of current between the control terminal of the second transistor and the second voltage rail to the first slew rate only during a transition of the second transistor from a first state to a second state, wherein the first state corresponds to the first regulation voltage, and wherein the second state corresponds to the second regulation voltage.

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