Graphene-based TFT including a nitrogen-doped graphene layer as an active layer

Abstract

The present invention relates to a high-quality, highly functional graphene-based thin film transistor (TFT) including a nitrogen-doped graphene layer as an active layer, and more specifically to a graphene-based TFT, which includes: a gate electrode; a gate insulating layer located on the gate electrode; an active layer located in a portion of the gate insulating layer, including a nitrogen-doped graphene layer; a first electrode located on a side region of the active layer; and a second electrode located on another side region of the active layer. In this invention, graphene can be grown directly on a Ti layer, and after being damaged by remote plasma, a graphene active layer is prepared by nitrogen doping, thereby obtaining a TFT with very excellent characteristics.

Description

Technical Field

[0001] The present invention relates to a high-quality, high-functionality graphene-based TFT comprising as an active layer a graphene layer grown directly on a Ti layer and then doped with nitrogen. Background Art

[0002] Recently, with the rapid development of information technology, we have entered the era of ubiquitous computing, where information can be accessed anytime and anywhere. As a result, the importance of new electronic components such as information transmission media and storage media that transmit a variety of information has gradually increased. In particular, consumer demand for displays exceeds the market supply and technology level, and the importance of development is increasing. In addition to light and thin thickness, high resolution, fast screen switching speed, and large area characteristics, the next generation of displays is strongly required to achieve environmental protection, low power consumption, ultra-high resolution, low-cost large area, flexibility, design, transparency, and actual images (3-Dimension).

[0003] Thin film transistors (TFT) are the main circuit substrates for supplying power, etc. to the backplane of the display, and they are responsible for the core role of driving the display. Therefore, if you want to achieve ultra-high resolution, fast screen switching speed, large screen characteristics, etc., which are the core technologies of the next generation of displays, the technology of thin film transistors needs to be further developed. In the past, thin film transistors using amorphous silicon as the active layer, low temperature polycrystalline silicon (LTPS) thin film transistors, indium gallium zinc oxide (IGZO) thin film transistors, etc. have been developed, or these have received much attention. However, these still have complex manufacturing processes and high production costs. In addition, although they are highly flexible, they are difficult to apply to resin substrates with low thermal stability compared to inorganic substrates such as glass substrates, and are therefore difficult to apply to flexible displays.

[0004] Graphene is a nanomaterial with a two-dimensional honeycomb structure and a thickness of one carbon atom. Theoretically, it has a diameter of 200,000 cm 2It has an electron mobility of 1000 v-1s-1, a thermal conductivity of ~5000 Wm-1K-1, a Young's modulus of ~1.0 TPa, and physical and chemical stability. It has an outstanding characteristic of having a transmittance of about 98% in the visible light region, as it absorbs very little visible light due to its thickness at the atomic layer level. In particular, graphene can make electrons migrate more than 100 times faster than single crystal silicon. In this regard, it has attracted much attention as a next-generation material that can replace silicon in existing silicon-based semiconductor devices and be used in flexible, transparent electronic devices. However, graphene has no band gap and has metallic characteristics. The on-off ratio of the working current is extremely small, and the flow of current cannot be controlled by electrical signals. This shortcoming is a decisive obstacle when it is used in electronic components such as semiconductors or transistors.

[0005] In this regard, many attempts have been made to give graphene an appropriate band gap to increase the on-off ratio of the operating current. For example, attempts have been made to create methods that destroy the symmetry of the graphene crystal structure presented by the lattice mismatch between graphene and the substrate, or to form a nanobelt morphology pattern, or to change the chemical composition of graphene, or to make a hybrid structure of a specific layer with semiconductor properties and graphene stacked. However, it is difficult to produce high-quality graphene, difficult to realize the produced graphene as a nanobelt structure, difficult to adjust the physical properties of graphene, and the increased on-off ratio is about several to several thousand, which is still worse than the on-off ratio of 10 based on silicon TFTs used in industry. 4 , which becomes an inhibitory factor for mass integration of components and high-speed driving. Summary of the invention

[0006] Technical issues

[0007] As can be seen, even though graphene itself has excellent properties, it has been difficult to provide high-quality graphene with a low on-off ratio, and it has been impossible to achieve integration of semiconductor devices or transistors using graphene as a raw material.

[0008] Therefore, an object of the present invention is to provide a graphene-based TFT using high-quality graphene and having an on-off ratio sufficient for practical use, a low threshold voltage, a high mobility, and a low subthreshold swing.

[0009] Technical Solution

[0010] The present invention for achieving the above-mentioned purpose is characterized in that a graphene-based TFT includes: a gate electrode; a gate insulating layer located on the above-mentioned gate electrode; an active layer located in a portion of the area on the above-mentioned gate insulating layer, including a nitrogen-doped graphene layer; a first electrode located on a side area of ​​the above-mentioned active layer; and a second electrode located on another side area of ​​the above-mentioned active layer.

[0011] Effects of the Invention

[0012] The graphene-based TFT of the present invention as described above has a fast charge transfer speed and a sufficiently high on-off ratio, and can be applied as a highly integrated semiconductor, transistor, etc.

[0013] Furthermore, according to the present invention, when forming an active layer, graphene is continuously synthesized in the same device and nitrogen is doped therein, which can reduce the production cost by simplifying the production process and achieve high quality of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a conceptual three-dimensional diagram of a thin film transistor of the present invention.

[0015] Figure 2 and Figure 3 Each of the graphs shows a preliminary experiment result for determining the transistor manufacturing process conditions in the embodiment of the present invention.

[0016] Figures 4 to 6 They are conceptual diagrams of thin film transistors manufactured according to embodiments of the present invention.

[0017] Figure 7 to Figure 9 The following are graphs respectively showing the operating characteristics of the thin film transistors manufactured according to the embodiments of the present invention.

[0018] Fig.10 This is a graph showing the stability of the device of Production Example 3 in the embodiment of the present invention.

[0019] Description of Reference Numerals

[0020] 110: substrate 120: gate electrode

[0021] 130: Gate insulating layer 140: Active layer

[0022] 151: first electrode 152: second electrode DETAILED DESCRIPTION

[0023] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. However, this description is only an illustration for easily illustrating the content and scope of the technical idea of ​​the present invention, and the technical scope of the present invention is not limited thereto or changed. Based on this illustration, various deformations and changes can be made within the scope of the technical idea of ​​the present invention, which is obvious to a person skilled in the art of the present invention. In the following figures, the size, thickness, shape, etc. of each structural element may be exaggerated or simplified.

[0024] In this specification, "upper part" or "on" or "above" may include not only directly contacting each other and being located directly on each other, but also another layer being located non-contactingly on each other as a medium. Also, in this specification, "A (layer) / B (layer)" means that the (A) layer is directly contacting and stacked on the B (layer).

[0025] The present invention relates to a TFT, characterized in that it has an active layer including a nitrogen-doped graphene layer. More specifically, the present invention is characterized in that the graphene-based TFT includes: a gate electrode; a gate insulating layer located on the gate electrode; an active layer located in a portion of the gate insulating layer, including a nitrogen-doped graphene layer; a first electrode located on a side region of the active layer; and a second electrode located on another side region of the active layer.

[0026] Figure 1 A conceptual perspective view showing a thin film transistor according to an embodiment of the present invention. Figure 1 The illustrated thin film transistor is a thin film transistor of a bottom gate structure in which a gate electrode 120 is disposed below an active layer 140. The gate electrode 120 may be disposed on a substrate 110. The substrate 110 may be a glass substrate, but may be other substrates, for example, a plastic substrate or a silicon substrate, and one of a variety of substrates used in conventional semiconductor device processes. The gate electrode 120 may be formed of a general conductive material, for example, a metal, polysilicon, a conductive oxide, etc. In the embodiment of the present invention, highly-doped p-Si and directly grown graphene are applicable.

[0027] A gate insulating layer 130 is provided covering the gate electrode 120. The gate insulating layer 130 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, but may also include other material layers, for example, a high dielectric material layer having a dielectric constant greater than that of the silicon nitride layer. The gate insulating layer 130 may have a structure in which at least two or more layers of such high dielectric material layers are stacked. SiO2 and Al2O3 are applicable in the embodiments of the present invention.

[0028] An active layer 140 including a nitrogen-doped graphene layer is provided on the gate insulating layer 130 of the TFT of the present invention. At this time, the nitrogen-doped graphene layer is preferably a layer formed by an in-situ growth method, that is, a graphene layer is deposited in an oxygen-free atmosphere and continuously doped, for example, a graphene layer is continuously deposited in the same device and doped with nitrogen.

[0029] In the drawing, the width of the active layer 140 is shown to be slightly smaller than the width of the gate electrode 120 , but may be similar to or larger than the width of the gate electrode 120 according to circumstances.

[0030] On the active layer 140 of the TFT of the present invention, a first electrode 151 and a second electrode 152 may be provided, which are in contact with the active layer 140 in a mutually spaced state in the first region and the second region. The first electrode 151 may be in contact with one end of the active layer 140, and the second electrode 152 may be in contact with the other end of the active layer 140. The first electrode 151 and the second electrode 152 may be formed of a general conductive material, such as metal, polysilicon, conductive oxide, etc. In the embodiment of the present invention, Au / Ti and graphene / Ti are suitable as the first electrode 151 and the second electrode 152.

[0031] When the first electrode 151 and the second electrode 152 include a conductive material layer and a Ti layer, preferably, the Ti layer is deposited in an oxygen-free atmosphere and then the conductive material layer is deposited, for example, Ti and the conductive material are continuously deposited in the same equipment.

[0032] The first electrode 151, the second electrode 152 and the gate electrode 120 may be the same material layer. The first electrode 151 and the second electrode 152 may be a single layer or multiple layers. The morphology and position of the first electrode 151 and the second electrode 152 may be different. For example, the first electrode 151 may have a structure extending from one end of the active layer 140 to the region of the gate insulating layer 130 adjacent thereto, and similarly, the second electrode 152 may have a structure extending from the other end of the active layer 140 to the region of the gate insulating layer 130 adjacent thereto. Furthermore, the first electrode 151 and the second electrode 152 may be arranged to contact the other two regions instead of the two ends (i.e., one end and the other end) of the active layer 140.

[0033] Although in Figure 1 Although not shown in the figure, the thin film transistor of the present invention may also be provided with an etching stop layer covering the active layer 140. The etching stop layer plays a role in preventing the active layer 140 from being damaged by the etching in the etching process for forming the first electrode 151 and the second electrode 152. The etching stop layer may include silicon oxide, silicon nitride, an organic insulator, etc. At this time, the first electrode 151 and the second electrode 152 are electrically connected to the active layer 140 through a predetermined hole formed in the etching stop layer.

[0034] The TFT of the present invention may be provided with a common protection layer (not shown) covering the exposed gate electrode 120, the gate insulating layer 130, the active layer 140, the first electrode 151 and the second electrode 152. The protection layer may have a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer or an organic insulating layer, or a structure in which at least two of these are stacked.

[0035] The TFT of the present invention as described above can implement the active layer forming step in the manner as described below.

[0036] First, a shadow mask corresponding to the morphology of the active layer formed on the gate insulating layer is attached, and a titanium film with a thickness of 3 to 10 nm is deposited. Then, an oxygen-free atmosphere is maintained, and a graphene film is grown on the titanium film in situ by remote plasma-assisted chemical vapor deposition. Thus, in the present invention, without a transfer process, the graphene layer is stably and closely formed on the gate insulating layer with the titanium layer as a medium. The graphene film thus grown is subjected to remote plasma treatment, so that the graphene film is subjected to prescribed damage. The plasma treatment conditions for appropriate damage are described in the following embodiments. Then, the damaged graphene film is exposed to remote plasma in an N2 atmosphere to be doped with nitrogen. In the absence of such a transfer process, a graphene layer is directly formed in situ, and a high-quality and high-stability TFT can be realized. In the following embodiments, a shadow mask is attached to the gate insulating layer before forming the titanium film, but depending on the situation, a method of patterning the active layer can be selected in any step of "after forming the titanium film to after doping the graphene layer with nitrogen".

[0037] Although not shown in the figure, it was confirmed that when the TFT fabricated in this way was exposed to the outside, the Ti layer under the graphene layer was partially oxidized and converted into TiO 2-x In this regard, in this specification, depending on the time point, "graphene / Ti" or "graphene / TiO" is used interchangeably. 2-x ”.

[0038] Preferably, the TFT of the present invention is subjected to an annealing process at 100 to 400° C. for a specified time after fabrication. This is used to remove plasma damage that may be generated during the deposition of the first electrode and the second electrode, and does not directly affect the properties of N-doped graphene. As confirmed in the following examples, the operating characteristics of the transistor are significantly improved by appropriate annealing. The annealing temperature and time are roughly asymmetric, so a person skilled in the art of the present invention can select appropriate annealing conditions.

[0039] In the above description, the bottom-gate thin film transistor is mainly used, but the gate electrode 120, the gate insulating layer 130, the active layer 140, the first electrode 151 and the second electrode 152 may be connected to the gate electrode 120, the gate insulating layer 130, the active layer 140, the first electrode 151 and the second electrode 152. Figure 1 It is obvious to those skilled in the art that the present invention can be applied to thin film transistors with different but opposite top gate structures in the same or similar manner.

[0040] As confirmed in the following examples, for the thin film transistor of the present invention, I on / I off For 10 9The above, the mobility is more than 300, the Vth (threshold voltage) is less than 0.3V, and the subthreshold swing is less than 0.1V, indicating very excellent characteristics. Therefore, the thin film transistor of the present invention can be used as an active matrix display, for example, a liquid crystal display or an organic light emitting display, a pixel switching element or a driving element of a display such as a next generation high-resolution active matrix liquid crystal display (AMLCD) that provides ultra-high definition (UHD) images, an active matrix organic light emitting diode (AMO LED), etc. In addition, the thin film transistor of the present invention can be applied to other electronic components such as storage components and logic components for a variety of purposes.

[0041] Example

[0042] The thin film transistor of the present invention was produced and its characteristics were evaluated.

[0043] 1. Fabrication of thin film transistors

[0044] The TFT of the present invention is fabricated from the materials shown in Table 1 below for substrate-gate layer-gate insulating layer-active layer-electrode. In Fabrication Examples 1 and 2, the gate electrode functions as a substrate.

[0045] Table 1

[0046]

[0047] At this time, the active layer formation process is as follows: Forming a Ti layer on the gate insulating layer → Forming a graphene layer on the Ti layer → Graphene layer damage → Doping graphene layer " is achieved in a sequential manner, with each process and the processes between processes being performed in an oxygen-free atmosphere to a minimum.

[0048] (1) Formation of active layer

[0049] In the following production examples, the formation of the graphene layer, the damage conditions of the graphene layer, and the nitrogen-doping conditions of the damaged graphene layer were determined by preliminary experiments. However, the conditions determined in this way and other process conditions are not excluded.

[0050] ① Forming a graphene / Ti layer on the gate insulating layer

[0051] At 150°C, a titanium film with a thickness of 3 to 10 nm was deposited on an insulating layer of SiO2 (Example 1, Example 2) or Al2O3 (Example 3) by sputtering under the following conditions: 20 W of DC power, 0.4 Pa of working pressure, 3 minutes of deposition time, 10 cm of spacing between spray guns, and 10 cm of spacing between plasma and substrate.

[0052] Next, while maintaining the oxygen-free atmosphere continuously, a graphene layer was formed on the Ti layer under the conditions mentioned in Table 2 below.

[0053] Table 2

[0054] parameter Graphene synthesis conditions Injection gas <![CDATA[H2 / Ar / CH4=10 / 10 / 0.3sccm]]> Operating temperature 150℃ Work Pressure 1.8torr Plasma power 70W Working hours 2h TT distance 10cm TS distance 10cm

[0055] ②Determination of damage conditions of graphene layer

[0056] In order to determine the appropriate damage conditions for graphene before doping, the Ar plasma exposure time was adjusted. Figure 2 Under the conditions shown, the Ar plasma exposure time (at this time, the interval between the spray guns was 10 cm, and the interval between the plasma and the substrate was 13 cm) was changed to 15 seconds, 30 seconds, and 45 seconds, and the damage degree was confirmed by Raman peak, surface resistance, and transparency (refer to Figure 2 ). After each sample was damaged, the characteristics were compared with those of the original (Pristine) graphene. The sample exposed to Ar plasma for 15 seconds showed no change in the Raman peak and transparency, but was almost not etched (damaged) as judged by a slight increase in the surface resistance. For the sample exposed for 30 seconds, appropriate plasma damage was confirmed by the generation of a slight D peak (meaning a defect in the graphene) in the Raman peak, and it was confirmed that the graphene was also damaged in the surface resistance and transparency measurements. It was confirmed that the graphene in the Raman peak of the sample exposed for 45 seconds was completely etched and disappeared. Therefore, it was confirmed that it was appropriate to subject it to damage for about 30 seconds, for example, about 25 to 35 seconds, under the treatment conditions described above. However, the treatment time may vary depending on the treatment conditions or environment.

[0057] ③Determination of nitrogen-doping conditions of graphene layer

[0058] After Ar plasma treatment for 30 seconds, nitrogen was doped using N2 plasma. In order to adjust the appropriate doping level, the doping time was fixed at 30 seconds and the amount of N2 gas was adjusted to 0.3, 0.5, and 1.0 sccm. The sample exposed to N2 0.3 sccm plasma (at this time, the interval between the spray guns was 10 cm, and the interval between the plasma and the substrate was 13 cm) had a G peak of 1576 cm -1 1580cm in the middle -1It shows a typical nitrogen-doping peak effect. The surface resistance is also appropriately increased by the nitrogen-doping effect. After nitrogen doping, the transparency is similar to the transparency after Ar etching (before nitrogen doping). It is confirmed that the sample exposed to N20.3sccm plasma is not etched, but is appropriately doped with nitrogen. Raman measurement confirms that the sample exposed to N20.5, 1.0sccm plasma is etched to make the graphene disappear and form a slight CN (refer to Figure 3 ). It is confirmed that the inspection result gas is appropriately supplied at 0.3 sccm or less. At this time, the processing time may also be different depending on the processing conditions or environment.

[0059] (2) Production example 1

[0060] According to the conventional method, a SiO2 insulating layer is formed with a thickness of 100 nm on a highly doped p-Si. Next, on the insulating layer, in order to pattern the active layer, a shadow mask is attached to the substrate, and the Ti layer and the graphene layer are directly grown continuously under the above-mentioned conditions, and then the graphene layer is damaged without changing, and nitrogen is doped in the graphene layer to complete the active layer.

[0061] The first electrode / second electrode mask was precisely placed on the substrate with the active layer patterned, and a Ti layer (thickness of 10 nm) and an Au layer (thickness of 50 nm) were continuously deposited by sputtering under the following conditions to form the first electrode and the second electrode. [Ti layer: DC power of 20 W, base pressure of 6.6×10 -4 pa, working pressure is 0.4Pa, deposition time is 3 minutes / Au layer: DC power is 12W, base pressure is 6.6×10 -4 Pa, working pressure is 0.4 Pa, and deposition time is 3 minutes and 30 seconds]. In this production example, the Ti layer and the Au layer are used as the first electrode and the second electrode, but the use of a single layer of a conductive raw material is not excluded.

[0062] In the manufacturing example 1, the active layer is made to be approximately 800×1200 μm, the first electrode and the second electrode are made to be approximately 800 μm (width), and the interval between the first electrode and the second electrode is made to be approximately 200 μm (length) (refer to Figure 4 B). This is based on the size of the shadow mask of the present invention group. The smaller the size, the more improved the TFT characteristics are. Therefore, this manufacturing example does not limit the size of the active layer or the first electrode and the second electrode.

[0063] The transistors (see Figure 4 A) is annealed.

[0064] (3) Production example 2

[0065] The same method as in Preparation Example 1 was used except that a graphene layer (single layer, 0.4 nm thick) was directly grown on the Ti layer (10 nm thick) to form the first electrode and the second electrode. Figure 5 ).

[0066] (4) Production example 3

[0067] In the above manner, a Ti layer and a graphene layer were formed in situ on a polyimide substrate in an oxygen-free atmosphere as a gate electrode, and an Al2O3 (thickness of 40 nm) was used as a gate insulating layer. The same method as in Example 2 was used (refer to Figure 6 ).

[0068] 2. Characteristics of thin film transistors

[0069] The transfer curve, output curve, and transistor characteristics of the transistor fabricated in this manner are analyzed based on annealing conditions.

[0070] Although not shown in the figure, it was confirmed that when the TFT fabricated in this way was exposed to the outside, the Ti layer under the graphene layer was partially oxidized and converted into TiO 2-x .

[0071] (1) Fabrication Example 1 Transistor

[0072] like Figure 7 As shown, the transistor of the manufacturing example 1 of the present invention also shows 4.23×10 7 The extremely high on-off ratio, when combined with 72cm 2 / Vs mobility, 1.5V threshold voltage, 0.50V / decade compared to the existing nitrogen-doped graphene, it shows very excellent characteristics. It can be confirmed that when the transistor of Example 1 is heat-treated at 200, 250, and 300°C, the performance of the transistor gradually becomes excellent. This is explained by the fact that the defects generated between the active layer and the electrode layer interface when Au and Ti are deposited by direct current (DC) sputtering for the first electrode and the second electrode and the physical pressure generated when the electrode layer is deposited are relieved and eliminated by heat treatment to express the original characteristics of the nitrogen-doped graphene transistor.

[0073] As can be seen from Table 3 below, it can be seen that among the characteristics of this nitrogen-doped transistor, the current on / off ratio (I on / off ), fluidity, threshold voltage (threshold voltage), subthreshold swing (Subthreshold swing, SS), etc. are very excellent.

[0074] Table 3

[0075] parameter No annealing 200℃ 250℃ 300℃ <![CDATA[I on ]]> <![CDATA[1.13×10 -4 A]]> <![CDATA[4.31×10 -4 A]]> <![CDATA[6.60×10 -4 A]]> <![CDATA[6.90×10 -4 A]]> <![CDATA[I off ]]> <![CDATA[2.65×10 -12 A]]> <![CDATA[1.67×10 -12 A]]> <![CDATA[1.76×10 -13 A]]> <![CDATA[1.75×10 -13 A]]> <![CDATA[I on / I off ]]> <![CDATA[4.23×10 7 ]]> <![CDATA[4.97×10 8 ]]> <![CDATA[3.75×10 9 ]]> <![CDATA[3.84×10 9 ]]> Liquidity <![CDATA[72cm 2 / V.s]]> <![CDATA[127cm 2 / V.s]]> <![CDATA[301cm 2 / V.s]]> <![CDATA[303cm 2 / V.s]]> <![CDATA[V th ]]> 1.5V 0.44V 0.41V 0.39V Subthreshold swing 0.50V / decade 0.21V / decade 0.11V / decade 0.11V / decade

[0076] (2) Fabrication Example 2 Transistor

[0077] like Figure 8 As shown, the first electrode and the second electrode are replaced by graphene / Ti electrodes in the transistor of Example 2. As in the transistor of Example 1, it can be confirmed that when heat-treated at 200, 250, and 300°C, the higher the temperature, the better the performance of the transistor is, for the reasons described above.

[0078] Therefore, it was confirmed that the graphene / Ti electrode can sufficiently replace the Au / Ti electrode.

[0079] Furthermore, as can be seen from Table 4 below, even if the Au / Ti electrode is replaced by the graphene / Ti electrode, the current on-off ratio, fluidity, threshold voltage, subthreshold swing, etc. are still very excellent.

[0080] Table 4

[0081] parameter No annealing 200℃ 250℃ 300℃ <![CDATA[I on ]]> <![CDATA[1.05×10 -4 A]]> <![CDATA[2.31×10 -4 A]]> <![CDATA[3.47×10 -4 A]]> <![CDATA[3.50×10 -4 A]]> <![CDATA[I off ]]> <![CDATA[1.75×10 -12 A]]> <![CDATA[1.67×10 -12 A]]> <![CDATA[1.02×10 -13 A]]> <![CDATA[9.94×10 -14 A]]> <![CDATA[I on / I off ]]> <![CDATA[6.00×10 7 ]]> <![CDATA[1.38×10 8 ]]> <![CDATA[3.40×10 9 ]]> <![CDATA[3.52×10 9 ]]> Liquidity <![CDATA[101cm 2 / V.s]]> <![CDATA[117cm 2 / V.s]]> <![CDATA[291cm 2 / V.s]]> <![CDATA[293cm 2 / V.s]]> <![CDATA[V th ]]> 1.38V 0.44V 0.34V 0.33V Subthreshold swing 0.34V / decade 026V / decade 0.10V / decade 0.10V / decade

[0082] (3) Fabrication Example 3 Transistor

[0083] like Fig. 9 As shown, in order to realize a transparent and flexible nitrogen-doped graphene transistor, the transistor of Example 3 is made by replacing the existing Si-based substrate and gate insulating layer with a flexible PI substrate and an Al2O3 gate insulating layer, and using a graphene / Ti first electrode and a second electrode. As in Example 1 and Example 2, it can be confirmed that the performance of the transistor becomes excellent when heat-treated at 250°C. Due to the degradation phenomenon of the PI substrate, the heat treatment test is omitted at temperatures above that.

[0084] Furthermore, as can be seen from the following Table 5, even when a flexible substrate is used, the current on-off ratio, fluidity, threshold voltage, subthreshold swing, etc. are very excellent.

[0085] Table 5

[0086] parameter No annealing 250℃ <![CDATA[I on ]]> <![CDATA[1.53×10 -7 A]]> <![CDATA[2.29×10 -4 A]]> <![CDATA[I off ]]> <![CDATA[1.14×10 -12 A]]> <![CDATA[1.01×10 -13 A]]> <![CDATA[I on / I off ]]> <![CDATA[1.34×10 5 ]]> <![CDATA[2.26×10 9 ]]> Liquidity <![CDATA[44cm 2 / V.s]]> <![CDATA[260cm 2 / V.s]]> <![CDATA[V th ]]> 1.1V 0.8V Subthreshold swing 1.07V / decade 0.22V / decade

[0087] The device stability of Preparation Example 3 in which a transparent and flexible nitrogen-doped graphene transistor was fabricated was confirmed by negative bias stress (NBS) and negative bias illumination stress (NBIS) measurements (refer to Fig.10). According to the NBS measurement results, Preparation Example 3 showed very stable device characteristics, with the measured value remaining unchanged even after 3600 seconds, and also showed very stable device characteristics in the NBIS measurement with the illumination set to 1500 lux. This is similar to the stability reported as very stable ZnON-F (Oxide Semiconductors, ACS Applied Materials & Interfaces, 2017, 9, 24688), which is a very excellent characteristic.

Claims

1. A graphene-based TFT, characterized in that: include: a gate electrode; A gate insulating layer, located on the gate electrode; An active layer, located in a portion of the gate insulating layer, comprising a nitrogen-doped graphene layer; A first electrode, located on a side region of the active layer; a second electrode, located on the other side of the active layer; Wherein, the active layer is a nitrogen-doped graphene layer / TiO 2-x The nitrogen-doped graphene layer is directly generated and doped after depositing a Ti layer on the gate insulating layer in an oxygen-free atmosphere, and the TiO 2-x The Ti layer is formed by partial oxidation of the Ti layer after exposing the active layer to an external environment.

2. The graphene-based TFT according to claim 1, characterized in that The gate electrode includes a graphene layer.

3. The graphene-based TFT according to claim 1, characterized in that The first electrode and the second electrode include a graphene layer / TiO 2-x layer.

4. A method for preparing a graphene-based TFT according to claim 1, characterized in that: The active layer forming step includes: A step of attaching a shadow mask corresponding to the shape of the active layer to be formed on the gate insulating layer, and depositing a titanium film with a thickness of 3 to 10 nm; Next, maintaining an oxygen-free atmosphere, a step of growing a graphene film in situ by remote plasma-assisted chemical vapor deposition; A step of performing remote plasma treatment on the grown graphene film to cause the graphene film to be subjected to specified damage; The damaged graphene film is exposed to remote plasma in a N2 atmosphere to dope nitrogen.

5. The method for preparing a graphene-based TFT according to claim 4, characterized in that: After the active layer forming step, the method further includes the following step: after forming the first electrode and the second electrode, performing annealing at 100° C. to 400° C. for a predetermined time.

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