Method for manufacturing a semiconductor device, semiconductor device, and semiconductor substrate

Abstract

The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor substrate. The method includes: forming an insulating film on a region of the substrate that serves as a scribe line; forming a first semiconductor layer while leaving a cavity in the insulating film; forming a second semiconductor layer on the first semiconductor layer; and dividing the substrate, the first semiconductor layer, and the second semiconductor layer into a plurality of pieces by pressing the substrate at a position corresponding to the region serving as the scribe line on a surface of the substrate opposite to the surface on which the first semiconductor layer is formed.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor substrate. Background Art

[0002] After forming a semiconductor layer and other components on a substrate (wafer), the wafer is divided to manufacture semiconductor devices such as light-emitting elements and light-receiving elements. For example, a technique of dividing a wafer using a blade of a dicing saw is known (for example, Japanese Patent Laid-Open No. 2008-270627). Summary of the Invention

[0003] A method for manufacturing a semiconductor device according to the present invention includes: forming an insulating film on a region of a substrate that serves as a scribe line; forming a first semiconductor layer while leaving a cavity in the insulating film; forming a second semiconductor layer on the first semiconductor layer; and dividing the substrate, the first semiconductor layer, and the second semiconductor layer into a plurality of pieces by pressing the substrate at a position corresponding to the region that serves as the scribe line on a surface of the substrate opposite to the surface on which the first semiconductor layer is formed.

[0004] A semiconductor substrate according to the present invention includes a semiconductor layer having a cavity embedded along a region that serves as a scribe line. Brief Description of the Drawings

[0005] Figure 1A is a cross-sectional view showing a semiconductor device according to a first embodiment.

[0006] Figure 1B is a plan view showing the semiconductor device.

[0007] Figure 2 is a plan view showing a method for manufacturing the semiconductor device.

[0008] Figure 3A is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0009] Figure 3B is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0010] Figure 4A is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0011] Figure 4B is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0012] Figure 5A is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0013] Figure 5B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0014] Figure 6A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0015] Figure 6B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0016] Figure 7A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0017] Figure 7B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0018] Figure 8A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0019] Figure 8B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0020] Figure 9 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0021] Figure 10A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0022] Figure 10B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0023] Figure 11A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0024] Figure 11B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0025] Figure 12A It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0026] Figure 12B It is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0027] Figure 13 It is a cross-sectional view showing a method for manufacturing a semiconductor device. Detailed Description

[0028] Dividing a substrate may cause generation of foreign matters, such as substrate fragments. These foreign matters may adhere to the chip, resulting in poor appearance and feature defects. Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor substrate capable of suppressing generation of foreign matters.

[0029] [Description of Embodiments of the Present Invention]

[0030] First, the content of the embodiments of the present invention will be enumerated and described.

[0031] A method for producing a semiconductor optical device according to an embodiment of the present invention includes: (1) forming an insulating film on a region of a substrate used as a scribe line; forming a first semiconductor layer while leaving a cavity in the insulating film; forming a second semiconductor layer on the first semiconductor layer; and dividing the substrate, the first semiconductor layer, and the second semiconductor layer into multiple pieces by pressing the substrate at a position corresponding to the region used as a scribe line on a surface of the substrate opposite to the surface on which the first semiconductor layer is formed. The first semiconductor layer grows to extend over the insulating film. A portion of the first semiconductor layer extending over the insulating film is more likely to break than other portions. The substrate can be divided along the scribe line, and generation of foreign matters due to the division can be suppressed.

[0032] (2) The method may further include: before forming the first semiconductor layer, etching the substrate using the insulating film as a mask to form a mesa. The first semiconductor layer grows to extend over the insulating film. A portion of the first semiconductor layer extending over the insulating film is more likely to break than other portions. The substrate can be divided along the scribe line, and generation of foreign matters due to the division can be suppressed.

[0033] (3) The first semiconductor layer can be formed by applying a growth gas of phosphine and trimethylindium, and an embedded layer can be formed by applying a growth gas of trimethylindium and chloromethane.

[0034] (4) A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer provided on a substrate; and an electrode provided on the semiconductor layer. The semiconductor layer has a recess embedded along a region used as a scribe line. The substrate can be divided along the region used as a scribe line, and generation of foreign matters due to the division can be suppressed.

[0035] (5) The semiconductor device may include an insulating film formed in the recess.

[0036] (6) The semiconductor device may be a light-emitting element or a light-receiving element.

[0037] (7) A semiconductor substrate according to an embodiment of the present invention includes a semiconductor layer having cavities embedded along an area used as a scribe line. The substrate can be divided along the area used as a scribe line, and generation of foreign matter due to the division can be suppressed.

[0038] (8) The semiconductor device may include an insulating film formed in the recess.

[0039] [Details of Embodiments of the Present Invention]

[0040] Descriptions will be given of embodiments of a method for manufacturing a semiconductor device and a semiconductor substrate according to embodiments of the present invention with reference to the accompanying drawings. The present invention is not limited to the specifically disclosed embodiments and variations, but may include other embodiments and variations without departing from the scope of the present invention.

[0041] [First Embodiment]

[0042] (Semiconductor Device)

[0043] Figure 1A is a cross-sectional view showing a semiconductor device 100 according to the first embodiment, and shows a cross-section along line A-A in Figure 1B . Figure 1B is a plan view of the semiconductor device 100 and is a schematic view as described below. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. The X-axis direction and the Y-axis direction are directions on two sides of the semiconductor device 100 that are orthogonal to each other. The Z-axis direction is the stacking direction of the semiconductor layers in the semiconductor device 100.

[0044] As Figure 1A and Figure 1B show, the semiconductor device 100 includes a mesa 11 (second mesa) and a mesa 15. Figure 1B Only the mesas 11 and 15 and the reflective film 19 in the semiconductor device 100 are shown. As Figure 1B shows, the mesa 15 is provided to surround the outer periphery of the semiconductor device 100. The mesa 15 extends in the X-axis direction and the Y-axis direction. The mesa 11 is provided at the center of the semiconductor device 100. The mesa 11 extends in the X-axis direction. For example, a reflective film 19 made of silicon nitride (SiN) is provided on both sides (i.e., the end faces on the X-axis side) of the semiconductor device 100 that extend in the Y-axis direction. The length L1 of the side portion of the mesa 15 in the X-axis direction and the length L2 of the side portion of the mesa 15 in the Y-axis direction are, for example, 300 μm.

[0045] As Figure 1AAs shown, the semiconductor device 100 is a light-emitting element, which includes a substrate 10, insulating films 12 and 25, a semiconductor layer 14 (corresponding to the first semiconductor layer), a semiconductor layer 22, an active layer 18, cladding layers 17 and 20, a contact layer 24, and electrodes 26 and 28. The semiconductor layer 22, the active layer 18, and the cladding layers 17 and 20 correspond to the second semiconductor layer.

[0046] The mesa 11 includes the semiconductor layer 14, the cladding layer 17, the active layer 18, and the cladding layer 20. In the mesa 11, the cladding layer 17 is disposed on the upper surface of the semiconductor layer 14, the active layer 18 is disposed on the upper surface of the cladding layer 17, and the cladding layer 20 is disposed on the upper surface of the active layer 18.

[0047] The mesa 15 is formed on the substrate 10. In the mesa 15, the insulating film 12 is disposed on the upper surface of the substrate 10. The semiconductor layer 14 is disposed from the side surface on the inner side (i.e., the mesa 11 side) of the substrate 10 to the upper side of the insulating film 12. A recess 16 is formed between the upper surface of the insulating film 12 and the semiconductor layer 14. That is, a part of each side surface of the semiconductor device 100 is recessed inward, and the insulating film 12 is embedded in the recess 16. The cladding layer 17, the active layer 18, and the cladding layer 20 are stacked on the semiconductor layer 14 in this order.

[0048] The surface 10a of the substrate 10 extends between the mesa 11 and the mesa 15. The height H1 of the mesa 15 from the surface 10a is, for example, 2 μm or more. The size (i.e., height) H2 of the recess 16 is, for example, 0.5 μm. The thickness T1 of the semiconductor layer 14 on the recess 16 is, for example, 2 μm. The width W1 of each of the insulating film 12 and the recess 16 is, for example, 1 μm or more and 2 μm or less. The thickness T2 from the lower surface of the substrate 10 to the surface 10a is, for example, 100 μm.

[0049] The semiconductor layer 22 is an embedded layer, which is disposed on the surface 10a of the substrate 10 and is embedded in the mesas 11 and 15. The contact layer 24 is disposed on the semiconductor layer 22 and the mesa 11. The insulating film 25 is disposed on the contact layer 24 and the semiconductor layer 22, and the electrode 26 is disposed on the insulating film 25. The electrode 26 contacts the contact layer 24 through the opening of the insulating film 25 and is electrically connected to the contact layer 24. The electrode 28 is disposed on the lower surface of the substrate 10 and is electrically connected to the substrate 10.

[0050] The substrate 10 is, for example, a semiconductor substrate made of n-type indium phosphide (n-InP). The semiconductor layer 14 is, for example, made of InP. The semiconductor layer 22 is, for example, made of InP doped with iron (Fe) and is a layer having a higher resistance than other semiconductor layers. The substrate 10 and the semiconductor layers 14 and 22 may include InP and semiconductors other than InP.

[0051] The active layer 18 includes, for example, multiple layers in which multiple indium gallium arsenide (InGaAs) layers and multiple indium gallium arsenide phosphide (InGaAsP) layers are stacked, and has a multi-quantum well (MQW) structure. The cladding layer 17 is made of, for example, n-InP with a thickness of 0.3 μm. The cladding layer 20 is made of, for example, p-InP with a thickness of 0.3 μm. The contact layer 24 is made of, for example, p-InGaAsP with a thickness of 1.5 μm. The active layer 18, the cladding layers 17 and 20, and the contact layer 24 can be made of semiconductors other than those described above.

[0052] The insulating film 12 is made of an insulating material such as silicon nitride (SiN) or silicon oxide (SiO 2 ) with a thickness of 200 nm or more and 300 nm or less. The insulating film 25 is a passivation film made of an insulating material such as SiN or SiO 2 . The electrodes 26 and 28 are made of a metal such as gold (Au). The electrode 26 is, for example, a p-electrode, and the electrode 28 is, for example, an n-electrode.

[0053] Optical gain is obtained by applying a voltage to the electrodes 26 and 28 and injecting carriers into the active layer 18. The light emitted from the active layer 18 propagates in the X-axis direction along the mesa 11. Figure 1B Each of the reflection films 19 shown in reflects a part of the light emitted from the active layer 18 and transmits the rest of the light.

[0054] (Manufacturing Method)

[0055] Figure 2 is a plan view showing a method for manufacturing the semiconductor device 100. Figures 3A to 8B is a cross-sectional view showing a method for manufacturing the semiconductor device 100, and shows a cross-section corresponding to Figure 1A .

[0056] As Figure 2 shown, the manufacturing process of the semiconductor device 100 is performed on the substrate 10 in a wafer state. The upper surface of the substrate 10 is the (001) surface of InP. The multiple regions 13a and 13b shown by solid lines on the substrate 10 are regions used as scribe lines. Each of the multiple regions 13a extends from one end to the other end of the wafer in the X-axis direction (i.e., the [01-1] direction of the substrate 10 or the direction of the alignment edge). Each of the multiple regions 13b extends from one end to the other end of the wafer in the Y-axis direction (i.e., the [01-1-] direction of the substrate 10 or the direction of the indication edge). The regions 13a and the regions 13b are orthogonal to each other. In the middle of the manufacturing process, an array 10c in which multiple regions 10b are connected together is formed. Finally, a single region 10b surrounded by the regions 13a and 13b becomes one chip, that is, the semiconductor device 100.

[0057] Figures 3A to 8B shows Figure 2 a single region 10b of Figure 3A As shown in, an insulating film 12 is formed in a region 13a on the upper surface of a substrate 10, and the insulating film 12 is also formed in a region 13b (not shown) at the same time. For example, the insulating film 12 is formed by a chemical vapor deposition (CVD) method or the like. Specifically, resist patterning is performed by photolithography and wet etching is performed using HF (hydrogen fluoride) to form the insulating film 12 in the regions 13a and 13b. The resist is removed.

[0058] As Figure 3B shown in, a mesa 15 is formed on the substrate 10 by using the insulating film 12 as a mask and performing dry etching using, for example, silicon tetrachloride gas (SiCl 4 4) / argon (Ar). Examples of the conditions for dry etching are as follows:

[0059] Antenna power: 200 - 250 W

[0060] Bias power: 100 - 200 W

[0061] SiCl 4 flow rate of 4: 5 to 10 sccm (8.335×10 -8 to 16.67×10 -8 m 3 / s)

[0062] Ar flow rate: 40 to 50 sccm (66.68×10 -8 to 83.35×10 -8 m 3 / s)

[0063] Pressure: 0.5 to 1.0 Pa

[0064] Temperature of the substrate 10: 180 to 220 °C

[0065] The mesa 15 is formed in Figure 2 the regions 13a and 13b shown. The height H1 of the mesa 15 is, for example, 2 μm or more. The inclination angle θ of the side surface of the mesa 15 with respect to the Z-axis direction is, for example, 10°. After the mesa 15 is formed, the insulating film 12 is not removed but remains on the mesa 15.

[0066] As Figure 4A and Figure 4B shown in, a semiconductor layer 14 of InP is epitaxially grown by a metalorganic vapor phase epitaxy (MOVPE) method using, for example, phosphine (PH 3 3) / trimethylindium (TMI) as a source gas. Examples of the growth conditions are as follows:

[0067] PH 3 Traffic of >TMI traffic

[0068] Growth temperature: 650℃

[0069] Growth pressure: 100mbar

[0070] Growth rate of semiconductor layer 14: 2 μm / h

[0071] like Figure 4A As shown, the semiconductor layer 14 grows upward from the upper surface of the substrate 10 and is embedded in the mesa 15. Figure 4B As shown, the semiconductor layer 14 reaches a position above the insulating film 12 and grows to protrude laterally from the outside to the inside of the insulating film 12. Figure 5A As shown, the semiconductor layer 14 is formed to embed the mesa 15 and cover the insulating film 12. Each portion 14a of the semiconductor layer 14 that overlaps the insulating film 12 in the thickness direction (i.e., the Z-axis direction) is a portion that promotes growth in the lateral direction, as described below. The insulating film 12 is embedded in the semiconductor layer 14. A cavity 16a is formed between the insulating film 12 and the semiconductor layer 14.

[0072] exist Figure 4A In the upward crystal growth shown in FIG. 1 , the semiconductor layer 14 mainly grows along the (100) direction. Figure 4B As shown, the semiconductor layer 14 also grows laterally to protrude above the terrace 15 and the insulating film 12. Unlike the upward crystal growth, this growth is promoted to a greater extent in the lateral direction than in the vertical direction. It is assumed that growth with weak surface orientation dependence is performed on the terrace 15. Due to the weak surface orientation dependence, the semiconductor layer 14 also grows in the lateral direction, thereby easily forming the cavity 16a. As shown in FIG. Figure 5A As shown in FIG. 1 , the portion of the semiconductor layer 14 in which the growth is laterally promoted is referred to as a portion 14a. Each portion 14a of the semiconductor layer 14 has a crystal structure different from that of other portions of the semiconductor layer 14. The portion 14a is formed at Figure 2 In each of the areas 13a and 13b shown.

[0073] like Figure 5B As shown, for example, the cladding layer 17, the active layer 18 and the cladding layer 20 are epitaxially grown in this order by the MOVPE method. Figure 5B The semiconductor substrate 110 is formed through the steps up to this point.

[0074] like Figure 6A As shown, an insulating layer 27 (third insulating film) is formed on the upper surface of the cladding layer 20 by, for example, CVD method, resist patterning, etc. The insulating film 27 is provided in the region 13a and the region 13b (here, in Figure 6Ain the unshown region 13b). Further, an insulating film 27 is provided in the region surrounded by regions 13a and 13b.

[0075] As Figure 6B shown, the insulating film 27 is used as a mask, and dry etching is performed using, for example, SiCl 4 / Ar. Figure 6B The conditions for dry etching in are, for example, the same as those for dry etching in the step of forming the mesa 15. The portions of the semiconductor layer 14, the cladding layers 17 and 20, and the active layer 18 that are protected by the insulating film 27 are retained, and the unprotected portions are removed. A mesa 11 is formed at a position between the mesas 15. The mesa 15 is covered by the semiconductor layer 14 from the side surface to the upper surface. The insulating film 12 and the cavity 16a are embedded in the semiconductor layer 14. The semiconductor layer 14 grows to cover the insulating film 12 and the cavity 16a. The cladding layer 17, the active layer 18, and the cladding layer 20 are stacked on the semiconductor layer 14 in this order.

[0076] As Figure 7A shown, for example, the semiconductor layer 22 embedded in the mesa 11 and the mesa 15 is epitaxially grown by the MOVPE method. In the growth conditions of the semiconductor layer 22, the growth temperature and the growth rate are the same as those of the semiconductor layer 14. The source gas is PH 3 / TMI gas. The flow rate of PH 3 is, for example, 600 sccm, and the flow rate of TMI is, for example, 500 sccm. The upper surface of the semiconductor layer 22 is at the same height as the upper surface of the cladding layer 20. After the semiconductor layer 22 is grown, the insulating film 27 is removed by etching using hydrogen fluoride (HF) or the like.

[0077] As Figure 7B shown, the contact layer 24 is epitaxially grown on the upper surface of the cladding layer 20 and the upper surface of the semiconductor layer 22 by the MOVPE method or the like. As Figure 8A shown, for example, the portion of the contact layer 24 located on the mesa 15 is removed by etching or the like, and the portion of the contact layer 24 located on the mesa 11 is retained. The insulating layer 25 is provided on the contact layer 24. At this time, the insulating film 25 in the region 13a used as a scribe line is removed, and the insulating film 25 in the region 13b (not shown) is also removed. Scribe lines are formed in each of the regions 13a and 13b. For example, the electrodes 26 are formed on the contact layer 24 and the insulating film 25 by vacuum deposition or the like, and the electrode 28 is formed on the lower surface of the substrate 10.

[0078] Using Figure 2 the region 13b shown in as a scribe line, the substrate 10 is divided by the same method as the method described with reference to Figure 8B to form a plurality of arrays 10c. Figure 1BThe reflective film 19 shown is provided on the end face of the array 10c.

[0079] As Figure 8B shown, the array 10c is further divided to form a plurality of chips (i.e., semiconductor devices 100). The blade 29 contacts the lower surface of the substrate 10, and the blade 29 presses the substrate 10 upward from the lower surface of the substrate 10. The positions where the blade 29 contacts are the respective regions 13a of the substrate 10. The semiconductor layer 14 corresponding to the region 13a is the portion 14a, and the portion 14a is more prone to cracking compared to the portions other than the portion 14a. By using the region 13a as a scribe line, the wafer including the substrate 10, the semiconductor layer 14, the coating layers 17 and 20, and the active layer 18 is split along the region 13a to form the semiconductor device 100 in a chip state.

[0080] According to the first embodiment, as Figure 3B shown, by etching using the insulating film 12 as a mask, the mesa 15 is formed in the regions 13a and 13b used as scribe lines. As Figure 5A shown, the semiconductor layer 14 embedding the mesa 15 is formed. The semiconductor layer 14 grows to project laterally above the insulating film 12, and the portions 14a are formed in the regions 13a and 13b used as scribe lines. Each portion 14a has a crystal structure different from the other portions of the semiconductor layer 14 and is prone to cracking. Therefore, the substrate 10 can be easily split along the regions 13a and 13b. Thus, the generation of foreign matter can be suppressed.

[0081] By pre-scratching the regions 13a and 13b used as scribe lines, the substrate 10 can be split without the semiconductor layer 14 growing laterally. However, since foreign matter is generated during splitting and these foreign matters adhere to the semiconductor device, it may cause poor appearance and characteristic defects. According to the first embodiment, the generation of foreign matter is suppressed by splitting the substrate 10 along the regions 13a and 13b where the portions 14a are formed. Thus, the yield of the semiconductor device is improved.

[0082] Use a gas containing PH 3 and TMI as a source gas to grow the semiconductor layers 14 and 22. By adjusting the growth conditions, the surface orientation dependence of crystal growth increases, and for example, the growth toward the (001) surface becomes faster.

[0083] After the semiconductor layer 14 grows, a cavity 16a is easily formed between the insulating film 12 and the semiconductor layer 14. Due to the presence of the cavity 16a, it is considered that the strength in the regions 13a and 13b is lower than that in the other portions. Therefore, the substrate 10 is easily split along the regions 13a and 13b, and the generation of foreign matter can be suppressed. The recess 16 is formed by the cavity 16a.

[0084] Preferably, Figure 3B The height H1 of the mesa 15 shown is, for example, 2 μm or more, and the inclination angle θ is, for example, 5° or more and 45° or less. The semiconductor layer 14 mainly grows upward until it reaches the upper surface of the insulating film 12 on the mesa 15, and the growth laterally protrudes at a position above the upper surface of the insulating film 12. Then, the portion 14a is formed on the semiconductor layer 14.

[0085] The mesa 15 and the portion 14a are formed in Figure 2 at least a part of the plurality of regions 13a and 13b shown. In particular, preferably, the mesa 15 and the portion 14a are formed in the entire portions of the plurality of regions 13a and the plurality of regions 13b. The mesa 15 is provided in the entire portions of the plurality of regions 13a and the plurality of regions 13b, and the portion 14a is formed on the mesa 15. This enables the wafer to be cleaved along the regions 13a and 13b, thereby suppressing the generation of foreign matter.

[0086] The mesa 11 is formed at a position surrounded by the mesa 15. The mesa 11 serves as a light-emitting unit. That is, the semiconductor device 100 is such a light-emitting element that causes the light generated by the active layer 18 to propagate along the mesa 11 and emit it to the outside. By suppressing the generation of foreign matter, it becomes difficult for these foreign matters to adhere to the light-emitting surface of the semiconductor device 100 (i.e., Figure 1B the surface on the X-axis side). Light can be emitted without being blocked by foreign matter.

[0087] [Second Embodiment]

[0088] (Semiconductor Device)

[0089] Figure 9 is a cross-sectional view showing a semiconductor device 200 according to the second embodiment. The description of the constituent elements corresponding to those in the first embodiment is omitted. As Figure 9 shown, the semiconductor device 200 is such a light-receiving element that includes a substrate 10, insulating films 12 and 36, a passivation film 34, a semiconductor layer 14 (corresponding to the first semiconductor layer), a semiconductor layer 22, a semiconductor layer 30 (corresponding to the second semiconductor layer), a contact layer 32, electrodes 38 and 40, and plating layers 42 and 44.

[0090] The semiconductor device 200 has a mesa 15. Each mesa 15 is formed by the substrate 10 and surrounds the outer periphery of the semiconductor device 200 as in Figure 1B the example of Figure 9As shown, the semiconductor layer 14 is provided on the surface 10a of the substrate 10, embedded in the mesa 15, and laterally protrudes above the mesa 15. In each mesa 15, the insulating film 12 is provided on the upper surface of the substrate 10. The recess 16 is formed between the upper surface of the insulating film 12 and the semiconductor layer 14. The mesa 11 is not provided.

[0091] For example, three semiconductor layers 30 are provided on the semiconductor layer 14. The middle semiconductor layer of the three semiconductor layers 30 may be referred to as the semiconductor layer 30a, and the semiconductor layers located on both sides of the semiconductor layer 30a may be referred to as the semiconductor layer 30b. The semiconductor layer 30b is separated from the semiconductor layer 30a and is located between the semiconductor layer 30a and the mesa 15.

[0092] A passivation film 34 is provided around each semiconductor layer 30. The insulating film 36 is provided on the semiconductor layer 30b and the passivation film 34. The insulating film 36 has an opening between the semiconductor layer 30a and the semiconductor layer 30b, and the electrode 40 is provided in the opening. The electrode 40 is electrically connected to the semiconductor layer 14. The plating layer 44 is provided on the insulating film 36 and the electrode 40 and is electrically connected to the electrode 40.

[0093] The contact layer 32 is provided on the upper surface of the semiconductor layer 30a, and the electrode 38 is provided on the upper surface of the contact layer 32. The electrode 38 is electrically connected to the contact layer 32. The plating layer 42 is provided on the upper surface of the electrode 38 and is electrically connected to the electrode 38. The plating layer 42 is separated from the plating layer 44 and is not electrically connected to the plating layer 44.

[0094] The semiconductor layer 30 includes, for example, an n+-InP layer, an undoped indium phosphide (i-InP) layer, a light absorption layer made of i-InGaAs, a graded layer made of i-InGaAsP, a field reduction layer made of n+-InP, a multiplication layer made of i-InP, and a p-InP layer, which are stacked upward from the semiconductor layer 14. The semiconductor layer 30 may also include other semiconductor layers. The contact layer 32 is made of, for example, p+-InGaAs.

[0095] The passivation film 34 is made of a semiconductor such as InP. The insulating film 36 is made of an insulator such as SiN or SiO 2 The electrodes 38 and 40 are made of a metal such as gold (Au). The plating layers 42 and 44 are made of a metal such as Au and have a thickness of 2 to 3 μm. The electrode 38 and the plating layer 42 serve as the p electrode, and the electrode 40 and the plating layer 44 serve as the n electrode.

[0096] When light is incident on the semiconductor device 200, the light absorption layer of the semiconductor layer 30 generates carriers, and current flows between the electrodes 38 and 40.

[0097] (Manufacturing method)

[0098] Next, a method of manufacturing the semiconductor device 200 will be described. This manufacturing method is applied to Figure 2 the substrate 10 in the form of a wafer as shown. Figures 10A to 13 is a cross-sectional view showing a method of manufacturing the semiconductor device 200. From Figures 3A to 5A the steps are also applicable to the second embodiment.

[0099] Also in the second embodiment, as in the first embodiment, by Figures 4A to 5A the steps, the semiconductor layer 14 is epitaxially grown. The semiconductor layer 14 grows upward from the upper surface of the substrate 10, and the growth protrudes laterally above the insulating film 12. After forming the semiconductor layer 14, for example, as Figure 10A shown, the semiconductor layer 30 and the contact layer 32 are epitaxially grown in this order on the upper surface of the semiconductor layer 14 by the MOVPE method. Thus, the semiconductor substrate 210 is formed.

[0100] As Figure 10B shown, an insulating film 50 of SiN or SiO 2 is formed on the contact layer 32. Using the insulating film 50 as a mask, the contact layer 32 is dry-etched with SiC 4 / Ar, and a part of the contact layer 32 near the mesa is removed. The part of the contact layer 32 surrounded by the mesa 15 is retained. The electrode 38 is provided on the remaining contact layer 32 as described below.

[0101] As Figure 11A shown, at a position sandwiched between the contact layer 32 and the mesa 15, an insulating film 52 of SiN or SiO 2 is formed on the upper surface of the semiconductor layer 30. Using the insulating films 50 and 52 as masks, dry etching is performed on the semiconductor layer 30. The part of the semiconductor layer 30 protected by the insulating films 50 and 52 is retained, and the unprotected part is removed. For example, by the MOVPE method, the passivation film 34 is selectively grown on the upper surface of the semiconductor layer 14 and at positions surrounding the semiconductor layer 30. The upper surface of the semiconductor layer 14 is exposed at positions where the passivation film 34 does not grow.

[0102] As Figure 11B shown, after removing the insulating films 50 and 52, an insulating film 36 is formed on the upper surfaces of the semiconductor layers 14 and 30, the contact layer 32, and the passivation film 34, for example, by a CVD method or the like. An opening is provided in a part of the insulating film 36 located on the contact layer 32 by etching. The electrode 38 is formed, for example, by vacuum deposition or the like on the upper surface of the contact layer 32 exposed from the opening.

[0103] As Figure 12AAs shown, an opening is formed in the insulating film 36 at a position between the semiconductor layer 30a and the semiconductor layer 30b by etching. The electrode 40 is formed, for example, by vacuum deposition or the like on the upper surface of the semiconductor layer 14 exposed from the opening. As Figure 12B shown, a plating process is performed to form a plating layer 42 on the upper surface of the electrode 38 and a plating layer 44 on the upper surface of the electrode 40.

[0104] As Figure 13 shown, the adhesive sheet 54 is attached to the lower surface of the substrate 10. The blade 29 contacts the lower surface of the substrate 10 via the adhesive sheet 54, and the substrate 10 is pressed upward from the lower surface of the substrate 10 by the blade 29 so that the crystal cracks. The positions where the blade 29 makes contact are each of the regions 13a and 13b used as scribe lines in the substrate 10. The wafers do not have to be formed in an array shape, and the reflective film 19 does not have to be provided. After cracking, the adhesive sheet 54 is expanded to increase the distance between adjacent semiconductor devices 200. Each semiconductor device 200 is removed from the adhesive sheet 54 using tweezers or a suction device. The semiconductor device 200 is formed through the above steps.

[0105] According to the second embodiment, as in the first embodiment, the semiconductor layer 14 has a portion 14a on the mesa 15. The portion 14a is formed in the regions 13a and 13b. Therefore, by cracking the substrate 10 along the regions 13a and 13b, generation of foreign matter can be suppressed. Light loss due to adhesion of foreign matter is also suppressed, and the light reception sensitivity of the semiconductor device 200 is improved.

[0106] The semiconductor device 100 according to the first embodiment is a light-emitting element, and the semiconductor device 200 according to the second embodiment is a light-receiving element. The present invention can be applied to semiconductor devices other than optical devices such as light-emitting elements and light-receiving elements.

[0107] In an embodiment of the present invention, a mesa 15 is formed in the region used as a scribe line, and lateral growth promotion of the semiconductor layer 14 is performed on the mesa 15. Instead of this embodiment, forming an insulating film in the region used as a scribe line on the substrate 10 and performing lateral growth promotion of the semiconductor layer 14 on the insulating film may have the same effect as forming the mesa 15.

[0108] The embodiments of the present invention have been described in detail. However, the scope of the present invention is not limited to the specific embodiments of the present invention. It should be understood that the scope of the present invention is defined by the appended claims and includes descriptions equivalent to the claims and all variations within the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an insulating film on a region of a substrate that serves as a scribe line; forming a first semiconductor layer while leaving a cavity in the insulating film; forming a second semiconductor layer on the first semiconductor layer; and dividing the substrate, the first semiconductor layer, and the second semiconductor layer into multiple pieces by pressing the substrate at a position corresponding to the region serving as the scribe line on a surface of the substrate opposite to the surface on which the first semiconductor layer is formed; before forming the first semiconductor layer, etching the substrate using the insulating film as a mask to form a mesa.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming the first semiconductor layer by applying a growth gas of phosphine and trimethylindium, and forming an embedded layer by applying a growth gas of trimethylindium and chloromethane.

3. A semiconductor device manufactured by the method according to any one of claims 1-2, comprising: a semiconductor layer provided on a substrate; and an electrode provided on the semiconductor layer; wherein the semiconductor layer has a recess that is embedded along a region serving as a scribe line.

4. The semiconductor device according to claim 3, further comprising: an insulating film formed in the recess.

5. The semiconductor device according to claim 3, wherein the semiconductor device is a light-emitting element or a light-receiving element.

6. A semiconductor substrate for the semiconductor device according to any one of claims 3-5, comprising: a semiconductor layer having a cavity that is embedded along the region serving as the scribe line.

7. The semiconductor substrate according to claim 6, further comprising: an insulating film formed in the cavity.

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