Complementary switching element

Abstract

The complementary switching element of the present invention includes a first TFET having a channel of a first conductivity type and a second TFET having a channel of a second conductivity type. Each of the first TFET and the second TFET has: a group-IV semiconductor substrate doped with the first conductivity type; a nanowire made of a III-V compound semiconductor disposed on the group-IV semiconductor substrate; a first electrode connected to the group-IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode that applies an electric field to the interface between the group-IV semiconductor substrate and the nanowire. The nanowire includes a first region connected to the group-IV semiconductor substrate and a second region doped with the second conductivity type. In the first TFET, the second electrode is the source electrode, and the first electrode is the drain electrode. In the second TFET, the first electrode is the source electrode, and the second electrode is the drain electrode.

Description

Technical Field

[0001] The present invention relates to complementary switching elements. Background Art

[0002] Semiconductor microprocessors and high - level integrated circuits are manufactured by integrating elements such as metal - oxide semiconductor (hereinafter referred to as "MOS") field - effect transistors (hereinafter referred to as "FETs") on a semiconductor substrate. Generally, complementary MOSFETs (hereinafter referred to as "CMOS") are basic elements (switching elements) of integrated circuits. As a material for the semiconductor substrate, silicon, which is a Group - IV semiconductor, is mainly used. By miniaturizing the transistors that make up the CMOS, the integration density and performance of semiconductor microprocessors and high - level integrated circuits can be improved. One of the technical problems when miniaturizing the CMOS is the increase in power consumption. As the main reasons for the increase in power consumption, the following two points can be cited: the number of CMOSs that can be mounted on one microchip increases; and the leakage current increases due to the short - channel effect. Among the above reasons, the increase in leakage current leads to an increase in the supply voltage. Therefore, for each CMOS, it is necessary to suppress the leakage current to reduce the operating voltage.

[0003] As an index representing the switching characteristics of the CMOS, the sub - threshold (mV / dec) is used. The sub - threshold is equivalent to the minimum driving voltage for turning on the MOSFET. The switching characteristics of conventional MOSFETs are based on the diffusion phenomenon of electrons and holes (carriers). Therefore, in conventional MOSFETs, the theoretical minimum value of the sub - threshold slope is 60 mV / dec, and it is impossible to achieve switching characteristics with a smaller sub - threshold.

[0004] As a switching element that operates with a smaller sub - threshold beyond this physical theoretical limit, reports on tunnel FETs (hereinafter referred to as "TFETs") have been made (for example, refer to Non - Patent Documents 1 and 2). Since the TFET has no short - channel effect and can achieve a high ON / OFF ratio at a low voltage, it is considered a strong candidate for the next - generation switching element.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Non-Patent Document 1: Bhuwalka, K.K., Schulze, J. and Eisele, I., "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering", IEEE transactions on electron devices, Vol.52, No.5, May (2005), pp.909-917.

[0008] Non-Patent Document 2: Bhuwalka, K.K., Schulze, J. and Eisele, I., "A simulation approach to optimize the electrical parameters of a vertical tunnel FET", IEEE transactions on electron devices, Vol.52, No.7, July (2005), pp.1541-1547. SUMMARY OF THE INVENTION

[0009] PROBLEM TO BE SOLVED BY THE INVENTION

[0010] When using a TFET to form a complementary switching element such as a CMOS, it is necessary to integrate the TFET as in the case of a MOSFET. However, since the structures of the source region and the drain region of the TFET are asymmetric, it is not as easy to integrate as a MOSFET with symmetric source and drain region structures.

[0011] An object of the present invention is to provide a complementary switching element including a TFET that can be easily integrated.

[0012] SOLUTION TO THE PROBLEM

[0013] The complementary switching element of the first aspect of the present invention includes a first tunnel field effect transistor having a channel of a first conductivity type and a second tunnel field effect transistor having a channel of a second conductivity type different from the first conductivity type. In the complementary switching element, each of the first tunnel field effect transistor and the second tunnel field effect transistor has: a group-IV semiconductor substrate having a (111) plane and doped with the first conductivity type; a group-III-V compound semiconductor nanowire disposed on the (111) plane and including a first region connected to the (111) plane and a second region doped with the second conductivity type; a first electrode connected to the group-IV semiconductor substrate; a second electrode connected to the second region; and a gate electrode that applies an electric field to the interface between the (111) plane and the first region. In the first tunnel field effect transistor, the second electrode is a source electrode and the first electrode is a drain electrode. In the second tunnel field effect transistor, the first electrode is a source electrode and the second electrode is a drain electrode.

[0014] The complementary switching element of the second aspect of the present invention includes a first tunnel field effect transistor having a channel of a first conductivity type and a second tunnel field effect transistor having a channel of a second conductivity type different from the first conductivity type. In the complementary switching element, each of the first tunnel field effect transistor and the second tunnel field effect transistor has: a group-IV semiconductor substrate including a first region having a (111) plane and a second region doped with the first conductivity type; a group-III-V compound semiconductor nanowire disposed on the (111) plane and undoped or doped with the second conductivity type; a first electrode connected to the group-III-V compound semiconductor nanowire; a second electrode connected to the second region; and a gate electrode that applies an electric field to the interface between the group-III-V compound semiconductor nanowire and the (111) plane. In the first tunnel field effect transistor, the first electrode is a source electrode and the second electrode is a drain electrode. In the second tunnel field effect transistor, the second electrode is a source electrode and the first electrode is a drain electrode.

[0015] Advantages of the Invention

[0016] According to the present invention, a complementary switching element including TFETs that can be easily integrated can be provided. Therefore, according to the present invention, a semiconductor microprocessor and a highly integrated circuit with low power consumption can be provided. Description of the Drawings

[0017] Figure 1 It is a cross-sectional view showing the structure of the complementary switching element of Embodiment 1.

[0018] Figure 2It is the energy band structure diagrams of the first TFET and the second TFET of the complementary switching element of Embodiment 1.

[0019] Figure 3 It is a diagram showing the electrical characteristics of the first TFET (p-TFET) and the second TFET (n-TFET).

[0020] Figure 4A It is a diagram showing the electrical characteristics of the second TFET (n-TFET), Figure 4B It is a diagram showing the electrical characteristics of the first TFET (p-TFET).

[0021] Figure 5A It is a perspective view showing an example of an inverter formed using the complementary switching element of Embodiment 1, Figure 5B is Figure 5A the circuit diagram of the shown inverter.

[0022] Figures 6A - 6D It is a schematic diagram showing an example of the manufacturing method of the complementary switching element of Embodiment 1.

[0023] Figure 7 It is a cross-sectional view showing the structure of the complementary switching element of Embodiment 2.

[0024] Figure 8 It is the energy band structure diagrams of the first TFET and the second TFET of the complementary switching element of Embodiment 2.

[0025] Figure 9 It is a cross-sectional view showing the structure of the complementary switching element of Embodiment 3.

[0026] Figure 10 It is the energy band structure diagrams of the first TFET and the second TFET of the complementary switching element of Embodiment 3.

[0027] Figure 11 It is a diagram showing the electrical characteristics of the first TFET (n-TFET) and the second TFET (p-TFET).

[0028] Figure 12A It is a perspective view showing an example of an inverter formed using the complementary switching element of Embodiment 3, Figure 12B is Figure 12A the circuit diagram of the shown inverter.

[0029] Figure 13 It is a diagram showing the electrical characteristics of the fin-type first TFET (n-TFET) and the fin-type second TFET (p-TFET).

[0030] Figures 14A - 14DIt is a schematic diagram showing an example of a manufacturing method of a complementary switching element according to Embodiment 3.

[0031] Figure 15 It is a cross-sectional view showing the structure of a complementary switching element according to Embodiment 4.

[0032] Figure 16 It is an energy band structure diagram of the first TFET and the second TFET of the complementary switching element according to Embodiment 4. Detailed Embodiments

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0034] [Embodiment 1]

[0035] In Embodiment 1, an example of a complementary switching element of the present invention is shown in which a III-V compound semiconductor nanowire extends vertically from the surface of a p-type highly doped IV-group semiconductor substrate.

[0036] (Structure of Complementary Switching Element)

[0037] Figure 1 It is a cross-sectional view showing the structure of the complementary switching element 100 according to Embodiment 1. As Figure 1 shown, the switching element 100 according to Embodiment 1 includes: at least one first tunnel field effect transistor (first TFET) 101 and at least one second tunnel field effect transistor (second TFET) 102.

[0038] The first TFET 101 is a TFET with a p-type channel (p-TFET), and the second TFET 102 is a TFET with an n-type channel (n-TFET). The first TFET 101 and the second TFET 102 have substantially the same structure. However, in the first TFET 101 and the second TFET 102, the source electrode ( Figure 1 denoted by "S" in Figure 1 and the drain electrode ( denoted by "D" in

[0039] have opposite positional relationships.The first TFET 101 includes a Group-IV semiconductor substrate 111, an insulating film 112, a Group-III-V compound semiconductor nanowire 113, a gate dielectric film 114, an insulating protective film 115, a first electrode (drain electrode) 116, a second electrode (source electrode) 117, and a gate electrode 118. The Group-III-V compound semiconductor nanowire 113 includes an undoped first region 113a and an n-type highly doped second region 113b. In the first TFET 101, the first electrode 116 is the drain electrode and the second electrode 117 is the source electrode. In the first TFET 101, tunneling occurs at the bonding interface between the (111) plane of the Group-IV semiconductor substrate 111 and the Group-III-V compound semiconductor nanowire 113.

[0040] The second TFET 102 includes a Group-IV semiconductor substrate 111, an insulating film 112, a Group-III-V compound semiconductor nanowire 123, a gate dielectric film 124, an insulating protective film 125, a first electrode (source electrode) 126, a second electrode (drain electrode) 127, and a gate electrode 128. The Group-III-V compound semiconductor nanowire 123 includes an undoped first region 123a and an n-type highly doped second region 123b. In the second TFET 102, the first electrode 126 is the source electrode and the second electrode 127 is the drain electrode. In the second TFET 102, tunneling occurs at the bonding interface between the (111) plane of the Group-IV semiconductor substrate 111 and the Group-III-V compound semiconductor nanowire 123.

[0041] The Group-IV semiconductor substrate 111 is composed of a Group-IV semiconductor such as silicon or germanium, and is a substrate whose upper surface is the (111) plane. The Group-IV semiconductor substrate 111 is, for example, a silicon (111) substrate. In the present embodiment, the Group-IV semiconductor substrate 111 is p-type highly doped. The entire Group-IV semiconductor substrate 111 may be doped, or only a part of the Group-IV semiconductor substrate 111 may be doped.

[0042] In addition, the Group-IV semiconductor substrate 111 constituting the first TFET 101 and the Group-IV semiconductor substrate 111 constituting the second TFET 102 are electrically or spatially separated. For example, a structure having a conductivity type different from that of the Group-IV semiconductor substrate 111 may be disposed between the Group-IV semiconductor substrate 111 constituting the first TFET 101 and the Group-IV semiconductor substrate 111 constituting the second TFET 102, so as to electrically separate the Group-IV semiconductor substrate 111 constituting the first TFET 101 and the Group-IV semiconductor substrate 111 constituting the second TFET 102. Alternatively, two silicon nanowire structures formed on a BOX (buried oxide) layer without contacting each other may be respectively set as the Group-IV semiconductor substrate 111 constituting the first TFET 101 and the Group-IV semiconductor substrate 111 constituting the second TFET 102, so as to spatially separate the Group-IV semiconductor substrate 111 constituting the first TFET 101 and the Group-IV semiconductor substrate 111 constituting the second TFET 102.

[0043] The insulating film 112 is an insulating film that covers at least the surface ((111) surface) on which the III-V compound semiconductor nanowires 113 and 123 are disposed among the two surfaces of the Group-IV semiconductor substrate 111. The insulating film 112 may or may not be formed on the other surface of the Group-IV semiconductor substrate 111 (the surface on which the III-V compound semiconductor nanowires 113 and 123 are not disposed). In the first TFET 101, there is no insulating film 112 between the Group-IV semiconductor substrate 111 and the III-V compound semiconductor nanowire 113, and between the Group-IV semiconductor substrate 111 and the first electrode (drain electrode) 116. In the second TFET 102, there is no insulating film 112 between the Group-IV semiconductor substrate 111 and the III-V compound semiconductor nanowire 123, and between the Group-IV semiconductor substrate 111 and the first electrode (source electrode) 126. Examples of the insulating film 112 include a silicon oxide film and a silicon nitride film. For example, the insulating film 112 is a silicon oxide film with a thickness of 20 nm.

[0044] III-V compound semiconductor nanowires 113 and 123 are structures composed of III-V compound semiconductors, with a diameter ranging from 2 nm to 100 nm and a length ranging from 50 nm to 10 μm. The III-V compound semiconductor nanowires 113 and 123 are arranged on the (111) plane of the group-IV semiconductor substrate 111 in such a way that their major axes are perpendicular to the (111) plane. The III-V compound semiconductor can be any one of semiconductors composed of two elements, semiconductors composed of three elements, semiconductors composed of four elements, and semiconductors composed of more than the above number of types of elements. Examples of III-V compound semiconductors composed of two elements include: InAs, InP, GaAs, GaN, InSb, GaSb, and AlSb. Examples of III-V compound semiconductors composed of three elements include: AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, and AlInSb. Examples of III-V compound semiconductors composed of four or more elements include: InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb, and AlInGaPSb.

[0045] As described above, the III-V compound semiconductor nanowires 113 and 123 include: undoped first regions 113a and 123a (intrinsic semiconductors) and n-type highly doped second regions 113b and 123b (n-type semiconductors). The first regions 113a and 123a are connected to the (111) plane of the group-IV semiconductor substrate 111. The second regions 113b and 123b are connected to the second electrodes 117 and 127. The first regions 113a and 123a of the III-V compound semiconductor nanowires 113 and 123 form a substantially dislocation-free and defect-free bonding interface with the (111) plane of the group-IV semiconductor substrate 111.

[0046] The gate dielectric films 114 and 124 are insulating films that cover at least a part of the side surfaces of the III-V compound semiconductor nanowires 113 and 123. In this embodiment, the gate dielectric films 114 and 124 cover the entire side surfaces of the III-V compound semiconductor nanowires 113 and 123 and one surface of the group-IV semiconductor substrate 111 (more precisely, the insulating film 112). The gate dielectric films 114 and 124 are, for example, high-k dielectric films such as hafnium aluminate (HfAlO x ) films.

[0047] The insulating protective films 115 and 125 are films made of an insulating resin that cover the III-V compound semiconductor nanowires 113 and 123, the gate dielectric films 114 and 124, and the gate electrodes 118 and 128. The type of the insulating resin is not particularly limited. The insulating resin is, for example, a BCB resin.

[0048] The first electrodes 116 and 126 are disposed on the group-IV semiconductor substrate 111 and connected to the group-IV semiconductor substrate 111 (p-type semiconductor). The first electrodes 116 and 126 are, for example, Ti / Au alloy films. The first electrodes 116 and 126 may be disposed on the surface of the group-IV semiconductor substrate 111 where the III-V compound semiconductor nanowires 113 and 123 are disposed among the two surfaces of the group-IV semiconductor substrate 111, or may be disposed on the other surface of the group-IV semiconductor substrate 111 (the surface where the III-V compound semiconductor nanowires 113 and 123 are not disposed). In the first TFET 101, the first electrode 116 functions as a drain electrode. On the other hand, in the second TFET 102, the first electrode 126 functions as a source electrode.

[0049] The second electrodes 117 and 127 are disposed on the III-V compound semiconductor nanowires 113 and 123 and the insulating protective films 115 and 125 and connected to the second regions 113b and 123b (n-type semiconductors) of the III-V compound semiconductor nanowires 113 and 123. The second electrodes 117 and 127 are, for example, Ti / Au alloy films or Ge / Au / Ni / Au alloy films. In the first TFET 101, the second electrode 117 functions as a source electrode. On the other hand, in the second TFET 102, the second electrode 127 functions as a drain electrode.

[0050] The gate electrodes 118 and 128 are disposed so as to be able to apply an electric field to the bonding interface between the group-IV semiconductor substrate 111 and the first regions 113a and 123a of the III-V compound semiconductor nanowires 113 and 123. In the present embodiment, the gate electrodes 118 and 128 are disposed on the gate dielectric films 114 and 124 so as to cover the peripheries of the first regions 113a and 123a of the III-V compound semiconductor nanowires 113 and 123. The gate electrodes 118 and 128 are, for example, Ti / Au alloy films.

[0051] In the first TFET 101 and the second TFET 102, the bonding interface between the (111) plane of the group-IV semiconductor substrate 111 and the first regions 113a and 123a of the III-V compound semiconductor nanowires 113 and 123 functions as a tunnel layer. As described above, the first TFET 101 and the second TFET 102 have substantially the same structure. However, in the first TFET 101 and the second TFET 102, the source electrode (Figure 1 In it, the position relationship between the source electrode (denoted by "S") and the drain electrode ( Figure 1 denoted by "D" in it) is opposite. The inventor of the present invention found that by simply swapping the positions of the electrodes in this way, as Figure 2 shown, the first TFET 101 can operate as a TFET (p-TFET) with a p-type channel, and the second TFET 102 can operate as a TFET (n-TFET) with an n-type channel. Figure 3 is a graph showing the electrical characteristics of the first TFET 101 (p-TFET) and the second TFET 102 (n-TFET). As shown in this graph, the subthresholds of the first TFET 101 and the second TFET 102 are both below 40 mV / dec.

[0052] Figure 4A is for each potential V of the drain electrode relative to the source electrode DS representing room temperature in the second TFET 102 (n-TFET), the gate voltage V G and the drain current I D or the gate current I G relationship graph. In addition, Figure 4B is for each potential V of the drain electrode relative to the source electrode DS representing room temperature in the first TFET 101 (p-TFET), the gate voltage V G and the drain current I D relationship graph. From these graphs, it can be seen that even if the potential V of the drain electrode relative to the source electrode DS changes, the subthresholds of the first TFET 101 and the second TFET 102 are as follows, that is, the subthreshold of the second TFET 102 is at least 21 mV / dec and the average is below 40 mV / dec, and the subthreshold of the first TFET 101 is at least 6 mV / dec and the average is 40 mV / dec. It can also be seen that by swapping the source electrode and the drain electrode, complementary switching operations can be achieved with the same structure.

[0053] In the switching element 100 of this embodiment, by appropriately connecting one or more first TFETs 101 and one or more second TFETs 102, it can function as various complementary switching elements. Figure 5A is a perspective view showing an example of an inverter constituted by using the complementary switching element 100, Figure 5B is Figure 5A the circuit diagram of the inverter shown. Figure 5AIn [the figure], an example in which a complementary switching element 100 is formed on a BOX layer is shown, where the insulating film 112, the gate dielectric films 114 and 124, and the insulating protective films 115 and 125 are omitted. Figure 5A In [the figure], two silicon nanowire structures formed on the BOX layer in a non-contact manner with each other are respectively set as the group-IV semiconductor substrate 111 constituting the first TFET 101 and the group-IV semiconductor substrate 111 constituting the second TFET 102.

[0054] (Manufacturing method of complementary switching element)

[0055] For the manufacturing method of the switching element 100 of the present embodiment, it is not particularly limited. For example, the first TFET 101 and the second TFET 102 can be manufactured by the method described in International Publication No. 2011 / 040012.

[0056] Figures 6A - 6D is a schematic diagram showing an example of the manufacturing method of the switching element 100. Since the first TFET 101 and the second TFET 102 can be simultaneously manufactured in the same steps, Figures 6A - 6D in [the figure], only the manufacturing method of the first TFET 101 is shown. Next, with reference to Figures 6A - 6D the manufacturing method of the switching element 100 will be described.

[0057] First, as Figure 6A shown, a p-type highly doped group-IV semiconductor substrate 111 is prepared. An insulating film 112 is formed on the (111) plane of the group-IV semiconductor substrate 111 by thermal oxidation or the like. Next, as Figure 6B shown, an opening of a specified size (for example, a diameter of 20 nm) is formed in the insulating film 112 on the group-IV semiconductor substrate 111 using photolithography or the like. Next, as Figure 6C shown, using the MOVPE (Metal-Organic Vapor Phase Epitaxy) method, starting from the (111) plane of the group-IV semiconductor substrate 111 exposed through the opening, the III-V compound semiconductor nanowire 113 is grown. At this time, it is preferable to form a thin film of the III-V compound semiconductor on the (111) plane of the group-IV semiconductor substrate 111 by the alternate raw material supply modulation method before growing the III-V compound semiconductor nanowire 113 (refer to International Publication No. 2011 / 040012). In addition, immediately after the III-V compound semiconductor nanowire 113 is formed, the second region 113b of the III-V compound semiconductor nanowire 113 is doped to form an undoped first region 113a and an n-type highly doped second region 113b. Finally, as Figure 6DAs shown, a gate dielectric film 114, an insulating protective film 115, a first electrode 116, a second electrode 117, and a gate electrode 118 are formed.

[0058] (Effect)

[0059] In the switching element 100 of the present embodiment, the first TFET 101 (p-TFET) and the second TFET 102 (n-TFET) have substantially the same structure. Therefore, the switching element 100 of the present embodiment can be easily integrated while being a complementary switching element including TFETs.

[0060] [Embodiment 2]

[0061] In Embodiment 2, an example of a complementary switching element of the present invention in which a III-V compound semiconductor nanowire extends in a vertical direction from the surface of an n-type highly doped group-IV semiconductor substrate is shown.

[0062] (Structure of complementary switching element)

[0063] Figure 7 It is a cross-sectional view showing the structure of the complementary switching element 200 of Embodiment 2. For components that are the same as those of the TFET in Embodiment 1, the same reference numerals are given and the description of the repeated parts is omitted.

[0064] As Figure 7 shown, the switching element 200 of Embodiment 2 has at least one first tunnel field effect transistor (first TFET) 201 and at least one second tunnel field effect transistor (second TFET) 202.

[0065] The first TFET 201 is a TFET (n-TFET) having an n-type channel, and the second TFET 202 is a TFET (p-TFET) having a p-type channel. The first TFET 201 and the second TFET 202 have substantially the same structure. However, in the first TFET 201 and the second TFET 202, the source electrode ( Figure 7 in which is represented by "S") and the drain electrode ( Figure 7 in which is represented by "D") have opposite positional relationships.

[0066] The first TFET 201 includes a Group-IV semiconductor substrate 211, an insulating film 112, a Group-III-V compound semiconductor nanowire 213, a gate dielectric film 114, an insulating protective film 115, a first electrode (drain electrode) 116, a second electrode (source electrode) 117, and a gate electrode 118. The Group-III-V compound semiconductor nanowire 213 includes an undoped first region 213a and a p-type highly doped second region 213b. In the first TFET 201, the first electrode 116 is the drain electrode and the second electrode 117 is the source electrode. In the first TFET 201, tunneling occurs at the bonding interface between the (111) plane of the Group-IV semiconductor substrate 211 and the Group-III-V compound semiconductor nanowire 213.

[0067] The second TFET 202 includes a Group-IV semiconductor substrate 211, an insulating film 112, a Group-III-V compound semiconductor nanowire 223, a gate dielectric film 124, an insulating protective film 125, a first electrode (source electrode) 126, a second electrode (drain electrode) 127, and a gate electrode 128. The Group-III-V compound semiconductor nanowire 223 includes an undoped first region 223a and a p-type highly doped second region 223b. In the second TFET 202, the first electrode 126 is the source electrode and the second electrode 127 is the drain electrode. In the second TFET 202, tunneling occurs at the bonding interface between the (111) plane of the Group-IV semiconductor substrate 211 and the Group-III-V compound semiconductor nanowire 223.

[0068] The Group-IV semiconductor substrate 211 is made of a Group-IV semiconductor such as silicon or germanium, and is a substrate with its upper surface being the (111) plane. The Group-IV semiconductor substrate 211 is, for example, a silicon (111) substrate. In the present embodiment, the Group-IV semiconductor substrate 211 is n-type highly doped. The entire Group-IV semiconductor substrate 211 may be doped, or only a part of the Group-IV semiconductor substrate 211 may be doped.

[0069] In addition, the Group-IV semiconductor substrate 211 that forms the first TFET 201 and the Group-IV semiconductor substrate 211 that forms the second TFET 202 are electrically or spatially separated. For example, a structure having a conductivity type different from that of the Group-IV semiconductor substrate 211 may be disposed between the Group-IV semiconductor substrate 211 that forms the first TFET 201 and the Group-IV semiconductor substrate 211 that forms the second TFET 202, so as to electrically separate the Group-IV semiconductor substrate 211 that forms the first TFET 201 and the Group-IV semiconductor substrate 211 that forms the second TFET 202. Alternatively, two silicon nanowire structures formed on the BOX layer in a non-contact manner with each other may be respectively set as the Group-IV semiconductor substrate 211 that forms the first TFET 201 and the Group-IV semiconductor substrate 211 that forms the second TFET 202, so as to spatially separate the Group-IV semiconductor substrate 211 that forms the first TFET 201 and the Group-IV semiconductor substrate 211 that forms the second TFET 202.

[0070] The III-V compound semiconductor nanowires 213 and 223 are structures made of III-V compound semiconductors, having a diameter of 2 nm to 100 nm and a length of 50 nm to 10 μm. The III-V compound semiconductor nanowires 213 and 223 are disposed on the (111) plane of the Group-IV semiconductor substrate 211 in such a manner that their major axes are perpendicular to the (111) plane. The III-V compound semiconductor may be any one of semiconductors composed of two elements, semiconductors composed of three elements, semiconductors composed of four elements, and semiconductors composed of more than the above number of types of elements.

[0071] The III-V compound semiconductor nanowires 213 and 223 include undoped first regions 213a and 223a (intrinsic semiconductors) and p-type highly doped second regions 213b and 223b (p-type semiconductors). The first regions 213a and 223a are connected to the (111) plane of the Group-IV semiconductor substrate 211. The second regions 213b and 223b are connected to the second electrodes 117 and 127. The first regions 213a and 223a of the III-V compound semiconductor nanowires 213 and 223 form a substantially dislocation-free and defect-free bonding interface with the (111) plane of the Group-IV semiconductor substrate 211.

[0072] In the first TFET 201 and the second TFET 202, the bonding interface between the (111) plane of the Group-IV semiconductor substrate 211 and the first regions 213a and 223a of the III-V compound semiconductor nanowires 213 and 223 functions as a tunnel layer. As described above, the first TFET 201 and the second TFET 202 have substantially the same structure. However, in the first TFET 201 and the second TFET 202, the source electrode (Figure 7 In it, the source electrode (denoted by "S") and the drain electrode Figure 7 In it, the source electrode (denoted by "S") and the drain electrode (denoted by "D") have opposite positional relationships. The inventor of the present invention found that by simply swapping the positions of the electrodes in this way, as Figure 8 shown, the first TFET 201 can operate as a TFET with an n-type channel (n-TFET), and the second TFET 202 can operate as a TFET with a p-type channel (p-TFET). Therefore, by appropriately connecting one or more first TFETs 201 and one or more second TFETs 202, various complementary switching elements can be functioned.

[0073] (Manufacturing method of complementary switching element)

[0074] The manufacturing method of the switching element 200 of the present embodiment is not particularly limited. The switching element 200 of the second embodiment can be manufactured by the same steps as the switching element 100 of the first embodiment.

[0075] (Effect)

[0076] In the switching element 200 of the present embodiment, the first TFET 201 (n-TFET) and the second TFET 202 (p-TFET) have substantially the same structure. Therefore, the switching element 200 of the present embodiment can be easily integrated while being a complementary switching element including TFETs.

[0077] [Embodiment III]

[0078] In Embodiment III, an example of the complementary switching element of the present invention in which a group III-V compound semiconductor nanowire extends in an inclined direction from the surface of a p-type lightly doped group IV semiconductor substrate is shown.

[0079] (Structure of complementary switching element)

[0080] Figure 9 is a cross-sectional view showing the structure of the complementary switching element 300 of Embodiment III. As Figure 9 shown, the switching element 300 of Embodiment III has: at least one first tunnel field effect transistor (first TFET) 301 and at least one second tunnel field effect transistor (second TFET) 302.

[0081] The first TFET 301 is a TFET with an n-type channel (n-TFET), and the second TFET 302 is a TFET with a p-type channel (p-TFET). The first TFET 301 and the second TFET 302 have substantially the same structure. However, in the first TFET 301 and the second TFET 302, the source electrodeFigure 9 in which, represented by “S”) and the drain electrode ( Figure 9 in which, represented by “D”) is opposite.

[0082] The first TFET 301 includes a Group-IV semiconductor substrate 311, a Group-III-V compound semiconductor nanowire 312, an insulating film (gate dielectric film) 313, a first electrode (source electrode) 314, a second electrode (drain electrode) 315, and a gate electrode 316. A partial region of the insulating film 313 functions as a gate dielectric film. The Group-IV semiconductor substrate 311 includes: an undoped first region 311a and an n-type highly doped second region 311b. In the first TFET 301, the first electrode 314 is the source electrode and the second electrode 315 is the drain electrode. In the first TFET 301, a tunneling phenomenon occurs at the bonding interface between the (111) plane 311c of the Group-IV semiconductor substrate 311 and the Group-III-V compound semiconductor nanowire 312.

[0083] The second TFET 302 includes a Group-IV semiconductor substrate 311, a Group-III-V compound semiconductor nanowire 322, an insulating film (gate dielectric film) 323, a first electrode (drain electrode) 324, a second electrode (source electrode) 325, and a gate electrode 326. A partial region of the insulating film 323 functions as a gate dielectric film. The Group-IV semiconductor substrate 311 includes: an undoped first region 321a and an n-type highly doped second region 321b. In the second TFET 302, the first electrode 324 is the drain electrode and the second electrode 325 is the source electrode. In the second TFET 302, a tunneling phenomenon occurs at the bonding interface between the (111) plane 321c of the Group-IV semiconductor substrate 311 and the Group-III-V compound semiconductor nanowire 322.

[0084] The Group-IV semiconductor substrate 311 is made of a Group-IV semiconductor such as silicon or germanium, and is a substrate with a (100) plane on its upper surface. The Group-IV semiconductor substrate 311 is, for example, a silicon (100) substrate. In the present embodiment, the Group-IV semiconductor substrate 311 is p-type lightly doped. In the first TFET 301, on the surface of the Group-IV semiconductor substrate 311 where the III-V compound semiconductor nanowires 312 are disposed among the two surfaces, an undoped first region 311a (intrinsic semiconductor) and an n-type highly doped second region 311b (n-type semiconductor) are formed adjacent to each other. The first region 311a has not only a (100) plane but also a (111) plane 311c. Similarly, in the second TFET 302, on the surface of the Group-IV semiconductor substrate 311 where the III-V compound semiconductor nanowires 322 are disposed among the two surfaces, an undoped first region 321a (intrinsic semiconductor) and an n-type highly doped second region 321b (n-type semiconductor) are formed adjacent to each other. The first region 321a has not only a (100) plane but also a (111) plane 321c.

[0085] The III-V compound semiconductor nanowires 312 and 322 are structures made of a III-V compound semiconductor, with a diameter of 2 nm to 100 nm and a length of 50 nm to 10 μm. The III-V compound semiconductor nanowires 312 and 322 are disposed on the (111) planes 311c and 321c of the Group-IV semiconductor substrate 311 such that their major axes are perpendicular to the (111) planes 311c and 321c. The III-V compound semiconductor can be any one of a semiconductor composed of two elements, a semiconductor composed of three elements, a semiconductor composed of four elements, and a semiconductor composed of more than the above number of types of elements. Examples of the III-V compound semiconductor composed of two elements include: InAs, InP, GaAs, GaN, InSb, GaSb, and AlSb. Examples of the III-V compound semiconductor composed of three elements include: AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, and AlInSb. Examples of the III-V compound semiconductor composed of four or more elements include: InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb, and AlInGaPSb.

[0086] The III-V compound semiconductor nanowires 312 and 322 are undoped or lightly p-doped. In this embodiment, the III-V compound semiconductor nanowires 312 and 322 are lightly p-doped. The III-V compound semiconductor nanowires 312 and 322 and the (111) planes 311c and 321c of the group-IV semiconductor substrate 311 form a substantially dislocation-free and defect-free bonding interface.

[0087] The insulating films 313 and 323 are insulating films that cover at least the entire surface ((100) plane) of the first regions 311a and 321a of the group-IV semiconductor substrate 311 and a part of the surface ((100) plane) of the second regions 311b and 321b. As described above, a part of the regions of the insulating films 313 and 323 functions as a gate dielectric film. In this embodiment, the insulating films 313 and 323 cover the entire surface of the first regions 311a and 321a, a part of the surface of the second regions 311b and 321b, and the part of the group-IV semiconductor substrate 311 located under the first electrodes 314 and 324. The insulating films 313 and 323 are, for example, high-k dielectric films such as hafnium aluminate (HfAlO x ) films.

[0088] The first electrodes 314 and 324 are disposed on the group-IV semiconductor substrate 311 with the insulating films 313 and 323 therebetween, and are connected to the III-V compound semiconductor nanowires 312 and 322 (p-type semiconductors). The first electrodes 314 and 324 are, for example, Ti / Au alloy films. In the first TFET 301, the first electrode 314 functions as a source electrode. On the other hand, in the second TFET 302, the first electrode 324 functions as a drain electrode.

[0089] The second electrodes 315 and 325 are disposed on the second regions 311b and 321b of the group-IV semiconductor substrate 311 and are connected to the second regions 311b and 321b (n-type semiconductors). The second electrodes 315 and 325 are, for example, Ti / Au alloy films or Ge / Au / Ni / Au alloy films. In the first TFET 301, the second electrode 315 functions as a drain electrode. On the other hand, in the second TFET 302, the second electrode 325 functions as a source electrode.

[0090] The gate electrodes 316 and 326 are disposed in such a manner that an electric field can be applied to the bonding interface between the first regions 311a and 321a of the group-IV semiconductor substrate 311 and the III-V compound semiconductor nanowires 312 and 322. In this embodiment, the gate electrodes 316 and 326 are disposed on the insulating films (gate dielectric films) 313 and 323 on the first regions 311a and 321a. The gate electrodes 316 and 326 are, for example, Ti / Au alloy films.

[0091] In the first TFET 301 and the second TFET 302, the bonding interfaces between the (111) planes 311c and 321c of the Group IV semiconductor substrate 311 and the Group III-V compound semiconductor nanowires 312 and 322 function as tunnel layers. As described above, the first TFET 301 and the second TFET 302 have substantially the same structure. However, in the first TFET 301 and the second TFET 302, the Figure 9 source electrode ( Figure 9 denoted by "S" herein) and the drain electrode ( Figure 10 denoted by "D" herein) have opposite positional relationships. The inventors of the present invention found that by simply swapping the positions of the electrodes in this way, as Figure 11 shown, the first TFET 301 can operate as a TFET with an n-type channel (n-TFET), and the second TFET 302 can operate as a TFET with a p-type channel (p-TFET). Figure 11 FIG. is a graph showing the electrical characteristics of the first TFET 301 (n-TFET) and the second TFET 302 (p-TFET). As shown in this graph, the minimum values of the subthresholds of the first TFET 301 and the second TFET 302 are both 50 mV / dec.

[0092] In the switching element 300 of the present embodiment, by appropriately connecting one or more first TFETs 301 and one or more second TFETs 302, it is possible to function as various complementary switching elements. Figure 12A FIG. is a perspective view showing an example of an inverter constituted by the complementary switching element 300, Figure 12B and Figure 12A FIG. is the circuit diagram of the inverter shown. Figure 12A FIG. shows an example of forming the complementary switching element 300 by forming fin-shaped first TFETs 301 and fin-shaped second TFETs 302 on a BOX layer, in which a part of the Group IV semiconductor substrate 311 is omitted. Figure 13 FIG. is a graph showing the electrical characteristics of the fin-shaped first TFET 301 (n-TFET) and the fin-shaped second TFET 302 (p-TFET). As shown in this graph, the subthresholds of the first TFET 301 and the second TFET 302 are both below 40 mV / dec.

[0093] (Manufacturing method of complementary switching element)

[0094] The manufacturing method of the switching element 300 of the present embodiment is not particularly limited. For example, the first TFET 301 and the second TFET 302 can be manufactured by the method described in International Publication No. 2011 / 040012.

[0095] Figures 14A - 14D FIG. Figures 14A - 14D is a schematic view showing an example of a method for manufacturing a switching element 300. Since the first TFET 301 and the second TFET 302 can be fabricated simultaneously in the same process steps, Figures 14A - 14D only the manufacturing method of the first TFET 301 is shown in FIG. Figures 14A - 14D . Hereinafter, with reference to Figures 14A - 14D FIG. Figures 14A - 14D , the manufacturing method of the switching element 300 will be described.

[0096] First, as shown in Figure 14A FIG. Figure 14A , a group-IV semiconductor substrate 311 is prepared. An undoped first region 311a and an n-type highly doped second region 311b are formed in the group-IV semiconductor substrate 311. Next, as shown in Figure 14B FIG. Figure 14B , anisotropic etching is performed on the first region 311a of the group-IV semiconductor substrate 311 to expose the (111) plane 311c. In addition, an insulating film 313 is formed on the surface of the group-IV semiconductor substrate 311 by thermal oxidation or the like. An opening is formed in the insulating film 313 so as to expose the (111) plane 311c of the first region 311a of the group-IV semiconductor substrate 311. Next, as shown in Figure 14C FIG. Figure 14C , by using the MOVPE method, a III-V compound semiconductor nanowire 312 is grown from the (111) plane 311c of the first region 311a through the opening. At this time, before growing the III-V compound semiconductor nanowire 312, it is preferable to form a thin film of a III-V compound semiconductor on the (111) plane 311c of the first region 311a by an alternate raw material supply modulation method (see International Publication No. 2011 / 040012). Finally, as shown in Figure 14D FIG. Figure 14D , a first electrode 314, a second electrode 315, and a gate electrode 316 are formed.

[0097] (Effect)

[0098] In the switching element 300 of the present embodiment, the first TFET 301 (n-TFET) and the second TFET 302 (p-TFET) have substantially the same structure. Therefore, the switching element 300 of the present embodiment can be easily integrated while being a complementary switching element including TFETs.

[0099] [Embodiment 4]

[0100] In Embodiment 4, an example of a complementary switching element of the present invention is shown in which a III-V compound semiconductor nanowire extends in an inclined direction from the surface of an n-type lightly doped group-IV semiconductor substrate.

[0101] (Structure of Complementary Switching Element)

[0102] Figure 15It is a cross-sectional view showing the structure of the complementary switching element 400 of Embodiment 4. Regarding the constituent elements identical to those of the TFET of Embodiment 3, the same reference numerals are given and the description of the repeated parts is omitted.

[0103] As Figure 15 shown, the switching element 400 of Embodiment 4 has: at least one first tunnel field effect transistor (first TFET) 401 and at least one second tunnel field effect transistor (second TFET) 402.

[0104] The first TFET 401 is a TFET with a p-type channel (p-TFET), and the second TFET 402 is a TFET with an n-type channel (n-TFET). The first TFET 401 and the second TFET 402 have substantially the same structure. However, in the first TFET 401 and the second TFET 402, the source electrode ( Figure 15 denoted by “S” herein) and the drain electrode ( Figure 15 denoted by “D” herein) have opposite positional relationships.

[0105] The first TFET 401 has a Group-IV semiconductor substrate 411, a Group-III-V compound semiconductor nanowire 412, an insulating film (gate dielectric film) 313, a first electrode (source electrode) 314, a second electrode (drain electrode) 315, and a gate electrode 316. A part of the region of the insulating film 313 also functions as a gate dielectric film. The Group-IV semiconductor substrate 411 includes: an undoped first region 411a and a p-type highly doped second region 411b. In the first TFET 401, the first electrode 314 is the source electrode and the second electrode 315 is the drain electrode. In the first TFET 401, tunneling occurs at the bonding interface between the (111) plane 411c of the Group-IV semiconductor substrate 411 and the Group-III-V compound semiconductor nanowire 412.

[0106] The second TFET 402 has a Group-IV semiconductor substrate 411, a Group-III-V compound semiconductor nanowire 422, an insulating film (gate dielectric film) 323, a first electrode (drain electrode) 324, a second electrode (source electrode) 325, and a gate electrode 326. A part of the region of the insulating film 323 also functions as a gate dielectric film. The Group-IV semiconductor substrate 411 includes: an undoped first region 421a and a p-type highly doped second region 421b. In the second TFET 402, the first electrode 324 is the drain electrode and the second electrode 325 is the source electrode. In the second TFET 402, tunneling occurs at the bonding interface between the (111) plane 421c of the Group-IV semiconductor substrate 411 and the Group-III-V compound semiconductor nanowire 422.

[0107] The Group-IV semiconductor substrate 411 is made of a Group-IV semiconductor such as silicon or germanium, and is a substrate having a (100) plane on its upper surface. The Group-IV semiconductor substrate 411 is, for example, a silicon (100) substrate. In the present embodiment, the Group-IV semiconductor substrate 411 is n-type lightly doped. In the first TFET 401, on the surface of the Group-IV semiconductor substrate 411 where the III-V compound semiconductor nanowires 412 are disposed among the two surfaces, an undoped first region 411a (intrinsic semiconductor) and a p-type highly doped second region 411b (p-type semiconductor) are formed so as to be adjacent to each other. The first region 411a has not only a (100) plane but also a (111) plane 411c. Similarly, in the second TFET 402, on the surface of the Group-IV semiconductor substrate 411 where the III-V compound semiconductor nanowires 422 are disposed among the two surfaces, an undoped first region 421a (intrinsic semiconductor) and a p-type highly doped second region 421b (p-type semiconductor) are formed so as to be adjacent to each other. The first region 421a has not only a (100) plane but also a (111) plane 421c.

[0108] The III-V compound semiconductor nanowires 412 and 422 are structures made of a III-V compound semiconductor, having a diameter of 2 nm to 100 nm and a length of 50 nm to 10 μm. The III-V compound semiconductor nanowires 412 and 422 are disposed on the (111) planes 411c and 421c of the Group-IV semiconductor substrate 411 such that their major axes are perpendicular to the (111) planes 411c and 421c. The III-V compound semiconductor can be any one of a semiconductor composed of two elements, a semiconductor composed of three elements, a semiconductor composed of four elements, and a semiconductor composed of more than the above number of types of elements.

[0109] The III-V compound semiconductor nanowires 412 and 422 are undoped or n-type lightly doped. In the present embodiment, the III-V compound semiconductor nanowires 412 and 422 are n-type lightly doped. The III-V compound semiconductor nanowires 412 and 422 form a substantially dislocation-free and defect-free bonding interface with the (111) planes 411c and 421c of the Group-IV semiconductor substrate 411.

[0110] In the first TFET 401 and the second TFET 402, the bonding interfaces between the (111) planes 411c and 421c of the Group IV semiconductor substrate 411 and the Group III-V compound semiconductor nanowires 412 and 422 function as tunnel layers. As described above, the first TFET 401 and the second TFET 402 have substantially the same structure. However, in the first TFET 401 and the second TFET 402, the positional relationship between the source electrode ( Figure 15 denoted by "S" herein) and the drain electrode ( Figure 15 denoted by "D" herein) is opposite. The inventors of the present invention have found that by simply swapping the positions of the electrodes in this way, as Figure 16 shown, the first TFET 401 can operate as a TFET with a p-type channel (p-TFET), and the second TFET 402 can operate as a TFET with an n-type channel (n-TFET). Therefore, by appropriately connecting one or more first TFETs 401 and one or more second TFETs 402, it is possible to function as various complementary switching elements.

[0111] (Method for manufacturing a complementary switching element)

[0112] The manufacturing method of the switching element 400 of the present embodiment is not particularly limited. The switching element 400 of the fourth embodiment can be manufactured by the same steps as the switching element 300 of the third embodiment.

[0113] (Effect)

[0114] In the switching element 400 of the present embodiment, the first TFET 401 (p-TFET) and the second TFET 402 (n-TFET) have substantially the same structure. Therefore, the switching element 400 of the present embodiment can be easily integrated while being a complementary switching element including TFETs.

[0115] In addition, in the present embodiment, a switching element having a single-gate TFET in which one gate electrode is arranged for one channel has been described. However, each TFET may also have a multi-gate TFET in which a plurality of gate electrodes are arranged for one channel.

[0116] This application claims priority based on Japanese Patent Application No. 2018-247228 filed on December 28, 2018. All the contents described in the specification and drawings of this application are incorporated herein by reference.

[0117] Industrial Applicability

[0118] The complementary switching element of the present invention is useful as a switching element formed in a semiconductor microprocessor and a high-level integrated circuit, for example.

[0119] Description of Reference Numerals

[0120] 100, 200 Complementary switching element

[0121] 101, 201 First tunnel field effect transistor (first TFET)

[0122] 102, 202 Second tunnel field effect transistor (second TFET)

[0123] 111, 211 Group IV semiconductor substrate

[0124] 112 Insulating film

[0125] 113, 123, 213, 223 III-V compound semiconductor nanowire

[0126] 113a, 123a, 213a, 223a First region

[0127] 113b, 123b, 213b, 223b Second region

[0128] 114, 124 Gate dielectric film

[0129] 115, 125 Insulating protective film

[0130] 116, 126 First electrode

[0131] 117, 127 Second electrode

[0132] 118, 128 Gate electrode

[0133] 300, 400 Complementary switching element

[0134] 301, 401 First tunnel field effect transistor (first TFET)

[0135] 302, 402 Second tunnel field effect transistor (second TFET)

[0136] 311, 411 Group IV semiconductor substrate

[0137] 311a, 321a, 411a, 421a First region

[0138] 311b, 321b, 411b, 421b Second region

[0139] 311c, 321c, 411c, 421c (111) plane

[0140] III-V compound semiconductor nanowires 312, 322, 412, 422

[0141] Insulating films (gate dielectric films) 313, 323

[0142] First electrodes 314, 324

[0143] Second electrodes 315, 325

[0144] Gate electrodes 316, 326

Claims

1. A complementary switching element having a first tunnel field effect transistor with a channel of a first conductivity type and a second tunnel field effect transistor with a channel of a second conductivity type different from the first conductivity type. In the complementary switching element, the first tunnel field effect transistor and the second tunnel field effect transistor each have: a Group-IV semiconductor substrate having a (111) plane and doped with the first conductivity type; a Group-III-V compound semiconductor nanowire disposed on the (111) plane and including a first region connected to the (111) plane and a second region doped with the second conductivity type; a first electrode connected to the Group-IV semiconductor substrate; a second electrode connected to the second region; and a gate electrode for applying an electric field to an interface between the (111) plane and the first region, in the first tunnel field effect transistor, the second electrode is a source electrode and the first electrode is a drain electrode, in the second tunnel field effect transistor, the first electrode is a source electrode and the second electrode is a drain electrode.

2. The complementary switching element according to claim 1, wherein the Group-IV semiconductor constituting the Group-IV semiconductor substrate is silicon or germanium, the Group-III-V compound semiconductor constituting the Group-III-V compound semiconductor nanowire is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, the major axis of the Group-III-V compound semiconductor nanowire is perpendicular to the (111) plane.

3. The complementary switching element according to claim 1 or 2, wherein the first tunnel field effect transistor and the second tunnel field effect transistor each further have a gate dielectric film disposed on a side surface of the Group-III-V compound semiconductor nanowire, the gate electrode is disposed on the gate dielectric film.

4. A complementary switching element having a first tunnel field effect transistor with a channel of a first conductivity type and a second tunnel field effect transistor with a channel of a second conductivity type different from the first conductivity type. In the complementary switching element, the first tunnel field effect transistor and the second tunnel field effect transistor each have: a Group-IV semiconductor substrate including a first region having a (111) plane and a second region doped with the first conductivity type; a Group-III-V compound semiconductor nanowire disposed on the (111) plane and being undoped or doped with the second conductivity type; a first electrode connected to the Group-III-V compound semiconductor nanowire; a second electrode connected to the second region; and A gate electrode that applies an electric field to the interface between the III-V compound semiconductor nanowire and the (111) plane, In the first tunnel field effect transistor, the first electrode is a source electrode and the second electrode is a drain electrode, In the second tunnel field effect transistor, the second electrode is a source electrode and the first electrode is a drain electrode.

5. The complementary switching element according to claim 4, wherein, The Group-IV semiconductor constituting the Group-IV semiconductor substrate is silicon or germanium, The III-V compound semiconductor constituting the III-V compound semiconductor nanowire is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, The major axis of the III-V compound semiconductor nanowire is perpendicular to the (111) plane.

6. The complementary switching element according to claim 4 or 5, wherein, Each of the first tunnel field effect transistor and the second tunnel field effect transistor further has a gate dielectric film disposed on the surface of the Group-IV semiconductor substrate, The gate electrode is disposed on the gate dielectric film.

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