Turn-off circuit for protecting a switch

Abstract

The switching circuit (108) includes: a power transistor (110) having a source coupled to a power supply terminal (104), a drain coupled to an output terminal (106), and a gate (131); a bipolar transistor (130) having a collector coupled to a power supply terminal (104), an emitter coupled to the gate (131) of the power transistor (110), and a base (132); a bias circuit (133) for controlling the emitter current of the bipolar transistor (130); and a resistor (138) coupled between the power supply terminal (104) and the base (132). The control circuit (139) receives current at the current input terminal to turn on the bipolar transistor (130) in response to a first state of the control input terminal (128), and stops receiving current at the current input terminal to reduce the gate-source voltage of the power transistor (110) in response to a different second state of the control input terminal (128).

Description

Background Technology

[0001] Electrical systems are designed to operate when powered by input power within a specific voltage range. Protective switches are typically used to connect the power supply output to the power input of a load circuit for operation. When the input power supply voltage exceeds a limit, the protective switch turns off to protect the load circuit from overvoltage conditions. Because the protective switch conducts current from the power supply to the load during normal operation, its size should be appropriate for the expected load current and input voltage. Furthermore, protective switches are typically large to provide low switching impedance to mitigate power dissipation in protective switches (such as the low drain-source on-state resistance (RDSON) of field-effect transistors (FETs). Additionally, a fast turn-off time is important for protecting load circuit systems where the power supply voltage rises rapidly. However, protective switches typically have large gate-drain and gate-source capacitances that require rapid discharge to turn off the protective switch in a short time. Summary of the Invention

[0002] According to one aspect, a switch circuit includes a power supply terminal, a reference terminal, and a power transistor having a source, drain, and gate coupled to the power supply terminal. A bipolar transistor has a collector, emitter, and base. The emitter is coupled to the power supply terminal, and the emitter is coupled to the gate of the power transistor. The switch circuit also includes a bias circuit coupled to the gate of the power transistor, and a resistor coupled between the power supply terminal and the base. A control circuit includes a control input, a current input, and a reference input. The current input is coupled to the base of the bipolar transistor, and the reference input is coupled to a reference terminal. The control circuit is configured to receive current at the current input in response to a first state at the control input, and to stop receiving current in response to a second state at the control input.

[0003] In one example, the bias circuit has a current source coupled between the gate of the power transistor and a reference terminal. In another example, the control circuit includes a control transistor having a drain, a source, and a gate. The drain is coupled to the base. The control circuit also includes a control current source coupled between the source of the control transistor and the reference terminal. In this example, the control circuit also includes a switching circuit coupled to the gate of the control transistor to turn on the control transistor to receive current at the current input in response to a first state at the control input, and to turn off the control transistor to interrupt the current through the resistor in response to a second state at the control input. In one implementation of this example, the switching circuit includes a first switch having a first terminal and a second terminal, the first terminal being coupled to a clamping power supply terminal having a clamping power supply voltage lower than a first voltage at the power supply terminal, the second terminal being coupled to the gate of the control transistor; and a second switch having a first terminal coupled to the gate of the control transistor and a second terminal coupled to the reference terminal.

[0004] One example includes a p-channel field-effect transistor (PFET) having a source coupled to a power supply terminal, a drain coupled to a base, and a gate, and a second resistor coupled between the power supply terminal and the gate. In this example, the control circuitry conducts a second current through the second resistor in response to a second state at the control input, and interrupts the second current in response to a first state at the control input.

[0005] In one example, the control circuitry includes a second control transistor having a drain, a source, and a gate. The drain is coupled to the gate of the PFET. In this example, the control circuitry turns on the second control transistor in response to a second state at the control input to receive a second current from the gate of the PFET at the second current input, and turns off the second control transistor in response to a first state at the control input to stop receiving the second current at the second current input. In one implementation of this example, the switching circuitry includes a first switch having a first terminal and a second terminal, the first terminal being coupled to a clamping power supply terminal having a clamping power supply voltage lower than a first voltage of the power supply terminal, the second terminal being coupled to the gate of the control transistor; and a second switch having a first terminal coupled to the gate of the control transistor and a second terminal coupled to a reference terminal.

[0006] The switching circuit in this example also includes a third switch having a first terminal coupled to a clamping power supply terminal and a second terminal coupled to the gate of a second control transistor; and a fourth switch having a first terminal coupled to the gate of the second control transistor and a second terminal coupled to a reference terminal. In this implementation, the switching circuit turns on the first and fourth switches in response to a first state at the control input, and turns off the first and fourth switches in response to a second state at the control input. In this example, the switching circuit turns off the second and third switches in response to a first state at the control input, and turns on the second and third switches in response to a second state at the control input.

[0007] In one example, the switching circuit also includes a second PFET having a source coupled to a power supply terminal, a drain coupled to the gate of a power transistor, and a gate coupled to a power supply terminal.

[0008] According to another aspect, a circuit is provided for turning off a power transistor coupled between a power supply terminal and an output terminal. The circuit includes a bipolar transistor having a collector, an emitter, and a base. The collector is configured to be coupled to the power supply terminal, and the emitter is configured to be coupled to a control terminal of the power transistor. A bias circuit is coupled between the control terminal and a reference terminal of the power transistor to control the emitter current of the bipolar transistor. A resistor is coupled between the power supply terminal and the base. The circuit also includes a control circuit having a control input, a reference input, and a current input. The current input is coupled to the base, and the reference input is coupled to the reference terminal. The control circuit is configured to receive current through the resistor at the current input to turn on the bipolar transistor in response to a first state at the control input, and to stop receiving current at the current input to reduce the gate-source voltage of the power transistor in response to a further second state at the control input.

[0009] In one example, the control circuitry includes a control transistor, a control current source, and a switching circuit. The control transistor has a drain, a source, and a gate coupled to its base, and the control current source is coupled between the source of the control transistor and a reference terminal. The switching circuitry is configured to turn on the control transistor in response to a first state at the control input to receive current from the base at the current input, and to turn off the control transistor in response to a second state at the control input to stop receiving current at the current input.

[0010] One example circuit includes a PFET and a second resistor. The PFET has a source configured to be coupled to a power supply terminal, a drain coupled to a base, and a gate. The second resistor has a first terminal configured to be coupled to the power supply terminal and a second terminal coupled to the gate of the PFET at a second current input of the control circuit. In this example, the control circuit is configured to receive a second current at the second current input to turn on the PFET in response to a second state at the control input, and to stop receiving the second current at the second current input to turn off the PFET in response to a first state at the control input.

[0011] In one example, the circuit also includes a second PFET having a source coupled to a power supply terminal, a drain coupled to a control terminal of a power transistor, and a gate coupled to the gate of the PFET.

[0012] According to another aspect, the protection system includes a clamping power supply circuit, a sensing circuit, a comparator, and a power transistor. The clamping power supply circuit has an input terminal and an output terminal, wherein the input terminal is coupled to a power supply terminal, and the output terminal is configured to provide a clamping power supply voltage lower than the power supply terminal voltage. The sensing circuit has an input terminal and an output terminal, the input terminal being coupled to sense the voltage at the power supply terminal. The comparator has a first input terminal, a second input terminal, and a comparator output terminal. The first input terminal is coupled to the output terminal of the sensing circuit, the second input terminal is coupled to a voltage reference terminal, and the comparator output terminal has a first state in response to the voltage at the output terminal of the sensing circuit being less than a reference voltage at the voltage reference terminal, and a second state in response to the voltage at the output terminal of the sensing circuit being greater than the reference voltage. The power transistor has a source, a drain, and a gate. The source is coupled to a power supply terminal, and the drain is coupled to an output terminal. The protection system also includes a bipolar transistor, a bias circuit, a resistor, and a control circuit. The bipolar transistor has a collector, an emitter, and a base. The collector is coupled to a power supply terminal, and the emitter is coupled to the gate of the power transistor. A bias circuit is coupled between the gate and a reference terminal of the power transistor and configured to control the emitter current of the bipolar transistor. A resistor is coupled between the power supply terminal and the base. The control circuit has a control input, a current input, and a reference input. The control input is coupled to the comparator output, the current input is coupled to the base, and the reference input is coupled to a reference terminal. The control circuit is configured to receive current at the control input to turn on the bipolar transistor in response to a first state at the comparator output, and to stop receiving current at the current input in response to a second state at the comparator output.

[0013] In one example, the control circuitry includes a control transistor, a control current source, and a switching circuit. The control transistor has a drain, a source, and a gate, with the drain coupled to the base, and the control current source coupled between the source of the control transistor and a reference terminal. In this example, the switching circuitry turns on the control transistor in response to a first state at the comparator output to receive current from the base at the current input, and turns off the control transistor in response to a second state at the comparator output to stop receiving current through the resistor at the current input.

[0014] The protection system in one example also includes a PFET and a second resistor. The PFET has a source coupled to a power supply terminal, a drain coupled to a base, and a gate, and the second resistor is coupled between the power supply terminal and the gate of the PFET. In this example, the second current input of the control circuit is configured to receive a second current in response to a second state at the comparator output, and to stop receiving the second current in response to a first state at the comparator output.

[0015] In one example, the protection system also includes a second PFET having a source coupled to a power supply terminal, a drain coupled to the gate of a power transistor, and a gate coupled to the gate of the PFET. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a protection system with a high-voltage protection switch circuit.

[0017] Figure 2 yes Figure 1 Signal diagram in the high-voltage protection switch circuit.

[0018] Figure 3 It is in the first state. Figure 1 A schematic diagram of an example of a high-voltage protection switch circuit.

[0019] Figure 4 It is in the second state. Figure 1 A schematic diagram of an example of a high-voltage protection switch circuit. Detailed Implementation

[0020] In the accompanying drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. Furthermore, the term "coupled" includes indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intermediate devices and connections. One or more operating characteristics of various circuits, systems, and / or components are described below in the context of their functions, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is powered and operated.

[0021] Figure 1 A protection system 100 for protecting a load is shown. The protection system 100 receives an input power supply voltage VSUP from a DC power supply 102 referenced to ground or a reference voltage at a reference terminal 103. The DC power supply 102 provides the power supply voltage VSUP at a power supply terminal 104. In one implementation, this is achieved via a power transistor 110 (in...) Figure 1 A high-voltage switching circuit 108 (labeled MP0) couples a power supply terminal 104 to an output terminal 106, which selectively couples a DC power supply 102 to a load 105. The switching circuit 108 includes circuitry for turning off a power transistor 110 in response to the power supply voltage VSUP reaching or exceeding a limit, thereby protecting the circuitry of the load 105 from overvoltage conditions. To accommodate high-voltage operation, the switching circuit 108 includes a level-shifting circuit 112 to facilitate low-power monitoring of the power supply voltage VSUP level and rapid turn-off of the power transistor 110. In one example, the power transistor 110 is a high-voltage p-channel FET having a source coupled to the power supply terminal 104, a drain coupled to the output terminal 106, and a gate. In one example, as... Figure 1 As schematically shown, power transistor 110 and other transistors in switching circuit 108 have body connections coupled to the source terminal. In operation, power transistor 110 is turned on, and load 105 has a load voltage VLOAD that is approximately equal to the supply voltage VSUP minus the source-drain voltage of power transistor 110.

[0022] The level shifting circuit 112 is powered by a clamping power supply voltage VDD_CMP provided by a clamping power supply circuit 114, which has an input coupled to power supply terminal 104 and an output providing the clamping power supply voltage VDD_CMP at clamping power supply terminal 116. In one example, the clamping power supply voltage VDD_CMP at clamping power supply terminal 116 is lower than the power supply voltage VSUP at power supply terminal 104. The protection system 100 also includes a comparator 118 powered by the clamping power supply voltage VDD_CMP. In the illustrated example, the comparator 118 is coupled in a single-ended configuration, with the positive power rail coupled to clamping power supply terminal 116 and the second power rail coupled to reference terminal 103.

[0023] The protection system 100 also includes a sensing circuit having a sensing circuit output 120 that provides a voltage divider power supply voltage signal VSUP_DIV to a first (e.g., non-inverting) input of comparator 118. The sensing circuit includes a first resistor 121 and a second resistor 122 that form a resistive voltage divider circuit. The first resistor 121 (labeled R0) has a first terminal coupled to the sensing circuit input terminal 104 and a second terminal coupled to the sensing circuit output 120. The second resistor 122 (labeled R1) has a first terminal coupled to the sensing circuit output 120 and a second terminal coupled to a reference terminal 103.

[0024] The second (e.g., inverting) input 124 of comparator 118 is coupled to a voltage reference terminal 126, which provides a reference voltage VREF referenced to the voltage at reference terminal 103. The comparator output 128 provides a control signal DIS_SW to a level shifter circuit 112 to selectively disable power transistor 110 (e.g., turn off power transistor 110 to disconnect load 105 from power supply terminal 104). In operation, in response to a voltage divider supply voltage VSUP_DIV being less than the reference voltage VREF at voltage reference terminal 126, the output 128 of comparator 118 provides a control signal DIS_SW in a first state (e.g., low). In response to a voltage divider supply voltage VSUP_DIV being greater than the reference voltage VREF, the output 128 of comparator 118 provides a control signal DIS_SW in a further second state (e.g., high). In one example, comparator 118 is a hysteresis comparator to mitigate undesirable switching between the first and second states. During operation, the supply voltage VSUP may exceed its nominal operating voltage by many times (e.g., in fault conditions). Therefore, comparator 118 is powered by the clamp supply voltage VDD_CMP, which is clamped to its maximum value, regardless of the supply voltage VSUP. For example, if the nominal supply voltage VSUP is 3.3V, the clamp supply voltage VDD_CMP in one example is 2.6V.

[0025] However, during a power failure, if the supply voltage VSUP becomes 15V, the clamping supply voltage VDD_CMP in this example will not exceed 3.5V. Furthermore, in one example, the supply voltage VSUP is not directly supplied to the comparator; therefore, the sensing circuit resistor dividers 121, 122 scale down the supply voltage VSUP to a divided supply voltage VSUP_DIV, and in this example, the ratio of resistors 121 and 122 is set such that when the supply voltage VSUP reaches its maximum voltage (e.g., 15V under fault conditions), VSUP_DIV will still be within the safe operating voltage range of the comparator input. The level shifting circuit 112 operates to shift the output of the comparator control signal DIS_SW to a voltage level suitable for driving the power transistor 110 (e.g., via the signal VG_SW). In one example, the power transistor 110 is a high-voltage extended-drain PMOS transistor (DEPMOS).

[0026] Based on the current state of the control input coupled to receive the control signal DIS_SW from the comparator output 128, the level shift circuit 112 operates so that it remains on when the control signal DIS_SW is in the first state (low) and selectively turns off the power transistor 110 in response to the control signal DIS_SW being in the second state (high). When the DC power supply 102 is initially powered on, the rising supply voltage VSUP at the source of the power transistor 110 provides the gate-source voltage VGS, and since the gate voltage of the power transistor 110 is lower than the rising source voltage, the power transistor 110 is turned on to couple the power supply terminal 104 to the output terminal 106. The clamping power supply circuit 114 provides the clamping power supply voltage VDD_CMP to the level shift circuit 112 and the comparator 118, and the system begins monitoring the level of the power supply voltage VSUP by comparing the divided supply voltage VSUP_DIV with the reference voltage VREF. In one example, as further described below, the relative values ​​of the reference voltage VREF and the sensing circuit resistors 121 and 122 are designed to establish a threshold below which the power transistor 110 is allowed to remain on, and above which the level shifting circuit 112 will initiate a rapid turn-off of the power transistor 110.

[0027] Switching circuit 108 includes bipolar transistor 130 (labeled QN0) coupled to level shifting circuit 112 to rapidly discharge the gate-source capacitance of power transistor 110 in response to control signal DIS_SW being in a second state, thereby rapidly turning off power transistor 110. Bipolar transistor 130 has a collector, an emitter, and a base. The collector is coupled to power supply terminal 104, the emitter is coupled to the gate of power transistor 110 at a first node 131, and the base is coupled to a second node 132. When bipolar transistor 130 is turned on, the voltage across the gate-source capacitance of power transistor 110 is just enough to charge the current path formed by the collector and emitter of bipolar transistor 130. Level shifting circuit 112 includes biasing circuit 133 coupled between the first node 131 (the gate of power transistor (110)) and reference terminal 103. The bias circuit 133 is configured to control the emitter current of the bipolar transistor 130 to facilitate the rapid discharge of the source-gate capacitance of the power transistor 110.

[0028] The bias circuit 133 has an n-channel field-effect transistor 134 (NFET, denoted as MN0) connected in series with a first current source 136 between a first node 131 and a reference terminal 103. The transistor 134 includes a drain, a source, and a gate. The drain is coupled to the first node 131, the source is coupled to the first current source 136, and the gate is coupled to a clamping power supply terminal 116. The first current source 136 is coupled between the source of the transistor 134 and the reference terminal 103. The transistor 134 is turned on in response to the establishment of the clamping power supply voltage VDD_CMP, allowing the bias circuit 133 to receive a current ISRC1 from the first node 131 to bias the bipolar transistor 130. The bipolar transistor 130 operates as an emitter follower, wherein the power transistor gate voltage VG_SW at the first node 131 follows the base voltage VB0 of the transistor base, and the gate voltage VG_SW is VB0 minus the base-emitter voltage VBE of the bipolar transistor 130.

[0029] The switching circuit 108 also includes a resistor 138 having a first terminal and a second terminal. Figure 1(Represented as R3). The first terminal is coupled to the power supply terminal 104, and the second terminal is coupled to the base at the second node 132. The level shifting circuit 112 includes a control circuit 139 coupled to the comparator output 128, the reference terminal 103, and the base at the second node 132. The control circuit 139 includes a control input, a current input, and a reference input. The control input is coupled to the comparator output 128 to receive the control signal DIS_SW. The control input has a first state when the control signal DIS_SW is in a first state, and a different second state when the control signal DIS_SW is in its second state. The control circuit 139 has a current input coupled to the base of the bipolar transistor 130 at the first node 131. The control circuit 139 has a reference input coupled to the reference terminal 103. In one example, the control circuit 139 also has a second current input. In operation, in response to a first state at the control input (e.g., in response to the control signal DIS_SW being in a first state), the control circuit 139 receives a current I1 through resistor 138 at the current input at node 132 to turn on bipolar transistor 130. In response to a second state at the control input (e.g., in response to the control signal DIS_SW being in a second state), the control circuit stops receiving current I1 through resistor 138 at the current input. The control circuit 139 includes a control transistor 140 (labeled MN0), a control current source 142, and a switching circuit having a first switch 144 (labeled S1) and a second switch (labeled S2). The first switch 144 has a first terminal coupled to clamp power supply terminal 116 and a second terminal coupled to the gate of control transistor 140. The second switch 146 has a first terminal coupled to the gate of control transistor 140 and a second terminal coupled to reference terminal 103.

[0030] In one example, the control transistor 140 is an NFET having a drain coupled to the base at a second node 132, a source coupled to a third node 141, and a gate. A control current source 142 is coupled between the third node 141 and a reference terminal 103. In operation, the switching circuit turns on the first switch 144 and turns off the second switch 146 in response to the control signal DIS_SW being in a first state. This couples the gate of the control transistor 140 to the clamping power supply terminal 116 and turns on the control transistor 140. In this case, the control current source 142 receives a current ISRC0 from the base at the second node, causing a current I1 to flow through resistor 138. At least a portion of the current received at the current input is supplied from the power supply terminal 104 through resistor 138. The bipolar transistor 130 is configured to turn on in response to the control circuit 139 receiving current at the current input, and the gate-source voltage VGS of the power transistor 110 decreases in response to the control circuit 139 ceasing to receive current at the current input. The current I1 establishes a voltage across resistor 138 (R3), which reduces the base voltage VB0 of bipolar transistor 130, and thus also reduces the gate voltage VG_SW of power transistor 110 at the first node 131. In one example, the current source 142 and the resistance of resistor 138 are designed such that when the control signal DIS_SW is in the first state, the established base voltage VB0 and the resulting gate voltage VG_SW keep power transistor 110 on.

[0031] In response to a second state at the control input (e.g., in response to the control signal DIS_SW being in the second state), the switching circuit turns off the control transistor 140 to stop receiving current I1 at the current input. In the illustrated example, the control circuit 139 responds to the change of the control signal DIS_SW to the second state by turning off the first switch 144 and turning on the second switch 146, thereby causing the control transistor 140 to turn off and stop receiving current I1 at the current input. As a result, the voltage across resistor 138 drops and the base voltage VB0 rises toward the supply voltage VSUP. In this state, the emitter follower configuration of the bipolar transistor 130 causes the gate voltage VG_SW at the first node to rise accordingly, which helps to turn off the power transistor 110 in response to the control signal DIS_SW being in the first state.

[0032] In one example, the switching circuit 108 further includes a PFET 148 (labeled MP1) and a second resistor 152. The PFET 148 has a source coupled to a power supply terminal 104, a drain coupled to a base at a second node 132, and a gate coupled to a fourth node 150. The second resistor 152 (labeled R2) has a first terminal coupled to the power supply terminal 104 and a second terminal coupled to the gate of the PFET at the fourth node 150. In this example, the control circuit 139 includes a second control transistor 154 (e.g., an n-channel FET or NFET labeled MN1) having a drain coupled to a second current input terminal of the control circuit coupled to the fourth node 150. The second control transistor 154 also includes a source coupled to a third node 141 and a gate. In addition, the switching circuit includes: a third switch 156 (marked S3) having a first terminal coupled to the clamping power supply terminal 116 and a second terminal coupled to the gate of the second control transistor 154; and a fourth switch 158 (marked S4) having a first terminal coupled to the gate of the second control transistor 154 and a second terminal coupled to the reference terminal 103.

[0033] In response to a second state at the control input (e.g., in response to the control signal DIS_SW being in the second state), the switching circuit turns on the third switch 156 and turns off the fourth switch 158 to turn on the second control transistor 154. In this case, the second control transistor 154 receives a current equal to the current ISRC0 from the control current source 142 (from the second current input at the fourth node 150) at the second current input, causing a second current I2 to flow through the second resistor 152. The second current I2 generates a voltage across the second resistor 152 and provides a non-zero gate-source voltage between the source and gate of the PFET 148, which turns on the PFET 148. When the PFET 148 is on, this helps to rapidly raise the base voltage VB0 at the second node 132 to or towards the supply voltage VSUP, and the emitter follower connection of the bipolar transistor 130 raises the gate voltage VG_SW at the first node 131 to near the supply voltage VSUP to help rapidly turn off the power transistor 110. In response to the control input having a first state (e.g., in response to the control signal DIS_SW being in the first state), the switching circuit turns off the third switch 156 and turns on the fourth switch 158 to turn off the second control transistor 154. In this case, the control circuit 139 stops receiving the second current I2 through the second resistor 152 at the second current input to turn off the PFET 148.

[0034] In this example, the corresponding second switch 146 and third switch 156 include control inputs coupled to the comparator output 128 to operate according to the control signal DIS_SW received at the control input of the control circuit 139. Figure 1 The switching circuit includes an inverter 160 having an input and an output. The input is coupled to the comparator output 128 to receive a control signal DIS_SW, and the output is coupled to provide an inverted control signal xDIS_SW to the control inputs of the corresponding first switch 144 and fourth switch 158. Figure 1 Table 170 is included, which shows the states of switches 144 (S1), 146 (S2), 156 (S3), and 158 (S4) and the power transistor 110 (MP0) according to the state of the control signal DIS_SW (e.g., low or high) to further illustrate the operation of the switching circuit.

[0035] In one example, the switching circuit 108 also includes a second PFET 162 (labeled MP2). The second PFET 162 has a source coupled to power supply terminal 104, a drain coupled to first node 131, and a gate coupled to fourth node 150. When the switching circuit turns on the second control transistor 154 in response to the control signal DIS_SW being in the second state, the voltage at fourth node 150 is less than the turn-on voltage of the second PFET 162. This creates a low-impedance path between the source and gate of power transistor 110 to further facilitate the fastest charging of the source-gate capacitance of power transistor 110.

[0036] Also refer to Figure 2-4 , Figure 2 Show Figure 1 The signal during operation of the example high-voltage protection switch circuit 108 Figure 3 This indicates that the control input has a first state (e.g., the control signal DIS_SW is in the first state). Figure 1 An example of a high-voltage protection switch circuit, and Figure 4 An example of a switching circuit 108 is shown with a second state at the control input (e.g., the control signal DIS_SW is in the second state). Figure 2The diagram shows: a graph 200 with example curve 201, which shows the power supply voltage VSUP as a function of time during operation of system 100; a graph 200 with curve 211, which shows the load voltage VLOAD at output terminal 106; and a graph 220 with curve 221, which shows the clamping power supply voltage VDD_CMP. Graphs 200, 210, and 220 include an indication of the nominal power supply voltage level labeled VNOM. In the example shown, the power supply voltage VSUP increases at time T1 beyond a threshold determined by the resistive voltage divider sensing circuits 121, 122, and the reference voltage VREF, as shown in graph 230, which has curve 231, showing the divided power supply voltage VSUP_DIV and the corresponding reference voltage VREF. Figure 2 Also shown is a graph 240 with curve 241, which represents the control signal DIS_SW provided by comparator output 128, and a graph 250 with curve 251, which shows the gate-source voltage VGS of power transistor 110.

[0037] exist Figure 2 Tl in the previous operation was performed with the power supply voltage VSUP within the normal operating range, and as Figure 3 As shown in the circuit diagram, the control signal DIS_SW is in the first state and the control input terminal of the control circuit 139 is in the first state. The switching circuit turns on the first control transistor 140 to allow the current ISRC0 from the control current source 142 to flow along... Figure 3 The current path 300 in the circuit passes through resistor 138 to the first control transistor 140. This creates a voltage drop across resistor 138 equal to ISRC0*R3. Furthermore, in this state, the first current source 136 provides a bias current ISRC1 to the bipolar transistor 130, configured as an emitter follower. As a result, the gate of the power transistor 110 at the first node 131 is driven to a voltage lower than the supply voltage VSUP, which is equal to VSUP - (ISRC0*R3 + VBE). In one example, the values ​​of ISRC0 and R3 are designed such that the maximum gate-source voltage VGS of the power transistor 110 is not exceeded.

[0038] like Figure 4 As shown in the circuit diagram, when the power supply voltage VSUP exceeds the normal operating range at Tl (e.g., reaches or exceeds the maximum voltage VM indicated in curve 210), the control signal DIS_SW at comparator output 128 transitions to the second state (e.g., high), and the control input of control circuit 139 also has the second state. In response, the switching circuit... Figure 4The second current path 400 via the second control transistor 154 transfers the current ISRC0 of the control current source 142 from the second resistor 152 through the second control transistor 154. This current I2 generates a voltage drop equal to ISRC0*R2, which quickly turns on the transistor 148. This raises the base voltage VB0 of the bipolar transistor 130 at the second node 132 to near the supply voltage VSUP (along with the emitter terminal at the first node 131), thereby rapidly pulling the gate of the power transistor 110 towards the supply voltage VSUP. In this case, the bipolar transistor 130 itself only pulls the voltage (VG_SW) of the first node 131 to VSUP-VBE, close to the threshold voltage of the power transistor 110. In operation, this only partially turns off the power transistor 110, and the power transistor 110 can have a drain-source impedance in the range of 100K ohms or greater when the VGS of MP0 equals the VBE of QN0. In some embodiments, while providing a relatively weak rise, the added transistor 162 is turned on by a reduced voltage at the fourth node 150, and the transistor 162 completes the rise of the gate voltage VG_SW at the first node 131 to the same voltage as the supply voltage VSUP, which, after a brief off-time T2-T1, Figure 2 The power transistor 110 is completely turned off at time T2.

[0039] The disclosed example provides a solution for low-power fast shutdown to protect load 105 from overvoltage conditions during all conditions of DC power supply 102. In the illustrated implementation, only the DC currents in control circuit 139 and bias circuit 133 are the currents ISRCO and ISRC1 of the corresponding current sources 142 and 136. In practice, these currents can be scaled according to the desired turn-off speed of power transistor 110. Furthermore, the circuitry of high-voltage switching circuit 108 and level shifting circuit 112 operate from a low-voltage clamping supply voltage VDD_CMP without any separate high-voltage side power supply. The disclosed solution thus offers power efficiency advantages over other implementations that use a separate positive-grounded power supply referenced to the supply voltage VSUP to establish the drive for turning power transistor 110 on and off. Furthermore, the disclosed solution allows scaling of the power transistor 110 for any desired current carrying capacity and any desired operating voltage, wherein the described shutdown circuit system provides an accelerated switching of the power transistor 110 in response to the detection of a potential overvoltage condition of the DC power supply 102 before the load 105 is exposed to an undesirable high voltage.

[0040] Modifications to the described example are permissible within the scope of the claims, and other implementations are also possible.

Claims

1. A switching circuit, comprising: Power terminals; Reference terminal; A power transistor having a source, a drain, and a gate, the source being coupled to the power supply terminal; A bipolar transistor having a collector, an emitter, and a base, the collector being coupled to the source of the power transistor, and the emitter being coupled to the gate of the power transistor; A bias circuit coupled to the gate of the power transistor; A resistor having a first terminal and a second terminal, the first terminal being coupled to the source of the power transistor and the second terminal being coupled to the base; as well as A control circuit has a control input, a current input, and a reference input, the current input being coupled to the base and the reference input being coupled to the reference terminal. The control circuit is configured to receive current at the current input in response to a first state at the control input and to stop receiving current at the current input in response to a second state at the control input. At least a portion of the received current is supplied from the power supply terminal through the resistor. The bipolar transistor is configured to turn on in response to the control circuit receiving current at the current input, and the gate-source voltage of the power transistor decreases in response to the control circuit stopping receiving current at the current input.

2. The switching circuit according to claim 1, wherein, The bias circuit includes a current source coupled between the gate and the reference terminal of the power transistor.

3. The switching circuit according to claim 1, wherein, The control circuit includes: A control transistor having a drain, a source, and a gate, wherein the drain of the control transistor is coupled to the base; A control current source coupled between the source of the control transistor and the reference terminal; and A switching circuit coupled to the gate of the control transistor, the switching circuit being configured to: turn on the control transistor to receive the current at the current input terminal in response to the control input terminal having a first state; and turn off the control transistor to stop receiving the current at the current input terminal in response to the control input terminal having a second state.

4. The switching circuit according to claim 3, further comprising: PFET has a source, drain, and gate; as well as The second resistor has a first terminal coupled to the source of the PFET and a second terminal coupled to the gate of the PFET; The control circuit includes a second current input terminal coupled to the gate of the PFET. The control circuit is configured to receive a second current at the second current input terminal to turn on the PFET in response to the control input terminal having a second state, and to stop receiving the second current at the second current input terminal to turn off the PFET in response to the control input terminal having a first state.

5. The switching circuit according to claim 4, wherein: The control circuit includes a second control transistor having a drain, a source, and a gate, wherein the drain of the second control transistor is coupled to the gate of the PFET, and the source of the second control transistor is coupled to the source of the control transistor. and The switching circuit is coupled to the gate of the second control transistor and configured to: turn on the second control transistor in response to the control input having the second state to receive the second current at the second current input; And in response to the control input having the first state, the second control transistor is turned off to stop receiving the second current at the second current input.

6. The switching circuit according to claim 5, wherein, The switching circuit includes: A first switch has a first terminal and a second terminal, the first terminal being coupled to a clamping power terminal having a clamping power voltage lower than the first voltage of the power terminal, and the second terminal being coupled to the gate of the control transistor. A second switch has a first terminal and a second terminal, the first terminal being coupled to the gate of the control transistor and the second terminal being coupled to the reference terminal; A third switch having a first terminal and a second terminal, the first terminal being coupled to the clamping power terminal and the second terminal being coupled to the gate of the second control transistor; and A fourth switch having a first terminal and a second terminal, the first terminal being coupled to the gate of the second control transistor and the second terminal being coupled to the reference terminal.

7. The switching circuit according to claim 6, wherein: The switching circuit includes an inverter having an input and an output, the input being coupled to the control input of the control circuit, and the output being coupled to the control input of the first switch and the fourth switch, to turn on the first switch and the fourth switch in response to the control input having a first state and to turn off the first switch and the fourth switch in response to the control input having a second state; A comparator having a first input terminal, a second input terminal, and a comparator output terminal, wherein the first input terminal is coupled to the output terminal of a sensing circuit, and the second input terminal is coupled to a voltage reference terminal; and The control input terminals of the second switch and the third switch are coupled to the output terminal of the comparator to turn off the second switch and the third switch in response to the first state of the control input terminal, and to turn on the second switch and the third switch in response to the second state of the control input terminal.

8. The switching circuit of claim 5, further comprising a second PFET having a source, a drain, and a gate, the source being coupled to the power supply terminal, the drain being coupled to the gate of the power transistor, and the gate being coupled to the gate of the PFET.

9. The switching circuit according to claim 5, wherein, The switching circuit includes: A first switch having a first terminal and a second terminal, the first terminal being coupled to a clamping power terminal having a clamping power voltage lower than the first voltage of the power supply terminal, and the second terminal being coupled to the gate of the control transistor; and A second switch has a first terminal and a second terminal, the first terminal being coupled to the gate of the control transistor and the second terminal being coupled to the reference terminal.

10. The switching circuit according to claim 9, wherein: The switching circuit includes an inverter having an input and an output, the input being coupled to the control input of the control circuit, and the output being coupled to the control input of the first switch to turn on the first switch in response to the control input having a first state, and to turn off the first switch in response to the control input having a second state. A comparator having a first input terminal, a second input terminal, and a comparator output terminal, wherein the first input terminal is coupled to the output terminal of a sensing circuit, and the second input terminal is coupled to a voltage reference terminal; as well as The control input terminal of the second switch is coupled to the output terminal of the comparator to turn off the second switch in response to the first state of the control input terminal and to turn on the second switch in response to the second state of the control input terminal.

11. The switching circuit of claim 4, further comprising a second PFET having a source, a drain, and a gate, the source being coupled to the power supply terminal, the drain being coupled to the gate of the power transistor, and the gate being coupled to the gate of the PFET.

12. The switching circuit according to claim 1, further comprising: A PFET has a source, a drain, and a gate, the source being coupled to the power supply terminal and the drain being coupled to the base; as well as A second resistor has a first terminal and a second terminal, the first terminal being coupled to the power supply terminal and the second terminal being coupled to the gate of the PFET; The control circuit includes a second current input terminal coupled to the gate of the PFET. The control circuit is configured to receive a second current at the second current input terminal to turn on the PFET in response to the control input terminal having a second state, and to stop receiving the second current to turn off the PFET in response to the control input terminal having a first state.

13. The switching circuit of claim 12, further comprising a second PFET having a source, a drain, and a gate, the source being coupled to the power supply terminal, the drain being coupled to the gate of the power transistor, and the gate being coupled to the gate of the PFET.

14. A circuit comprising: A bipolar transistor having a collector, an emitter, and a base, wherein the collector is adapted to be coupled to a power supply terminal and the emitter is adapted to be coupled to a control terminal of a power transistor; A bias circuit adapted to be coupled to the control terminal of the power transistor; A resistor having a first terminal and a second terminal, the first terminal being adapted to be coupled to a power supply terminal and the second terminal being coupled to the base; as well as A control circuit has a control input, a current input, and a reference input, the current input being coupled to the base, the reference input being adapted to be coupled to a reference terminal, the control circuit being configured to receive current at the current input in response to a first state at the control input, and to stop receiving current at the current input in response to a second state at the control input, wherein at least a portion of the received current is supplied from the power supply terminal through the resistor, the bipolar transistor is configured to turn on in response to the control circuit receiving current at the current input, and the gate-source voltage of the power transistor decreases in response to the control circuit stopping receiving current at the current input.

15. The circuit according to claim 14, wherein, The control circuit includes: A control transistor having a drain, a source, and a gate, wherein the drain of the control transistor is coupled to the base; A control current source coupled between the source of the control transistor and the reference terminal; and A switching circuit coupled to the gate of the control transistor, the switching circuit being configured to: turn on the control transistor to receive the current at the current input terminal in response to the control input terminal having a first state; and turn off the control transistor to stop receiving the current at the current input terminal in response to the control input terminal having a second state.

16. The circuit of claim 14, further comprising: A PFET has a source, a drain, and a gate, the source being coupled to the power supply terminal and the drain being coupled to the base; as well as A second resistor has a first terminal and a second terminal, the first terminal being coupled to the power supply terminal and the second terminal being coupled to the gate of the PFET; The control circuit includes a second current input terminal coupled to the gate of the PFET. The control circuit is configured to receive a second current at the second current input terminal to turn on the PFET in response to the control input terminal having a second state, and to stop receiving the second current to turn off the PFET in response to the control input terminal having a first state.

17. The circuit of claim 16, further comprising a second PFET having a source, a drain, and a gate, the source being coupled to the power supply terminal, the drain being coupled to the control terminal of the power transistor, and the gate being coupled to the gate of the PFET.

18. A protection system comprising: A clamping power supply circuit having an input terminal coupled to a power supply terminal and an output terminal for providing a clamping power supply voltage lower than that of the power supply terminal; A sensing circuit having an input terminal and an output terminal, the input terminal being coupled to the power supply terminal; A comparator has a first input terminal, a second input terminal, and a comparator output terminal. The first input terminal is coupled to the output terminal of the sensing circuit, the second input terminal is coupled to a voltage reference terminal, and the comparator output terminal has a first state in response to the voltage at the output terminal of the sensing circuit being less than the reference voltage at the voltage reference terminal, and a second state in response to the voltage at the output terminal of the sensing circuit being greater than the reference voltage. A power transistor having a source, a drain, and a gate, the source being coupled to the power supply terminal and the drain being coupled to the output terminal; A bipolar transistor having a collector, an emitter, and a base, the collector being coupled to the power supply terminal, and the emitter being coupled to the gate of the power transistor; A bias circuit coupled between the gate and reference terminal of the power transistor, the bias circuit being configured to control the emitter current of the bipolar transistor; A resistor having a first terminal coupled to the power supply terminal and a second terminal coupled to the base; as well as A control circuit has a control input, a current input, and a reference input, the control input being coupled to the comparator output, the current input being coupled to the base, and the reference input being coupled to the reference terminal. The control circuit is configured to receive current at the current input in response to the comparator output having a first state, and to stop receiving current at the current input in response to the comparator output having a second state.

19. The protection system according to claim 18, wherein, The control circuit includes: A control transistor having a drain, a source, and a gate, wherein the drain of the control transistor is coupled to the base; A control current source coupled between the source of the control transistor and the reference terminal; and A switching circuit, coupled to the gate of the control transistor, is configured to: turn on the control transistor to receive the current at the current input in response to the comparator output being in the first state; and turn off the control transistor to stop receiving the current at the current input in response to the comparator output being in the second state.

20. The protection system according to claim 18, further comprising: A PFET has a source, a drain, and a gate, the source being coupled to the power supply terminal and the drain being coupled to the base; as well as A second resistor has a first terminal and a second terminal, the first terminal being coupled to the power supply terminal and the second terminal being coupled to the gate of the PFET; The control circuit includes a second current input terminal coupled to the gate of the PFET. The control circuit is configured to receive a second current at the second current input terminal in response to the comparator output terminal having the second state, and to stop receiving the second current at the second current input terminal in response to the comparator output terminal having the first state.

21. The protection system of claim 20, further comprising a second PFET having a source, a drain, and a gate, the source being coupled to the power supply terminal, the drain being coupled to the gate of the power transistor, and the gate being coupled to the gate of the PFET.

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