Current generating circuit, driving circuit and current adjusting method

Abstract

The current generating circuit of the present invention includes: a MOS transistor, in which any one of a power line and a ground line is connected to a source terminal; a voltage generating circuit, which generates a first voltage corresponding to the resistance value of the wiring between the one line and the source terminal; and a control circuit, which causes the MOS transistor to generate a specified current based on the first voltage.

Description

Technical Field

[0001] The invention relates to a current generating circuit, a driving circuit and a current regulating method. Background Art

[0002] There is a current generating circuit that generates a current for driving a switching element (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2017 / 195864 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] When a current generating circuit is integrated, the current generated by the current generating circuit may be affected by wiring resistance due to, for example, circuit area requirements. As a result, the current generating circuit may not be able to generate a target current.

[0008] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a current generating circuit capable of generating a current with high accuracy.

[0009] Technical means for solving technical problems

[0010] The first method of the current generating circuit of the present invention for solving the above-mentioned problem includes: a MOS transistor, in which any one of a power line and a ground line is connected to a source terminal; a voltage generating circuit, which generates a first voltage corresponding to the resistance value of the wiring between the one line and the source terminal; and a control circuit, which causes the MOS transistor to generate a specified current based on the first voltage.

[0011] In addition, a second mode of the current generating circuit of the present invention includes: more than two n MOS transistors, in which any one of a power line and a ground line is connected to a source terminal; a voltage generating circuit, which generates a first voltage corresponding to the resistance value of each of the n wirings between the one line and the source terminal of each of the n MOS transistors for each of the n wirings; and a control circuit, which causes the n MOS transistors to generate a specified current based on the n first voltages.

[0012] In addition, the driving circuit method of the present invention is a driving circuit that turns on a switching element based on a first signal and turns off the switching element based on a second signal, and includes: a PMOS transistor, in which a power line is connected to a source terminal; a voltage generating circuit, which generates a first voltage corresponding to the resistance value of a first wiring resistor between the power line and the source terminal of the PMOS transistor; a control circuit, which, when the first signal is input, causes the PMOS transistor to generate a specified current for charging a gate capacitance of the switching element based on the first voltage; and a first NMOS transistor, in which a ground line is connected to a source terminal, is turned on based on the second signal, and discharges the gate capacitance of the switching element.

[0013] In addition, in the current adjustment method of the present invention, step 1 and step 2 are performed on a current generating circuit, wherein the current generating circuit includes: a MOS transistor, in which any one of a power line and a ground line is connected to a source terminal; a voltage generating circuit, which includes a variable resistance circuit and generates a voltage corresponding to the resistance value of the wiring between the one line and the source terminal; and a control circuit, which causes the MOS transistor to generate a current based on the voltage of the voltage generating circuit, wherein in the first step, the current generated by the MOS transistor is measured, and in the second step, the resistance value of the variable resistance circuit is adjusted so that the current generated by the MOS transistor becomes a specified current.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide a current generating circuit capable of generating a current with high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram showing the structure of the power module 100 .

[0017] Figure 2 is a diagram showing the structure of the LVIC 210 .

[0018] Figure 3 is a diagram showing an example of the structure of the driving circuit 410 a.

[0019] Figure 4 is a diagram showing an example of the variable resistor 12 a.

[0020] Figure 5 This is a diagram for explaining the driving circuit 410a when adjusting the variable resistance.

[0021] Figure 6is a diagram illustrating an exemplary adjustment method 700 of the variable resistor 12 a performed by the semiconductor testing device 600 .

[0022] Figure 7 This is a diagram for explaining the driving circuit 410a when adjusting the variable resistance.

[0023] Figure 8 is a diagram illustrating an exemplary adjustment method 800 of the switch 53 .

[0024] Fig. 9 4 is a diagram showing output currents of respective phases when the drive circuit 410 a is used for the drive circuits 410 , 420 , and 430 .

[0025] Fig.10 It is a diagram showing an example of the configuration of the driving circuit 415 .

[0026] Fig.11 4 is a diagram showing output currents of respective phases of the drive circuit 415 .

[0027] Fig.12 is a diagram showing an example of the structure of the driving circuit 410b.

[0028] Fig.13 FIG. 1 is a diagram showing an embodiment of a discharge circuit 55 used in place of the discharge circuit 50 . DETAILED DESCRIPTION

[0029] Cross-reference to related applications

[0030] This application claims priority based on Japanese patent application No. 2019-165321 filed on September 11, 2019, and cites the contents thereof.

[0031] At least the following matters will become clear through the description of this specification and the accompanying drawings.

[0032] ======Present Implementation Method======

[0033] Figure 1 1 is a diagram showing a structure of a power module 100 as one embodiment of the present invention. The power module 100 is a semiconductor device for driving a three-phase motor 120, and includes a bridge circuit 200 for power conversion, LVIC 210, HVIC 220, 230, 240, and terminals HU, HV, HW, LX, LY, LZ, P, U, V, W, NX, NY, and NZ.

[0034] The bridge circuit 200 includes IGBTs (Insulated Gate Bipolar Transistors) 300 , 301 , 302 , 303 , 304 , and 305 (hereinafter referred to as “IGBTs 300 to 305 ”), FWDs (Free Wheeling Diodes) 310 , 311 , 312 , 313 , 314 , and 315 , and resistors Rx, Ry, and Rz.

[0035] The IGBT 300 is a switching element for the U phase, and the IGBT 301 is a switching element for the X phase. The IGBTs 300 and 301 are provided with FWDs 310 and 311 , respectively.

[0036] The IGBT 302 is a switching element for the V phase, and the IGBT 303 is a switching element for the Y phase. The IGBTs 302 and 303 are provided with FWDs 312 and 313 , respectively.

[0037] The IGBT 304 is a switching element for the W phase, and the IGBT 305 is a switching element for the Z phase. The IGBTs 304 and 305 are provided with FWDs 314 and 315 , respectively.

[0038] In addition, in the present embodiment, the IGBTs 300 to 305 are used as the switching elements of the power module 100 , but, for example, power MOS transistors may be used.

[0039] The resistors Rx, Ry, and Rz are resistors for detecting currents flowing through the switching elements of the X phase, the Y phase, and the Z phase, respectively.

[0040] A power supply voltage Vdc is applied to the terminal P, a load, namely a three-phase motor 120 is provided to the terminals U, V, and W, and the terminals NX, NY, and NZ are grounded.

[0041] The HVICs 220 , 230 , and 240 are integrated circuits for switching the IGBTs 300 , 302 , and 304 of the upper arms in accordance with signals input from a microcomputer (not shown) via the terminals HU, HV, and HW, respectively.

[0042] The LVIC 210 is an integrated circuit for switching the IGBTs 301 , 303 , and 305 of the lower arm according to drive signals Vdrx, Vdry, and Vdrz input from a microcomputer (not shown) via terminals LX, LY, and LZ.

[0043] like Figure 2 As shown, the LVIC 210 includes driving circuits 410 , 420 , 430 for three phases.

[0044] <<<Structure of driving circuit 410a>>>

[0045] Figure 3 1 is a diagram showing an example of the structure of a drive circuit 410a, which is one embodiment of the drive circuit 410. The drive circuit 410a is a circuit that drives the IGBT 301 by turning on the PMOS transistor 60 or the NMOS transistor 51. The drive circuit 410a is configured to include: a voltage generating circuit 1a including a voltage detection circuit 10a and an adding circuit 20a; a control circuit 30a; a switching circuit 40a; a discharge circuit 50; and a PMOS transistor 60.

[0046] <<Voltage generating circuit 1a>>

[0047] The voltage generating circuit 1 a is a circuit that generates a reference voltage VREF2 adjusted in accordance with the resistance value of the wiring between the power supply line L1 and the source terminal of the PMOS transistor 60 .

[0048] <<Voltage detection circuit 10a>>

[0049] The voltage detection circuit 10a is a circuit for generating an adjustment voltage Von corresponding to a wiring resistance Ron of a wiring La between a power supply line L1 and a source terminal of a PMOS transistor 60. The voltage detection circuit 10a is configured to include an operational amplifier 11a and variable resistors 12a, 13a, 14a, and 15a (hereinafter referred to as "variable resistors 12a to 15a").

[0050] Here, a large current for driving the IGBT 301 flows through the PMOS transistor 60, so the size becomes larger. As a result, the wiring of the PMOS transistor 60 in the integrated circuit becomes longer, so a wiring resistance Ron is generated between the source terminal of the PMOS transistor 60 and the power line L1. On the other hand, the back gate terminal of the PMOS transistor 60 is connected to the power line L1. Then, a back gate effect that increases the threshold voltage of the PMOS transistor 60 occurs in the PMOS transistor 60.

[0051] Therefore, even if the gate voltage of the PMOS transistor 60 is a desired voltage, the output current value of the PMOS transistor 60 deviates from the target output current value depending on the value of the wiring resistance Ron between the source terminal of the PMOS transistor 60 and the power supply line L1 .

[0052] Therefore, in this embodiment, the variable resistors 12a to 15a are provided to suppress the influence of the wiring resistance Ron. The variable resistors 12a to 15a will be described in detail later.

[0053] In order to detect the voltage drop generated between both ends of the wiring resistor Ron, one end of each of the variable resistors 12a and 13a is connected to the vicinity of the power line L1 of the wiring La and the vicinity of the source terminal of the PMOS transistor 60. Figure 3 In the figure, for ease of understanding, the variable resistors 12a and 13a are described as having one end away from the vicinity of the power line L1 and the vicinity of the source terminal, respectively.

[0054] The other end of the variable resistor 12a is connected to one end of the variable resistor 14a and the non-inverting input terminal of the operational amplifier 11a. The other end of the resistor 14a is grounded. The other end of the variable resistor 13a is connected to one end of the variable resistor 15a and the inverting input terminal of the operational amplifier 11a. The other end of the variable resistor 15a is connected to the output terminal of the operational amplifier 11a.

[0055] In addition, a back gate terminal of the PMOS transistor 60 is connected to the power supply line L1. A drain terminal of the PMOS transistor 60 is connected to the terminal OUTX.

[0056] Therefore, the adjustment voltage Von generated by the voltage detection circuit 10a according to the wiring resistance Ron becomes (1).

[0057] Von=(R2p / R1p)×(V2p-V1p)···(1)

[0058] Here, the resistance value R1p is the resistance value of the variable resistors 12a and 13a, and the resistance value R2p is the resistance value of the variable resistors 14a and 15a. In addition, the voltage V1p is the voltage of the node connecting the source terminal of the PMOS transistor 60 and the variable resistor 13a, and the voltage V2p is the voltage of the node connecting the power supply line L1 of the wiring La and the variable resistor 12a.

[0059] The wiring resistor Ron corresponds to the "first wiring resistor", the power line L1 corresponds to the "power line", the operational amplifier 11a corresponds to the "voltage output circuit", the variable resistors 12a to 15a correspond to the "variable resistor circuit", and the adjustment voltage Von corresponds to the "second voltage".

[0060] <<An example of variable resistor 12a>>

[0061] Figure 4 1 is a diagram showing an example of a variable resistor 12a. A variable resistor circuit is a circuit whose resistance value can be changed by a built-in switch. In addition, here, the variable resistor 12a is described, but the same applies to the variable resistors 13a to 15a.

[0062] The variable resistor 12 a includes, for example, resistors 510 , 521 , 522 , 523 , 524 , 525 , and 526 (hereinafter referred to as “resistors 521 to 526 ”); switches 540 , 551 , 552 , 553 , 554 , and 555 (hereinafter referred to as “switches 551 to 555 ”); and an EPROM 560 .

[0063] One end of the resistor 510 of the variable resistor 12a is called an input terminal, and the other end is connected to one end of each of the resistors 521 to 526. The other ends of the resistors 521 to 525 are respectively connected to one end of the switches 551 to 555. The other ends of the switches 551 to 555 and the other end of the resistor 526 are connected to the output terminal of the variable resistor 12a.

[0064] Furthermore, the switch 540 is connected between one end and the other end of the resistor 510 , and the resistor 526 is connected in series to the resistor 510 between the input terminal and the output terminal.

[0065] The switches 540 and 551 to 555 are formed of, for example, MOS transistors, and are set to be turned on or off by data stored in the EPROM 560 during a wafer test.

[0066] In addition, in this embodiment, a chip is used as an element for realizing the variable resistor 12a, but the present invention is not limited to this. For example, a Zener diode capable of Zener switching or a polysilicon fuse capable of laser trimming may be used to realize the variable resistor.

[0067] <<Adding circuit 20a>>

[0068] The adding circuit 20a is a circuit that adds the adjustment voltage Von to the predetermined reference voltage VREF and generates the voltage obtained as the reference voltage VREF2. The adding circuit 20a is configured to include an operational amplifier 21a, resistors 22a, 23a, and 24a (hereinafter referred to as "resistors 22a to 24a"), and an inverting amplifier 25a. Although the details will be described later, the adjustment voltage Von is adjusted in advance so that the PMOS transistor 60 can generate a predetermined current value.

[0069] One end of the resistor 22a is connected to the output terminal of the operational amplifier 11a, and the other end of the resistor 22a is connected to the inverting input terminal of the operational amplifier 21a. A reference voltage VREF is applied to one end of the resistor 23a, and the other end of the resistor 23a is connected to the inverting input terminal of the operational amplifier 21a. One end of the resistor 24a is connected to the inverting input terminal of the operational amplifier 21a, and the other end of the resistor 24a is connected to the output terminal of the operational amplifier 21a. In addition, the non-inverting input terminal of the operational amplifier 21a is grounded. In addition, the output terminal of the operational amplifier 21a is connected to the inverting amplifier 25a. In addition, the inverting amplifier 25a outputs the adjusted reference voltage VREF2.

[0070] In the present embodiment, the resistance values ​​R of the resistors 22 a to 24 a are the same, and therefore the reference voltage VREF2 after adjustment can be obtained as follows.

[0071] VREF2=VREF+Von···(2)

[0072] In addition, the adding circuit 20a corresponds to the "adding circuit", and the reference voltage VREF2 corresponds to the "first voltage".

[0073] <<Control circuit 30a>>

[0074] The control circuit 30a is a circuit that generates a current in the PMOS transistor 60 based on the reference voltage VREF2. The control circuit 30a includes an operational amplifier 31a, an NMOS transistor 32a, a resistor 33a, a PMOS transistor 34a, and a PMOS transistor 38a.

[0075] The reference voltage VREF2 is applied to the non-inverting input terminal of the operational amplifier 31a. The inverting input terminal of the operational amplifier 31a is connected to one end of a resistor 33a and a source terminal of an NMOS transistor 32a for detecting a current I1a flowing through the NMOS transistor 32a and the PMOS transistor 34a.

[0076] When the PMOS transistor 38a is turned off, current is supplied from the diode-connected PMOS transistor 34a to the NMOS transistor 32a. Then, the operational amplifier 31a controls the NMOS transistor 32a so that the voltage of the inverting input terminal becomes the reference voltage VREF2 applied to the non-inverting input terminal.

[0077] As a result, a current I1a determined by the reference voltage VREF2 and the resistance value of the resistor 33a flows through the diode-connected PMOS transistor 34a.

[0078] In addition, the PMOS transistor 34 a and the PMOS transistor 60 form a current mirror circuit. Therefore, a current I2 corresponding to the current I1 a flowing through the PMOS transistor 34 a flows through the PMOS transistor 60 .

[0079] The PMOS transistor 38a is an element for switching the on / off of the PMOS transistor 34a and the PMOS transistor 60 based on the output of the level shifter 42a (described later). In this embodiment, when the PMOS transistor 38a is turned off, the PMOS transistor 34a and the PMOS transistor 60 operate, so the PMOS transistor 60 generates the current I2.

[0080] On the other hand, when the PMOS transistor 38 a is turned on, the PMOS transistor 34 a and the PMOS transistor 60 are turned off, so the generation of the current I2 stops.

[0081] The ground line L2 corresponds to a “ground line”, and a circuit obtained by combining the PMOS transistor 60, the voltage detection circuit 10a, the adding circuit 20a, and the control circuit 30a corresponds to a “current generating circuit”.

[0082] <<Switching circuit 40a>>

[0083] When the drive signal Vdrx from the microcomputer (not shown) is, for example, at a low level (hereinafter referred to as an L level), the switching circuit 40a operates the discharge circuit 50 to turn off the IGBT 301. When the drive signal Vdrx is, for example, at a high level (hereinafter referred to as an H level), the switching circuit 40a operates the current mirror circuit composed of the PMOS transistor P34a and the PMOS transistor 60 to turn on the IGBT 301.

[0084] The switching circuit 40a is configured to include an inverter 41a and a level shifter 42a.

[0085] The inverter 41 a inverts the logic level of the drive signal Vdrx and outputs the inverted logic level to the gate terminals of the NMOS transistors 51 and 52 of the discharge circuit 50 (described later).

[0086] The level shifter 42a performs level shifting on the drive signal Vdrx, and outputs a signal for turning on / off the PMOS transistor 38a of the control circuit 30a. Specifically, when the drive signal Vdrx becomes the H level, the PMOS transistor 38a is turned off, so that the PMOS transistor 60 generates the current I2. On the other hand, when the drive signal Vdrx becomes the L level, the level shifter 42a turns on the PMOS transistor 38a and pulls up the gate terminal of the PMOS transistor 34a. As a result, the generation of the current I2 of the PMOS transistor 60 stops.

[0087] In addition, the driving signal Vdrx at the H level corresponds to the “first signal”, and the driving signal Vdrx at the L level corresponds to the “second signal”.

[0088] <<Discharge circuit 50>>

[0089] The discharge circuit 50 is a circuit for discharging the gate capacitance of the IGBT 301 to turn off the IGBT 301 when the drive signal Vdrx becomes an L level. The discharge circuit 50 includes NMOS transistors 51 and 52 and a switch 53 .

[0090] The gate terminals of the NMOS transistors 51 and 52 are connected to the output of the inverter 41a of the switching circuit 40a. The drain terminals of the NMOS transistors 51 and 52 are connected to the terminal OUTX.

[0091] Here, a large current for discharging the gate capacitance of the IGBT 301 flows through the NMOS transistor 51, so the size becomes large. Then, when the NMOS transistor 51 in the integrated circuit is wired, a wiring resistance Roff is generated between the source terminal of the NMOS transistor 51 and the ground line L2. In addition, the back gate terminal of the NMOS transistor 51 is connected to the ground line L2.

[0092] Therefore, a back gate effect that increases the threshold voltage of the NMOS transistor 51 occurs in the NMOS transistor 51. Therefore, due to the wiring resistance Roff and the back gate effect of the NMOS transistor 51, the gate capacitance of the IGBT 301 may not be discharged in a short time.

[0093] Therefore, in the present embodiment, in order to prevent the gate capacitance of the IGBT 301 from being unable to be discharged in a short time, an NMOS transistor 52 connected in parallel to the NMOS transistor 51 is provided.

[0094] In addition, the NMOS transistor 52 may be operated only when the NMOS transistor 51 cannot discharge the gate capacitance of the IBGT 301 in a short time.

[0095] Therefore, a switch 53 is connected between the gate terminal of the NMOS transistor 52 and the ground line L2 to assist the discharge of the NMOS transistor 51. Although the details will be described later, the switch 53 is turned off when the total of the wiring resistance Roff and the on-resistance of the NMOS transistor 51 is larger than a predetermined value.

[0096] In addition, the wiring resistance Roff corresponds to the “second wiring resistance”, the NMOS transistor 51 corresponds to the “first NMOS transistor”, and the NMOS transistor 52 corresponds to the “second NMOS transistor”.

[0097] <<Adjustment method of variable resistors 12a to 15a>>

[0098] Figure 5 This is a diagram for explaining adjustment of the variable resistors 12a to 15a. Figure 5 For convenience, only the main structures are shown.

[0099] Figure 6 1 is a diagram showing an exemplary method 700 for adjusting the variable resistors 12a to 15a performed by the semiconductor testing device 600. The variable resistors can also be adjusted in the same manner in the drive circuits 410b and 410c described later.

[0100] Here, when testing a wafer of the LVIC 210 on which the drive circuit 410a is mounted, the variable resistors 12a to 15a are adjusted. In addition, power is supplied to the drive circuit 410a.

[0101] First, the semiconductor test device 600 applies the H-level drive signal Vdrx to the terminal INX, and applies the test voltage Vtest to the test pad 603 located on the wiring from the output terminal of the voltage detection circuit 10a (S710). In addition, here, the voltage detection circuit 10a stops the bias current from the bias current circuit (not shown) that operates the voltage detection circuit 10a, and stops the operation.

[0102] When the test voltage Vtest is applied, the adding circuit 20a adds the test voltage Vtest to the reference voltage VREF and outputs the adjusted reference voltage VREF2. A current I1a corresponding to the adjusted reference voltage VREF2 and the resistance value of the resistor 33a flows through the control circuit 30a. As a result, a source current I2 corresponding to the current I1a flows through the PMOS transistor 60 for charging the gate capacitance of the IGBT 301.

[0103] Then, when the source current I2 is output from the terminal OUTX, the semiconductor testing device 600 measures the source current I2 corresponding to the test voltage Vtest ( S720 ).

[0104] Furthermore, the semiconductor testing device 600 adjusts the test voltage Vtest so that the source current I2 becomes the predetermined current value Ia (S730). Furthermore, when the test voltage Vtest is adjusted, the semiconductor testing device 600 activates a bias current circuit (not shown) which activates the voltage detection circuit 10a.

[0105] Then, the semiconductor testing device 600 adjusts the resistance values ​​of the variable resistors 12a to 15a so that the adjustment voltage Von of the voltage detection circuit 10a becomes equal to the test voltage Vtest when the current I2 is equal to the predetermined current value Ia (S740).

[0106] Specifically, the semiconductor test device 600 generates data stored in the EPROM 560 so that the adjustment voltage Von of the voltage detection circuit 10a becomes equal to the test voltage Vtest when the current I2 is equal to the specified current value Ia. As a result, the switch of the variable resistor 12a, that is, the MOS transistor, is turned on or off based on the data of the EPROM 560.

[0107] The same also applies when a Zener diode capable of Zener switching is used as an element for adjusting the variable resistor 12a. The semiconductor test device 600 applies a voltage to both ends of the Zener diode and burns out the Zener diode so that the adjustment voltage Von of the voltage detection circuit 10a becomes equal to the test voltage Vtest when the current I2 is equal to the specified current value Ia.

[0108] The same is true when a polysilicon fuse capable of laser trimming is used as an element for adjusting the variable resistor 12a. The semiconductor test device 600 irradiates the fuse with laser to cut the fuse so that the adjustment voltage Von of the voltage detection circuit 10a becomes equal to the test voltage Vtest when the current I2 is equal to the specified current value Ia.

[0109] In addition, S710, S720, S730, and S740 correspond to the "current adjustment method." In addition, S720 corresponds to the "first step", and S740 corresponds to the "second step".

[0110] An example of a method for adjusting the variable resistors 12a to 15a is described above. There are various other similar adjustment methods, and these adjustment methods can be adopted.

[0111] <<How to adjust switch 53>>

[0112] Figure 7 This is a diagram for explaining adjustment of the switch 53, and for the sake of convenience, only the main structure is shown here. Figure 8is a diagram illustrating an exemplary adjustment method 800 of the switch 53 .

[0113] Here, the semiconductor testing device 600 adjusts the switch 53 in a state where power is supplied to the driving circuit 410 a .

[0114] First, when the driving circuit 410a outputs a signal of L level to the terminal OUTX, the semiconductor testing device 600 supplies a predetermined current to the terminal OUTX (S810). Here, the "predetermined current" is a current having a predetermined current value (for example, 1A).

[0115] Furthermore, the semiconductor testing device 600 measures the total resistance value of the on-resistance of the NMOS transistor 51 and the wiring resistance Roff of the wiring Lb based on the current value of the predetermined current and the voltage value of the terminal OUTX ( S820 ).

[0116] When the measurement result indicates that the resistance value is larger than the specified value, the semiconductor testing device 600 stores data for turning off the switch 53 in the EPROM 560 (S830).

[0117] As a result, when the NMOS transistor 51 is turned on, the NMOS transistor 52 is also turned on. Therefore, the discharge circuit 50 can prevent the discharge time of the gate capacitance of the IGBT 301 from being prolonged.

[0118] In addition, similarly to the case of the variable resistor 12a, the switch 53 may be realized by other elements such as a Zener diode capable of Zener switching, a polysilicon fuse, etc.

[0119] <<<Operation of Driving Circuit 410a>>>

[0120] Next, the operation of the driving circuit 410a will be described. Figure 3 The variable resistors 12a to 15a of the driving circuit 410a have been implemented by Figure 6 The processing of switch 53 is adjusted by executing Figure 8 is disconnected due to processing.

[0121] When the drive signal Vdrx in the drive circuit 410 a becomes H level, the inverter 41 a of the switching circuit 40 a applies an L level signal to the gate terminals of the NMOS transistors 51 and 52 , so that the NMOS transistors 51 and 52 are turned off.

[0122] On the other hand, the level shifter 42a sets the gate terminal of the PMOS transistor 43a to H level, so the PMOS transistor 43a is turned off. As a result, the gate terminal of the PMOS transistor 34a is not pulled up, and the current mirror circuit composed of the PMOS transistor 34a and the PMOS transistor 60 operates.

[0123] Here, the voltage detection circuit 10a generates an adjustment voltage Von corresponding to the resistance value of the wiring resistance Ron of the wiring La. Then, the adding circuit 20a adds the adjustment voltage Von to the reference voltage VREF to generate an adjusted reference voltage VREF2.

[0124] The operational amplifier 31 a of the control circuit 30 a adjusts the output voltage based on the adjusted reference voltage VREF2 and the resistor 33 a so that the current I1 a flows.

[0125] As a result, the PMOS transistor 60 generates a predetermined current value Ia for charging the gate capacitance of the IGBT 301 regardless of the resistance value of the wiring resistance Ron of the wiring La.

[0126] When the drive signal Vdrx becomes L level, the level shifter 42a sets the gate terminal of the PMOS transistor 38a to L level, so that the PMOS transistor 38a is turned on. As a result, the gate terminal of the PMOS transistor 34a is pulled up, and the PMOS transistor 60 is turned off.

[0127] On the other hand, the inverter 41 a of the switching circuit 40 a applies an H-level signal to the gate terminals of the NMOS transistors 51 and 52 , so that the NMOS transistors 51 and 52 are turned on.

[0128] As a result, the NMOS transistors 51 and 52 discharge the gate capacitance of the IGBT 301 .

[0129] <<<Using the driving circuit 410a for Figure 2 Output current of each phase in the case of the drive circuits 410, 420, and 430>>>

[0130] Fig. 9 is a diagram showing the use of the drive circuit 410a for Figure 2 Graph showing the output current of each phase in the case of the drive circuits 410, 420, and 430. In addition, the case where the drive circuit 410a is used for the drive circuits 410, 420, and 430 respectively refers to the following case: the drive circuit 410 is set to the drive circuit 410a, the drive circuit 420 is set to the drive circuit 410a, and the drive circuit 430 is set to the drive circuit 410a.

[0131] When the driving circuit 410a is used for each of the driving circuits 410, 420, and 430, generally, the wiring resistance Ron on the source side of the PMOS transistor 60 of each of the driving circuits 410, 420, and 430 is greatly different. Figure 6 Adjustment method shown.

[0132] As a result, the influence of the wiring resistance Ron is reduced, and the drive circuits 410 , 420 , and 430 can set their respective output currents to the predetermined current value Ia.

[0133] The predetermined current value Ia is a current value output when the PMOS transistor 60 has a predetermined size. Therefore, when the size of the PMOS transistor 60 is changed, for example, by executing Figure 6 The adjustment method shown can also cause a predetermined current value Ia corresponding to the size of the PMOS transistor 60 to flow.

[0134] Thus, when the power module 100 in which the drive circuit 410 a is used for each of the drive circuits 410 , 420 , and 430 , for example, the three-phase currents on the lower arm side can be made consistent with high accuracy.

[0135] <<<Structure of driving circuit 415>>>

[0136] Fig.10 4 is a diagram showing a general structure of a driving circuit 415. The driving circuit 415 is a circuit that determines the current value of a source current for driving the IGBT 301 based on a reference voltage VREF. The driving circuit 415 includes a control circuit 30a, a switching circuit 40a, a PMOS transistor 60, and an NMOS transistor 51.

[0137] The configurations of the control circuit 30a and the switching circuit 40a are the same as those of the drive circuit 410a, and thus their description is omitted. In addition, the operation of the NMOS transistor 51 is the same as that of the drive circuit 410a.

[0138] On the other hand, the source current of the PMOS transistor 60 flowing through the IGBT 301 is determined only by the voltage value of the reference voltage VREF. In the above case, the source current of the PMOS transistor 60 is affected by the resistance value of the wiring resistance Ron of the wiring La.

[0139] <<<Using the drive circuit 415 for Figure 2 Output current of each phase in the case of the drive circuits 410, 420, and 430>>>

[0140] Fig.11is a diagram showing the use of the drive circuit 415 for Figure 2 Graph showing the output current of each phase in the case of the drive circuits 410, 420, and 430. In addition, the case where the drive circuit 415 is used for the drive circuits 410, 420, and 430 respectively refers to the following case: the drive circuit 410 is set as the drive circuit 415, the drive circuit 420 is set as the drive circuit 415, and the drive circuit 430 is set as the drive circuit 415.

[0141] The drive circuit 415 drives the IGBT 301 with the current value of the source current determined only by the value of the reference voltage VREF. Therefore, the drive circuits 410, 420, and 430 are each affected by the resistance value of the wiring resistance Ron of the wiring La. As a result, the output current of each of the drive circuits 410, 420, and 430 deviates from the specified current value Ia.

[0142] Therefore, when the power module 100 in which the general drive circuit 415 is used for each of the drive circuits 410 , 420 , and 430 , for example, it is difficult to make the three-phase currents on the lower arm side coincide with each other with high accuracy.

[0143] <<<Structure of driving circuit 410b>>>

[0144] Fig.12 1 is a diagram showing an example of a configuration of a drive circuit 410 b which is one embodiment of the drive circuit 410 . The drive circuit 410 b includes a control circuit 30 a , a switching circuit 40 a , a discharge circuit 50 , a PMOS transistor 60 , and a voltage divider circuit 70 .

[0145] The control circuit 30 a , the switching circuit 40 a , the discharge circuit 50 , and the PMOS transistor 60 are the same as those of the drive circuit 410 a , and thus description thereof will be omitted.

[0146] <<Voltage divider circuit 70>>

[0147] The voltage divider circuit 70 is a circuit for dividing a predetermined voltage V1 to generate an adjusted reference voltage VREF2. The voltage divider circuit 70 includes resistors 71, 72, 73, and 74 (hereinafter referred to as "resistors 71 to 74") and switches 75, 76, 77, and 78 (hereinafter referred to as "switches 75 to 78").

[0148] The resistors 71 to 74 are connected in series between one end to which a predetermined voltage V1 is applied and the other end to which the ground is connected. The switches 75 to 78 are connected in parallel to the resistors 71 to 74, respectively.

[0149] Here, the switch of the voltage divider circuit 70 can be adjusted by, for example, the above-mentioned Figure 6The same method is used to implement the above-mentioned operation. Specifically, the semiconductor testing device 600 adjusts the switches 75 to 78 to generate the reference voltage VREF3 that sets the current I2 of the PMOS transistor 60 to the predetermined current value Ia.

[0150] As a result, the drive circuit 410 b can charge the gate capacitance of the IGBT 301 with the predetermined current value Ia regardless of the magnitude of the wiring resistance Ron on the source side of the PMOS transistor 60 .

[0151] In addition, similarly to the driving circuit 410a, the driving circuit 410b can be used for Figure 2 In this case, the output currents of the respective phases can be made consistent with each other with high accuracy.

[0152] The voltage divider circuit 70 corresponds to a “variable resistor circuit”, and the adjusted reference voltage VREF3 corresponds to a “first voltage”. The predetermined voltage V1 corresponds to a “predetermined voltage”, and the node providing the adjusted reference voltage VREF3 corresponds to a “predetermined node”.

[0153] <<<Other structures of discharge circuit>>>

[0154] Fig.13 FIG. 1 is a diagram showing an embodiment of a discharge circuit 55 used in place of the discharge circuit 50 .

[0155] The discharge circuit 55 is a circuit for discharging the gate capacitance of the IGBT 301 with a predetermined current I3 and is configured to include a voltage generation circuit 1 b including a voltage detection circuit 10 b and an adder circuit 20 b , a control circuit 30 b , a switching circuit 40 b , and an NMOS transistor 51 .

[0156] <<Voltage generating circuit 1b>>

[0157] The voltage generating circuit 1 b is a circuit that generates a reference voltage VREF4 adjusted in accordance with the resistance value of the wiring between the power supply line L2 and the source terminal of the NMOS transistor 51 .

[0158] <<Voltage detection circuit 10b>>

[0159] The voltage detection circuit 10b is a circuit for generating an adjustment voltage Voff corresponding to the resistance value of the wiring resistance Roff of the wiring Lb between the power line L2 and the source terminal of the NMOS transistor 51. The voltage detection circuit 10b is configured to include an operational amplifier 11b and variable resistors 12b, 13b, 14b, and 15b (hereinafter referred to as "variable resistors 12b to 15b").

[0160] The configuration of the voltage detection circuit 10b is the same as that of the voltage detection circuit 10a, and thus the description thereof is omitted. The variable resistors 12b to 15b are adjusted in the same manner as the variable resistor 12a.

[0161] <<Adding circuit 20b>>

[0162] The adding circuit 20b is a circuit that adds the adjustment voltage Voff to the reference voltage VREF and outputs the resulting voltage as an adjusted reference voltage VREF4. The adding circuit 20b includes an operational amplifier 21b, resistors 22b, 23b, 24b, and an inverting amplifier 25b.

[0163] In addition, the configuration of the adding circuit 20b is the same as that of the adding circuit 20a, and therefore the description thereof is omitted.

[0164] <<Control circuit 30b>>

[0165] The control circuit 30b is a circuit that generates a current in the NMOS transistor 51 based on the adjusted reference voltage VREF4. The control circuit 30b includes an operational amplifier 31b, an NMOS transistor 32b, a resistor 33b, PMOS transistors 35b and 36b, and an NMOS transistor 37b.

[0166] The non-inverting input terminal of the operational amplifier 31b is applied with the adjusted reference voltage VREF4. The inverting input terminal of the operational amplifier 31b is connected to one end of a resistor 33b and a source terminal of an NMOS transistor 32b, wherein the resistor 33b is used to detect the current I1b flowing through the NMOS transistor 32b and the PMOS transistor 35b. In addition, the other end of the resistor 33b is connected to the ground line L2.

[0167] Current is supplied from the diode-connected PMOS transistor 35b to the NMOS transistor 32b. Then, the operational amplifier 31b controls the NMOS transistor 32b so that the voltage of the inverting input terminal becomes the reference voltage VREF4 applied to the non-inverting input terminal.

[0168] As a result, a current I1b determined by the reference voltage VREF4 and the resistance value of the resistor 33b flows through the diode-connected PMOS transistor 35b.

[0169] In addition, the PMOS transistors 35b and 36b constitute a current mirror circuit, so that a current corresponding to the current I1b flows through the diode-connected NMOS transistor 37b. Then, the NMOS transistor 37b and the NMOS transistor 51 also constitute a current mirror circuit. Therefore, when the NMOS transistor 38b is turned off, the NMOS transistor 51 generates a current I3 corresponding to the current I1b.

[0170] The NMOS transistor 38b is an element for switching the NMOS transistor 37b and the NMOS transistor 51 on and off based on the drive signal Vdrx. In the present embodiment, when the NMOS transistor 38b is off, the NMOS transistor 51 generates a current I3 corresponding to the current I1b.

[0171] On the other hand, when the NMOS transistor 38 b is turned on, the NMOS transistor 51 is turned off, and thus the generation of the current I3 stops.

[0172] Here, in the discharge circuit 55, the variable resistors 12b to 15b are connected by the above Figure 6 As a result, the discharge circuit 55 can discharge the gate capacitance of the IGBT 301 at a predetermined current value regardless of the size of the wiring resistance Roff.

[0173] Furthermore, if the above-described discharge circuit 55 is used for each of the drive circuits 410 , 420 , and 430 , the three-phase sink currents on the lower arm side of the power module 100 become consistent with high accuracy.

[0174] ===Others===

[0175] The voltage detection circuit 10a and the voltage divider circuit 70 of this embodiment adjust the resistance value of the variable resistor to generate a reference voltage, but other methods can also be used to make the voltage detection circuit 10a and the voltage divider circuit 70 generate a desired voltage (for example, the adjustment voltage Von, the reference voltage VREF2).

[0176] For example, a desired voltage can be generated using an analog-digital converter that generates an analog voltage based on a digital value stored in ERPOM. In this case, the analog-digital converter corresponds to a "voltage generation circuit."

[0177] ===Summary===

[0178] The power module 100 of the present embodiment has been described above. Generally speaking, in the LVIC 210 in which the plurality of drive circuits 410, 420, and 430 of the power module 100 are integrated, the wiring resistances Ron and Roff of the wirings La and Lb in the drive circuits become different depending on the configuration of the drive circuits. As a result, the output current of the drive circuits 410, 420, and 430 affected by the resistance value of the wiring resistance Ron cannot be brought close to the target value. However, for example, the drive circuit 410a of the present embodiment adjusts the variation of the output current caused by the wiring resistances Ron and Roff. As a result, the influence of the wiring resistances Ron and Roff can be reduced, and the output current of the drive circuit 410a can be brought close to the target value.

[0179] Furthermore, the output current of the driving circuit 410 a can be brought close to a target value by causing the PMOS transistor 60 and the NMOS transistor 51 to generate a current corresponding to the wiring resistance Ron of the wiring La and the wiring resistance Roff of the wiring Lb.

[0180] In addition, by using the voltage detection circuit 10a and the adding circuit 20a that generate the adjustment voltage Von corresponding to the resistance value of the wiring resistance Ron of the wiring La, the output current of the driving circuit 410a can be linearly fine-tuned, and the influence of the resistance value of the wiring resistance Ron can be reduced. In addition, assuming that it is necessary to change the target value of the output current of the driving circuit 410a, it is sometimes difficult to make the output current close to the target value based only on the adjustment voltage Von. However, in this embodiment, the output current can be changed based on the reference voltage VREF and the adjustment voltage Von. Therefore, even if the target value of the output current is greatly changed, the value of the output current can be easily adjusted.

[0181] Furthermore, by generating the reference voltage VREF3 adjusted by the voltage dividing circuit 70 , the driving circuit 410 b in which the influence of the resistance value of the wiring resistance Ron is reduced can be manufactured with a small circuit scale.

[0182] In addition, the voltage detection circuit 10a, the adding circuit 20a and the control circuit 30a of the driving circuit 410a can also be used to make the NMOS transistor 51 generate a current, like the voltage detection circuit 10b, the adding circuit 20b and the control circuit 30b of the driving circuit 410c.

[0183] Furthermore, even when the drive circuit 410 a is used for each of the three (n) drive circuits 410 , 420 , and 430 , the output current of each of the drive circuits 410 , 420 , and 430 can be brought close to the target value.

[0184] Alternatively, a circuit may be realized in which a circuit for causing the PMOS transistor 60 to generate a source current of the IGBT 301 is combined with a circuit for causing the NMOS transistors 51 and 52 to discharge the gate capacitance of the IGBT 301. This circuit can also reduce the scale of the circuit for discharging the gate capacitance of the IGBT 301.

[0185] Furthermore, by measuring the source current flowing through the terminal OUTX of the driving circuit 410 a and adjusting the resistance value of the variable resistor, the source current flowing through the terminal OUTX can be adjusted so as to approach a target value.

[0186] Description of symbols

[0187] 100 Power Modules,

[0188] 120 three-phase motor,

[0189] 200 bridge circuit,

[0190] 210 LVIC,

[0191] 220, 230, 240 HVIC,

[0192] 300~305 IGBT,

[0193] 310~315 FWD,

[0194] 410, 410a, 410b, 410c, 415, 420, 430 driving circuit,

[0195] 1a, 1b Voltage generation circuit,

[0196] 10a, 10b voltage detection circuit,

[0197] 20a, 20b Adding circuit,

[0198] 30a, 30b control circuit,

[0199] 40a Switching circuit,

[0200] 50, 55 discharge circuit,

[0201] 70 voltage divider circuit,

[0202] 34a, 43a, 60, 35b, 36b, 38a PMOS transistors,

[0203] 32a, 51, 52, 32b, 37b, 38b NMOS transistors,

[0204] 53, 75-78, 540, 551-555 switches,

[0205] 12a~15a, 12b~15b variable resistors,

[0206] 22a~24a、22b~24b、33a、33b、71~74、510、521~526 resistors,

[0207] 11a, 21a, 31a, 11b, 21b, 31b operational amplifiers,

[0208] 25a, 25b Inverting amplifier,

[0209] 41a Inverter,

[0210] 42 level shifters,

[0211] 560 EPROM.

Claims

1. A current generating circuit, characterized in that: include: A MOS transistor in which any one of a power supply line and a ground line is connected to a source terminal; a voltage generating circuit that generates a first voltage corresponding to a resistance value of a wiring between the one line and the source terminal; as well as a control circuit that causes the MOS transistor to generate a predetermined current based on the first voltage, The voltage generating circuit generates the first voltage based on a voltage of a first node on the one line side of the wiring and a voltage of a second node on the source terminal side of the wiring, The voltage generating circuit comprises: a variable resistance circuit, the variable resistance circuit receiving inputs of the voltage of the first node and the voltage of the second node; Operational amplifier; as well as Adding circuit, The variable resistance circuit is connected between the first node and the second node and the operational amplifier so that a second voltage corresponding to a difference between a voltage at the first node and a voltage at the second node and a resistance value of the variable resistance circuit is output from the operational amplifier. The adding circuit adds the second voltage and a reference voltage, and outputs the resulting voltage as the first voltage.

2. The current generating circuit according to claim 1, wherein: The MOS transistor is a PMOS transistor in which the power supply line is connected to the source terminal.

3. The current generating circuit according to claim 1, wherein: The MOS transistor is an NMOS transistor in which the ground line and the source terminal are connected.

4. A current generating circuit, characterized in that: include: Two or more n MOS transistors, in which any one of a power supply line and a ground line is connected to a source terminal; n voltage generating circuits for generating, for each of the n wirings, a first voltage corresponding to a resistance value of each of the n wirings between the one line and the source terminals of each of the n MOS transistors; as well as a control circuit that causes the n MOS transistors to generate a predetermined current based on the n first voltages, The n voltage generating circuits generate the n first voltages based on the voltage of the first node on the one line side of the corresponding wiring among the n wirings and the voltage of the second node on the source terminal side of the corresponding wiring among the n wirings, respectively. The n voltage generating circuits respectively include: a variable resistance circuit, the variable resistance circuit receiving inputs of the voltage of the first node and the voltage of the second node; Operational amplifier; as well as Adding circuit, The variable resistance circuit is connected between the first node and the second node and the operational amplifier so that a second voltage corresponding to a difference between a voltage at the first node and a voltage at the second node and a resistance value of the variable resistance circuit is output from the operational amplifier. The adding circuit adds the second voltage and a reference voltage, and outputs the resulting voltage as the first voltage.

5. A driving circuit, The switch element is turned on based on the first signal and turned off based on the second signal, and the driving circuit is characterized in that it includes: A PMOS transistor, in which a power line is connected to a source terminal; a voltage generating circuit that generates a first voltage corresponding to a resistance value of a wiring between the power line and the source terminal of the PMOS transistor; a control circuit that, when the first signal is input, causes the PMOS transistor to generate a predetermined current for charging a gate capacitance of the switching element based on the first voltage; as well as a first NMOS transistor in which a ground line is connected to a source terminal, the first NMOS transistor is turned on based on the second signal, and discharges the gate capacitance of the switching element, The voltage generating circuit generates the first voltage based on a voltage of a first node on the power line side of the wiring and a voltage of a second node on the source terminal side of the wiring, The voltage generating circuit comprises: a variable resistance circuit, the variable resistance circuit receiving inputs of the voltage of the first node and the voltage of the second node; Operational amplifier; as well as Adding circuit, The variable resistance circuit is connected between the first node and the second node and the operational amplifier so that a second voltage corresponding to a difference between a voltage at the first node and a voltage at the second node and a resistance value of the variable resistance circuit is output from the operational amplifier. The adding circuit adds the second voltage and a reference voltage, and outputs the resulting voltage as the first voltage.

6. The driving circuit according to claim 5, characterized in that: A second NMOS transistor is included, the second NMOS transistor being connected in parallel with the first NMOS transistor, being turned on based on the second signal, and discharging the gate capacitance of the switching element.

7. A current adjustment method, characterized in that: The first step and the second step are performed on a current generating circuit, wherein the current generating circuit comprises: A MOS transistor in which any one of a power supply line and a ground line is connected to a source terminal; a voltage generating circuit including a variable resistance circuit for generating a voltage corresponding to a resistance value of the wiring between the one line and the source terminal based on a voltage of a first node on the one line side of the wiring, a voltage of a second node on the source terminal side of the wiring, and a resistance value of the variable resistance circuit; and a control circuit that causes the MOS transistor to generate a current based on the voltage of the voltage generating circuit, In the first step, the current generated by the MOS transistor is measured. In the second step, the resistance value of the variable resistance circuit is adjusted so that the current generated by the MOS transistor becomes a predetermined current.

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