Interconnect structure and method for forming the same

Abstract

The present application discloses an interconnect structure and a method for forming the same. The method comprises: providing a substrate having a first dielectric layer formed thereon, the first dielectric layer having an opening formed therein that penetrates the first dielectric layer; forming a first conductive layer in the opening; after forming the first conductive layer, etching back a portion of the first dielectric layer to expose the top sidewall of the first conductive layer; after etching back the first dielectric layer, forming a second dielectric protective layer on the surface of the first dielectric layer and the exposed surface of the first conductive layer; and after forming the second dielectric protective layer, performing a planarization process until the top surface of the first conductive layer is exposed. The interconnect structure and the method for forming the same disclosed in the present application improve the performance of the interconnect structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an interconnect structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the integration level of ultra-large-scale integrated circuit chips has reached billions or even tens of billions of devices, and metal interconnection technology has been widely used.

[0003] The polishing fluid generated in the planarization process after the conductive connection layer is formed may penetrate along the gap between the dielectric layer and the conductive connection layer, thereby corroding the metal layer below the conductive connection layer, thereby damaging the performance of the semiconductor device.

[0004] Therefore, there is a need to improve the method of forming interconnect structures. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present application is to provide an interconnection structure and a method for forming the same, which improves the performance of the interconnection structure.

[0006] One aspect of the present application provides a method for forming an interconnect structure, comprising: providing a substrate, on which a first dielectric layer is formed, and an opening is formed in the first dielectric layer that penetrates the first dielectric layer; forming a first conductive layer in the opening; after forming the first conductive layer, etching back a portion of the first dielectric layer to expose the top sidewall of the first conductive layer; after etching back the first dielectric layer, forming a second dielectric protective layer on the surface of the first dielectric layer and the exposed surface of the first conductive layer; and after forming the second dielectric protective layer, performing a planarization process until the top surface of the first conductive layer is exposed.

[0007] Optionally, the method further includes: forming a sacrificial layer on the surface of the second dielectric protective layer after forming the second dielectric protective layer and before the planarization treatment; the process of performing the planarization treatment includes: planarizing the sacrificial layer and the second dielectric protective layer until the top surface of the first conductive layer is exposed.

[0008] Optionally, the thickness of the sacrificial layer is 500 angstroms to 1000 angstroms; and the material of the sacrificial layer includes silicon nitride.

[0009] Optionally, the first dielectric layer and the second dielectric protection layer are made of the same or different materials.

[0010] Optionally, during the process of etching back a portion of the first dielectric layer, the sidewall of the first conductive layer will also be etched to remove a portion, so that the first conductive layer has a stepped sidewall surface.

[0011] Optionally, in the process of etching back a portion of the first dielectric layer, an etching selectivity ratio between the first dielectric layer and the first conductive layer is greater than 30:1.

[0012] Optionally, the thickness of the sacrificial layer is greater than twice the thickness of the first dielectric layer removed in the etch-back.

[0013] Optionally, the thickness of the first conductive layer removed in the planarization process is 10 angstroms to 50 angstroms less than the thickness of the first dielectric layer removed in the etch-back process.

[0014] Optionally, the first dielectric layer is etched back to a depth of 200 angstroms to 400 angstroms.

[0015] Optionally, the process of forming the second dielectric protection layer includes chemical vapor deposition.

[0016] Optionally, the process of forming the first conductive layer includes a selective chemical vapor deposition process.

[0017] Optionally, a second conductive layer is formed in the substrate, and the opening is located on the second conductive layer; after the first conductive layer is formed, the first conductive layer and the second conductive layer are in contact.

[0018] Optionally, the material of the first conductive layer includes cobalt, and the material of the second conductive layer includes tungsten.

[0019] The present application also provides an interconnect structure, which includes: a substrate; a first dielectric layer located on the substrate; a first conductive layer extending through the first dielectric layer, wherein the surface of the first dielectric layer is lower than the top surface of the first conductive layer, and the sidewalls of the first conductive layer are in contact with the first dielectric layer; and a second dielectric protective layer located on the first dielectric layer and in contact with part of the sidewalls of the first conductive layer.

[0020] Optionally, the first dielectric layer and the second dielectric protection layer are made of the same or different materials.

[0021] Optionally, the material of the second dielectric protection layer includes silicon oxide; and the thickness of the second dielectric protection layer is 200 angstroms to 400 angstroms.

[0022] Optionally, a top surface of the second dielectric protection layer is flush with a top surface of the first conductive layer.

[0023] Optionally, a characteristic size of the first conductive layer in contact with the second dielectric protection layer is smaller than a characteristic size of the first conductive layer in contact with the first dielectric layer.

[0024] Optionally, a second conductive layer is formed in the substrate; and the first conductive layer is located on and in contact with the second conductive layer.

[0025] Optionally, the material of the first conductive layer includes tungsten.

[0026] The technical solution of this application has the following beneficial effects:

[0027] By etching back a portion of the first dielectric layer and redepositing a second dielectric protective layer thereon, the tightness between the second dielectric protective layer and the first conductive layer can be enhanced, thereby further reducing or substantially eliminating the gap between the second dielectric protective layer and the first conductive layer, and preventing the polishing liquid from penetrating along the contact surface between the first dielectric layer or the second dielectric protective layer and the first conductive layer during the subsequent planarization process. Furthermore, the technical solution of this application eliminates the need for providing an adhesive layer between the first conductive layer and the first dielectric layer, and between the first conductive layer and the second dielectric protective layer, thereby further reducing contact resistance and improving the performance of the interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present disclosure. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0029] Figures 1A to 1E A schematic structural diagram of a process of forming an interconnect structure;

[0030] Figure 2 is a flow chart of a method for forming an interconnect structure according to an embodiment of the present application;

[0031] Figures 3A to 3G Schematic diagram of the interconnection structure forming process according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments shown, but is to be construed in the widest sense consistent with the claims.

[0033] The technical solution of this application is described in detail below with reference to the embodiments and drawings.

[0034] like Figures 1A to 1E As shown, a method for forming an interconnect structure includes: providing a substrate 10, in which a second conductive layer 20 (e.g., cobalt) is formed; forming a dielectric layer 30 (e.g., oxide) on the substrate 10, wherein the dielectric layer 30 has an opening 32, and the opening 32 exposes a portion of the second conductive layer 20; forming a first conductive layer 40 (e.g., tungsten) in the opening 32; forming a first sacrificial layer 50 (e.g., titanium nitride) over the dielectric layer 30 and the first conductive layer 40; forming a second sacrificial layer 60 (e.g., tungsten) on the first sacrificial layer 50; and performing a planarization process to remove the first sacrificial layer 50 and the second sacrificial layer 60 and make the top surface of the dielectric layer 30 flush with the top surface of the first conductive layer 40.

[0035] Because the first conductive layer 40 is formed upward from the second conductive layer 20 at the bottom of the opening 30 via a selective chemical vapor deposition process, it does not form nucleation sites on the sidewalls of the opening 30 for its growth and adhesion. This results in poor adhesion between the first conductive layer 40 and the sidewalls of the opening 30, and may cause gaps. Therefore, during the subsequent planarization process, the polishing fluid generated may penetrate through the gap between the dielectric layer 30 and the first conductive layer 40, thereby corroding the second conductive layer 20 located below the first conductive layer 40, resulting in device performance degradation or damage.

[0036] In order to solve the above problems, the present invention provides a method for forming an interconnection structure. Figure 2 As shown, the following steps are included:

[0037] Step S11: providing a substrate, wherein a first dielectric layer is formed on the substrate, and an opening penetrating the first dielectric layer is formed in the first dielectric layer;

[0038] Step S12: forming a first conductive layer in the opening;

[0039] Step S13: after forming the first conductive layer, etching back a portion of the first dielectric layer to expose a top sidewall of the first conductive layer;

[0040] Step S14: after etching back the first dielectric layer, forming a second dielectric protection layer on the surface of the first dielectric layer and the exposed surface of the first conductive layer;

[0041] Step S15: After forming the second dielectric protection layer, performing a planarization process until the top surface of the first conductive layer is exposed.

[0042] The following combination Figures 3A to 3GThe above steps are described in detail. It should be noted that methods that perform the above and following steps in other orders also fall within the scope of protection of the present disclosure.

[0043] like Figure 3A As shown, a substrate 100 is provided, and a second conductive layer 200 is formed in the substrate 100 .

[0044] The material of substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as III-V compounds such as gallium arsenide. The material of substrate 100 can be polycrystalline silicon. Substrate 100 can also be a silicon-on-insulator structure or an epitaxial layer structure on silicon. Semiconductor devices (not shown), such as metal oxide semiconductor devices having a gate, a source, and a drain, can be formed in substrate 100.

[0045] The material of the second conductive layer 200 can be tungsten (W), cobalt (Co), or other metal materials suitable for selectively growing a conductive connection layer thereon. In this embodiment, the material of the second conductive layer 200 includes cobalt. The second conductive layer 200 can be formed in the trench of the substrate 100 by a process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The trench can be formed by various etching processes.

[0046] like Figure 3B As shown, a first dielectric layer 300 is formed on the substrate 100 . An opening 302 penetrating the first dielectric layer 300 is formed in the first dielectric layer 300 . The opening 302 is located on the second conductive layer 200 .

[0047] The material of the first dielectric layer 300 can be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, etc. In this embodiment, the material of the first dielectric layer 300 can be silicon oxide (SiO2). The first dielectric layer 300 can be formed by physical vapor deposition, chemical vapor deposition, etc.

[0048] The opening 302 may be formed by spin coating photoresist on the surface of the first dielectric layer 300, forming an opening pattern in the photoresist after an exposure and development process, and then etching to form the opening 302. After etching, oxygen plasma is introduced to ash to remove the remaining photoresist.

[0049] like Figure 3C As shown, a first conductive layer 400 is formed in the opening 302 .

[0050] The material of the first conductive layer 400 can be cobalt or tungsten. In this embodiment, the material of the first conductive layer 400 includes tungsten. The first conductive layer 400 can be formed by processes such as physical vapor deposition and chemical vapor deposition. In this embodiment, the process for forming the first conductive layer 400 is a selective chemical vapor deposition process, that is, using the second conductive layer 200 exposed by the opening 302 as the growth substrate, the first conductive layer 400 is formed upward from the top surface of the second conductive layer 200. In some embodiments, the first conductive layer 400 at least fills the opening 302.

[0051] In this embodiment, after the first conductive layer 400 is formed, the first conductive layer 400 is in contact with the second conductive layer 200 .

[0052] like Figure 3D As shown, after the first conductive layer 400 is formed, a portion of the first dielectric layer 300 is etched back to expose the top sidewall of the first conductive layer 400 .

[0053] The first dielectric layer 300 is etched back to a depth of 200 to 400 angstroms, for example, 110 to 350 angstroms. In some embodiments, during the etching back of a portion of the first dielectric layer 300, the etching selectivity between the first dielectric layer 300 and the first conductive layer 400 is greater than 30:1. In this case, while etching back the first dielectric layer 300, the sidewalls of the first conductive layer 400 are also etched to remove a portion, resulting in the first conductive layer 400 having a stepped sidewall surface. Specifically, a step-like structure is formed at the junction of the exposed portion of the first conductive layer 400 and the unexposed portion of the first conductive layer 400. Due to gravity, the vertical penetration rate of the polishing liquid is much greater than its horizontal penetration rate. Since the stepped structure changes the trajectory of the polishing liquid penetration from vertical to horizontal, it can effectively inhibit or reduce further penetration of the polishing liquid.

[0054] like Figure 3E As shown, after the first dielectric layer 300 is etched back, a second dielectric protection layer 500 is formed on the surface of the first dielectric layer 300 and the exposed surface of the first conductive layer 400 .

[0055] After the end portion of the first conductive layer 400 is exposed, a second dielectric protection layer 500 is formed on the surface of the first dielectric layer 300 and the exposed surface of the first conductive layer 400 .

[0056] The material of the second dielectric protective layer 500 can be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, etc. The materials of the first dielectric layer 300 and the second dielectric protective layer 500 can be the same or different. In this embodiment, the material of the second dielectric protective layer 500 can be silicon oxide (SiO2). In this embodiment, the second dielectric protective layer 500 can be formed by a process such as chemical vapor deposition. In other embodiments, the second dielectric protective layer 500 can also be formed by physical vapor deposition.

[0057] like Figure 3F As shown, after the second dielectric protection layer 500 is formed, a sacrificial layer 600 is formed on the surface of the second dielectric protection layer 500 .

[0058] In this embodiment, the material of the sacrificial layer 600 can be silicon nitride, and its thickness can be 500 angstroms to 1000 angstroms. The sacrificial layer 600 can be formed by processes such as physical vapor deposition and chemical vapor deposition. Since the top surface of the entire interconnect structure may be uneven after the second dielectric protection layer 500 is formed, this may affect the effect of the subsequent planarization process. Therefore, the provision of the sacrificial layer 600 can make the top surface of the entire interconnect structure more flat, so as to facilitate the implementation of the subsequent planarization process. In some embodiments, the thickness of the sacrificial layer 600 is greater than twice the thickness of the first dielectric layer 300 removed in the back etching, so as to obtain better surface morphology (topography) in the planarization process.

[0059] like Figure 3G As shown, after the second dielectric protection layer 500 is formed, a planarization process is performed until the top surface of the first conductive layer 400 is exposed.

[0060] In this embodiment, the planarization process is chemical-mechanical polishing (CMP). The planarization process includes planarizing the sacrificial layer 600 and the second dielectric protection layer 500 until the top surface of the first conductive layer 400 is exposed. In this embodiment, after the planarization process, the top of the first conductive layer 400 can be flush with the top of the second dielectric protection layer 500.

[0061] The thickness of the first conductive layer 400 removed during the planarization process is smaller than the thickness of the first dielectric layer 300 removed during the etch-back process (eg, 10 angstroms to 50 angstroms) to ensure that the stepped sidewall surface of the first conductive layer 400 is not affected.

[0062] By etching away a portion of the first dielectric layer 300 and redepositing the second dielectric protective layer 500 thereon, the tightness between the second dielectric protective layer 500 and the first conductive layer 400 can be enhanced, thereby further reducing or substantially eliminating the gap between them. This is because, compared to a selective chemical vapor deposition process that can only grow on specific metals, the second dielectric protective layer 500 is not restricted during deposition and can directly form nucleation points on the sidewalls of the first conductive layer 400, thereby achieving better sidewall adhesion than before. Therefore, during the planarization process, the polishing fluid generated cannot penetrate along the interface between the second dielectric protective layer 500 and the first conductive layer 400, thereby protecting the second conductive layer 200 below the first conductive layer 400 from corrosion by the polishing fluid.

[0063] In addition, the stepped sidewall surface of the first conductive layer 400 can also effectively prevent leakage of the polishing liquid. Furthermore, because the adhesion between the second dielectric protection layer 500 and the first conductive layer 400 meets the required requirements, the technical solution of the present application eliminates the need for an adhesive layer between the first conductive layer and the first dielectric layer and the second dielectric protection layer, thus simplifying the process flow and further reducing the contact resistance of the interconnect structure, thereby improving the performance of the interconnect structure.

[0064] Accordingly, the present application also provides an interconnection structure, which includes:

[0065] substrate 100;

[0066] A first dielectric layer 300 located on the substrate 100;

[0067] a first conductive layer 400 penetrating the first dielectric layer 300 , wherein a surface of the first dielectric layer 300 is lower than a top surface of the first conductive layer 400 , and a sidewall of the first conductive layer 400 is in contact with the first dielectric layer 300 ; and

[0068] A second dielectric protection layer 500 is located on the first dielectric layer 300 and contacts a portion of the sidewall of the first conductive layer 400 .

[0069] The material of substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as III-V compounds such as gallium arsenide. The material of substrate 100 can be polycrystalline silicon. Substrate 100 can also be a silicon-on-insulator structure or an epitaxial layer on silicon structure.

[0070] The material of the first dielectric layer 300 can be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, etc. In this embodiment, the material of the first dielectric layer 300 can be silicon oxide (SiO2). The first dielectric layer 300 can be formed by a process such as chemical vapor deposition.

[0071] The material of the first conductive layer 400 can be cobalt or tungsten. In this embodiment, the material of the first conductive layer 400 includes tungsten. The first conductive layer 400 can be formed by a selective chemical vapor deposition process.

[0072] The material of the second dielectric protective layer 500 can be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, etc. The materials of the first dielectric layer 300 and the second dielectric protective layer 500 can be the same or different. In this embodiment, the material of the second dielectric protective layer 500 can be silicon oxide (SiO2). In this embodiment, the second dielectric protective layer 500 can be formed by a process such as chemical vapor deposition. In this embodiment, the thickness of the second dielectric protective layer is 200 to 400 angstroms.

[0073] In some embodiments, the top surface of the second dielectric protection layer 500 is flush with the top surface of the first conductive layer 400 .

[0074] In some embodiments, the characteristic size of the first conductive layer 400 in contact with the second dielectric protection layer 500 is smaller than the characteristic size of the first conductive layer 400 in contact with the first dielectric layer 300 .

[0075] In some embodiments, a second conductive layer 200 is formed in the substrate 100 ; and the first conductive layer 400 is located on and in contact with the second conductive layer 200 .

[0076] The material of the second conductive layer 200 can be tungsten, cobalt, or other metal materials suitable for selectively growing a conductive connection layer thereon. In this embodiment, the material of the second conductive layer 200 includes cobalt. The second conductive layer 200 can be formed in the trench of the substrate 100 by a process such as physical vapor deposition or chemical vapor deposition.

[0077] In summary, after reading this detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure may be presented by way of example only and may not be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are intended to be suggested by this disclosure and are within the spirit and scope of the exemplary embodiments of the present disclosure.

Claims

1. A method for forming an interconnect structure, characterized in that: include: Providing a substrate, wherein a first dielectric layer is formed on the substrate, and an opening is formed in the first dielectric layer and penetrates the first dielectric layer; forming a first conductive layer in the opening; After forming the first conductive layer, etching back a portion of the first dielectric layer to expose a top sidewall of the first conductive layer. During the etching back of the portion of the first dielectric layer, an etching selectivity ratio between the first dielectric layer and the first conductive layer is greater than 30:1, and a portion of the sidewall of the first conductive layer is also etched away, so that the first conductive layer has a stepped sidewall surface. After etching back the first dielectric layer, forming a second dielectric protection layer on the surface of the first dielectric layer and the exposed surface of the first conductive layer; as well as After forming the second dielectric protective layer, a sacrificial layer is formed on the surface of the second dielectric protective layer, wherein the thickness of the sacrificial layer is greater than twice the thickness of the first dielectric layer removed in the back etching; and a planarization process is performed until the top surface of the first conductive layer is exposed; wherein the first dielectric layer and the second dielectric protective layer are made of the same material.

2. The method for forming an interconnect structure according to claim 1, wherein: The process of performing the planarization treatment includes: performing a planarization treatment on the sacrificial layer and the second dielectric protection layer until the top surface of the first conductive layer is exposed.

3. The method for forming an interconnect structure according to claim 2, wherein: The thickness of the sacrificial layer is 500 angstroms to 1000 angstroms; the material of the sacrificial layer includes silicon nitride.

4. The method for forming an interconnect structure according to claim 1, wherein: The thickness of the first conductive layer removed in the planarization process is 10 angstroms to 50 angstroms less than the thickness of the first dielectric layer removed in the etch-back process.

5. The method for forming an interconnect structure according to claim 1, wherein: The first dielectric layer is etched back to a depth of 200 angstroms to 400 angstroms.

6. The method for forming an interconnect structure according to claim 1, wherein: The process of forming the second dielectric protection layer includes chemical vapor deposition.

7. The method for forming an interconnect structure according to claim 1, wherein: The process of forming the first conductive layer includes a selective chemical vapor deposition process.

8. The method for forming an interconnect structure according to claim 1, wherein: A second conductive layer is formed in the substrate, and the opening is located on the second conductive layer; after the first conductive layer is formed, the first conductive layer and the second conductive layer are in contact with each other.

9. The method for forming an interconnect structure according to claim 8, wherein: The material of the first conductive layer includes cobalt, and the material of the second conductive layer includes tungsten.

10. An interconnection structure, characterized in that: Formed by any one of claims 1 to 9, comprising: substrate; a first dielectric layer located on the substrate; a first conductive layer extending through the first dielectric layer, wherein a surface of the first dielectric layer is lower than a top surface of the first conductive layer to expose a portion of the surface of the first conductive layer, a sidewall of the first conductive layer contacts the first dielectric layer, and a step-like structure is formed at a junction between the exposed portion of the first conductive layer and the unexposed portion of the first conductive layer; and A second dielectric protection layer is located on the first dielectric layer and contacts a portion of the sidewall of the first conductive layer; wherein the first dielectric layer and the second dielectric protection layer are made of the same material.

11. The interconnect structure according to claim 10, wherein: The material of the second dielectric protection layer includes silicon oxide; the thickness of the second dielectric protection layer is 200 angstroms to 400 angstroms.

12. The interconnect structure according to claim 10, wherein: A top surface of the second dielectric protection layer is flush with a top surface of the first conductive layer.

13. The interconnect structure according to claim 10, wherein: The characteristic size of the first conductive layer in contact with the second dielectric protection layer is smaller than the characteristic size of the first conductive layer in contact with the first dielectric layer.

14. The interconnect structure according to claim 10, wherein: A second conductive layer is formed in the substrate; the first conductive layer is located on and in contact with the second conductive layer.

15. The interconnect structure according to claim 10, wherein The material of the first conductive layer includes tungsten.

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