Integrated circuit and transistor device thereof and preparation method thereof

Abstract

An integrated circuit and a transistor device thereof and a preparation method thereof. The transistor device comprises a first MOS tube and a second MOS tube. The source of the first MOS tube and the drain of the second MOS tube are jointly formed in a first doped region, and the first doped region is coupled to a pin of the integrated circuit. The gate, source and substrate of the second MOS tube are grounded, so that the second MOS tube is integrated in the first MOS tube and connected in series with the first MOS tube, so that the second MOS tube can discharge the surge current of the pin and the first MOS tube to the ground, thereby realizing ESD suppression for the first MOS tube and the integrated circuit in which the first MOS tube is located. That is, the transistor device can realize ESD suppression by itself without additionally connecting a surge protection device, thereby solving the problem that the traditional technical solution cannot perform ESD surge protection and occupies a large space of the integrated circuit.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to an integrated circuit and a transistor device thereof, and a preparation method thereof. Background Art

[0002] At present, well-designed semiconductor devices will bring great convenience to integrated circuit and layout design. In the integrated circuit layout, in the LED lighting driver chip, the source of the high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) is connected to the internal circuit elements of the driver chip on the one hand, and is connected to the external input and output pins of the driver chip on the other hand. When the pins of the driver chip are exposed to ESD (ElectroStatic Discharge) surges, it is easy to damage the LDMOS and the chip where it is located. Therefore, it is necessary to protect the source of the LDMOS. In the existing technical solution, generally an additional GGMOS (Gate-Gnd Metal Oxide Semiconductor) is connected in parallel at the source end of the LDMOS, but this GGMOS needs to occupy an additional chip space. Therefore, the traditional technical solution has the problem of being unable to perform ESD surge protection or occupying a large integrated circuit space. Summary of the invention

[0003] The purpose of the present application is to provide an integrated circuit and a transistor device thereof and a preparation method thereof, aiming to solve the problem that the traditional technical solution cannot provide ESD surge protection or occupies a large space of the integrated circuit.

[0004] A first aspect of an embodiment of the present application provides a transistor device for an integrated circuit, comprising a first MOS tube and a second MOS tube, wherein a source of the first MOS tube and a drain of the second MOS tube are jointly formed in a first doped region, the first doped region is coupled to a pin of the integrated circuit, a gate, a source and a substrate of the second MOS tube are grounded, and the second MOS tube is configured to discharge surge current of the pin and the first MOS tube.

[0005] A second aspect of an embodiment of the present application provides an integrated circuit, comprising: the transistor device described in the first aspect of an embodiment of the present application.

[0006] A third aspect of the embodiments of the present application provides a method for manufacturing a transistor device, comprising:

[0007] forming a first well region of the first conductivity type and a second well region of the second conductivity type on a substrate of the first conductivity type;

[0008] Growing a first silicon dioxide layer on the upper surface of the first well region and the upper surface of the second well region, and forming a field oxide layer by photolithography and etching;

[0009] Growing a second silicon dioxide layer on the upper surface of the first well region to form a gate oxide layer, and forming a first semi-finished structure of the transistor device;

[0010] Depositing a polysilicon layer on the upper surface of the first semi-finished product structure, and defining a first polysilicon gate and a second polysilicon gate by photolithography and etching methods;

[0011] Forming a first doping region and a second doping region of the second conductivity type at intervals on the upper surface of the first well region;

[0012] A third doping region of the first conductivity type is formed on the upper surface of the first well region to form a second semi-finished structure of the transistor device, and the third doping region and the second doping region are arranged spaced apart from each other along the length direction of the first doping region;

[0013] Depositing a dielectric layer on the upper surface of the second semi-finished structure, and opening a plurality of lead holes on the dielectric layer by photolithography and etching;

[0014] Depositing a metal layer on the dielectric layer, and defining a plurality of metal electrodes for external connection on the metal layer by photolithography and etching;

[0015] The first doped region, the second polysilicon gate, the first well region and the second well region constitute a first MOS transistor, the first well region, the first doped region, the second doped region, the third doped region and the first polysilicon gate constitute a second MOS transistor, and the first MOS transistor and the second MOS transistor constitute the transistor device.

[0016] The transistor device of the above-mentioned integrated circuit includes a first MOS tube and a second MOS tube. The source of the first MOS tube and the drain of the second MOS tube are jointly formed in a first doped region, and the first doped region is coupled to a pin of the integrated circuit, and the gate, source and substrate of the second MOS tube are grounded, so that the second MOS tube is integrated in the first MOS tube and connected in series with the first MOS tube, so that the second MOS tube can discharge the surge current of the pin and the first MOS tube to the ground, thereby realizing ESD suppression for the first MOS tube and the integrated circuit in which it is located, that is, the transistor device can realize ESD suppression by itself without additionally connecting a surge protection device, thereby solving the problem that the traditional technical solution cannot perform ESD surge protection or occupies a large space of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A circuit diagram of a transistor device provided in one embodiment of the present application;

[0018] Figure 2 for Figure 1 A schematic diagram of a planar structure of a transistor device shown;

[0019] Figure 3 for Figure 2 A schematic diagram of the vertical structure of the transistor device extending line A shown;

[0020] Figure 4 for Figure 2 A schematic diagram of the vertical structure of the transistor device extending line B shown;

[0021] Figure 5 A specific flow chart of a method for preparing a transistor device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0024] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0026] In the existing technical solution, an additional GGMOS is generally connected in parallel to the source of LDMOS to discharge the ESD surge current of LDMOS, but this GGMOS needs to occupy an additional chip space, which limits the area of ​​the chip. In addition, in this way, the GGMOS discharges the LDMOS current unevenly, so the ESD protection effect is not ideal.

[0027] Figure 1 A circuit diagram of a transistor device provided in an embodiment of the present application is shown. For ease of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0028] See also Figure 1 and Figure 2 The transistor device for an integrated circuit in this embodiment includes a first MOS transistor Q1 and a second MOS transistor Q2. The source S1 of the first MOS transistor Q1 and the drain D2 of the second MOS transistor Q2 are formed together in a first doping region 31. The first doping region 31 is coupled to a pin of the integrated circuit. The gate G2, the source S2 and the substrate 10 of the second MOS transistor Q2 are grounded, and are configured to discharge surge currents of the pin and the first MOS transistor Q1.

[0029] It should be understood that in this embodiment, the source S1 of the first MOS transistor Q1 and the drain D2 of the second MOS transistor Q2 are formed together in the first doping region 31, so that the first MOS transistor Q1 and the second MOS transistor Q2 are connected in series and integrated into a transistor device as a whole; the gate G2, the source S2 and the substrate 10 of the second MOS transistor Q2 in this embodiment are grounded through a ground pin of the integrated circuit. The first MOS transistor Q1 and the second MOS transistor Q2 can be LDMOS transistors and GGMOS transistors respectively.

[0030] Optionally, the integrated circuit in this embodiment can be a single transistor device integrated circuit. When the integrated circuit is a single transistor device integrated circuit, the integrated circuit includes a high potential end, a control end, a low potential end and a discharge end, wherein the drain D1 of the first MOS tube Q1 is coupled to the high potential end (a pin), the gate G1 of the first MOS tube Q1 is coupled to the control end, the gate G2, the source S2 and the substrate 10 of the second MOS tube Q2 are coupled to the low potential end, the first doped region 31 is coupled to the discharge end, and the low potential end is used for grounding.

[0031] Optionally, the integrated circuit in this embodiment can also be any integrated circuit including the transistor device and other internal devices, such as an LED lighting driver chip, the LED lighting driver chip includes a transistor device and other internal devices, and the LED lighting driver chip includes multiple pins, wherein the first doped region 31 is coupled to a pin (Pad1) of the integrated circuit, other internal devices are coupled to the pin (Pad1) of the integrated circuit, and the gate G2, source and substrate 10 of the second MOS tube Q2 are grounded through the ground pin (Pad2) of the integrated circuit. When the pin (Pad1) of the integrated circuit is connected to a surge current, the second MOS tube Q2 discharges the surge current to the ground, thereby avoiding damage to the first MOS tube Q1 and other internal devices due to the surge current.

[0032] The transistor device in this embodiment includes a first MOS transistor Q1 and a second MOS transistor Q2. The source S1 of the first MOS transistor Q1 and the drain D2 of the second MOS transistor Q2 are formed together in the first doping region 31, and the gate G2, the source and the substrate 10 of the second MOS transistor Q2 are grounded, so that the second MOS transistor Q2 is monolithically integrated in the first MOS transistor Q1 and connected in series with the first MOS transistor Q1, so that the second MOS transistor Q2 can discharge the surge current of a pin of the integrated circuit and the first MOS transistor Q1 to the ground, thereby achieving ESD suppression for the first MOS transistor Q1 and the integrated circuit where the first MOS transistor Q1 is located, that is, the transistor device can achieve ESD suppression by itself without additionally connecting a surge protection device, thereby solving the problem that the traditional technical solution cannot perform ESD surge protection or occupies a large space of the integrated circuit.

[0033] See also Figure 3 In one embodiment, the invention further includes a substrate 10 and a first well region 11 of a first conductivity type formed on the substrate 10 , and a first doped region 31 is formed on an upper surface of the first well region 11 .

[0034] It should be understood that the substrate 10 in this embodiment is a semiconductor substrate 10, and optionally, it can be a wafer substrate 10, a chip substrate 10 or a composite semiconductor substrate 10, etc. The substrate 10 in this embodiment is of the first conductivity type (P-), and the first doped region 31 is of the second conductivity type (N+).

[0035] Optionally, in this embodiment, ions of the first conductivity type (P-) are implanted into the substrate 10 by ion implantation to form the first well region 11 .

[0036] See also Figure 2 and Figure 3In one embodiment, it also includes a second well region 12 of a second conductivity type (N-), the second well region 12 is formed on the substrate 10, and the second well region 12 is arranged adjacent to the first well region 11, and the second well region 12 serves as the drain D1 of the first MOS tube Q1.

[0037] It should be understood that in this embodiment, ions of the second conductivity type may be implanted into the substrate 10 by ion implantation to form the second well region 12 .

[0038] See also Figure 2 , Figure 3 as well as Figure 4 In one embodiment, the present invention further comprises: a second doping region 32 of a second conductivity type (N+) and a third doping region 33 of a first conductivity type (P+), wherein the second doping region 32 and the first doping region 31 are formed on the upper surface of the first well region 11 at intervals, the second doping region 32 comprises a first number of first sub-regions 32-1, each of which is short-circuited by a metal wire to become the source of the second MOS transistor Q2; the third doping region 33 and the first doping region 31 are formed on the upper surface of the first well region 11 at intervals, the third doping region 33 comprises a first number of second sub-regions 33-1, each of which is short-circuited by a metal wire to become the body of the transistor device, each of which is arranged at intervals with each of which along the length direction of the first doping region 31, and each of which forms a first number of PN junctions with each of which.

[0039] It should be understood that each first sub-region 32-1 and each second sub-region 33-1 in this embodiment are arranged adjacent to each other in sequence along the length direction of the first doping region 31 (i.e., the direction parallel to the upper surface of the substrate 10), so as to form a PN junction chain including multiple PN junctions, namely: first sub-region 32-1-second sub-region 33-1-first sub-region 32-1-second sub-region 33-1-....-first sub-region 32-1-second sub-region 33-1, or can be: second sub-region 33-1-first sub-region 32-1-second sub-region 33-1-first sub-region 32-1-...-second sub-region 33-1-first sub-region 32-1. The first number can be any desired number. The first number in this embodiment is set to 3, and in other embodiments, it can also be set to other values.

[0040] It should be understood that the body of the transistor device further includes the first well region 11 , that is, the first well region 11 and the third doped region 33 together serve as the body of the transistor device.

[0041] It should be understood that in this embodiment, by adding

[0042] See also Figure 3In one embodiment, it also includes a first polysilicon gate 21, which is formed on the upper surface of the first well region 11, and the first polysilicon gate 21 is located above the area between the first doping region 31 and the second doping region 32, and the first polysilicon gate 21 serves as the gate G2 of the second MOS tube Q2.

[0043] It should be understood that in this embodiment, the first polysilicon gate 21 and the first doping region 31 are staggered and opposite to each other, and the first polysilicon gate 21 and the second doping region 32 are staggered and opposite to each other.

[0044] The transistor device in this embodiment arranges the first polysilicon gate 21, the first doping region 31, the second doping region 32 and the third doping region 33 relatively close to each other, so that in the transistor device, the surge current connected to the first doping region 31 can be quickly discharged.

[0045] See also Figure 3 In one embodiment, the gate oxide layer 41 is further included. The gate oxide layer 41 is formed on the lower surface of the first polysilicon gate 21 .

[0046] It should be understood that the gate oxide layer 41 may be made of silicon dioxide. Specifically, the silicon dioxide may be formed by a furnace oxidation method.

[0047] See also Figure 3 In one embodiment, the present invention further includes: a field oxide layer 42 , wherein the field oxide layer 42 is formed on the upper surface of the second well region 12 and a portion of the upper surface of the first well region 11 .

[0048] It should be understood that the field oxide layer 42 in this embodiment can be composed of silicon dioxide, and specifically, silicon dioxide can be formed by a furnace oxidation method. The field oxide layer 42 can be an oxide layer with a certain slope shape, and optionally, the field oxide layer 42 can be etched into a preset shape by directional etching.

[0049] See also Figure 3 In one embodiment, a second polysilicon gate 22 is included. The second polysilicon gate 22 is formed on the upper surface of the field oxide layer 42 and serves as the gate G1 of the first MOS transistor Q1. It should be understood that the shape of the second polysilicon gate 22 corresponds to the shape of the field oxide layer 42.

[0050] Optionally, in one embodiment, an insulating layer is further included, which covers the exposed upper surfaces of the first doping region 31, the second doping region 32, the third doping region 33, the first polysilicon gate 21, the second polysilicon gate 22, the first well region 11, and the second well region 12, and the insulating layer is provided with a plurality of through holes, each of which is filled with a conductive material, and the two ends of the through holes are electrically connected through the conductive material. Furthermore, it also includes a first contact electrode, a second contact electrode, a third contact electrode and a fourth contact electrode, wherein the first contact electrode, the second contact electrode, the third contact electrode and the fourth contact electrode are arranged above the insulating layer, and the first contact electrode, the second contact electrode, the third contact electrode and the fourth contact electrode can be made of metal materials, wherein the first contact electrode is connected to the first well region 12 through the conductive material filled in the first through hole of the insulating layer, the second contact electrode is connected to the second polysilicon gate 22 through the conductive material filled in the second through hole of the insulating layer, the third contact electrode is connected to the first doped region 31 through the conductive material filled in the third through hole of the insulating layer, and the fourth contact electrode is connected to the second doped region 32, the third doped region 33 and the first polysilicon gate 21 through the conductive material filled in the fourth through hole of the insulating layer. Optionally, the first contact electrode serves as a high potential end of the transistor device (for example, a drain electrode of an LDMOS tube), the second contact electrode serves as a control end of the transistor device (for example, a gate electrode of an LDMOS tube), the third contact electrode serves as an ESD protection end of the transistor device, and the fourth contact electrode serves as a low potential end (ground end) of the transistor device.

[0051] In one embodiment, the first MOS transistor Q1 is a LDMOS device, and the second MOS transistor Q2 is a GGMOS device.

[0052] It should be understood that the first conductivity type in this embodiment is P type and the second conductivity type is N type. In other embodiments, the first conductivity type may be N type and the second conductivity type may be P type.

[0053] A second aspect of the embodiments of the present invention provides an integrated circuit, comprising the transistor device as described in the first aspect of the embodiments of the present invention.

[0054] Optionally, the integrated circuit in this embodiment can be a single transistor device integrated circuit. When the integrated circuit is a single transistor device integrated circuit, the integrated circuit includes a high potential end, a control end, a low potential end and a discharge end, wherein the drain D1 of the first MOS tube Q1 is coupled to the high potential end (a pin), the gate G1 of the first MOS tube Q1 is coupled to the control end, the gate G2, the source S2 and the substrate 10 of the second MOS tube Q2 are coupled to the low potential end, the first doped region 31 is coupled to the discharge end, and the low potential end is used for grounding.

[0055] Optionally, the integrated circuit in this embodiment can also be any integrated circuit including the transistor device and other internal devices, such as an LED lighting driver chip, the LED lighting driver chip includes a transistor device and other internal devices, and the LED lighting driver chip includes multiple pins, wherein the first doped region 31 is coupled to a pin (Pad1) of the integrated circuit, other internal devices are coupled to the pin (Pad1) of the integrated circuit, and the gate G2, source and substrate 10 of the second MOS tube Q2 are grounded through the ground pin (Pad2) of the integrated circuit. When the pin (Pad1) of the integrated circuit is connected to a surge current, the second MOS tube Q2 discharges the surge current to the ground, thereby avoiding damage to the first MOS tube Q1 and other internal devices due to the surge current.

[0056] See also Figure 5 A third aspect of an embodiment of the present invention provides a method for manufacturing a transistor device, comprising:

[0057] Step S100: forming a first well region 11 of a first conductivity type and a second well region 12 of a second conductivity type on a substrate 10 of a first conductivity type;

[0058] It should be understood that a first well region 11 of a first conductivity type and a second well region 12 of a second conductivity type may be formed on the semiconductor substrate 10 by ion implantation.

[0059] Step S200: growing a first silicon dioxide layer on the upper surface of the first well region 11 and the upper surface of the second well region 12, and forming a field oxide layer 42 by photolithography and etching;

[0060] It should be understood that the redundant portion of the first silicon dioxide layer can be removed by photolithography and etching, leaving only the portion above the second well region 12 and above a portion of the first well region 11 , thereby forming the field oxide layer 42 .

[0061] Step S300: growing a second silicon dioxide layer on the upper surface of the first well region 11 to form a gate oxide layer 41, and forming a first semi-finished structure of a transistor device;

[0062] It should be understood that the first semi-finished structure of the transistor device includes a stacked structure consisting of the substrate, the first well region 11 , the second well region 12 , the field oxide layer 42 and the gate oxide layer 41 mentioned above.

[0063] Step S400: depositing a polysilicon layer on the upper surface of the first semi-finished product structure, and defining a first polysilicon gate 21 and a second polysilicon gate 22 by photolithography and etching methods;

[0064] It should be understood that after a polysilicon layer is deposited on the upper surface of the first semi-finished product structure, a photoresist layer (photoresist layer) may be arranged on the polysilicon layer, the photoresist layer covers the polysilicon layer, a defined mask layer is placed on the photoresist layer, and light of a specific wavelength is irradiated, and the photoresist layer is changed into a shape consistent with that defined by the mask layer through a corresponding washing liquid, a first polysilicon region and a second polysilicon region are defined according to the shape of the photoresist layer, a first polysilicon gate 21 is directionally etched in the first polysilicon region, and a second polysilicon gate 22 is directionally etched in the second polysilicon region;

[0065] Step S500: forming a first doping region 31 and a second doping region 32 of the second conductivity type on the upper surface of the first well region 11 at intervals;

[0066] It should be understood that a first doped region 31 of the second conductivity type (N+) is formed on the upper surface of the first well region 11, and the first doped region 31 is located in the middle area between the first polysilicon gate 21 and the second polysilicon gate 22, that is, in the middle area between the first polysilicon gate 21 and the second polysilicon gate 22, ions of the second conductivity type (N+) are injected into the upper surface of the first well region 11 to form a first doped region 31 of the second conductivity type, the first doped region 31 is located on one side of the first polysilicon gate 21 and is offset and opposite to the first polysilicon gate 21, and ions of the second conductivity type are injected into the upper surface of the first well region 11 on the other side close to the first polysilicon gate 21 to form a second doped region 32, the second doped region 32 is spaced apart from the first doped region 31 and is offset and opposite to the second polysilicon gate 21, and the second doped region 32 includes a first number of first sub-regions 32-1, and each first sub-region 32-1 is arranged at intervals along the length direction of the first doped region 31.

[0067] Step S600: forming a third doping region 33 of the first conductivity type on the upper surface of the first well region 11 to form a second semi-finished structure of the transistor device, wherein the third doping region 33 and the second doping region 32 are arranged spaced apart from each other along the length direction of the first doping region 31;

[0068] It should be understood that the third doping region 33 includes a first number of second sub-regions 33-1, and the second sub-regions 33-1 are arranged at intervals along the length direction of the first doping region 31, and the first sub-regions 32-1 and the second sub-regions 33-1 are adjacent to each other along the length direction of the first doping region; it should be understood that the position of the first sub-region 32-1 is opposite to the first doping region 31, and the position of the second sub-region 33-1 is opposite to the first doping region 31.

[0069] Optionally, each first sub-region 32-1 is short-circuited by a metal wire and ions of the second conductivity type are implanted into each first sub-region 32-1 to form a second doped region 32, and each second sub-region 33-1 and the first well region 11 are short-circuited by another metal wire and ions of the first conductivity type are implanted into each second sub-region 33-1 to form a third doped region 33;

[0070] Step S700: depositing a dielectric layer on the upper surface of the second semi-finished product structure, and opening a plurality of lead holes on the dielectric layer by photolithography and etching;

[0071] It should be understood that the dielectric layer is an insulating layer.

[0072] Step S800: depositing a metal layer on the dielectric layer, and defining a plurality of metal electrodes for external connection on the metal layer by photolithography and etching;

[0073] It should be understood that the plurality of metal electrodes are respectively connected to the second well region 12 , the first polysilicon gate 21 , the second polysilicon gate 22 , the first doping region 31 , the second doping region 32 and the third doping region 33 .

[0074] The first doped region 31, the second polysilicon gate 22, the first well region 11 and the second well region 12 constitute a first MOS transistor Q1, the first well region 11, the first doped region 31, the second doped region 32, the third doped region 33 and the first polysilicon gate 21 constitute a second MOS transistor Q2, and the first MOS transistor Q1 and the second MOS transistor Q2 constitute a transistor device.

[0075] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A transistor device for an integrated circuit, characterized in that: The method comprises a first MOS tube and a second MOS tube, wherein the source of the first MOS tube and the drain of the second MOS tube are formed together in a first doped region, the first doped region is coupled to a pin of the integrated circuit, the gate, the source and the substrate of the second MOS tube are grounded, and the second MOS tube is configured to discharge surge current of the pin and the first MOS tube; The transistor device further includes a substrate and a first well region of a first conductivity type formed on the substrate, the first doped region is formed on an upper surface of the first well region, and the first doped region is of a second conductivity type; a second well region of a second conductivity type, the second well region being formed on the substrate, the second well region being disposed adjacent to the first well region, and the second well region serving as a drain of the first MOS transistor; A second doping region of a second conductivity type, the second doping region and the first doping region are formed on the upper surface of the first well region at intervals, the second doping region includes a first number of first sub-regions, and each of the first sub-regions is short-circuited by a metal wire to become a source of the second MOS tube; A third doped region of the first conductivity type is formed on the upper surface of the first well region at intervals with the first doped region, the third doped region includes a first number of second sub-regions, each of the second sub-regions is short-circuited by a metal wire to become a body electrode of the transistor device, the first sub-regions are respectively arranged with the second sub-regions at intervals along the length direction of the first doped region, and each of the first sub-regions and each of the second sub-regions together form the first number of PN junctions.

2. The transistor device according to claim 1, characterized in that It also includes a first polysilicon gate, which is formed on the upper surface of the first well region and is located above the area between the first doped region and the second doped region, and the first polysilicon gate serves as the gate of the second MOS tube.

3. The transistor device according to claim 2, characterized in that It also includes a gate oxide layer, which is formed on the lower surface of the first polysilicon gate.

4. The transistor device according to claim 3, characterized in that Also includes: A field oxide layer is formed on an upper surface of the second well region and a portion of an upper surface of the first well region.

5. The transistor device according to claim 4, characterized in that It also includes a second polysilicon gate, which is formed on the upper surface of the field oxide layer and serves as the gate of the first MOS tube.

6. An integrated circuit, characterized in that: include: A transistor device as claimed in any one of claims 1 to 5.

7. A method for preparing a transistor device, characterized in that: include: forming a first well region of the first conductivity type and a second well region of the second conductivity type on a substrate of the first conductivity type; Growing a first silicon dioxide layer on the upper surface of the first well region and the upper surface of the second well region, and forming a field oxide layer by photolithography and etching; Growing a second silicon dioxide layer on the upper surface of the first well region to form a gate oxide layer, and forming a first semi-finished structure of the transistor device; Depositing a polysilicon layer on the upper surface of the first semi-finished product structure, and defining a first polysilicon gate and a second polysilicon gate by photolithography and etching methods; Forming a first doping region and a second doping region of the second conductivity type at intervals on the upper surface of the first well region; A third doping region of the first conductivity type is formed on the upper surface of the first well region to form a second semi-finished structure of the transistor device, and the third doping region and the second doping region are arranged spaced apart from each other along the length direction of the first doping region; Depositing a dielectric layer on the upper surface of the second semi-finished structure, and opening a plurality of lead holes on the dielectric layer by photolithography and etching; Depositing a metal layer on the dielectric layer, and defining a plurality of metal electrodes for external connection on the metal layer by photolithography and etching; The first doped region, the second polysilicon gate, the first well region and the second well region constitute a first MOS transistor, the first well region, the first doped region, the second doped region, the third doped region and the first polysilicon gate constitute a second MOS transistor, and the first MOS transistor and the second MOS transistor constitute the transistor device.

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