Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device can include a horizontal structure that can be located on an upper surface of a substrate and can include a first horizontal pattern and a second horizontal pattern that are sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode can have first inner sidewalls facing each other, with the separation structure interposed therebetween. The second horizontal pattern can have second inner sidewalls facing each other, with the separation structure interposed therebetween. A maximum distance in the first direction between the first inner sidewalls can be less than a maximum distance in the first direction between the second inner sidewalls.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0033416, filed on March 18, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Embodiments of the present inventive concept relate to a three-dimensional (3D) semiconductor memory device, and more particularly, to a 3D semiconductor memory device having improved reliability and integration density. BACKGROUND

[0004] Semiconductor devices have been highly integrated to provide excellent performance and low manufacturing costs. The integration density of a semiconductor device can directly affect the cost of the semiconductor device, thereby increasing the demand for highly integrated semiconductor devices. The integration density of a two-dimensional (2D) or planar semiconductor device can be mainly determined by the area occupied by a unit memory cell. Accordingly, the integration density of a 2D or planar semiconductor device can be affected by a technology of forming a fine pattern. However, since a fine pattern can be formed using an expensive apparatus, an increase in the integration density of a 2D semiconductor device can be limited. Accordingly, a three-dimensional (3D) semiconductor memory device has been developed to overcome the above-described limitations. The 3D semiconductor memory device can include memory cells arranged in three dimensions. SUMMARY

[0005] Embodiments of the present inventive concept can provide a three-dimensional (3D) semiconductor memory device capable of improving reliability and integration density.

[0006] According to some embodiments of the inventive concept, a 3D semiconductor memory device can include a horizontal structure that can be located on an upper surface of a substrate and can include a first horizontal pattern and a second horizontal pattern that can be sequentially stacked on the upper surface of the substrate in a vertical direction; a stack structure including a plurality of electrodes stacked on the horizontal structure in the vertical direction; a vertical pattern extending through the plurality of electrodes and connected to the first horizontal pattern; and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode of the plurality of electrodes can have first inner sidewalls that can face each other and can be spaced apart from each other in a first direction, the separation structure being interposed between the first inner sidewalls, and the second horizontal pattern can have second inner sidewalls that can face each other and can be spaced apart from each other in the first direction, the separation structure being interposed between the second inner sidewalls. A maximum distance between the first inner sidewalls in the first direction can be less than a maximum distance between the second inner sidewalls in the first direction.

[0007] According to some embodiments of the inventive concept, a 3D semiconductor memory device can include a substrate including a recess in an upper surface thereof; a stack structure including a plurality of electrodes stacked on the upper surface of the substrate in a vertical direction; a horizontal structure that can be located between the stack structure and the substrate and can include a first horizontal pattern and a second horizontal pattern that can be sequentially stacked on the upper surface of the substrate in the vertical direction; and a separation structure intersecting the stack structure and the horizontal structure in a first direction parallel to the upper surface of the substrate. A portion of the separation structure can be located in the recess of the substrate. The first horizontal pattern can have first inner sidewalls that can face each other and can be spaced apart from each other in a second direction that can be perpendicular to the first direction, the separation structure being interposed between the first inner sidewalls. A maximum width of the recess in the second direction can be greater than a maximum distance between the first inner sidewalls in the second direction.

[0008] According to some embodiments of the inventive concept, a 3D semiconductor memory device can include a peripheral logic circuit on a lower substrate, a lower insulating layer on the peripheral logic circuit, a substrate on the lower insulating layer and including a recess in an upper surface thereof, a stack structure including a plurality of electrodes vertically stacked on the upper surface of the substrate, a horizontal structure that can be located between the stack structure and the substrate and can include a first horizontal pattern and a second horizontal pattern that can be sequentially stacked on the upper surface of the substrate, a vertical pattern extending through the plurality of electrodes and connected to the first horizontal pattern, a partition structure intersecting the stack structure and the horizontal structure in a first direction parallel to the upper surface of the substrate and including a portion located in the recess of the substrate, an interface layer between the first horizontal pattern and the second horizontal pattern, and a first insulating layer between the substrate and the portion of the partition structure located in the recess. The interface layer can extend on a first portion of an upper surface of the first horizontal pattern, and the first insulating layer can extend on a second portion of the upper surface of the first horizontal pattern.

[0009] According to some embodiments of the inventive concept, a 3D semiconductor memory device can include a substrate including a first recess and a second recess that can be located in an upper surface of the substrate and can be spaced apart from each other in a first direction, a stack structure including a plurality of electrodes stacked in a vertical direction on the upper surface of the substrate, a horizontal structure that can be located between the stack structure and the substrate and can include a first horizontal pattern and a second horizontal pattern that can be sequentially stacked in the vertical direction on the upper surface of the substrate, a vertical pattern extending through the plurality of electrodes and connected to the first horizontal pattern, a first partition structure extending through the stack structure and the horizontal structure in the vertical direction and including a portion located in the first recess, and a second partition structure extending through the stack structure and the horizontal structure in the vertical direction and including a portion located in the second recess. The first partition structure and the second partition structure can have different maximum widths in the first direction at a lower level than respective levels of the upper surface of the substrate in the vertical direction. BRIEF DESCRIPTION OF DRAWINGS

[0010] The inventive concept will become apparent from the drawings and accompanying detailed description.

[0011] FIG. 1 is a schematic circuit diagram showing a unit array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concepts.

[0012] FIG. 2 is a top view showing a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0013] FIG. 3A FIG. 3B and FIG. 3C are cross-sectional views taken along lines A-A', B-B' and C-C' of FIG. 2 respectively, to show a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0014] FIG. 4A through FIG. 4E is an enlarged view of portion "AA" of FIG. 3B .

[0015] FIG. 5A and FIG. 5B are enlarged cross-sectional views of portion "BB" of FIG. 4A .

[0016] FIG. 6 is an enlarged cross-sectional view corresponding to portion "AA" of FIG. 3B to show a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0017] FIG. 7A is a cross-sectional view taken along line B-B' of FIG. 2 to show a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0018] FIG. 7B is an enlarged cross-sectional view of portion "CC" of FIG. 7A .

[0019] FIG. 8 is a cross-sectional view taken along line D-D' of FIG. 2 to show a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0020] FIG. 9 shows enlarged cross-sectional views of portions "DD" and "EE" of FIG. 8 .

[0021] FIG. 10 is a top view showing a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0022] FIG. 11 is a cross-sectional view taken along line E-E' of FIG. 10 to show a 3D semiconductor memory device according to some embodiments of the inventive concepts.​

[0023] FIG. 12 enlarged cross-sectional view of a portion "FF" and "GG" of FIG. 11

[0024] FIG. 13A FIG. 14A FIG. 15A FIG. 16A FIG. 17A FIG. 20A are cross-sectional views taken along line B-B' of FIG. 2 to illustrate a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0025] FIG. 13B FIG. 14B are cross-sectional views taken along line A-A' of FIG. 2 to illustrate a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0026] FIG. 15B is an enlarged view of a portion AAA of FIG. 15A FIG. 16B FIG. 16C is an enlarged view of a portion AAA of FIG. 16A FIG. 17B FIG. 18 FIG. 19 is an enlarged view of a portion AAA of FIG. 17A FIG. 20B FIG. 20C are enlarged views of a portion "AAA" of FIG. 20A DETAILED DESCRIPTION

[0027] Example embodiments of the inventive concept will be described in detail below with reference to the attached drawings.

[0028] FIG. 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0029] Referring to FIG. 1 , the cell array of the 3D semiconductor memory device can include a common source line CSL, a plurality of bit lines BL0 to BL2, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL0 to BL2.

[0030] ​​​​​​​​​​​​​​​The cell strings CSTR can be two-dimensionally arranged along the first direction D1 and the second direction D2 and can extend in the third direction D3. As used herein, “an element A extends in a direction X” (or similar language) can mean that the element A extends lengthwise in the direction X.

[0031] The plurality of cell strings CSTR can be connected in parallel to each of the bit lines BL0 to BL2. The cell strings CSTR can be collectively connected to a common source line CSL. In other words, the plurality of cell strings CSTR can be disposed between a single common source line CSL and a plurality of bit lines BL0 to BL2. A plurality of common source lines CSL can be disposed, and the plurality of common source lines CSL can be two-dimensionally arranged. In some embodiments, the same voltage can be applied to the plurality of common source lines CSL. In some embodiments, the common source lines CSL can be electrically controlled independently of each other. As used herein, “an element A is connected to an element B” (or similar language) can mean that the element A is electrically and / or physically connected to the element B. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0032] In some embodiments, each cell string CSTR can include a string selection transistor SST1 and SST2 connected in series to each other, a storage cell transistor MCT connected in series to each other, a ground selection transistor GST, and an erase control transistor ECT. Each storage cell transistor MCT can include a data storage element.

[0033] In some embodiments, each cell string CSTR can include a first string selection transistor SST1 and a second string selection transistor SST2 connected in series to each other, and the second string selection transistor SST2 can be connected to one of the bit lines BL0 to BL2. In some embodiments, each cell string CSTR can include a single string selection transistor. In some embodiments, in each cell string CSTR, similar to the first string selection transistor SST1 and the second string selection transistor SST2, the ground selection transistor GST can include a plurality of MOS transistors connected in series to each other.

[0034] Each cell string CSTR can include a plurality of memory cell transistors MCT disposed at different distances from a common source line CSL, respectively. The memory cell transistors MCT can be connected in series between a first string select transistor SST1 and a ground select transistor GST. An erase control transistor ECT can be connected between the ground select transistor GST and the common source line CSL. In addition, each cell string CSTR can also include dummy memory cell transistors DMC connected between the first string select transistor SST1 and an uppermost one of the memory cell transistors MCT, and between the ground select transistor GST and a lowermost one of the memory cell transistors MCT, respectively.

[0035] In some embodiments, the first string select transistor SST1 can be controlled by a first string select line SSL1, and the second string select transistor SST2 can be controlled by a second string select line SSL2. The memory cell transistors MCT can be controlled by word lines WL0 to WLn, respectively, and the dummy memory cell transistors DMC can be controlled by a dummy word line DWL, respectively. The ground select transistor GST can be controlled by a ground select line GSL0, GSL1, or GSL2, and the erase control transistor ECT can be controlled by an erase control line ECL. The common source line CSL can be commonly connected to a source of the erase control transistor ECT.

[0036] The gate electrodes of the memory cell transistors MCT (or the dummy memory cell transistors DMC) disposed at substantially the same horizontal level (or distance) from the common source line CSL can be commonly connected to one of the word lines WL0 to WLn and DWL, thereby being in an equipotential state. In some embodiments, even though the gate electrodes of the memory cell transistors MCT are disposed at substantially the same horizontal level from the common source line CSL, the gate electrodes disposed in one row (or column) can be controlled independently from the gate electrodes disposed in another row (or column).

[0037] The ground select lines GSL0 to GSL2 and the string select lines SSL1 and SSL2 can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. The ground select lines GSL0 to GSL2 disposed at substantially the same horizontal level from the common source line CSL can be electrically isolated from each other, and the string select lines SSL1 or SSL2 disposed at substantially the same horizontal level from the common source line CSL can be electrically isolated from each other. In addition, the erase control transistors ECT of the different cell strings CSTR from each other can be commonly controlled by the erase control line ECL. The erase control transistors ECT can generate gate induced drain leakage (GIDL) in the erase operation of the cell array. According to some embodiments, in the erase operation of the cell array, an erase voltage can be applied to the bit lines and / or the common source line CSL, and a GIDL current can be generated from the string select transistors SST2 and / or the erase control transistors ECT.

[0038] FIG. 2 is a top view showing a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 3A 、 FIG. 3B and FIG. 3C are cross-sectional views taken along lines A-A', lines B-B', and lines C-C' of FIG. 2 to show a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 4A through FIG. 4E is a close-up view of portion "AA" of FIG. 3B . FIG. 5A and FIG. 5B are close-up cross-sectional views of portion "BB" of FIG. 4A .

[0039] Referring to FIG. 2 and FIG. 3A through FIG. 3C , a 3D semiconductor memory device according to some embodiments can include a peripheral logic structure PS and a cell array structure CS disposed on the peripheral logic structure PS.

[0040] The peripheral logic structure PS can include a peripheral logic circuit PTR integrated on a lower substrate 10 and a lower insulating layer 50 covering the peripheral logic circuit PTR. As used herein, "element A covers element B" (or similar language) means that element A is on element B, but does not necessarily mean that element A completely covers element B.

[0041] The lower substrate 10 can include a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The lower substrate 10 can include an active region defined by a device isolation layer 13.

[0042] A peripheral logic circuit PTR can be disposed on the active region. The peripheral logic circuit PTR can include row and column decoders, page buffers, and / or control circuits. More specifically, the peripheral logic circuit PTR can include a peripheral gate insulating layer on the lower substrate 10, a peripheral gate electrode on the peripheral gate insulating layer, and source / drain regions disposed in the active region on both sides of the peripheral gate electrode.

[0043] The peripheral circuit interconnect lines 33 can be electrically connected to the peripheral logic circuit PTR through the peripheral contact plug 31. For example, the peripheral contact plug 31 and the peripheral circuit interconnect lines 33 can be connected to NMOS and PMOS transistors.

[0044] A lower insulating layer 50 can be disposed on the entire top surface of the lower substrate 10. The lower insulating layer 50 can cover the peripheral logic circuit PTR, the peripheral contact plug 31, and the peripheral circuit interconnect lines 33 on the lower substrate 10. The lower insulating layer 50 can include a plurality of stacked insulating layers. For example, the lower insulating layer 50 can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a low-k dielectric layer.

[0045] A cell array structure CS can be disposed on the lower insulating layer 50. The cell array structure CS can include a horizontal semiconductor layer 100, a horizontal structure SC, a stack structure ST, and a vertical structure VS. In some embodiments, FIG. 1 The illustrated cell string CSTR can be integrated on the horizontal semiconductor layer 100. The stack structure ST and the vertical structure VS can constitute FIG. 1 The illustrated cell string CSTR. The horizontal semiconductor layer 100 can be referred to as a substrate.

[0046] More specifically, the horizontal semiconductor layer 100 can be disposed on a top surface of the lower insulating layer 50. The horizontal semiconductor layer 100 can be formed of a semiconductor material. For example, the horizontal semiconductor layer 100 can include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). The horizontal semiconductor layer 100 can include a semiconductor material doped with a dopant of a first conductivity type (e.g., N-type) and / or an intrinsic semiconductor material not doped with a dopant. The horizontal semiconductor layer 100 can have a crystal structure including at least one of a single-crystal structure, an amorphous structure, or a polycrystalline structure.

[0047] The horizontal structure SC can be disposed between the stack structure ST and the horizontal semiconductor layer 100. The horizontal structure SC can be parallel to a top surface of the horizontal semiconductor layer 100 and can extend in the first direction D1 and the second direction D2 in parallel to the stack structure ST. The horizontal structure SC can be referred to as a channel region. FIG. 1The described common source line CSL. The horizontal structure SC can include a first horizontal pattern SCP1 and a second horizontal pattern SCP2 located on the first horizontal pattern SCP1. The first horizontal pattern SCP1 and the second horizontal pattern SCP2 can be sequentially stacked on the horizontal semiconductor layer 100. The first horizontal pattern SCP1 and the second horizontal pattern SCP2 can be formed of a semiconductor material doped with a dopant (e.g., phosphorus (P) or arsenic (As)) having a first conductivity type. In some embodiments, the first horizontal pattern SCP1 and the second horizontal pattern SCP2 can each be formed of a semiconductor material doped with an N-type dopant, and a concentration of the N-type dopant in the first horizontal pattern SCP1 can be greater than a concentration of the N-type dopant in the second horizontal pattern SCP2.

[0048] The stack structure ST can be disposed on the horizontal semiconductor layer 100. The stack structure ST can be spaced apart from the horizontal semiconductor layer 100 with the horizontal structure SC intervening therebetween. The horizontal semiconductor layer 100 can have a top surface extending in a first direction D1 and a second direction D2 perpendicular to the first direction D1. The horizontal semiconductor layer 100 can include a cell array region CAR and a connection region CNR arranged in the second direction D2. The stack structure ST can extend from the cell array region CAR onto the connection region CNR in the second direction D2 and can have a stepped structure on the connection region CNR. The stack structure ST can include electrodes EGE, GGE, CGE, and SGE stacked in a third direction D3 (e.g., a vertical direction) perpendicular to the first direction D1 and the second direction D2. The length of the electrodes of the stack structure ST in the second direction D2 can sequentially decrease as a vertical distance from the lower substrate 10 increases, and the height of the stack structure ST can decrease as a horizontal distance from the cell array region CAR increases. Each electrode can have a pad portion on the connection region CNR, and the pad portions of the electrodes can be located at positions horizontally and vertically different from each other.

[0049] In some embodiments, the electrodes EGE, GGE, CGE, and SGE can include an erase control gate electrode EGE adjacent to the horizontal structure SC, a ground select gate electrode GGE located on the erase control gate electrode EGE, a plurality of cell gate electrodes CGE sequentially stacked on the ground select gate electrode GGE, and a string select gate electrode SGE located on an uppermost cell gate electrode of the cell gate electrodes CGE.

[0050] The erase control gate electrode EGE can be adjacent to the horizontal structure SC and can function as a gate electrode of an erase control transistor ECT (see FIG. 1 ) for controlling an erase operation of a memory cell array. The erase control gate electrode EGE can function as an erase control transistor ECT (seeFIG. 1 ) of the ground select gate electrode GGE. The ground select gate electrode GGE can function as a gate electrode of a ground select transistor GST (see FIG. 1 ) for controlling an electrical connection between the common source line CSL (see FIG. 1 ) and the vertical pattern VC of the vertical structure VS. The cell gate electrode CGE can function as control gate electrodes WL0 to WLn and DWL (see FIG. 1 ) of the memory cell transistor MCT and the dummy memory cell transistor DMC (see FIG. 1 ) corresponding to the uppermost electrode among the electrodes EGE, GGE, CGE, and SGE. The string select gate electrode SGE can function as a gate electrode of a string select transistor SST2 (see FIG. 1 ) for controlling an electrical connection between the bit line BL and the vertical pattern VC. The thickness of the insulating layers ILD between the cell gate electrodes CGE can be substantially equal to each other, and the insulating layer ILD between the ground select gate electrode GGE and the lowermost cell gate electrode among the cell gate electrodes CGE can be thicker than the other insulating layers ILD.

[0051] The vertical structure VS can be disposed on the cell array region CAR of the horizontal semiconductor layer 100, and the dummy vertical structure DVS can be disposed on the connection region CNR of the horizontal semiconductor layer 100. The vertical structure VS and the dummy vertical structure DVS can extend in a third direction D3 substantially perpendicular to a top surface of the horizontal semiconductor layer 100, and can penetrate the stacked structure ST and the horizontal structure SC.

[0052] When viewed in a top view, the vertical structure VS can be arranged in a straight line or a zigzag form in one direction. The dummy vertical structure DVS can penetrate an end portion of the electrode. The vertical structure VS can include a vertical pattern VC, a filling insulating pattern VI, a data storage pattern DSP, and a bit line conductive pad PAD.

[0053] The vertical pattern VC can have a tubular or a penne shape. The filling insulating pattern VI can fill a hollow space surrounded by the vertical pattern VC. The vertical pattern VC can include a semiconductor material such as silicon (Si), germanium (Ge), or a combination thereof. In addition, the vertical pattern VC can include a semiconductor material doped with a dopant or an intrinsic semiconductor material not doped with a dopant. The vertical pattern VC can include, for example, a polycrystalline semiconductor material. The vertical pattern VC including the semiconductor material can function as a channel of the memory cell transistor MCT and the dummy memory cell transistor DMC (see FIG. 1Channel regions of the erase control transistor ECT, the string select transistor SST2, the ground select transistor GST, and the memory cell transistor MCT are described. The vertical pattern VC can be electrically connected to the bit line BL through the bit line conductive pad PAD. As used herein, “element A fills element B” (or similar language) can mean that element A is in element B, but does not necessarily mean that element A completely fills element B.

[0054] A data storage pattern DSP can be disposed between the stack structure ST and the vertical pattern VC. The data storage pattern DSP can extend in the third direction D3 and can surround a sidewall of the vertical pattern VC. The data storage pattern DSP can have a tubular or penne shape. A bottom surface of the data storage pattern DSP can be disposed at a lower level than a bottom surface of the erase gate electrode EGE and can be in contact with the first horizontal pattern SCP1.

[0055] A dummy vertical structure DVS can be disposed on the connection region CNR of the horizontal semiconductor layer 100. The dummy vertical structure DVS can penetrate a pad portion of an electrode located on the connection region CNR. In some embodiments, a width of the dummy vertical structure DVS can be greater than a width of the vertical structure VS. Additionally, the dummy vertical structure DVS can have substantially the same stack structure and materials as the vertical structure VS.

[0056] An upper planarization insulating layer 150 can be disposed on the horizontal semiconductor layer 100 to cover the staircase structure of the stack structure ST. The upper planarization insulating layer 150 can have a substantially planar top surface and can include a single insulating layer or a plurality of stacked insulating layers. The upper planarization insulating layer 150 can include, for example, a silicon oxide layer and / or a low-k dielectric layer.

[0057] A plurality of separation structures SS can be disposed on the horizontal semiconductor layer 100. The separation structures SS can be arranged in the first direction D1 and can extend in the second direction D2 to intersect the stack structure ST. In some embodiments, the separation structures SS can be spaced apart from each other in the first direction D1, as FIG. 2Each separation structure SS can penetrate the stack structure ST and the horizontal structure SC, and can be inserted in the horizontal semiconductor layer 100. Thus, each of the electrodes EGE, GGE, CGE, and SGE in the stack structure ST can be separated into portions spaced apart from each other with the separation structure SS interposed therebetween in the first direction D1. The separation structure SS can extend from the cell array region CAR onto the connection region CNR. The separation structure SS can be located between the vertical structures VS on the cell array region CAR. The separation structure SS can be located between the cell contact plugs CPLG on the connection region CNR. A bottom end of the separation structure SS can be located at a horizontal level lower than a top surface of the horizontal semiconductor layer 100, and a top end of the separation structure SS can be located at a horizontal level higher than a top surface of the stack structure ST. The separation structure SS can include an insulating material. The separation structure SS can include, for example, at least one of silicon oxide or silicon nitride.

[0058] More specifically, referring to FIG. 2 , FIG. 3A through FIG. 3C and FIG. 4A , the data storage pattern DSP can include a plurality of thin layers. The data storage pattern DSP can be a data storage layer of a NAND flash memory device, and can include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BLK stacked sequentially on a sidewall of a vertical pattern VC. For example, the charge storage layer CIL can include a trap insulating layer, a floating gate electrode, and / or an insulating layer including electrically conductive nanodots. The charge storage layer CIL can include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystal silicon layer, or a stacked trap layer. The tunnel insulating layer TIL can include at least one of a material having a band gap greater than a band gap of the charge storage layer CIL. The blocking insulating layer BLK can include, for example, a high-k dielectric layer such as an aluminum oxide layer and / or a hafnium oxide layer.

[0059] The first horizontal pattern SCP1 can penetrate the data storage pattern DSP and the vertical pattern VC, and can be connected to the vertical pattern VC. The first horizontal pattern SCP1 can have a sidewall portion adjacent to the fill insulating pattern VI, and a thickness of the sidewall portion can be greater than a thickness of another portion of the first horizontal pattern SCP1 extending in a horizontal direction. The sidewall portion of the first horizontal pattern SCP1 can cover a portion of a sidewall of the second horizontal pattern SCP2.

[0060] The horizontal semiconductor layer 100 can have a recessed region RS adjacent to a top surface thereof. The recessed region RS can be recessed from the top surface of the horizontal semiconductor layer 100. The recessed region RS can have a shape recessed from the top surface of the horizontal semiconductor layer 100 toward a bottom surface of the horizontal semiconductor layer 100. A lower portion of the separation structure SS can be inserted in the horizontal semiconductor layer 100 to fill the recessed region RS.

[0061] The separator SS can vertically penetrate the stacked structure ST and the horizontal structure SC, such as... FIG. 3B As shown. Therefore, each of the electrodes EGE, GGE, CGE, and SGE of the horizontal structure SC and the stacked structure ST can have inner sidewalls facing each other in the first direction D1, with the separating structure SS between these facing inner sidewalls. In some embodiments, the inner sidewalls of each of the electrodes EGE, GGE, CGE, and SGE of the horizontal structure SC and the stacked structure ST can be spaced apart from each other in the first direction D1, as shown. FIG. 3B As shown.

[0062] like FIG. 4A As shown, the first insulating layer ILL can be disposed between the horizontal structure SC and the separating structure SS, and between the horizontal semiconductor layer 100 and the separating structure SS. The first insulating layer ILL can cover the inner sidewall of the horizontal structure SC and the inner surface of the recessed region RS. Additionally, the first insulating layer ILL can be disposed between the insulating layer ILD and the electrodes EGE, GGE, CGE, and SGE of the stacked structure ST, and between the data storage pattern DSP and the electrodes EGE, GGE, CGE, and SGE. The first insulating layer ILL can include, for example, aluminum oxide.

[0063] like FIG. 4A and FIG. 4B As shown, the lowest electrode EGE among electrodes EGE, GGE, CGE, and SGE can have first inner sidewalls sw1 facing each other, with partition structures SS positioned between the first inner sidewalls sw1 facing each other. The second horizontal pattern SCP2 of the horizontal structure SC can have second inner sidewalls sw2 facing each other, with partition structures SS positioned between the second inner sidewalls sw2 facing each other. The first horizontal pattern SCP1 of the horizontal structure SC can have third inner sidewalls sw3 facing each other, with partition structures SS positioned between the third inner sidewalls sw3 facing each other. The first inner sidewalls sw1, second inner sidewalls sw2, and third inner sidewalls sw3 can be located on the cell array region CAR, as shown. FIG. 2 and FIG. 3B As shown.

[0064] The first inner sidewall sw1 of the lowest electrode EGE can be tilted relative to the direction perpendicular to the top surface of the horizontal semiconductor layer 100 (i.e., the third direction D3). The distance between the first inner sidewalls sw1 in the first direction D1 can gradually decrease towards the horizontal structure SC. FIG. 4A As shown, in some embodiments, the distance between the first inner sidewalls sw1 can have a maximum value (e.g., d1) at the same vertical horizontal height as the top surface of the lowermost electrode EGE. FIG. 4BAs shown, in some embodiments, the distance between the first inner sidewalls sw1 can have a minimum value (e.g., d4) at the same vertical level as the bottom surface of the lowermost electrode EGE.

[0065] The second inner sidewalls sw2 of the second horizontal pattern SCP2 can have a concave shape in the first direction D1 and the direction opposite to the first direction D1. In other words, the middle portion of the second inner sidewalls sw2 can be more concave than the upper and lower portions of the second inner sidewalls sw2. As shown, FIG. 4A As shown, in some embodiments, the distance between the second inner sidewalls sw2 can have a maximum value (e.g., d2) at a vertical level lower than the upper surface of the second horizontal pattern SCP2 and higher than the lower surface of the second horizontal pattern SCP2. For example, the distance between the second inner sidewalls sw2 can have a maximum value at the vertical center portion of the second inner sidewalls sw2. In some embodiments, the distance between the second inner sidewalls sw2 can have a maximum value near the center of the second inner sidewalls sw2 in the third direction D3. As shown, FIG. 4B As shown, in some embodiments, the distance between the second inner sidewalls sw2 can have a minimum value (e.g., d5) at the same vertical level as the bottom surface (or top surface) of the second horizontal pattern SCP2.

[0066] The third inner sidewalls sw3 of the first horizontal pattern SCP1 can have a concave shape in the first direction D1 and the direction opposite to the first direction D1. In other words, the middle portion of the third inner sidewalls sw3 can be more concave than the upper and lower portions of the third inner sidewalls sw3. As shown, FIG. 4A As shown, in some embodiments, the distance between the third inner sidewalls sw3 can have a maximum value (e.g., d3) at the vertical center portion of the second inner sidewalls sw2. In some embodiments, the distance between the third inner sidewalls sw3 can have a maximum value near the center of each third inner sidewall sw3 in the third direction D3. As shown, FIG. 4B As shown, in some embodiments, the distance between the third inner sidewalls sw3 can have a minimum value (e.g., d6) at the same vertical level as the bottom surface (or top surface) of the first horizontal pattern SCP1.

[0067] Because the first and second horizontal patterns SCP1 and SCP2 have horizontally concave inner sidewalls, the separation structure SS can have a horizontally convex shape on the second and third inner sidewalls sw2 and sw3.

[0068] The second inner side wall sw2 can be more recessed in the horizontal direction than the first inner side wall sw1 and the third inner side wall sw3. In other words, a maximum distance d2 between the second inner side wall sw2 can be greater than a maximum distance d1 between the first inner side wall sw1 and a maximum distance d3 between the third inner side wall sw3. Since the second inner side wall sw2 is more recessed in the horizontal direction than the third inner side wall sw3, a portion of a top surface of the first horizontal pattern SCP1 can be exposed. In some embodiments, the portion of the top surface of the first horizontal pattern SCP1 can not be covered by the second horizontal pattern SCP2, as shown in FIG. 10A. The first insulating layer ILL can cover the portion of the top surface of the first horizontal pattern SCP1. In some embodiments, the first insulating layer ILL can contact the portion of the top surface of the first horizontal pattern SCP1, as shown in FIG. 10B. FIG. 4A FIG. 4A

[0069] As shown in FIG. 10A, the recessed region RS can have a polygonal shape in a cross-section of the horizontal semiconductor layer 100 taken along the first direction D1. The recessed region RS can have an asymmetric shape in the first direction D1. The recessed region RS can have a bottom surface that is inclined with respect to a top surface of the horizontal semiconductor layer 100. A lower portion of the separation structure SS located in the recessed region RS can have a shape similar to that of the recessed region RS. When viewed in a cross-sectional view taken along the first direction D1, the lower portion of the separation structure SS can have a polygonal shape. The lower portion of the separation structure SS can have an asymmetric shape in the first direction D1. FIG. 4A through FIG. 4E

[0070] The separation structure SS can have a maximum width (e.g., w1) in the first direction D1 at a vertical level lower than a bottom surface of the first horizontal pattern SCP1. In other words, a portion (i.e., a lower portion) of the separation structure SS located in the recessed region RS can have a width greater than another portion of the separation structure SS located outside the recessed region RS in the first direction D1.

[0071] A width w1 of the recessed region RS can be greater than a maximum distance d3 between the third inner side wall sw3, as shown in FIG. 10A. FIG. 4A

[0072] A depth t1 of the recessed region RS can be greater than a thickness t2 of the first horizontal pattern SCP1 and a thickness t3 of the second horizontal pattern SCP2, as shown in FIG. 10A. FIG. 4C

[0073] A portion of a bottom surface bs of the recessed region RS can protrude toward the horizontal structure SC, as shown in FIG. 10A. In other words, the horizontal semiconductor layer 100 can have a protrusion PP protruding toward the horizontal structure SC in the recessed region RS. FIG. 4D ​​​​​​

[0074] The separation structure SS can have portions that vertically overlap the electrodes EGE, GGE, CGE, and SGE of the stack structure ST, as shown. For example, a bottom end SSb of the separation structure SS can vertically overlap the electrodes EGE, GGE, CGE, and SGE of the stack structure ST. As used herein, “overlapping with element A in a vertical direction with element B” (or similar language) means that there is at least one vertical line that intersects both element A and element B. FIG. 4E

[0075] Referring again to FIG. 4A through FIG. 4E An interface layer IPL can be provided to partially surround the first horizontal pattern SCP1. The interface layer IPL can be disposed between the first horizontal pattern SCP1 and the second horizontal pattern SCP2 and between the first horizontal pattern SCP1 and the horizontal semiconductor layer 100. Additionally, the interface layer IPL can be disposed between the data storage pattern DSP and the second semiconductor pattern 100 and between the vertical pattern VC and the first horizontal pattern SCP1. The interface layer IPL can not cover the third inner sidewall sw3. The interface layer IPL can include, for example, an electrically conductive material. The interface layer IPL can include, for example, carbon (C). The interface layer IPL can also include, for example, nitrogen (N) and oxygen (O).

[0076] Referring to FIG. 5A In some embodiments, a top surface SCP1t of the first horizontal pattern SCP1 can protrude toward the separation structure SS beyond one of the second inner sidewalls sw2 of the second horizontal pattern SCP2, such that the second horizontal pattern SCP2 can not vertically overlap a first portion of the top surface SCP1t of the first horizontal pattern SCP1, as shown. The first insulating layer ILL can cover the first portion of the top surface SCP1t of the first horizontal pattern SCP1, and the interface layer IPL can cover a second portion of the top surface SCP1t of the first horizontal pattern SCP1. In some embodiments, the first insulating layer ILL can contact the first portion of the top surface SCP1t of the first horizontal pattern SCP1, and the interface layer IPL can contact the second portion of the top surface SCP1t of the first horizontal pattern SCP1, as shown. FIG. 5A FIG. 5A

[0077] In some embodiments, a bottom surface SCP1b of the first horizontal pattern SCP1 can protrude toward the separation structure SS beyond a sidewall of the recessed region RS, as shown. FIG. 5A ​​​The interface layer IPL can cover a first portion of the bottom surface SCP1b of the first horizontal pattern SCP1, and the first insulating layer ILL can cover a second portion of the bottom surface SCP1b of the first horizontal pattern SCP1. In some embodiments, the interface layer IPL can contact the first portion of the bottom surface SCP1b of the first horizontal pattern SCP1, and the first insulating layer ILL can contact the second portion of the bottom surface SCP1b of the first horizontal pattern SCP1, as shown in FIG. 1C-1. FIG. 5A In some embodiments, the first insulating layer ILL can be in direct contact with the top surface SCP1t and the inner sidewall of the first horizontal pattern SCP1.

[0078] Referring to FIG. 5B , a second insulating layer ILI can be disposed between the first insulating layer ILL and the horizontal semiconductor layer 100, and between the first insulating layer ILL and the horizontal structure SC. The second insulating layer ILI can be in direct contact with the inner surface of the recessed region RS of the horizontal semiconductor layer 100 and the inner sidewall of the horizontal structure SC. The second insulating layer ILI can include, for example, at least one of silicon oxide or silicon nitride.

[0079] Referring again to FIG. 2 through FIG. 3C , a first interlayer insulating layer 121 can be disposed on the stack structure ST and the upper planarization insulating layer 150, and a second interlayer insulating layer 123 can be disposed on the first interlayer insulating layer 121. The separation structure SS can penetrate the first interlayer insulating layer 121. The second interlayer insulating layer 123 can cover a top surface of the separation structure SS. The bit line BL can be disposed on the second interlayer insulating layer 123. The bit line BL can extend in the first direction D1. The bit line BL can be electrically connected to the bit line conductive pad PAD through the bit line contact plug BPLG.

[0080] FIG. 6 is a magnified cross-sectional view corresponding to a portion "AA" of FIG. 3B to illustrate a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0081] Referring to FIG. 6 , the first horizontal pattern SCP1 can penetrate the data storage pattern DSP, thereby connecting to the sidewall of the vertical pattern VC. Unlike FIG. 4A through FIG. 4E , the first horizontal pattern SCP1 can not penetrate the vertical pattern VC.

[0082] FIG. 7A is a cross-sectional view taken along line B-B' of FIG. 2 to illustrate a 3D semiconductor memory device according to some embodiments of the inventive concepts. FIG. 7B is a magnified cross-sectional view of a portion "CC" of FIG. 7A .

[0083] Referring toFIG. 7A and FIG. 7B The separation structure SS can include a common source plug CSP and a sidewall spacer SL. The common source plug CSP can be connected to a common source region CSR formed in the horizontal semiconductor layer 100 between the stack structures ST. The common source plug CSP can be electrically connected to the horizontal structure SC. For example, the common source plug CSP can include at least one of a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). In some embodiments, the common source plug CSP can have a substantially uniform upper width, and can extend in the second direction D2. The sidewall spacer SL formed of an insulating material can be disposed between the common source plug CSP and the stack structures ST. The common source region CSR can include N-type dopants, and can extend parallel to the stack structures ST in the second direction D2. In some embodiments, the common source region CSR can be omitted.

[0084] FIG. 8 is a cross-sectional view taken along the line D-D' of FIG. 2 to illustrate a 3D semiconductor memory device according to some embodiments of the inventive concepts. FIG. 9 shows an enlarged cross-sectional view of portions "DD" and "EE" of FIG. 8 In the following, descriptions of components identical or similar to those mentioned with reference to FIG. 1 through FIG. 7B may be omitted for the purpose of convenience and ease of explanation.

[0085] With reference to FIG. 8 and FIG. 9 A first separation structure SS1 can be disposed on one sidewall of the stack structure ST, and a second separation structure SS2 can be disposed on another sidewall of the stack structure ST. The first separation structure SS1 and the second separation structure SS2 can be two of the plurality of separation structures SS adjacent to each other in the first direction D1. In some embodiments, as shown in FIG. 8 no separation structure is disposed between the first separation structure SS1 and the second separation structure SS2.

[0086] The first separation structure SS1 and the second separation structure SS2 can have different lengths in the vertical direction (i.e., the third direction D3). The first separation structure SS1 can fill the first recessed region RS1 of the horizontal semiconductor layer 100, and the second separation structure SS2 can fill the second recessed region RS2 of the horizontal semiconductor layer 100. A depth t4 of the first recessed region RS1 can be different from a depth t5 of the second recessed region RS2. In some embodiments, the depth t5 of the second recessed region RS2 can be greater than the depth t4 of the first recessed region RS1, and thus, a length of the second separation structure SS2 in the vertical direction can be greater than a length of the first separation structure SS1 in the vertical direction.

[0087] A width w3 of the second recessed region RS2 can be greater than a width w2 of the first recessed region RS1. Thus, a width of a lower portion of the second separation structure SS2 can be greater than a width of a lower portion of the first separation structure SS1.

[0088] FIG. 10 is a top view showing a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 11 is a cross-sectional view taken along the line E-E' of FIG. 10 to show a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 12 shows an enlarged cross-sectional view of the portions "FF" and "GG" of FIG. 11 may be omitted below for the sake of convenience and ease of explanation. FIG. 1 through FIG. 9 components referred to in connection with the components.

[0089] Referring to FIG. 10 through FIG. 12 A 3D semiconductor memory device according to some embodiments of the inventive concept can include a through-hole interconnection structure THV.

[0090] The through-hole interconnection structure THV can penetrate a portion of the stack structure ST and a portion of the horizontal semiconductor layer 100. In some embodiments, the through-hole interconnection structure THV can penetrate a portion of the stack structure ST that is spaced apart from the stepped structure of the stack structure ST. In other words, the through-hole interconnection structure THV can be disposed on the cell array region CAR. The through-hole interconnection structure THV can be adjacent to one of the separation structures SS in the first direction D1. Some vertical structures VS can be disposed between the through-hole interconnection structure THV and the one of the separation structures SS. The some vertical structures VS can be vertical structures VS that do not constitute a vertical stack structure VS. FIG. 1dummy vertical structure of a cell string CSTR. The through interconnect structure THV can include a through insulating pattern 200, a through plug PPLG penetrating the through insulating pattern 200, and a wire DL connected to the through plug PPLG. The through plug PPLG can penetrate the through insulating pattern 200, thereby connecting to a peripheral circuit interconnect line 33 of the peripheral logic structure PS.

[0091] A vertical length of the second separation structure SS2 closest to the through interconnect structure THV can be greater than a vertical length of the first separation structure SS1, as shown in FIG. 11 and FIG. 12 More specifically, a depth t5 of a second recessed region RS2 filled with the second separation structure SS2 can be greater than a depth t4 of a first recessed region RS1 filled with the first separation structure SS1. Here, a width w3 of the second recessed region RS2 can be greater than a width w2 of the first recessed region RS1.

[0092] [Manufacturing method]

[0093] FIG. 13A , FIG. 14A , FIG. 15A , FIG. 16A , FIG. 17A and FIG. 20A are cross-sectional views taken along line B-B' of FIG. 2 to illustrate a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 13B and FIG. 14B are cross-sectional views taken along line A-A' of FIG. 2 to illustrate a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept. FIG. 15B is an enlarged view of a portion AAA of FIG. 15A , FIG. 16B and FIG. 16C are enlarged views of a portion AAA of FIG. 16A , FIG. 17B , FIG. 18 and FIG. 19 are enlarged views of a portion AAA of FIG. 17A , FIG. 20B and FIG. 20C are enlarged views of a portion "AAA" of FIG. 20A to illustrate a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0094] Referring to FIG. 13A and FIG. 13B , a peripheral logic structure PS can be formed on a lower substrate 10. The lower substrate 10 can be, for example, a bulk silicon substrate. A device isolation layer 13 can be formed in the lower substrate 10 to define an active region.

[0095] The formation of the peripheral logic structure PS can include forming the peripheral logic circuit PTR on the lower substrate 10, forming the peripheral interconnect structures 31 and 33 connected to the peripheral logic circuit PTR, and forming the lower insulating layer 50. Here, the peripheral logic circuit PTR can include MOS transistors using a portion of the lower substrate 10 as a channel. For example, the formation of the peripheral logic circuit PTR can include forming a device isolation layer 13 defining an active region in the lower substrate 10, forming a peripheral gate insulating layer and a peripheral gate electrode sequentially stacked on the lower substrate 10, and forming source / drain regions by adding (e.g., implanting) dopants into the lower substrate 10 on both sides of the peripheral gate electrode. A peripheral gate spacer can be formed on both sidewalls of the peripheral gate electrode.

[0096] The lower insulating layer 50 can include a single insulating layer or a plurality of stacked insulating layers covering the peripheral logic circuit PTR. For example, the lower insulating layer 50 can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a low-k dielectric layer.

[0097] The formation of the peripheral interconnect structures 31 and 33 can include forming a peripheral contact plug 31 penetrating a portion of the lower insulating layer 50 and forming a peripheral circuit interconnect line 33 connected to the peripheral contact plug 31.

[0098] The horizontal semiconductor layer 100 can be formed by depositing a semiconductor material on the lower insulating layer 50. For example, the horizontal semiconductor layer 100 can include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). The horizontal semiconductor layer 100 can include a semiconductor material doped with a dopant and / or an intrinsic semiconductor material not doped with a dopant. The horizontal semiconductor layer 100 can have a crystal structure including at least one of a single crystal structure, an amorphous structure, or a polycrystalline structure.

[0099] A first buffer insulating layer 17 can be formed on the horizontal semiconductor layer 100, and a lower sacrificial layer LSL can be formed on the first buffer insulating layer 17. The first buffer insulating layer 17 can be formed by thermally oxidizing a surface of the horizontal semiconductor layer 100, or can be formed by depositing a silicon oxide layer.

[0100] The lower sacrificial layer LSL can be formed of a material having etch selectivity with respect to the first buffer insulating layer 17. For example, the lower sacrificial layer LSL can be formed of at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, or a silicon germanium layer. The formation of the lower sacrificial layer LSL can include depositing a lower sacrificial layer on the entire top surface of the horizontal semiconductor layer 100, forming a first mask pattern (not shown) exposing a portion of the deposited lower sacrificial layer, and etching the deposited lower sacrificial layer using the first mask pattern as an etch mask to expose the first buffer insulating layer 17 or the horizontal semiconductor layer 100. Accordingly, an opening can be formed in the lower sacrificial layer LSL disposed on the connection region CNR.

[0101] A second buffer insulating layer 19 and a second horizontal pattern SCP2 of uniform thickness can be sequentially deposited on the lower sacrificial layer LSL. The second buffer insulating layer 19 and the second horizontal pattern SCP2 can also be formed in the opening of the lower sacrificial layer LSL. In some embodiments, the second buffer insulating layer 19 can be omitted, and the second horizontal pattern SCP2 can be directly deposited on the lower sacrificial layer LSL. For example, the second buffer insulating layer 19 can be a silicon oxide layer, and the second horizontal pattern SCP2 can be a polysilicon layer doped with an N-type dopant and / or carbon (C).

[0102] Referring to FIG. 14A and FIG. 14B An insulating layer ILD and an upper sacrificial layer USL can be vertically and alternately stacked on the second horizontal pattern SCP2, thereby forming a molding structure ML. In the molding structure ML, the upper sacrificial layer USL can be formed of a material having etch selectivity with respect to the insulating layer ILD. For example, the upper sacrificial layer USL can be formed of an insulating material different from the insulating material of the insulating layer ILD. The upper sacrificial layer USL can be formed of the same material as the lower sacrificial layer LSL. For example, each upper sacrificial layer USL can be formed of a silicon nitride layer, and each insulating layer ILD can be formed of a silicon oxide layer. The thicknesses of the upper sacrificial layers USL can be substantially equal to each other, and the thickness of at least one of the insulating layers ILD can be different from the thicknesses of the other insulating layer(s) of the insulating layers ILD.

[0103] Referring to FIG. 15A and FIG. 15B A vertical structure VS penetrating the molding structure ML can be formed.

[0104] The formation of the vertical structure VS can include forming vertical holes that penetrate the mold structure ML and forming data storage layers and vertical patterns VC that are sequentially stacked on inner surfaces of each vertical hole. The data storage layers can include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BLK. The sum of the thicknesses of the data storage layers and the vertical patterns VC on the inner sidewalls of the vertical holes can be less than about half of the upper width of the vertical holes. In other words, the data storage layers and the vertical patterns VC can define an empty space in each vertical hole, and the empty space can be filled with a fill insulating pattern VI.

[0105] Subsequently, a bit line conductive pad PAD can be formed on a top end of each vertical pattern VC. The bit line conductive pad PAD can be a doped region doped with a dopant, or can be formed of a conductive material. A bottom surface of the bit line conductive pad PAD can be located at a level higher than a top surface of the uppermost sacrificial layer among the upper sacrificial layers USL. After the bit line conductive pad PAD is formed, a first interlayer insulating layer 121 can be formed on the mold structure ML to cover the bit line conductive pad PAD.

[0106] Next, a trench can be formed to penetrate the first interlayer insulating layer 121 and the mold structure ML, and a preliminary sacrificial spacer layer 130p can be formed in the trench.

[0107] The formation of the trench can include forming a mask pattern (not shown) that defines planar positions of the trench on the first interlayer insulating layer 121 and etching (e.g., anisotropically etching) the first interlayer insulating layer 121 and the mold structure ML using the mask pattern as an etching mask. The sidewalls of the upper sacrificial layers USL and the sidewalls of the insulating layers ILD can be exposed by the trench. In the anisotropic etching process for forming the trench, the second buffer insulating layer 19 can serve as an etching stop layer, and the second horizontal pattern SCP2 can also be etched. The trench can expose a portion of the second buffer insulating layer 19.

[0108] Subsequently, the preliminary sacrificial spacer layer 130p can be formed on the inner surfaces of the trench. The initial sacrificial spacer layer 130p can conformally cover the sidewalls and the bottom surface of the trench. In other words, the preliminary sacrificial spacer layer 130p can cover the sidewalls of the upper sacrificial layers USL, the sidewalls of the insulating layers ILD, the sidewalls of the second horizontal pattern SCP2, and the top surface of the second buffer insulating layer 19 that are exposed by the trench. In some embodiments, the preliminary sacrificial spacer layer 130p can have a uniform thickness along the sidewalls and the bottom surface of the trench, as shown in FIG. 13B. FIG. 15A The initial sacrificial spacer layer 130p can be formed of a material that has etching selectivity with respect to the mold structure ML and the lower sacrificial layers LSL. For example, the preliminary sacrificial spacer layer 130p can be formed of a polysilicon layer.

[0109] Referring toFIG. 16A and FIG. 16B An etching process (e.g., an anisotropic etching process) can be performed on the preliminary sacrificial spacer layer 130p to form a sacrificial spacer layer 130 covering sidewalls of each trench. In the anisotropic etching process for forming the sacrificial spacer layer 130, the second buffer insulating layer 19 under the trench can be etched. Accordingly, the lower sacrificial layer LSL can be exposed. At this time, a portion of the horizontal semiconductor layer 100 can be exposed in the opening of the lower sacrificial layer LSL.

[0110] An etching process (e.g., an isotropic etching process) can be performed on the exposed lower sacrificial layer LSL to form a horizontal recessed region exposing a portion of the data storage layer. The horizontal recessed region can be formed during the isotropic etching process using an etching recipe having etching selectivity with respect to the sacrificial spacer layer 130, the first and second buffer insulating layers 17 and 19, and the data storage layer. When the lower sacrificial layer LSL includes a silicon nitride layer or a silicon oxynitride layer, the isotropic etching process can be performed on the lower sacrificial layer LSL using an etching solution including phosphoric acid.

[0111] The horizontal recessed region can horizontally extend from the trench to between the second horizontal pattern SCP2 and the horizontal semiconductor layer 100, and can be an empty space between the second horizontal pattern SCP2 and the horizontal semiconductor layer 100. The horizontal recessed region can expose a portion of the data storage layer located between the second horizontal pattern SCP2 and the horizontal semiconductor layer 100. When the horizontal recessed region is formed, a portion of the second horizontal pattern SCP2 located in the opening of the lower sacrificial layer LSL can serve as a support for the support mold structure ML so that the mold structure ML does not collapse.

[0112] The portion of the data storage layer exposed by the horizontal recessed region can be isotropically etched to form an undercut region exposing a portion of the vertical pattern VC. The undercut region can be an empty space extending perpendicularly from the horizontal recessed region, and can be defined between the vertical pattern VC and the sidewall of the second horizontal pattern SCP2.

[0113] As the isotropic etching process is performed on the data storage layer, the data storage layer can be divided into data storage patterns and dummy data storage patterns vertically spaced apart from each other. The isotropic etching process performed on the data storage layer can use an etching recipe having etching selectivity with respect to the horizontal semiconductor layer 100, the second horizontal pattern SCP2, the vertical pattern VC, and the sacrificial spacer layer 130.

[0114] The isotropic etching of the data storage layer can include sequentially and isotropically etching the blocking insulating layer BLK, the charge storage layer CIL, and the tunnel insulating layer TIL exposed by the horizontal recessed region. In more detail, the isotropic etching process for forming the undercut region can include a first etching process for etching a portion of the blocking insulating layer BLK, a second etching process for etching a portion of the charge storage layer CIL, and a third etching process for etching a portion of the tunnel insulating layer TIL. The first etching process, the second etching process, and the third etching process can be performed sequentially. For example, the first etching process and the third etching process can use an etching solution including hydrofluoric acid or sulfuric acid, and the second etching process can use an etching solution including phosphoric acid. The first buffer insulating layer 17 and the second buffer insulating layer 19 can be removed in the isotropic etching process of the data storage layer. Next, the exposed portion of the vertical pattern VC can be removed to expose a portion of the fill insulating pattern VI in the horizontal recessed region. In some embodiments, the process for removing the exposed portion of the vertical pattern VC can be omitted. Subsequently, the interface layer IPL can be formed on the inner surfaces of the horizontal recessed region and the undercut region, as shown in FIG. 1C-2. Next, the sacrificial spacer layer 130 on the sidewalls of the trench can be removed. FIG. 16C

[0115] Referring to FIG. 17A and FIG. 17B , a preliminary horizontal pattern SCP1p can be formed in the undercut region, the horizontal recessed region, and the trench. The preliminary horizontal pattern SCP1p can be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The preliminary horizontal pattern SCP1p can be, for example, a semiconductor layer doped with a dopant (e.g., an N-type dopant).

[0116] The preliminary horizontal pattern SCP1p can cover the inner surfaces of the undercut region, the horizontal recessed region, and the trench by the deposition process. The preliminary horizontal pattern SCP1p can not completely fill the trench, and can define a gap region in the trench. The preliminary horizontal pattern SCP1p can be connected to the portion of the vertical pattern VC located under the second horizontal pattern SCP2 by the interface layer IPL.

[0117] In more detail, a semiconductor source gas can be supplied into the undercut region, the horizontal recessed region, and the trench in the deposition process for forming the preliminary horizontal pattern SCP1p, so that a semiconductor material can be deposited on the inner surfaces of the undercut region, the horizontal recessed region, and the trench.

[0118] ​When forming the preliminary horizontal pattern SCP1p, the deposition rate of the semiconductor material can vary depending on the characteristics of the surface exposed by the horizontally recessed regions. In other words, the deposition rate of the semiconductor material on the top surface of the horizontal semiconductor layer 100 can be different from the deposition rate of the semiconductor material on the bottom surface of the second horizontal pattern SCP2. Additionally, when forming the preliminary horizontal pattern SCP1p, the crystal structure of the semiconductor material can be determined depending on the crystal structure of the surface exposed by the horizontally recessed regions. In some embodiments, the thickness of the semiconductor material deposited on the top surface of the horizontal semiconductor layer 100 can be less than the thickness of the semiconductor material deposited on the bottom surface of the second horizontal pattern SCP2. In some embodiments, the thickness of the semiconductor material deposited on the top surface of the horizontal semiconductor layer 100 can be substantially equal to the thickness of the semiconductor material deposited on the bottom surface of the second horizontal pattern SCP2.

[0119] Referring to FIG. 18 and FIG. 19 , an etching process can be performed on the preliminary horizontal pattern SCP1p and the horizontal semiconductor layer 100. Accordingly, the first horizontal pattern SCP1 and the recessed regions RS can be formed. The etching process on the preliminary horizontal pattern SCP1p and the horizontal semiconductor layer 100 can be performed using an etching recipe including ADM (ammonia deionized mixture). The etching process on the preliminary horizontal pattern SCP1p and the horizontal semiconductor layer 100 can use ADM as an etchant.

[0120] Referring to FIG. 20A and FIG. 20B , an etching process for removing the upper sacrificial layer USL can be performed. Next, as shown in FIG. 20C , a first insulating layer ILL can be conformally formed in the space formed by removing the upper sacrificial layer USL. In some embodiments, the first insulating layer ILL can have a uniform thickness, as shown in FIG. 20C .

[0121] Referring again to FIG. 3A and FIG. 3B , the above-described stack structure ST can be formed by performing a process for forming the electrodes EGE, GGE, CGE, and SGE in the space formed by removing the upper sacrificial layer USL.

[0122] After forming the stack structure ST, a separation structure SS can be formed in the trench and the recessed regions RS. In some embodiments, the separation structure SS can include a common source plug CSP and a sidewall spacer SL, as shown in FIG. 7A and FIG. 7BAs shown. In this case, the formation of the sidewall spacers SL may include depositing a spacer layer of uniform thickness on a horizontal semiconductor layer 100 on which a stacked structure ST is formed, and performing an etch-back process on the spacer layer to expose the horizontal semiconductor layer 100. Subsequently, a conductive layer may be deposited to fill the trenches and recessed regions RS with the sidewall spacers SL, and then the deposited conductive layer may be planarized until the top surface of the first interlayer insulating layer 121 is exposed, thereby forming a common source plug CSP. The common source plug CSP may be connected to the horizontal semiconductor layer 100.

[0123] Subsequently, a second interlayer insulating layer 123 can be formed on the first interlayer insulating layer 121 to cover the top surface of the separating structure SS. A bit line contact plug BPLG can be formed to penetrate the second interlayer insulating layer 123 and the first interlayer insulating layer 121. The bit line contact plug BPLG can be connected to the bit line conductive pad PAD. The aforementioned bit line BL can be formed on the second interlayer insulating layer 123.

[0124] According to some embodiments of the present invention, the operating characteristics and reliability of 3D semiconductor memory devices can be improved, and 3D semiconductor memory devices can be easily manufactured.

[0125] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope of the inventive concept. Therefore, it should be understood that the embodiments described herein are not restrictive but illustrative. Consequently, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the foregoing description.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A horizontal structure located on the upper surface of a substrate, the horizontal structure comprising a first horizontal pattern and a second horizontal pattern sequentially stacked in a vertical direction on the upper surface of the substrate; A stacked structure comprising a plurality of electrodes stacked on a horizontal structure in the vertical direction; A vertical pattern that extends through the plurality of electrodes and connects to the first horizontal pattern; and A separating structure that intersects with the stacked structure and the horizontal structure and protrudes into the upper surface of the substrate. The lowermost electrode among the plurality of electrodes includes first inner sidewalls facing each other and spaced apart in a first direction, with a partition structure between the first inner sidewalls; and the second horizontal pattern includes second inner sidewalls facing each other and spaced apart in the first direction, with a partition structure between the second inner sidewalls. Wherein, the maximum distance between the first inner sidewalls in the first direction is less than the maximum distance between the second inner sidewalls in the first direction.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The vertical pattern includes a plurality of vertical patterns, and the separating structure is located between a first vertical pattern and a second vertical pattern among the plurality of vertical patterns and extends longitudinally in a second direction parallel to the upper surface of the substrate.

3. The three-dimensional semiconductor memory device according to claim 1, wherein, The first horizontal pattern includes third inner sidewalls facing each other and spaced apart from each other in the first direction, the separating structure being between the third inner sidewalls, and the maximum distance between the third inner sidewalls in the first direction being less than the maximum distance between the second inner sidewalls in the first direction.

4. The three-dimensional semiconductor memory device according to claim 1, wherein, The first horizontal pattern includes third inner sidewalls facing each other and spaced apart from each other in the first direction, and the separating structure is located between the third inner sidewalls. Wherein, the maximum width of the partition structure in the first direction is greater than the maximum distance between the third inner sidewalls in the first direction.

5. The three-dimensional semiconductor memory device according to claim 1, wherein, The dividing structure has its maximum width in the first direction at a horizontal height below the lower surface of the first horizontal pattern in the vertical direction.

6. The three-dimensional semiconductor memory device according to claim 1, further comprising: An insulating layer extends between the partition structure and one of the second inner sidewalls of the second horizontal pattern, wherein the insulating layer covers a portion of the upper surface of the first horizontal pattern.

7. The three-dimensional semiconductor memory device according to claim 1, wherein, The substrate includes a recess, and a portion of the partition structure is located within the recess. Wherein, the depth of the recess in the vertical direction is greater than the thickness of the first horizontal pattern in the vertical direction.

8. The three-dimensional semiconductor memory device according to claim 1, wherein, The first horizontal pattern includes an upper surface, the upper surface including a first portion and a second portion facing the second horizontal pattern, the second portion protruding toward the dividing structure beyond one of the second inner sidewalls of the second horizontal pattern, such that the second horizontal pattern does not overlap with the second portion of the upper surface of the first horizontal pattern in the vertical direction.

9. The three-dimensional semiconductor memory device according to claim 8, further comprising an interface layer located between the first horizontal pattern and the second horizontal pattern. in, The interface layer comprises carbon or a conductive material, and Wherein, the interface layer does not overlap with the second portion of the upper surface of the first horizontal pattern in the vertical direction.

10. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A substrate, wherein the upper surface of the substrate includes a recess; A stacked structure comprising a plurality of electrodes stacked in a vertical direction on the upper surface of the substrate; A horizontal structure located between the stacked structure and the substrate, the horizontal structure comprising a first horizontal pattern and a second horizontal pattern sequentially stacked on the upper surface of the substrate in the vertical direction; and A separating structure intersects the stacked structure and the horizontal structure in a first direction parallel to the upper surface of the substrate, a portion of the separating structure being located within the recess of the substrate. The first horizontal pattern includes first inner sidewalls facing each other and spaced apart from each other in a second direction perpendicular to the first direction, and the separating structure is located between the first inner sidewalls; Wherein, the maximum width of the recess in the second direction is greater than the maximum distance between the first inner sidewalls in the second direction.

11. The three-dimensional semiconductor memory device according to claim 10, further comprising: Multiple vertical patterns extend through the multiple electrodes and connect to the first horizontal pattern. The separating structure is located between the first vertical pattern and the second vertical pattern among the plurality of vertical patterns.

12. The three-dimensional semiconductor memory device according to claim 10, wherein, The portion of the partition structure located in the recess overlaps with the lowermost electrode of the plurality of electrodes in the vertical direction.

13. The three-dimensional semiconductor memory device according to claim 10, wherein, The second horizontal pattern includes second inner sidewalls facing each other and spaced apart from each other in the second direction, the separating structure being located between the second inner sidewalls, and Wherein, the maximum distance between the second inner sidewalls in the second direction is greater than the maximum distance between the first inner sidewalls in the second direction.

14. The three-dimensional semiconductor memory device according to claim 10, further comprising: An interface layer that extends between the first horizontal pattern and the second horizontal pattern and includes carbon.

15. The three-dimensional semiconductor memory device according to claim 10, wherein, The first horizontal pattern includes a lower surface, the lower surface including a first portion facing the substrate and a second portion protruding beyond the recessed sidewall toward the partition structure.

16. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: Peripheral logic circuitry, wherein the peripheral logic circuitry is located on the lower substrate; A lower insulating layer, the lower insulating layer being located on the peripheral logic circuit; A substrate, the substrate being located on the lower insulating layer, the upper surface of the substrate including a recess; A stacked structure comprising a plurality of electrodes vertically stacked on the upper surface of the substrate; A horizontal structure located between the stacked structure and the substrate, the horizontal structure comprising a first horizontal pattern and a second horizontal pattern sequentially stacked on the upper surface of the substrate; A vertical pattern that extends through the plurality of electrodes and connects to the first horizontal pattern; A partition structure intersects the stacked structure and the horizontal structure in a first direction parallel to the upper surface of the substrate, and a portion of the partition structure is located in the recess of the substrate; An interface layer is located between the first horizontal pattern and the second horizontal pattern; and A first insulating layer is located between the substrate and the portion of the partition structure located in the recess of the substrate. The interface layer extends on a first portion of the upper surface of the first horizontal pattern, and the first insulating layer extends on a second portion of the upper surface of the first horizontal pattern.

17. The three-dimensional semiconductor memory device according to claim 16, wherein, The interface layer extends on a first portion of the lower surface of the first horizontal pattern, and the first insulating layer extends on a second portion of the lower surface of the first horizontal pattern.

18. The three-dimensional semiconductor memory device according to claim 16, wherein, The first horizontal pattern includes first inner sidewalls facing each other, and the separating structure is located between the first inner sidewalls. The interface layer is in direct contact with the first insulating layer.

19. The three-dimensional semiconductor memory device according to claim 16, wherein, The first horizontal pattern includes first inner sidewalls facing each other, and the separating structure is located between the first inner sidewalls. The interface layer does not cover the first inner sidewall.

20. The three-dimensional semiconductor memory device according to claim 16, further comprising: A through-interconnect structure, the through-interconnect structure including a through-insulation pattern extending vertically through the stacked structure and through-plugs extending vertically through the through-insulation pattern to connect to the peripheral logic circuitry.

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