Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, comprising: a substrate, the substrate comprising a plurality of first regions and a second region, the second region being located between adjacent first regions; a plurality of gate structures located on the first region of the substrate; a dielectric layer located on the substrate, the gate structure being located within the dielectric layer; a first opening located on the second region of the substrate, the first opening extending from the dielectric layer to the substrate; a transition layer located on the bottom surface and part of the sidewall surface of the first opening, the top surface of the transition layer being lower than the top plane of the dielectric layer; and an anti-diffusion layer located on the top of the transition layer, the anti-diffusion layer sealing the first opening into a closed cavity. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase their speed. At present, due to the demand for high device density, high performance and low cost, the semiconductor industry has advanced to the nanotechnology process node, and the preparation of semiconductor devices is restricted by various physical limits.

[0003] As the size of CMOS devices continues to shrink, challenges from manufacturing and design have prompted the development of three-dimensional designs such as fin field-effect transistors (FinFETs). Compared with existing planar transistors, FinFETs are advanced semiconductor devices used in 20nm and below process nodes. They can effectively control the short channel effect that is difficult to overcome due to device scaling down, and can also effectively increase the density of transistor arrays formed on the substrate. At the same time, the gate in FinFET is set around the fin (fin-shaped channel), so it can control static electricity from three sides, and its performance in static electricity control is also more outstanding.

[0004] In order to further improve the density of devices in the FinFET process, many single diffusion breaks (SDBs) can be designed to form more and narrower shallow trench isolations to save the area of ​​the gate array.

[0005] However, the existing process and performance of designing a single diffusion region cut to form shallow trench isolation still need to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, which can improve the performance of the semiconductor structure.

[0007] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a plurality of first regions and a second region, the second region being located between adjacent first regions; a plurality of gate structures located on the first region of the substrate; a dielectric layer located on the substrate, the gate structure being located within the dielectric layer; a first opening located on the second region of the substrate, the first opening extending from the dielectric layer to the substrate; a transition layer located on the bottom surface and part of the sidewall surface of the first opening, the top surface of the transition layer being lower than the top plane of the dielectric layer; and an anti-diffusion layer located on the top of the transition layer, the anti-diffusion layer sealing the first opening into a closed cavity.

[0008] Optionally, the aspect ratio of the first opening is in the range of 4-10.

[0009] Optionally, the substrate includes a base and a fin structure located on the base; the gate structure spans the fin structure; and the bottom of the first opening is lower than or flush with a bottom plane of the fin structure.

[0010] Optionally, the anti-diffusion layer is also located on the side wall surface of the first opening.

[0011] Optionally, it also includes: a blocking layer located on the top surface of the gate structure in the first region.

[0012] Optionally, the material of the barrier layer is different from the material of the dielectric layer.

[0013] Optionally, the material of the barrier layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon and silicon oxycarbide.

[0014] Optionally, the material of the anti-diffusion layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon and silicon oxycarbide.

[0015] Optionally, the material of the transition layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride carbon and silicon oxycarbide.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of first regions and a second region, the second region being located between adjacent first regions; forming a plurality of initial gate structures on the first region and the second region; forming a dielectric layer on the substrate, the initial gate structure being located within the dielectric layer, the dielectric layer exposing the surface of the initial gate structure; removing the initial gate structure on the second region, forming a first opening on the second region of the substrate, the first opening extending from the dielectric layer to the substrate; forming a transition layer on the bottom surface and a portion of the side wall surface of the first opening, the top surface of the transition layer being lower than the top plane of the dielectric layer; after forming the transition layer, forming an anti-diffusion layer on the top of the transition layer, the anti-diffusion layer sealing the first opening into a closed cavity.

[0017] Optionally, the substrate includes a base and a fin structure located on the base; the initial gate structure spans the fin structure; and the bottom of the first opening is lower than or flush with a bottom plane of the fin structure.

[0018] Optionally, the initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the gate dielectric layer material is less than or equal to 3.9, and the material of the gate dielectric layer includes silicon oxide; and the material of the gate layer includes polysilicon.

[0019] Optionally, the initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the gate dielectric layer material is greater than 3.9, and the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes metal, and the metal includes tungsten.

[0020] Optionally, the method for forming the initial gate structure includes: forming a dummy gate structure on a substrate; forming a dielectric layer on the substrate, wherein the dummy gate structure is located within the dielectric layer; removing the dummy gate structure to form a gate opening within the dielectric layer; and forming the initial gate structure within the gate opening.

[0021] Optionally, the method for forming the dielectric layer includes: forming a dielectric material layer on a substrate; planarizing the dielectric material layer until the top surface of the pseudo gate structure is exposed to form the dielectric layer, wherein the surface of the dielectric layer has a first groove.

[0022] Optionally, the method for forming the first opening includes: forming a mask structure on the surface of the substrate, the mask structure exposing the surface of the initial gate structure on the second region; etching the initial gate structure and the substrate using the mask structure as a mask to form a first opening on the second region of the substrate.

[0023] Optionally, before forming the mask structure, it also includes: etching back the initial gate structure to form a gate structure on the first area and the second area, and forming a second opening in the dielectric layer on the top of the gate structure; forming an initial barrier layer in the second opening and on the surface of the dielectric layer, the surface of the initial barrier layer on the dielectric layer having a second groove; the mask structure exposes the surface of the initial barrier layer on the second area.

[0024] Optionally, before forming the mask structure on the surface of the initial barrier layer, the method further includes: forming a sacrificial structure on the surface of the initial barrier layer, wherein the mask structure is located on the surface of the sacrificial structure.

[0025] Optionally, the sacrificial structure includes a first sacrificial layer, and the first sacrificial layer is located in the second groove.

[0026] Optionally, the sacrificial structure further includes a second sacrificial layer located on the surfaces of the first sacrificial layer and the initial barrier layer.

[0027] Optionally, the method for forming the first sacrificial layer includes: forming a first sacrificial material layer on the surface of the initial barrier layer; planarizing the first sacrificial material layer until the surface of the initial barrier layer is exposed, and forming the first sacrificial layer in the second groove.

[0028] Optionally, the material of the sacrificial structure is different from the material of the initial barrier layer.

[0029] Optionally, the material of the initial barrier layer is different from the material of the dielectric layer.

[0030] Optionally, the material of the initial blocking layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon and silicon oxycarbide.

[0031] Optionally, the mask structure includes an initial hard mask layer; a liner layer located on the initial hard mask layer; and a photoresist layer located on the liner layer, wherein the photoresist layer exposes a surface of the liner layer on the second region.

[0032] Optionally, the method for forming the transition layer includes: forming an initial transition layer on the inner wall surface of the first opening and the surface of the sacrificial structure; after forming the initial transition layer, forming a protective layer in the first opening, the top surface of the protective layer is lower than the top surface of the dielectric layer, and the protective layer exposes a portion of the side wall surface of the initial transition layer; removing the portion of the initial transition layer exposed by the protective layer to form the transition layer.

[0033] Optionally, after forming the transition layer, the sacrificial structure on the surface of the initial barrier layer is removed; after removing the sacrificial structure, the protective layer is removed.

[0034] Optionally, after removing the sacrificial structure and before removing the protective layer, the method further includes: performing hydrophilic treatment on the side wall of the first opening.

[0035] Optionally, after forming the first opening and before forming the transition layer, the method further includes: forming a hard mask layer on the surface of the sacrificial structure, wherein the material of the hard mask layer is different from the material of the sacrificial structure.

[0036] Optionally, the material of the transition layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride carbon and silicon oxycarbide.

[0037] Optionally, the aspect ratio of the first opening is in the range of 4-10.

[0038] Optionally, the anti-diffusion layer is also located on the side wall surface of the first opening.

[0039] Optionally, the material of the anti-diffusion layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon and silicon oxycarbide.

[0040] Optionally, the method for forming the anti-diffusion layer includes: forming an anti-diffusion material layer in the first opening and on the surface of the initial barrier layer; flattening the anti-diffusion material layer and the initial barrier layer until the surface of the dielectric layer is exposed, forming a barrier layer on the top of the gate structure, and forming an anti-diffusion layer in the first opening.

[0041] Optionally, the process of forming the anti-diffusion material layer includes a chemical vapor deposition process.

[0042] Optionally, before planarizing the anti-diffusion material layer and the initial barrier material layer, the method further includes: forming a covering layer on the anti-diffusion material layer.

[0043] Optionally, the process of planarizing the anti-diffusion material layer and the initial barrier material layer includes a Hydra etching process or a gas cluster ion beam treatment process.

[0044] Optionally, after the anti-diffusion layer is formed, the initial barrier layer is removed and a gate plug is formed on the top of the gate structure.

[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0046] The semiconductor structure of the technical solution of the present invention has an anti-diffusion layer located on the top of the transition layer in the second region, and the anti-diffusion layer seals the first opening into a closed cavity. The closed cavity can play a good role in isolating ions in the substrate and the dielectric layer, so that the electrical performance of the device structures on both sides of the anti-diffusion layer can not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure.

[0047] Furthermore, the anti-diffusion layer is also located on the side wall surface of the first opening. The closed cavity formed by the anti-diffusion layer sealing the first opening has good airtightness, thereby preventing gas or liquid in subsequent processes from entering the closed cavity and affecting the isolation effect of the closed cavity.

[0048] In the formation method of the technical solution of the present invention, the initial gate structure on the second region is removed, a first opening is formed on the second region of the substrate, and then an anti-diffusion layer is formed on the sidewall surface of the first opening, the anti-diffusion layer is located on the top of the transition layer, and the anti-diffusion layer seals the first opening into a closed cavity. The closed cavity can play a good role in isolating the ions in the substrate and the dielectric layer, so that the electrical performance of the device structure on both sides of the anti-diffusion layer can not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure; at the same time, the anti-diffusion layer with the closed cavity has a smaller dielectric constant, thereby reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.

[0049] Furthermore, the anti-diffusion layer is also located on the side wall surface of the first opening. The closed cavity formed by the anti-diffusion layer sealing the first opening has good airtightness, thereby preventing gas or liquid in subsequent processes from entering the closed cavity and affecting the isolation effect of the closed cavity.

[0050] Furthermore, a transition layer is provided on the side wall surface of the first opening, and the transition layer can further enhance the barrier effect of the anti-diffusion layer, so that the isolation effect of the anti-diffusion layer is better.

[0051] Furthermore, the barrier layer and the anti-diffusion layer can be formed simultaneously, thereby simplifying the process flow and improving work efficiency.

[0052] Furthermore, a sacrificial structure is formed on the surface of the initial barrier layer, and a mask structure is formed on the sacrificial structure, so that the sacrificial structure can fill the surface of the initial barrier layer, so that the plane flatness of the mask structure is higher, and thus the position accuracy of the pattern formed by the mask structure is higher, so that a first opening can be formed on the second area of ​​the substrate; at the same time, the sacrificial structure can subsequently form an etching stop layer of the transition layer.

[0053] Furthermore, after forming the first opening and before forming the transition layer, a hard mask layer is formed on the surface of the sacrificial structure, and the material of the hard mask layer is different from the material of the sacrificial structure. When the transition layer is subsequently formed, the hard mask layer can adjust the height of the transition layer in the first opening to meet the height requirement of the transition layer formed in the first opening, so that the top plane of the formed transition layer is lower than the top plane of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0055] Figures 4 to 16 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] As described in the background art, the existing process and performance of designing a single diffusion region to cut off and form shallow trench isolation still need to be improved. Now, an analysis and description will be made in conjunction with a specific embodiment.

[0057] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0058] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0059] Please refer to Figure 1 , providing a substrate 100; the substrate 100 has a fin 101; the substrate 100 has a plurality of dummy gate structures 103, the dummy gate structures 103 spanning the fin 101; the substrate 100 has a dielectric layer 102, the dummy gate structures 103 are located in the dielectric layer 102.

[0060] Please refer to Figure 2 , a mask structure (not shown) is formed on the substrate 100, wherein the mask structure exposes a portion of the top surface of the dummy gate structure 103; a portion of the dummy gate structure 103 and the fin 101 are removed using the mask structure as a mask, and an opening (not shown) is formed in the dielectric layer 102; and an anti-diffusion structure 104 is formed in the opening.

[0061] Please refer to Figure 3 , remove the dummy gate structure 103 to form a gate structure 105.

[0062] During the formation of the semiconductor structure, the anti-diffusion structure 104 is used to block ion diffusion in the fin 101 , so that when different devices are formed on both sides of the anti-diffusion structure 104 , the anti-diffusion structure 104 can play a role of electrical isolation.

[0063] However, the depth and width of the opening formed by removing part of the pseudo gate structure 103 and the fin 101 are relatively large, so when the anti-diffusion structure 104 is formed in the opening by a deposition process, the anti-diffusion structure 104 formed is loose and has holes. When the pseudo gate structure 103 is subsequently removed to form the gate structure 105, the material of the gate structure 105 is metal, and the metal material will fill the holes of the anti-diffusion structure 104, thereby weakening the anti-diffusion ability of the anti-diffusion structure 104, and then causing the semiconductor structure to have the risk of short circuit, affecting the performance of the formed semiconductor structure. In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by forming an anti-diffusion structure with a closed cavity, the closed cavity can play a good role in isolating the ions in the substrate and the dielectric layer, so that the electrical properties of the device structures on both sides of the anti-diffusion structure can not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure; at the same time, the anti-diffusion structure with a closed cavity has a smaller dielectric constant, thereby reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.

[0064] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0065] Figures 4 to 16 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention.

[0066] Please refer to Figure 4 , providing a substrate, the substrate comprising a plurality of first regions I and second regions II, wherein the second regions II are located between adjacent first regions I.

[0067] In this embodiment, the substrate includes a base 200 and a fin structure 201 located on the base 200 .

[0068] The material of the substrate 200 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or silicon on insulator; the material of the fin structure 201 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or silicon on insulator.

[0069] In this embodiment, the material of the substrate 200 includes silicon; the material of the fin structure 201 includes silicon.

[0070] In other embodiments, the substrate comprises a planar substrate.

[0071] Please refer to Figure 5 , a plurality of initial gate structures 203 are formed on the first region I and the second region II, and the initial gate structures 203 span the fin structure 201 .

[0072] The initial gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0073] In this embodiment, the dielectric constant of the gate dielectric layer material is greater than 3.9, and the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes metal, and the metal includes tungsten.

[0074] In another embodiment, the dielectric constant of the gate dielectric layer material is less than or equal to 3.9, and the material of the gate dielectric layer includes silicon oxide; and the material of the gate layer includes polysilicon.

[0075] The method for forming the initial gate structure 203 includes: forming a dummy gate structure (not shown) on a substrate; forming a dielectric layer 202 on the substrate, wherein the dummy gate structure is located within the dielectric layer 202; removing the dummy gate structure and forming a gate opening (not shown) within the dielectric layer 202; and forming the initial gate structure 203 within the gate opening, wherein the dielectric layer 202 exposes the surface of the initial gate structure 203.

[0076] The method for forming the dielectric layer 202 includes: forming a dielectric material layer (not shown) on a substrate; planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed to form the dielectric layer 202 , wherein the surface of the dielectric layer 202 has a first groove 204 .

[0077] In this embodiment, the planarization process is a chemical mechanical polishing process, which has a high etching rate for the dielectric material layer, thereby forming a first groove 204 on the surface of the dielectric layer 202 when the top surface of the dummy gate structure is completely exposed.

[0078] The material of the dielectric layer 202 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0079] In this embodiment, the material of the dielectric layer 202 includes silicon oxide.

[0080] Please refer to Figure 6 , the initial gate structure 203 is etched back to form a gate structure 205 on the first region I and the second region II, and a second opening (not shown) is formed in the dielectric layer 202 on the top of the gate structure 205.

[0081] The second opening is used for subsequently forming a barrier layer on top of the gate structure 205 .

[0082] Please continue to refer to Figure 6An initial barrier layer 207 is formed in the second opening and on the surface of the dielectric layer 202 , and a second groove 206 is formed on the surface of the initial barrier layer 207 on the dielectric layer 202 .

[0083] The material of the initial barrier layer 207 is different from the material of the dielectric layer 202 .

[0084] The material of the initial barrier layer 207 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0085] In this embodiment, the material of the initial barrier layer 207 includes silicon nitride.

[0086] The material of the initial barrier layer 207 is different from that of the dielectric layer 202, so that the barrier layer formed subsequently has a greater etching selectivity ratio with the dielectric layer 202. A conductive plug is subsequently formed on the top of the gate structure 205. When the barrier layer on the top of the gate structure 205 is removed, the process of removing the barrier layer causes less damage to the dielectric layer 202, so that the position of the conductive plug can be self-aligned and formed on the top of the gate structure 205.

[0087] The process of forming the initial barrier layer 207 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the initial barrier layer 207 includes a chemical vapor deposition process. Since the dielectric layer 202 has a first groove 204, the surface of the initial barrier layer 207 formed on the dielectric layer 202 by the chemical vapor deposition process also has a second groove 206.

[0088] Next, a sacrificial structure is formed on the surface of the initial barrier layer 207 , and the material of the sacrificial structure is different from that of the initial barrier layer 207 .

[0089] A sacrificial structure is formed on the surface of the initial barrier layer 207, so that when a mask structure is subsequently formed on the sacrificial structure, the sacrificial structure can fill the surface of the initial barrier layer 207, so that the plane flatness of the mask structure is higher, and thus the position accuracy of the pattern formed by the mask structure is higher, so that the gate structure and the fin structure on the second region II can be accurately removed to form a first opening, and an anti-diffusion layer can be formed in the first opening; at the same time, the sacrificial structure can also serve as an etching stop layer for the subsequent formation of a transition layer in the first opening.

[0090] The sacrificial structure includes a first sacrificial layer, and the first sacrificial layer is located in the second groove 206 .

[0091] In this embodiment, the sacrificial structure further includes a second sacrificial layer located on the surface of the first sacrificial layer and the initial barrier layer 207 .

[0092] Please refer to Figure 7 , a first sacrificial layer 208 is formed in the second groove 206 .

[0093] The method for forming the first sacrificial layer 208 includes: forming a first sacrificial material layer (not shown) on the surface of the initial barrier layer 207 and in the second groove 206 ; planarizing the first sacrificial material layer until the surface of the initial barrier layer 207 is exposed, and forming the first sacrificial layer 208 in the second groove 206 .

[0094] The material of the first sacrificial layer 208 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0095] In this embodiment, the material of the first sacrificial layer 208 includes silicon oxide.

[0096] The material of the first sacrificial layer 208 is different from that of the initial barrier layer 207 , so when planarizing the first sacrificial material layer, the planarization process can stop at the surface of the initial barrier layer 207 , thereby forming the first sacrificial layer 208 in the second groove 206 .

[0097] The process of forming the first sacrificial material layer includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the first sacrificial material layer includes a chemical vapor deposition process.

[0098] Please refer to Figure 8 A second sacrificial layer 209 is formed on the surface of the first sacrificial layer 208 and the initial barrier layer 207 .

[0099] The material of the second sacrificial layer 209 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0100] In this embodiment, the material of the second sacrificial layer 209 includes silicon oxide.

[0101] The material of the second sacrificial layer 209 is different from that of the initial blocking layer 207, so that when a transition layer is subsequently formed, the second sacrificial layer 209 can play a certain protective role on the initial blocking layer 207 to avoid damage to the surface of the initial blocking layer 207 and affect the formation of subsequent blocking layers; at the same time, when a transition layer is subsequently formed in the first opening, the second sacrificial layer 209 has a certain thickness, so that the sacrificial structure has a better stopping effect as a stopping layer.

[0102] In this embodiment, the thickness of the second sacrificial layer 209 is in the range of 50 angstroms to 150 angstroms. If the thickness of the second sacrificial layer 209 is too thin, the protection effect of the second sacrificial layer 209 on the initial blocking layer 207 is poor, and when the sacrificial structure is used as a stop layer, the stop effect is poor; if the thickness of the second sacrificial layer 209 is too thick, the subsequent removal requires increased conditions, which will cause process waste.

[0103] The process of forming the second sacrificial layer 209 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the second sacrificial layer 209 includes a chemical vapor deposition process.

[0104] In other embodiments, the second sacrificial layer may not be formed.

[0105] Please refer to Fig. 9 , a mask structure is formed on the surface of the sacrificial structure, and the mask structure exposes the surface of the gate structure 205 on the second region II.

[0106] The mask structure includes an initial hard mask layer 210 ; a liner layer 211 located on the initial hard mask layer 210 ; and a photoresist layer 212 located on the liner layer 211 , wherein the photoresist layer 212 exposes a surface of the liner layer 211 on the second region II.

[0107] The initial hard mask layer 210 provides a material layer for a hard mask layer formed subsequently.

[0108] The material of the initial hard mask layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, and silicon carbide.

[0109] In this embodiment, the material of the initial hard mask layer 210 includes silicon nitride. The material of the initial hard mask layer 210 is different from the material of the sacrificial structure, so that when a transition layer is subsequently formed in the first opening, the sacrificial structure can serve as an etch stop layer for etching the subsequently formed initial transition layer and hard mask layer to form the transition layer.

[0110] The material of the liner layer 211 includes an organic material or an inorganic material. In this embodiment, the material of the liner layer 211 includes an organic material, and the organic material includes amorphous carbon.

[0111] Please refer to Fig.10 The gate structure 205 and the fin structure 201 on the second region II are etched using the mask structure as a mask to form a first opening 213 on the second region II, wherein the bottom of the first opening 213 is lower than or flush with the bottom plane of the fin structure 201 .

[0112] The bottom of the first opening 213 is lower than or flush with the bottom plane of the fin structure 201, so that when an anti-diffusion layer is subsequently formed in the first opening 213, the anti-diffusion layer can block the diffusion of ions in the fin structure 201, so that when different devices are formed on both sides of the anti-diffusion layer, the anti-diffusion layer can play a better role in electrical isolation, so that the electrical performance of the device structures on both sides of the anti-diffusion layer will not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure.

[0113] In this embodiment, the aspect ratio of the first opening 213 is in the range of 4-10.

[0114] The aspect ratio of the first opening 213 is in the range of 4 to 10, so that when an anti-diffusion layer is subsequently formed in the first opening 213, the anti-diffusion layer located on the top sidewall surface of the first opening can seal the first opening 213 into a closed cavity, so that the anti-diffusion layer with a closed cavity can have a better isolation effect.

[0115] In the process of etching the gate structure 205 and the fin structure 201 on the second region II using the mask structure as a mask to form a first opening 213, the etching process also simultaneously etches the mask structure to form a hard mask layer 214 on the surface of the sacrificial structure. The material of the hard mask layer 214 is different from that of the sacrificial structure.

[0116] The material of the hard mask layer 214 is different from the material of the sacrificial structure. After an initial transition layer is subsequently formed on the inner wall surface of the first opening 213 and the surface of the hard mask layer 214, when etching the initial transition layer in the first opening 213, the etching process stops at the surface of the sacrificial structure, so that the hard mask layer 214 can increase the etching depth of the initial transition layer in the first opening 213 to meet the height requirement of the formed transition layer in the first opening 213, so that the top plane of the formed transition layer is lower than the top plane of the dielectric layer 202.

[0117] In this embodiment, the hard mask layer 214 has a thickness ranging from 50 angstroms to 150 angstroms.

[0118] In other embodiments, the hard mask layer may not be formed.

[0119] Next, a transition layer is formed on the bottom surface and a portion of the sidewall surface of the first opening 213 , and the top surface of the transition layer is lower than the top plane of the dielectric layer 202 .

[0120] Please refer to Fig.11, an initial transition layer 215 is formed on the inner wall surface of the first opening and the surface of the hard mask layer 214; after the initial transition layer 215 is formed, a protective layer 216 is formed in the first opening 213, the top surface of the protective layer 216 is lower than the top surface of the dielectric layer 202, and the protective layer 216 exposes a portion of the side wall surface of the initial transition layer 215.

[0121] The initial transition layer 215 provides a material layer for subsequently forming a transition layer.

[0122] The material of the initial transition layer 215 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride and silicon oxycarbide. The process of forming the initial transition layer 215 includes a chemical vapor deposition process or an atomic layer deposition process.

[0123] In this embodiment, the material of the initial transition layer 215 includes silicon nitride. The process of forming the initial transition layer 215 includes an atomic layer deposition process, and the atomic layer deposition process can form the initial transition layer 215 with a dense structure and a relatively thin thickness.

[0124] The protective layer 216 is used to protect the surface of the transition layer formed subsequently when a portion of the initial transition layer 215 is removed, thereby preventing the process of removing a portion of the initial transition layer 215 from damaging the transition layer.

[0125] The method for forming the protective layer 216 includes: forming a protective material layer (not shown) in the first opening 213 and on the surface of the hard mask layer 214 ; etching back the protective material layer to form the protective layer 216 , wherein the top plane of the protective layer 216 is lower than the top plane of the dielectric layer 202 .

[0126] The material of the protective layer 216 includes an organic material or an inorganic material. In this embodiment, the material of the protective layer 216 includes an organic material, and the organic material includes amorphous carbon.

[0127] Please refer to Fig.12 , remove the portion of the initial transition layer 215 exposed by the protection layer 216 until the surface of the sacrificial structure is exposed, and form a transition layer 217 on the sidewall surface of the first opening 213 , wherein the top plane of the transition layer 217 is lower than the top plane of the dielectric layer 202 .

[0128] The transition layer 217 can further enhance the barrier effect of the subsequently formed anti-diffusion layer, so that the anti-diffusion layer has a better isolation effect.

[0129] The process of removing part of the initial transition layer 215 includes one or more of a dry etching process and a wet etching process. In this embodiment, the process of removing part of the initial transition layer 215 includes a dry etching process.

[0130] When a portion of the initial transition layer 215 is removed, the hard mask layer 214 is also removed until the surface of the sacrificial structure is exposed.

[0131] The material of the hard mask layer 214 is different from the material of the sacrificial structure, so that when removing part of the initial transition layer 215, the etching process can stop at the surface of the sacrificial structure, so that the hard mask layer 214 can increase the etching depth of the initial transition layer 215 in the first opening 213 to meet the height requirement of the formed transition layer 217 in the first opening 213, so that the top plane of the formed transition layer 217 is lower than the top plane of the dielectric layer 202.

[0132] The top plane of the transition layer 217 is lower than the top plane of the dielectric layer 202, so that the anti-diffusion material layer subsequently formed on the top of the transition layer 217 has a larger volume. Therefore, when the anti-diffusion material layer is subsequently flattened, the flattening process is not easy to expose the closed cavity sealed by the anti-diffusion layer, thereby ensuring a better isolation effect of the closed cavity sealed by the anti-diffusion layer and avoiding the reaction gas or liquid from entering the closed cavity during the subsequent process.

[0133] Please refer to Fig.13 After forming the transition layer 217 , the sacrificial structure on the surface of the initial barrier layer 207 is removed.

[0134] The process of removing the sacrificial structure includes a Certas dry etching process or a chemical mechanical polishing process.

[0135] In this embodiment, the process of removing the sacrificial structure includes a Certas dry etching process. The Certas dry etching process has a high etching stop accuracy and can obtain an initial barrier layer 207 with a high surface flatness, which is beneficial to the formation of a subsequent barrier layer.

[0136] In this embodiment, after removing the sacrificial structure, the exposed sidewalls of the first opening 213 are subjected to a hydrophilic treatment.

[0137] The hydrophilic treatment solution includes: ethanol solution or isopropanol solution.

[0138] The hydrophilic treatment can reduce the contact angle of the exposed side wall surface of the first opening 213, so that when an anti-diffusion layer is subsequently formed in the first opening 213, the material of the anti-diffusion layer can be preferentially formed on the top side wall surface of the first opening 213, thereby facilitating the anti-diffusion layer to seal the first opening 213 to form a closed cavity, so that the closed cavity has a better isolation effect.

[0139] In other embodiments, the exposed sidewall of the first opening may not be subjected to the hydrophilic treatment.

[0140] Please continue to refer to Fig.13 After removing the sacrificial structure, the protective layer 216 is removed.

[0141] The process of removing the protective layer 216 includes one or more of a dry etching process and a wet etching process. In this embodiment, the process of removing the protective layer 216 includes a dry etching process.

[0142] Next, after forming the transition layer 217 , an anti-diffusion layer is formed in the first opening 213 . The anti-diffusion layer is located on the top of the transition layer, and the anti-diffusion layer seals the first opening 213 into a closed cavity.

[0143] Please refer to Fig.14 A diffusion-preventing material layer 218 is formed in the first opening 213 and on the surface of the initial barrier layer 207 .

[0144] The anti-diffusion material layer 218 provides a material layer for subsequently forming an anti-diffusion layer.

[0145] The material of the diffusion prevention material layer 218 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride and silicon oxycarbide. In this embodiment, the material of the diffusion prevention material layer 218 includes silicon nitride.

[0146] In this embodiment, the process of forming the diffusion prevention material layer 218 includes a chemical vapor deposition process. The deposition rate of the chemical vapor deposition process is relatively fast, which is conducive to the formation of the diffusion prevention material layer 218 on the top sidewall surface of the first opening 213 first, so that the diffusion prevention layer can seal the first opening 213 to form a closed cavity, so that the closed cavity has a better isolation effect.

[0147] Please continue to refer to Fig.14 , a covering layer 219 is formed on the anti-diffusion material layer 218 .

[0148] The covering layer 219 is used to increase the surface flatness of the anti-diffusion material layer 218. When the anti-diffusion material layer 218 is subsequently flattened to form an anti-diffusion layer, the initial barrier layer 207 will also be flattened to form a barrier layer. The surface flatness of the anti-diffusion material layer 218 is relatively high, so the stop position of the flattening process can be precisely controlled, and a plane with good flatness can be obtained, which is beneficial to the size uniformity of the subsequent formation of the gate plug.

[0149] The material of the capping layer 219 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride and silicon oxycarbide. The process of forming the capping layer 219 includes a chemical vapor deposition process or an atomic layer deposition process.

[0150] In this embodiment, the material of the cover layer 219 includes silicon oxide; and the process of forming the cover layer 219 includes a chemical vapor deposition process.

[0151] In other embodiments, the cover layer may not be formed.

[0152] Please refer to Fig.15 , planarizing the cover layer 219 until the surface of the anti-diffusion material layer 218 is exposed; after planarizing the cover layer 219, planarizing the anti-diffusion material layer 218 and the initial barrier layer 207 until the surface of the dielectric layer 202 is exposed, forming a barrier layer 221 on the top of the gate structure 205, and forming an anti-diffusion layer 220 on the top of the transition layer 217, the anti-diffusion layer 220 seals the first opening 213 into a closed cavity.

[0153] In this embodiment, the anti-diffusion layer 220 is also located on the side wall surface of the first opening 213, so that the closed cavity formed by the anti-diffusion layer 220 sealing the first opening 213 has better airtightness, thereby preventing gas or liquid in subsequent processes from entering the closed cavity and affecting the isolation effect of the closed cavity.

[0154] In this embodiment, the process of planarizing the cover layer 219 includes a chemical mechanical polishing process; the process of planarizing the anti-diffusion material layer and the initial barrier material layer includes a Hydra etching process or a gas cluster ion beam processing (GCIB).

[0155] The Hydra etching process has substantially the same etching rate for silicon oxide material and silicon nitride material, and thus the Hydra etching process has substantially the same etching rate for the initial barrier layer 207 and the dielectric layer 202, so that the surface of the formed barrier layer 221 and the surface of the dielectric layer 202 are on the same plane, which is beneficial to the subsequent process.

[0156] The etching rates of silicon oxide material and silicon nitride material by the gas cluster ion beam treatment process are basically the same, and thus the etching rates of the initial barrier layer 207 and the dielectric layer 202 by the gas cluster ion beam treatment process are basically the same, so that the surface of the formed barrier layer 221 and the surface of the dielectric layer 202 are on the same plane, which is beneficial to the development of subsequent processes.

[0157] The etching gas of the Hydra etching process includes: C 4 F 8 and CH 3 F mixed gas.

[0158] The etching gas of the gas cluster ion beam treatment process includes a mixed gas of argon gas and carbon fluorine gas.

[0159] At this point, the anti-diffusion layer 220 is formed, and the anti-diffusion layer 220 is located on the top of the transition layer 217, and the anti-diffusion layer 220 seals the first opening 213 into a closed cavity. The closed cavity can play a good role in isolating the ions in the fin structure 201 and the dielectric layer 202, so that the electrical performance of the device structures on both sides of the anti-diffusion layer 220 can not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure.

[0160] In this embodiment, the barrier layer 221 can be formed simultaneously with the anti-diffusion layer 220 , thereby simplifying the process flow and improving work efficiency.

[0161] Please refer to Fig.16 After forming the anti-diffusion layer 220 , the barrier layer 221 is removed, and a gate plug 222 is formed on the top of the gate structure 205 .

[0162] The gate plug 222 is made of a metal, and the metal includes one or more combinations of copper, tungsten, aluminum, and titanium nitride.

[0163] Since the materials of the barrier layer 221 and the dielectric layer 202 are different, when the barrier layer 221 is removed, the process of removing the barrier layer 221 causes less damage to the dielectric layer 202, so that when the gate plug 222 is formed on the top of the gate structure 205, the gate plug 222 can be self-aligned and formed on the top of the gate structure 205, so that the position accuracy of the gate plug 222 is better and the electrical connection effect with the gate structure 205 is better.

[0164] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Fig.15 ,include:

[0165] A substrate, the substrate comprising a plurality of first regions I and second regions II, wherein the second regions II are located between adjacent first regions I;

[0166] A plurality of gate structures 205 located on the first region I of the substrate;

[0167] A dielectric layer 202 located on the substrate, wherein the gate structure 205 is located in the dielectric layer 202;

[0168] A first opening (not shown) located on the second region II of the substrate, wherein the first opening extends from the dielectric layer 202 to the substrate;

[0169] A transition layer 217 located on the bottom surface and a portion of the sidewall surface of the first opening, wherein the top surface of the transition layer 217 is lower than the top plane of the dielectric layer 202;

[0170] The anti-diffusion layer 220 is located on the top of the transition layer 217 , and the anti-diffusion layer 220 seals the first opening into a closed cavity.

[0171] In this embodiment, the aspect ratio of the first opening is in the range of 4-10.

[0172] In this embodiment, the substrate includes a base 200 and a fin structure 201 located on the base 200 ; the gate structure 205 spans across the fin structure 201 ; and the bottom of the first opening is lower than or flush with the bottom plane of the fin structure 201 .

[0173] In this embodiment, the anti-diffusion layer 220 is also located on the sidewall surface of the first opening.

[0174] In this embodiment, it further includes: a barrier layer 221 located on the top surface of the gate structure 205 in the first region I.

[0175] In this embodiment, the material of the barrier layer 221 is different from the material of the dielectric layer 202 .

[0176] In the present embodiment, the material of the barrier layer 221 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0177] In the present embodiment, the material of the anti-diffusion layer 220 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0178] In the present embodiment, the material of the transition layer 217 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

[0179] In the semiconductor structure, the anti-diffusion layer 220 is located on the top of the transition layer 217 in the second region II, and the anti-diffusion layer 220 seals the first opening into a closed cavity. The closed cavity can play a good role in isolating the ions in the fin structure 201 and the dielectric layer 202, so that the electrical performance of the device structures on both sides of the anti-diffusion layer 220 can not interfere with each other, thereby improving the electrical performance stability of the formed semiconductor structure.

[0180] Furthermore, the anti-diffusion layer 220 is also located on the side wall surface of the first opening. The closed cavity formed by the anti-diffusion layer sealing the first opening has good airtightness, thereby preventing gas or liquid in subsequent processes from entering the closed cavity and affecting the isolation effect of the closed cavity.

[0181] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a plurality of first regions and second regions, wherein the second regions are located between adjacent first regions; A plurality of gate structures located on the first region of the substrate; A dielectric layer located on the substrate, wherein the gate structure is located in the dielectric layer; a first opening located on the second region of the substrate, the first opening extending from the dielectric layer to the substrate, and the first opening being formed by removing a gate structure on the second region; A partition layer located on the bottom surface and a portion of the sidewall surface of the first opening, wherein the top surface of the partition layer is lower than the top plane of the dielectric layer; The anti-diffusion layer is located on the side wall surface of the first opening at the top of the isolation layer, and the anti-diffusion layer seals the first opening into a closed cavity.

2. The semiconductor structure according to claim 1, wherein: The aspect ratio of the first opening is in the range of 4-10.

3. The semiconductor structure according to claim 1, wherein: The substrate includes a base and a fin structure located on the base; the gate structure spans across the fin structure; and the bottom of the first opening is lower than or flush with a bottom plane of the fin structure.

4. The semiconductor structure according to claim 1, wherein: Also includes: A barrier layer is located on the top surface of the gate structure in the first region.

5. The semiconductor structure according to claim 4, characterized in that The material of the barrier layer is different from that of the dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that The material of the barrier layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

7. The semiconductor structure according to claim 1, wherein: The material of the anti-diffusion layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

8. The semiconductor structure according to claim 1, wherein: The material of the isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride carbon and silicon oxycarbide.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of first regions and second regions, wherein the second regions are located between adjacent first regions; Forming a plurality of initial gate structures and a dielectric layer on the first region and the second region; the initial gate structure is located in the dielectric layer, and the dielectric layer exposes the surface of the initial gate structure; Removing the initial gate structure on the second region, forming a first opening on the second region of the substrate, wherein the first opening extends from the dielectric layer to the substrate; Forming a partition layer on the bottom surface and part of the sidewall surface of the first opening, wherein the top surface of the partition layer is lower than the top plane of the dielectric layer; After the isolation layer is formed, an anti-diffusion layer is formed on the side wall surface of the first opening at the top of the isolation layer, and the anti-diffusion layer seals the first opening into a closed cavity.

10. The method for forming a semiconductor structure according to claim 9, wherein: The substrate includes a base and a fin structure located on the base; the initial gate structure spans across the fin structure; and the bottom of the first opening is lower than or flush with a bottom plane of the fin structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: The initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the gate dielectric layer material is less than or equal to 3.9, and the material of the gate dielectric layer includes silicon oxide; and the material of the gate layer includes polysilicon.

12. The method for forming a semiconductor structure according to claim 10, wherein: The initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the gate dielectric layer material is greater than 3.9, and the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes metal, and the metal includes tungsten.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the initial gate structure includes: forming a dummy gate structure on a substrate; forming a dielectric layer on the substrate, wherein the dummy gate structure is located in the dielectric layer; removing the dummy gate structure to form a gate opening in the dielectric layer; and forming the initial gate structure in the gate opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the dielectric layer comprises: forming a dielectric material layer on a substrate; planarizing the dielectric material layer until the top surface of the pseudo gate structure is exposed to form the dielectric layer, wherein the surface of the dielectric layer has a first groove.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening includes: forming a mask structure on the surface of the substrate, the mask structure exposing the surface of the initial gate structure on the second region; etching the initial gate structure and the substrate using the mask structure as a mask to form a first opening on the second region of the substrate.

16. The method for forming a semiconductor structure according to claim 15, wherein: Before forming the mask structure, it also includes: etching back the initial gate structure to form a gate structure on the first area and the second area, and forming a second opening in the dielectric layer on the top of the gate structure; forming an initial barrier layer in the second opening and on the surface of the dielectric layer, and the surface of the initial barrier layer on the dielectric layer has a second groove; the mask structure exposes the surface of the initial barrier layer on the second area.

17. The method for forming a semiconductor structure according to claim 16, wherein: Before forming the mask structure on the surface of the initial barrier layer, the method further includes: forming a sacrificial structure on the surface of the initial barrier layer, wherein the mask structure is located on the surface of the sacrificial structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The sacrificial structure includes a first sacrificial layer, and the first sacrificial layer is located in the second groove.

19. The method for forming a semiconductor structure according to claim 18, wherein: The sacrificial structure further includes a second sacrificial layer located on the surfaces of the first sacrificial layer and the initial barrier layer.

20. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the first sacrificial layer comprises: forming a first sacrificial material layer on the surface of the initial barrier layer; planarizing the first sacrificial material layer until the surface of the initial barrier layer is exposed, and forming the first sacrificial layer in the second groove.

21. The method for forming a semiconductor structure according to claim 17, wherein: The material of the sacrificial structure is different from that of the initial barrier layer.

22. The method for forming a semiconductor structure according to claim 16, wherein: The material of the initial barrier layer is different from that of the dielectric layer.

23. The method for forming a semiconductor structure according to claim 22, wherein: The material of the initial barrier layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride carbide, and silicon oxycarbide.

24. The method for forming a semiconductor structure according to claim 15, wherein: The mask structure includes an initial hard mask layer; a liner layer located on the initial hard mask layer; and a photoresist layer located on the liner layer, wherein the photoresist layer exposes a surface of the liner layer on the second region.

25. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the isolation layer comprises: forming an initial isolation layer on the inner wall surface of the first opening and the surface of the sacrificial structure; after forming the initial isolation layer, forming a protective layer in the first opening, wherein the top surface of the protective layer is lower than the top surface of the dielectric layer, and the protective layer exposes a portion of the side wall surface of the initial isolation layer; The portion of the initial isolation layer exposed by the protective layer is removed to form the isolation layer.

26. The method for forming a semiconductor structure according to claim 25, wherein: After forming the isolation layer, the sacrificial structure on the surface of the initial barrier layer is removed; after removing the sacrificial structure, the protective layer is removed.

27. The method for forming a semiconductor structure according to claim 26, wherein: After removing the sacrificial structure and before removing the protective layer, the method further includes: performing a hydrophilic treatment on the sidewall of the first opening.

28. The method for forming a semiconductor structure according to claim 17, wherein: After forming the first opening and before forming the isolation layer, the method further includes: forming a hard mask layer on the surface of the sacrificial structure, wherein the material of the hard mask layer is different from the material of the sacrificial structure.

29. The method for forming a semiconductor structure according to claim 9, wherein: The material of the isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride carbon and silicon oxycarbide.

30. The method for forming a semiconductor structure according to claim 9, wherein: The aspect ratio of the first opening is in the range of 4-10.

31. The method for forming a semiconductor structure according to claim 9, wherein: The material of the anti-diffusion layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, silicon oxynitride carbon, and silicon oxycarbide.

32. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the anti-diffusion layer includes: forming an anti-diffusion material layer in the first opening and on the surface of the initial barrier layer; flattening the anti-diffusion material layer and the initial barrier layer until the surface of the dielectric layer is exposed, forming a barrier layer on the top of the gate structure, and forming an anti-diffusion layer in the first opening.

33. The method for forming a semiconductor structure according to claim 32, wherein: The process of forming the anti-diffusion material layer includes a chemical vapor deposition process.

34. The method for forming a semiconductor structure according to claim 32, wherein: Before planarizing the anti-diffusion material layer and the initial barrier material layer, the method further includes: forming a covering layer on the anti-diffusion material layer.

35. The method for forming a semiconductor structure according to claim 32, wherein: The process of planarizing the anti-diffusion material layer and the initial barrier material layer includes a Hydra etching process or a gas cluster ion beam treatment process.

36. The method for forming a semiconductor structure according to claim 16, wherein: After forming the anti-diffusion layer, the initial barrier layer is removed, and a gate plug is formed on the top of the gate structure.

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