Transistor and method of forming the same

Abstract

A thin film transistor and a method for forming the same, the thin film transistor comprising: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region and a channel region, the channel region being disposed between the source region and the drain region and overlapping with the word line in a vertical direction perpendicular to the plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in a vertical direction; a gate dielectric layer disposed between the channel region and the word line; and a source electrode and a drain electrode electrically coupled to the source region and the drain region, respectively.

Description

Technical Field

[0001] Embodiments of the present application relate to transistors and methods of forming the same. Background Art

[0002] In the semiconductor industry, there is a continuing desire to increase the areal density of integrated circuits. To this end, individual transistors are becoming smaller and smaller. However, the rate at which individual transistors can be made smaller is slowing. Moving peripheral transistors from the front end of line (FEOL) of manufacturing to the back end of line (BEOL) can be advantageous because functionality can be added in the BEOL while valuable chip area can be gained in the FEOL. Thin film transistors (TFTs) made from oxide semiconductors are an attractive option for BEOL integration because TFTs can be processed at low temperatures and therefore will not damage previously fabricated devices.

[0003] However, such BEOL transistors may still be affected by gases in the surrounding environment during the formation of other BEOL devices. For example, the BEOL transistors may be exposed to plasma and air in the surrounding environment. Ambient gases such as hydrogen may damage the layers of the BEOL transistors and reduce the efficiency of the manufactured devices. Summary of the invention

[0004] Some embodiments of the present application provide a transistor, comprising: a word line, arranged on a substrate; a semiconductor layer, arranged on the substrate, the semiconductor layer having a source region, a drain region and a channel region, the channel region being arranged between the source region and the drain region and overlapping with the word line in a vertical direction perpendicular to the plane of the substrate; a hydrogen diffusion barrier film, overlapping with the channel region in a vertical direction; a gate dielectric layer, arranged between the channel region and the word line; and a source electrode and a drain electrode, electrically coupled to the corresponding source region and drain region.

[0005] Some other embodiments of the present application provide a transistor, comprising: a word line, arranged on a substrate; a semiconductor layer, arranged on the substrate, the semiconductor layer comprising a source region, a drain region and a channel region, the channel region being arranged between the source region and the drain region and overlapping with the word line in a vertical direction perpendicular to the plane of the substrate; a hydrogen diffusion barrier film, overlapping with the channel region in a vertical direction; a gate dielectric layer, arranged between the channel region and the word line; a source electrode and a drain electrode, electrically coupled to the corresponding source region and the drain region; a first dielectric layer, arranged between the semiconductor layer and the substrate; a second dielectric layer, arranged on the first dielectric layer, covering the semiconductor layer and the hydrogen diffusion barrier film, wherein the source region and the drain region directly contact the second dielectric layer; and the channel region directly contacts the hydrogen diffusion barrier film.

[0006] Still other embodiments of the present application provide a method for forming a transistor, comprising: depositing a first dielectric layer on a substrate; forming a semiconductor layer on the first dielectric layer; forming a hydrogen diffusion barrier film on a channel region of the semiconductor layer; depositing a second dielectric layer on the semiconductor layer and the hydrogen diffusion barrier film; and performing a thermal annealing process to diffuse hydrogen into the semiconductor layer to form a source region and a drain region on opposite sides of the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A is a vertical cross-sectional view of a first exemplary structure before forming an array of TFTs according to an embodiment of the present invention.

[0009] Figure 1B is a vertical cross-sectional view of a first exemplary structure during formation of a BEOL transistor in accordance with an embodiment of the present invention.

[0010] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming an upper level metal interconnect structure according to an embodiment of the present invention.

[0011] Figure 2A is a plan view of an intermediate structure of a TFT after depositing a first dielectric layer over a substrate according to various embodiments of the present invention.

[0012] Figure 2B According to various embodiments of the present invention, Figure 2A A vertical cross-sectional view taken along line AA'.

[0013] Figure 3A is a plan view of an intermediate structure of a TFT after forming a word line trench in a first dielectric layer according to various embodiments of the present invention.

[0014] Figure 3B According to various embodiments of the present invention, Figure 3A A vertical cross-sectional view taken along line AA'.

[0015] Figure 4A is a plan view of an intermediate structure of a TFT after depositing a metal filling material in a word line trench to form a word line according to various embodiments of the present invention.

[0016] Figure 4B According to various embodiments of the present invention, Figure 4AA vertical cross-sectional view taken along line AA'.

[0017] Figure 5A is a plan view of an intermediate structure of a TFT after deposition of gate dielectric blanket layer and semiconductor blanket layer materials according to various embodiments of the present invention.

[0018] Figure 5B According to various embodiments of the present invention, Figure 5A A vertical cross-sectional view taken along line AA'.

[0019] Fig. 6A is a plan view of an intermediate structure of a TFT after patterning the gate dielectric blanket layer and the semiconductor blanket layer according to various embodiments of the present invention.

[0020] Figure 6B According to various embodiments of the present invention, Fig. 6A A vertical cross-sectional view taken along line AA'.

[0021] Fig. 7A is a plan view of an intermediate structure of a TFT after a hydrogen diffusion barrier film layer is deposited over the patterned gate dielectric layer and the semiconductor layer according to various embodiments of the present invention.

[0022] Figure 7B According to various embodiments of the present invention, Fig. 7A A vertical cross-sectional view taken along line AA'.

[0023] Fig. 8A is a plan view of an intermediate structure of a TFT after patterning a hydrogen diffusion barrier film according to various embodiments of the present invention.

[0024] Figure 8B According to various embodiments of the present invention, Fig. 8A A vertical cross-sectional view taken along line AA'.

[0025] Fig.9A is a plan view of an intermediate structure of a TFT after depositing a second dielectric layer according to various embodiments of the present invention.

[0026] Fig. 9B According to various embodiments of the present invention, Fig.9A A vertical cross-sectional view taken along line AA'.

[0027] Fig.10 is a vertical cross-sectional view of a TFT during an annealing process step for forming an active region according to various embodiments of the present invention.

[0028] Fig.11A is a plan view of an intermediate structure of a TFT after forming an active area electrode via cavity according to various embodiments of the present invention.

[0029] Fig. 11B According to various embodiments of the present invention, Fig.11A A vertical cross-sectional view taken along line AA'.

[0030] Fig. 12A is a plan view of a complete structure of a TFT after forming an active area electrode according to various embodiments of the present invention.

[0031] Fig. 12B According to various embodiments of the present invention, Fig. 12A A vertical cross-sectional view taken along line AA'.

[0032] Fig.13 is a plan semi-transparent diagram of a complete structure of a TFT after forming an active area electrode according to various embodiments of the present invention.

[0033] Fig.14A is a plan semi-transparent diagram of the complete structure of an optional TFT after forming an active area electrode according to various embodiments of the present invention.

[0034] Fig. 14B According to various embodiments of the present invention, Fig.14A A vertical cross-sectional view taken along line AA'.

[0035] Fig.15A is a plan view of an intermediate structure of a TFT after depositing a metal filling material in the source line trench and the drain line trench to form source lines and drain lines according to various alternative embodiments of the present invention.

[0036] Fig. 15B According to various optional embodiments of the present invention Fig.15A A vertical cross-sectional view taken along line AA'.

[0037] Fig.16A is a plan view of an intermediate structure of a TFT after depositing a semiconductor blanket layer over the source and drain lines according to various alternative embodiments of the present invention.

[0038] Fig. 16B According to various optional embodiments of the present invention Fig.16A A vertical cross-sectional view taken along line AA'.

[0039] Fig.17A is a plan view of an intermediate structure of a TFT after patterning a semiconductor channel over source and drain lines according to various alternative embodiments of the present invention.

[0040] Fig. 17B According to various optional embodiments of the present invention Fig.17AA vertical cross-sectional view taken along line AA'.

[0041] Fig.18A is a plan view of an intermediate structure of a TFT after depositing a hydrogen diffusion barrier film layer, a gate dielectric blanket layer, and a word line blanket layer over a semiconductor channel according to various alternative embodiments of the present invention.

[0042] Fig.18B According to various embodiments of the present invention, Fig.18A A vertical cross-sectional view taken along line AA'.

[0043] Fig.19A is a plan view of an intermediate structure of a TFT after patterning a hydrogen diffusion barrier film, a gate dielectric layer, and a word line according to various alternative embodiments of the present invention.

[0044] Fig.19B According to various embodiments of the present invention, Fig.19A A vertical cross-sectional view taken along line AA'.

[0045] Fig. 20A is a plan view of an intermediate structure of a TFT after depositing a second dielectric layer according to various alternative embodiments of the present invention.

[0046] Fig. 20B According to various optional embodiments of the present invention Fig. 20A A vertical cross-sectional view taken along line AA'.

[0047] Fig.21 is a vertical cross-sectional view of a TFT during an annealing process step for forming an active region according to various alternative embodiments of the present invention.

[0048] Fig. 22 is a process flow chart of a method of forming a back-gated TFT 200 according to various embodiments of the present invention.

[0049] Fig.23 is a process flow chart of a method of forming a front-gate TFT 400 according to various alternative embodiments of the present invention. DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0051] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference number is deemed to have the same material composition and have a thickness within the same thickness range. As used herein, the terms "substantially" and "approximately" refer to variations of + / - 5%.

[0052] The present invention relates to a semiconductor device, and more particularly to a TFT device including a hydrogen diffusion barrier film for protecting a semiconductor channel layer from exposure to an ambient gas that may degrade TFT performance, and a method for forming the same.

[0053] The memory device includes a grid of independently operated memory cells formed on a substrate. The memory device may include volatile memory cells or non-volatile (NV) memory cells. Emerging memory technologies attempt to store more data at a lower cost than the expensive silicon chips used in popular consumer electronics. Such emerging memory devices may be used to replace existing memory technologies such as flash memory in the near future. Although existing resistive random access memories are generally adequate for their intended purposes, they are not completely satisfactory in all aspects as devices continue to shrink.

[0054] In some memory devices, CMOS transistors can be used as select transistors. However, the size limitations of CMOS transistor technology can be a limiting factor in improving the size and memory cell density of memory devices. Various embodiments described herein provide improved TFTs that can be used as select transistors in various devices.

[0055] TFTs can be manufactured in the BEOL location. By manufacturing TFTs in the BEOL location, functionality can be added in the BEOL while valuable chip area can be gained in the FEOL. In addition, TFTs made of oxide semiconductors are an attractive option for BEOL integration because the TFTs can be processed at low temperatures and therefore will not damage previously manufactured devices. Although manufacturing TFTs in the BEOL can protect the TFTs from many harsh conditions, the BEOL transistors may still be affected by gases in the surrounding environment during the formation of other BEOL devices. For example, BEOL transistors may be exposed to plasma and air in the surrounding environment. Ambient gases such as hydrogen may damage the layers of the BEOL transistors and reduce the efficiency of the manufactured devices. Therefore, various embodiments disclosed herein attempt to protect the TFTs by incorporating a hydrogen diffusion barrier film layer.

[0056] refer to Figure 1A , a first exemplary structure according to an embodiment of the present invention is shown before forming an array of memory structures according to various embodiments of the present invention. The first exemplary structure includes a substrate 8 including a semiconductor material layer 10. The substrate 8 may include: a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8; or a semiconductor-on-insulator layer, which includes the semiconductor material layer 10 as a top semiconductor layer located above a buried insulating layer (such as a silicon dioxide layer). The exemplary structure may include various device regions, which may include a memory array region 50, wherein an array of at least one non-volatile memory cell may be subsequently formed.

[0057] For example, the array of at least one nonvolatile memory cell may include resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase change memory (PCM) devices. The exemplary structure may also include a peripheral logic region 52, where electrical connections between each array of nonvolatile memory cells and peripheral circuits including field effect transistors may be subsequently formed. Areas of the memory array region 50 and the logic region 52 may be used to form various elements of the peripheral circuits.

[0058] During FEOL operations, semiconductor devices such as field effect transistors (FETs) may be formed on and / or in the semiconductor material layer 10. For example, a shallow trench isolation structure 12 may be formed in the upper portion of the semiconductor material layer 10 by forming a shallow trench and then filling the shallow trench with a dielectric material such as silicon dioxide. Other suitable dielectric materials are within the contemplation of the present invention. Various doped wells (not explicitly shown) may be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0059] A gate structure 20 may be formed above the top surface of the substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28, which is referred to herein as a gate stack (22, 24, 28). An ion implantation process may be performed to form an extended implant region, which may include a source extension region and a drain extension region. A dielectric gate spacer 26 may be formed around the gate stack (22, 24, 28). Each combination of a gate stack (22, 24, 28) and a dielectric gate spacer 26 constitutes a gate structure 20. An additional ion implantation process using the gate structure 20 as a self-aligned implantation mask may be performed to form a deep active region. Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may overlap with a portion of the extended implant region. Each combination of extended implant regions and deep active regions can constitute an active region 14, which can be a source region or a drain region, depending on the electrical bias. A semiconductor channel 15 can be formed below each gate stack (22, 24, 28) between adjacent pairs of active regions 14. A metal-semiconductor alloy region 18 can be formed on the top surface of each active region 14. A field effect transistor can be formed on the semiconductor material layer 10. Each field effect transistor may include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which is used as a source region and the other as a drain region) and an optional metal-semiconductor alloy region 18. A complementary metal oxide semiconductor (CMOS) circuit 75 can be provided on the semiconductor material layer 10, which may include peripheral circuits for an array of TFTs to be formed subsequently.

[0060] Subsequently, various interconnection hierarchical structures may be formed, which are formed before forming an array of fin-back gate field effect transistors and are referred to herein as lower interconnection hierarchical structures (L0, L1, L2). If a two-dimensional array of TFTs is to be formed above two levels of interconnection hierarchical metal lines, the lower interconnection hierarchical structures (L0, L1, L2) may include a contact hierarchical structure L0, a first interconnection hierarchical structure L1, and a second interconnection hierarchical structure L2. The contact hierarchical structure L0 may include: a planarization dielectric layer 31A, including a planarizable dielectric material such as silicon dioxide; and various contact via structures 41V, contacting a corresponding one of the active region 14 or the gate electrode 24 and formed in the planarization dielectric layer 31A. The first interconnection hierarchical structure L1 includes a first interconnection hierarchical dielectric layer 31B and a first metal line 41L formed in the first interconnection hierarchical dielectric layer 31B. The first interconnection hierarchical dielectric layer 31B is also referred to as a first line level dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnection level structure L2 includes a second interconnection level dielectric layer 32, which may include a first via level dielectric material layer and a second line level dielectric layer or a stack of line and via level dielectric material layers. The second interconnection level dielectric layer 32 may have a second interconnection level metal interconnect structure (42V, 42L) formed therein, which includes a first metal via structure 42V and a second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second interconnection level dielectric layer 32.

[0061] refer to Figure 1B , an array 95 of nonvolatile memory cells and TFT selector devices may be formed in the memory array region 50 above the second interconnect hierarchy structure L2. Details of the structure and processing steps of the array 95 of nonvolatile memory cells and TFT selector devices are described in detail subsequently below. A third interconnect hierarchy dielectric layer 33 may be formed during the formation of the array 95 of nonvolatile memory cells and TFT selector devices. The collection of all structures formed at the level of the array 95 of nonvolatile memory cells and TFT selector device transistors is referred to herein as the third interconnect hierarchy structure L3.

[0062] refer to Figure 1C, a third interconnection level metal interconnect structure (43V, 43L) may be formed in the third interconnection level dielectric layer 33. The third interconnection level metal interconnect structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L. An additional interconnection level structure may be subsequently formed, which is referred to herein as an upper interconnection level structure (L4, L5, L6, L7). For example, the upper interconnection level structure (L4, L5, L6, L7) may include a fourth interconnection level structure L4, a fifth interconnection level structure L5, a sixth interconnection level structure L6, and a seventh interconnection level structure L7. The fourth interconnection level structure L4 may include a fourth interconnection level dielectric layer 34 in which a fourth interconnection level metal interconnect structure (44V, 44L) is formed, and the fourth interconnection level metal interconnect structure may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnection level structure L5 may include a fifth interconnection level dielectric layer 35 having a fifth interconnection level metal interconnect structure (45V, 45L) formed therein, which may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnection level structure L6 may include a sixth interconnection level dielectric layer 36 having a sixth interconnection level metal interconnect structure (46V, 46L) formed therein, which may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection level structure L7 may include a seventh interconnection level dielectric layer 37 having a sixth metal via structure 47V (which is a seventh interconnection level metal interconnect structure) and a metal bonding pad 47B formed therein. The metal bonding pad 47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

[0063] Each interconnect level dielectric layer may be referred to as an interconnect level dielectric (ILD) layer 30. Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and a metal line located above the same interconnect level structure (L2-L7) may be formed into two different structures in sequence by using two single damascene processes, or may be formed into a single structure by using a dual damascene process at the same time. Each of the metal interconnect structures 40 may include a corresponding metal liner (such as a layer of TiN, TaN or WN having a thickness in the range of 2nm to 20nm) and a corresponding metal filling material (such as W, Cu, Co, Mo, Ru, other elemental metals or alloys or combinations thereof). Other suitable materials used as metal liner and metal filling material are within the contemplation of the present invention. Each etching stop dielectric layer and dielectric cap layer may be inserted between vertically adjacent pairs of ILD layers 30, or may be incorporated into one or more of the ILD layers 30.

[0064] Although the present invention is described using an embodiment in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed as a component of a third interconnect hierarchy L3, embodiments in which the array 95 of nonvolatile memory cells and TFT selector devices can be formed as a component of any other interconnect hierarchy (e.g., L1-L7) are expressly contemplated herein. In addition, although the present invention is described using an embodiment in which a set of eight interconnect hierarchical structures are formed, embodiments using a different number of interconnect hierarchical structures are expressly contemplated herein. In addition, embodiments in which two or more arrays 95 of nonvolatile memory cells and TFT selector devices can be provided within multiple interconnect hierarchical structures in the memory array region 50 are expressly contemplated herein. Although the present invention is described using an embodiment in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed in a single interconnect hierarchy, embodiments in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed above two vertically adjacent interconnect hierarchical structures are expressly contemplated herein.

[0065] Conventional TFTs include source and drain electrodes that contact a channel layer and overlap a gate electrode that is separated from the channel by a gate insulating layer. However, during manufacturing, the channel region of the channel layer may be degraded due to processing conditions such as deposition process plasma and / or contact with air. In addition, it may be difficult to precisely control the N + Formation of doped regions.

[0066] Figure 2A is a plan view of an intermediate structure of a TFT after depositing a first dielectric layer over a substrate according to various embodiments of the present invention. Figure 2B According to various embodiments of the present invention, Figure 2A A vertical cross-sectional view taken along the line A-A'. Figure 2A and Figure 2B , a first dielectric layer 102 may be deposited on a substrate 100. The substrate 100 may be any suitable substrate, such as a plastic, glass, or semiconductor substrate, and may include control elements formed during a FEOL process. In some embodiments, the substrate 100 may be an interconnect level dielectric (ILD) layer, such as an interconnect level dielectric (ILD) layer 33. The first dielectric layer 102 may be formed of any suitable dielectric material, as described above. The first dielectric layer 102 may be deposited using any suitable deposition process. Herein, suitable deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), sputtering, laser ablation, and the like.

[0067] Figure 3Ais a plan view of an intermediate structure of a TFT after forming a word line trench in a first dielectric layer according to various embodiments of the present invention. Figure 3B According to various embodiments of the present invention, Figure 3A A vertical cross-sectional view taken along the line A-A'. Figure 3A and Figure 3B , a photoresist layer 101 may be applied over the first dielectric layer 102. The photoresist layer 101 may be photolithographically patterned to form a line and space pattern including strips of photoresist material extending along a first horizontal direction hd1. An anisotropic etching process may be performed to etch unmasked portions of the first dielectric layer 102. Word line trenches 103 extending along the first horizontal direction hd1 may be formed in areas not masked by the strips of photoresist material. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0068] Figure 4A is a plan view of an intermediate structure of a TFT after depositing a metal filling material in a word line trench to form a word line according to various embodiments of the present invention. Figure 4B According to various embodiments of the present invention, Figure 4A A vertical cross-sectional view taken along the line A-A'. Figure 4A and Figure 4B , a conductive metal fill material may be deposited over the first dielectric layer 102 to fill the word line trench 103. A planarization process such as CMP may then be performed to planarize the upper surface of the first dielectric layer 102 and the word line 110, and remove any excess conductive metal fill material from the upper surface of the first dielectric layer 102 and the word line trench 103. The word line 110 may be formed of any suitable conductive metal fill material using any suitable deposition method described herein. For example, the word line 110 may be formed of copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, and the like. Other suitable conductive metal fill materials are within the contemplation of the present invention.

[0069] Figure 5A is a plan view of an intermediate structure of a TFT after deposition of gate dielectric blanket layer and semiconductor blanket layer materials according to various embodiments of the present invention. Figure 5B According to various embodiments of the present invention, Figure 5A A vertical cross-sectional view taken along the line A-A'. Figure 5A and Figure 5B, a blanket layer 116L of gate dielectric material and a blanket layer 120L of semiconductor material may be deposited on the first dielectric layer 102 to cover the word line 110. In particular, the blanket layer 116L of gate dielectric material may be formed of any suitable dielectric material using any suitable deposition process, as described herein. The blanket layer 120L of semiconductor material may be deposited using any suitable deposition process, as described herein. The blanket layer 120L of semiconductor material may include polycrystalline silicon, amorphous silicon, or a metal oxide semiconductor material, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x etc. However, other suitable semiconductor materials are within the contemplated scope of the present invention.

[0070] Fig. 6A is a plan view of an intermediate structure of a TFT after patterning the gate dielectric blanket layer and the semiconductor blanket layer according to various embodiments of the present invention. Figure 6B According to various embodiments of the present invention, Fig. 6A A vertical cross-sectional view taken along the line A-A'. Fig. 6A and Figure 6B , the semiconductor material blanket layer 120L may be patterned to form the semiconductor layer 120. In particular, a photoresist layer 101 may be applied over the semiconductor material blanket layer 120L. The photoresist layer 101 may be photolithographically patterned to form a line pattern including strips of photoresist material extending along the second horizontal direction hd2. An anisotropic etching process may be implemented to etch the unmasked portion of the semiconductor material blanket layer 120L. The semiconductor layer 120 and the gate dielectric 116 may be formed, both of which extend along the second horizontal direction hd2 in the area not masked by the strips of photoresist material. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0071] like Fig. 6A and Figure 6B As shown, the gate dielectric layer 116 may also be etched. However, in other embodiments, the blanket layer of semiconductor material 120L may be etched selectively to the gate dielectric layer (eg, the gate dielectric layer 116L may remain substantially unetched).

[0072] Fig. 7A is a plan view of an intermediate structure of a TFT after a hydrogen diffusion barrier film layer is deposited over the patterned gate dielectric layer and the semiconductor layer according to various embodiments of the present invention. Figure 7B According to various embodiments of the present invention, Fig. 7A A vertical cross-sectional view taken along the line A-A'. Fig. 7A and Figure 7B, a blanket layer 122L of barrier material may be deposited over the semiconductor layer 120 and the underlying gate dielectric 116. The blanket layer 122L of barrier material may be deposited using any suitable deposition process described herein, such as sputtering, CVD, etc. The blanket layer 122L of barrier material may include a dielectric hydrogen diffusion barrier material, such as aluminum oxide (Al2O3), silicon carbide, silicon oxynitride, stacked silicon dioxide / nitride, etc. However, other dielectric hydrogen diffusion barrier materials are within the scope of the present invention.

[0073] Fig. 8A is a plan view of an intermediate structure of a TFT after patterning a hydrogen diffusion barrier film according to various embodiments of the present invention. Figure 8B According to various embodiments of the present invention, Fig. 8A A vertical cross-sectional view taken along the line A-A'. Fig. 8A and Figure 8B , the hydrogen diffusion barrier film material layer 122L may be patterned to form a hydrogen diffusion barrier film 122. In particular, a photoresist layer 101 may be applied over the hydrogen diffusion barrier film material layer 122L. The photoresist layer 101 may be photolithographically patterned to form a line pattern including photoresist material strips extending along a first horizontal direction hd1. An anisotropic etching process may be performed to etch an unmasked portion of the hydrogen diffusion barrier film material layer 122L. A hydrogen diffusion barrier film 122 extending along the first horizontal direction hd1 may be formed in an area not masked by the photoresist material strips. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing. The resulting hydrogen diffusion barrier film 122 may have a thickness in the range of about 1 nm to about 200 nm, such as from about 1 nm to about 20 nm, but thicker or thinner hydrogen diffusion barrier films may be used.

[0074] Fig.9A is a plan view of an intermediate structure of a TFT after depositing a second dielectric layer according to various embodiments of the present invention. Fig. 9B According to various embodiments of the present invention, Fig.9A A vertical cross-sectional view taken along the line A-A'. Fig.9A and Fig. 9B , a second dielectric layer 106 may be deposited on the hydrogen diffusion barrier film 122, the semiconductor layer 120, the gate dielectric layer 116, and the first dielectric layer 102. In particular, the second dielectric layer 106 may be formed by depositing any suitable dielectric material, using any suitable deposition process, as described herein. For example, in some embodiments, the second dielectric layer 106 may be made of silicon dioxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiN x O y) is formed. Other suitable dielectric layer materials are within the contemplation of the present invention. The second dielectric layer 106 material can be the same as or different from the first dielectric layer 102 material. The second dielectric layer 106 substantially embeds the TFT device.

[0075] Fig.10 is a vertical cross-sectional view of a TFT during an annealing process step of forming an active region according to various embodiments of the present invention. Fig.10 , Fig.9A and Fig. 9B The embedded structure shown may undergo an annealing process. The annealing process diffuses hydrogen into portions of the semiconductor layer 120 to form active drain regions 120D and source regions 120S. In particular, Fig.9A and Fig. 9B The embedded structure shown may be heated to a temperature of at least 100° C., such as a temperature in the range of about 100° C. to about 300° C. In various embodiments, the annealing process may be performed in an atmosphere containing hydrogen (H2) or in an atmosphere containing H2 and nitrogen (N2). In some embodiments, the annealing may be performed in an inert atmosphere, and the second dielectric layer 106 may include trapped hydrogen.

[0076] Hydrogen may diffuse through the second dielectric layer 106 and into the opposing portion of the semiconductor layer 120 to form N + The doped source region 120S and drain region 120D. The hydrogen diffusion barrier film 122 can block the diffusion of ambient hydrogen into the semiconductor layer 120 region. Therefore, a semiconductor channel region 120C can be formed in the semiconductor layer 120, below the hydrogen diffusion barrier film 122, between the source region 120S and the drain region 120D. In this way, a self-aligned process can be used to form an active region. In particular, the source region 120S and the drain region 120D can have a higher hydrogen content (e.g., doping level) than the channel region 120C.

[0077] Fig.11A is a plan view of an intermediate structure of a TFT after forming an active area electrode via cavity according to various embodiments of the present invention. Fig. 11B According to various embodiments of the present invention, Fig.11A A vertical cross-sectional view taken along the line A-A'. Fig.11A and Fig. 11B , the second dielectric layer 106 may be patterned to form the active area electrode via cavity 105. In particular, a photoresist layer (not shown) may be applied over the second dielectric layer 106. The photoresist layer may be photolithographically patterned to form a pattern including the via spacing. The patterned photoresist layer may be patterned to represent any one of the various via spacings. For example, although in Fig.11A and Fig. 11B, substantially circular through-hole spacing is shown, but square, rectangular or any closed polygonal shape may be used. An anisotropic etching process may be implemented to etch the unmasked portion of the second dielectric layer 106. An active region electrode through-hole cavity 105 extending through the top surface of the second dielectric layer 106 may be formed to expose portions of the active source region 120S and the active drain region 120D. In some embodiments, the active region electrode through-hole cavity 105 may overlap the hydrogen diffusion barrier film 122. Thus, the sidewalls and top surface portions of the hydrogen diffusion barrier film 122 may be exposed in the bottom of the active region electrode through-hole cavity 105. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer (not shown) may then be removed, for example, by ashing.

[0078] Fig. 12A is a plan view of a complete structure of a TFT after forming an active area electrode according to various embodiments of the present invention. Fig. 12B According to various embodiments of the present invention, Fig. 12A A vertical cross-sectional view taken along the line A-A'. Fig. 12A and Fig. 12B , a source electrode 112 (e.g., a source line) and a drain electrode 114 (e.g., a bit line) may be formed in the active region electrode via cavity 105. In particular, a conductive metal filling material may be deposited over the second dielectric layer 106 and in the active region electrode via cavity 105. A planarization process such as CMP may then be performed to remove any excess conductive metal filling material. The planarization process may make the top surfaces of the source electrode 112 (e.g., a source line) and the drain electrode 114 (e.g., a bit line) coplanar with the top surface of the second dielectric layer 106. In some embodiments, before depositing the conductive metal filling material, a metal liner (not shown) such as TiN may be conformally deposited in the active region electrode via cavity 105 to provide better electrical connection between the source electrode 112 and the drain electrode 114 and the corresponding active source region 120S and the drain region 120D. A complete back-gated TFT 200 consistent with various embodiments of the present invention may be formed on the substrate 100.

[0079] Fig.13 is a plan semi-transparent diagram of the complete structure of the TFT 200 after forming the active area electrode according to various embodiments of the present invention. Fig. 12A , Fig. 12B and Fig.13, the source electrode 112 and the drain electrode 114 may overlap with the channel region 120C and the portion of the word line 110 in a vertical direction perpendicular to the plane of the substrate 100. In other words, the separation distance D between the source electrode 112 and the drain electrode 114 may be smaller than the width C of the channel region 120C. The separation distance D between the source electrode 112 and the drain electrode 114 may also be smaller than the width W of the word line 110. The source electrode 112 and the drain electrode 114 may be electrically connected to the source region 120S and the drain region 120D, respectively.

[0080] Fig.14A is a plan semi-transparent diagram of the complete structure of the back-gated TFT 300 according to various embodiments of the present invention. Fig. 14B is along Fig.14A A vertical cross-sectional view taken along the line A-A'. Fig.14A and Fig. 14B , the patterned photoresist layer used to form the active area electrode through hole cavity 105 may be modified so that the separation distance D between the source electrode 112 and the drain electrode 114 is greater than the width W of the word line 110. In particular, the source electrode 112 and the drain electrode 114 may vertically overlap with the source region 120S and the drain region 120D, but may not vertically overlap with the word line 110 or the channel region 120C. The width C of the channel region 120C may be equal to or less than the width W of the word line 110.

[0081] In an alternative embodiment, the front gate TFT 400 may be formed with a hydrogen diffusion barrier film to prevent hydrogen from accidentally diffusing into the channel region 120C. For example, in an alternative embodiment of forming the front gate TFT, the above-mentioned Figure 2A and Figure 2B The intermediate structure formed in the Fig.15A is a plan view of an intermediate structure of a TFT after depositing a metal filling material in the source line trench and the drain line trench to form source lines and drain lines according to various alternative embodiments of the present invention. Fig. 15B According to various optional embodiments of the present invention Fig.15A A vertical cross-sectional view taken along the line A-A'. Fig.15A and Fig. 15B, a photoresist layer (not shown) may be applied over the first dielectric layer 102. In the front gate TFT embodiment, the first dielectric layer 102 may include a dielectric hydrogen diffusion barrier material, such as aluminum oxide (Al2O3), silicon carbide, silicon oxynitride, stacked silicon dioxide / nitride, etc. The photoresist layer may be photolithographically patterned to form a line and space pattern, which includes a photoresist material strip extending along a first horizontal direction hd1 and extending periodically along a second horizontal direction hd2. An anisotropic etching process may be implemented to etch the unmasked portion of the first dielectric layer 102. A source line trench (not shown) and a bit (drain) line trench (not shown) extending along the first horizontal direction hd1 may be formed in an area not masked by the photoresist material strip. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer may then be removed, for example, by ashing.

[0082] A conductive metal filling material layer may be deposited over the first dielectric layer 102 and in the source line trench and the drain line trench to form a source line 112 and a bit (drain) line 114 within the first dielectric layer 102. Excess conductive metal filling material may be removed in a planarization process such as CMP, so that the top surfaces of the source line 112 and the bit (drain) line 114 are coplanar with the top surface of the first dielectric layer 102.

[0083] Fig.16A is a plan view of an intermediate structure of a front-gate TFT after depositing a semiconductor blanket layer over the source and drain lines according to various alternative embodiments of the present invention. Fig. 16B According to various optional embodiments of the present invention Fig.16A A vertical cross-sectional view taken along the line A-A'. Fig.16A and Fig. 16B A semiconductor material blanket layer 120L may be formed on the first dielectric layer 102 to cover the source line and the bit (drain) line 114. The semiconductor material blanket layer 120L may include any suitable semiconductor material, such as amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor material, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x etc. However, other suitable semiconductor materials are within the contemplated scope of the present invention.

[0084] Fig.17A is a plan view of an intermediate structure of a TFT after patterning a semiconductor channel over source and drain lines according to various alternative embodiments of the present invention. Fig. 17B According to various optional embodiments of the present invention Fig.17A A vertical cross-sectional view taken along the line A-A'. Fig.17A and Fig. 17B , the semiconductor material blanket layer 120L may be patterned to form the semiconductor layer 120. In particular, a photoresist layer 101 may be applied over the semiconductor material blanket layer 120L. The photoresist layer 101 may be photolithographically patterned to form a line pattern comprising strips of photoresist material extending along the second horizontal direction hd2. An anisotropic etching process may be performed to etch unmasked portions of the semiconductor material blanket layer 120L. A channel region 120C extending along the second horizontal direction hd2 may be formed in an area not masked by the strips of photoresist material. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0085] Fig.18A is a plan view of an intermediate structure of a TFT after depositing a hydrogen diffusion barrier film layer, a gate dielectric blanket layer, and a word line blanket layer over a semiconductor channel according to various alternative embodiments of the present invention. Fig.18B According to various embodiments of the present invention, Fig.18A A vertical cross-sectional view taken along the line A-A'. Fig.18A and Fig.18B , a blanket layer 122L of hydrogen diffusion barrier material, a blanket layer 116L of gate dielectric material, and a blanket layer 110L of conductive word line gate material may be sequentially deposited over the first semiconductor layer 102 and the channel region 120C. The layers 122L, 116L, 110L may be formed of materials and using deposition methods, as described above. For example, the blanket layer 122L of hydrogen diffusion barrier material may include Al2O3, the gate dielectric material layer 116L may include a dielectric material, and the blanket layer 110L of conductive word line gate material may include a conductive metal material, as discussed above.

[0086] Fig.19A is a plan view of an intermediate structure of a front-gate TFT after patterning a hydrogen diffusion barrier film, a gate dielectric layer, and a word line according to various alternative embodiments of the present invention. Fig.19B According to various embodiments of the present invention, Fig.19A A vertical cross-sectional view taken along the line A-A'. Fig.19A and Fig.19B, the hydrogen diffusion barrier blanket layer 122L, the gate dielectric material blanket layer 116L, and the conductive word line gate material blanket layer 110L may be patterned to form the hydrogen diffusion barrier film 122, the gate dielectric layer 116, and the word line 110 (e.g., gate electrode). In particular, a photoresist layer 101 may be applied over the conductive word line gate material blanket layer 110L and the underlying gate dielectric material blanket layer 116L and hydrogen diffusion barrier blanket layer 122L. The photoresist layer 101 may be photolithographically patterned to form a line pattern including strips of photoresist material extending along a first horizontal direction hd1. An anisotropic etching process may be performed to etch unmasked portions of the hydrogen diffusion barrier blanket layer 122L, the gate dielectric material blanket layer 116L, and the conductive word line gate material blanket layer 110L. A hydrogen diffusion barrier film 122, a gate dielectric layer 116, and a word line 110 extending along a first horizontal direction hd1 may be formed in an area not masked by the photoresist material strip. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0087] Fig. 20A is a plan view of an intermediate structure of a front gate TFT after depositing a second dielectric layer according to various alternative embodiments of the present invention. Fig. 20B According to various optional embodiments of the present invention Fig. 20A A vertical cross-sectional view taken along the line A-A'. Fig. 20A and Fig. 20B , a second dielectric layer 106 may be deposited on the hydrogen diffusion barrier film 122, the semiconductor layer 120, the gate dielectric layer 116, and the first dielectric layer 102. In particular, the second dielectric layer 106 may be formed by depositing any suitable dielectric material, using any suitable deposition process, as described herein. For example, in some embodiments, the second dielectric layer 106 may be made of silicon dioxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiN x O y ) is formed. Other suitable dielectric layer materials are within the scope of the present invention. The second dielectric layer 106 material can be the same as or different from the first dielectric layer 102 material. The second dielectric layer 106 substantially embeds the front gate TFT device. A planarization process such as CMP can be performed to remove any excess portion of the second dielectric layer 106. The top surface of the second dielectric layer 106 and the top surface of the word line 110 can be coplanar.

[0088] Fig.21 is a vertical cross-sectional view of a front gate-controlled TFT during an annealing process step for forming an active region according to various alternative embodiments of the present invention. Fig.21 , Fig. 20A and Fig. 20BThe embedded structure shown may undergo an annealing process. The annealing process diffuses hydrogen into portions of the semiconductor layer 120 to form active drain regions 120D and source regions 120S. In particular, Fig.9A and Fig. 9B The embedded structure shown may be heated to a temperature of at least 100° C., such as a temperature in the range of about 100° C. to about 300° C. In various embodiments, the annealing process may be performed in an atmosphere containing hydrogen (H2) or in an atmosphere containing H2 and nitrogen (N2). In some embodiments, the annealing may be performed in an inert atmosphere, and the second dielectric layer 106 may include trapped hydrogen.

[0089] Hydrogen may diffuse through the second dielectric layer 106 and into the opposing portion of the semiconductor layer 120 to form N + Doped source region 120S and drain region 120D. The hydrogen diffusion barrier film 122 can block the diffusion of ambient hydrogen into the semiconductor layer 120 region. Therefore, a semiconductor channel region 120C can be formed in the semiconductor layer 120, below the hydrogen diffusion barrier film 122, between the source region 120S and the drain region 120D. In this way, a self-aligned process can be used to form an active region. In particular, the source region 120S and the drain region 120D can have a higher hydrogen content (e.g., doping level) than the channel region 120C. In particular, the channel region 120C can be substantially free of hydrogen doping. Therefore, at least a front gate-controlled TFT 400 can be formed on the substrate 100.

[0090] A separation distance D between the source line 112 and the bit (drain) line 114 may be greater than a width W of the channel region 120C and the word line 110. In other words, the source line 112 and the bit (drain) line 114 may not vertically overlap the channel region 120C or the word line 110. The source line 112 and the bit (drain) line 114 may be electrically connected to the source region 120S and the drain region 120D, respectively.

[0091] Fig. 22 is a process flow chart of a method for forming a back-gated TFT 200 according to various embodiments of the present invention. FIG. 2A to FIG. 14B and Fig. 22In operation 2201, a first dielectric layer 102 may be deposited over a substrate 100. In operation 2202, the first dielectric layer 102 may be patterned to form a wordline trench 103. In operation 2203, a metal filling material may be deposited over the first dielectric layer 102 and in the wordline trench 103 to form a wordline 110. The first dielectric layer 102 and the wordline 110 may be planarized so that the top surfaces of the first dielectric layer 102 and the wordline are coplanar. In operation 2204, a gate dielectric blanket layer 116L and a semiconductor material blanket layer 120L may be sequentially deposited over the first dielectric layer 102 and the wordline 110. In operation 2205, the semiconductor material blanket layer 120L and the gate dielectric blanket layer 116L may be patterned to form a first channel portion 120 and a gate dielectric layer 116. In operation 2206, a hydrogen diffusion barrier blanket layer 122L may be deposited over the first channel portion 120 and the gate dielectric layer 116. In operation 2207, the hydrogen diffusion barrier blanket layer 122L may be patterned to form a hydrogen diffusion barrier film 122. In operation 2208, a second dielectric layer 106 may be deposited over the hydrogen diffusion barrier film, the semiconductor channel 120, and the gate dielectric layer 116. In operation 2209, the entire intermediate structure may be annealed to diffuse ambient hydrogen into portions of the semiconductor layer 120 to form active drain regions 120D and source regions 120S. In operation 2210, the second dielectric layer 106 may be patterned to form an active region electrode via cavity 105. In operation 2211, a metal fill material may be deposited over the second dielectric layer 106 and in the active region electrode via cavity 105 to form a source electrode 112 and a drain electrode 114. The second dielectric layer 106 and the source and drain electrodes 112 and 114 may be planarized such that top surfaces of the second dielectric layer 106 and the source and drain electrodes 112 and 114 are coplanar.

[0092] Fig.23 is a process flow chart of a method for forming a front gate TFT 400 according to various alternative embodiments of the present invention. Figure 2A , Figure 2B and FIG. 15A to FIG. 21In operation 2301, a first dielectric layer 102 may be deposited over the substrate 100. In a front-gate TFT embodiment, the first dielectric layer 102 may be formed of a dielectric hydrogen diffusion barrier material, such as aluminum oxide (Al2O3), silicon carbide, silicon oxynitride, stacked silicon dioxide / nitride, etc. In operation 2302, the first dielectric layer 102 may be patterned to form source line trenches and bit (drain) line trenches 103. A metal filling material may be deposited over the first dielectric layer 102 and in the source line trenches and bit (drain) line trenches 103 to form source lines 112 and bit (drain) lines 114. The first dielectric layer 102 and the source line 112 and the bit (drain) line 114 may be planarized so that the top surfaces of the first dielectric layer 102 and the source line 112 and the bit (drain) line 114 are coplanar. In operation 2303, a semiconductor material blanket layer 120L may be deposited over the first dielectric layer 102 and the source line 112 and the bit (drain) line 114. In operation 2304, the semiconductor material blanket layer 120L may be patterned to form a first channel portion 120. In operation 2305, a hydrogen diffusion barrier blanket layer 122L, a gate dielectric blanket layer 116L, and a conductive word line gate material blanket layer 110L may be sequentially deposited over the first channel portion 120. In operation 2306, the hydrogen diffusion barrier blanket layer 122L, the gate dielectric blanket layer 116L, and the conductive word line gate material blanket layer 110L may be patterned to form a hydrogen diffusion barrier film 122, a gate dielectric layer 116, and a word line 110. In operation 2307, a second dielectric layer 106 may be deposited over the word line 110, the gate dielectric layer 116, the hydrogen diffusion barrier film 122, and the semiconductor channel 120. The second dielectric layer 106 and wordline 110 may be planarized such that top surfaces of wordline 110 and second dielectric layer 106 are coplanar. In operation 2308, the entire intermediate structure may be annealed to diffuse ambient hydrogen into portions of semiconductor layer 120 to form active drain region 120D and source region 120S.

[0093] According to various embodiments, a transistor including a patterned hydrogen diffusion barrier film disposed on a semiconductor layer is provided. The hydrogen diffusion barrier film blocks hydrogen from penetrating into a channel region of the semiconductor layer during an annealing process, wherein hydrogen is doped into other portions of the semiconductor layer to form an active source region and a drain region. Therefore, the channel region is protected from damage during processing, and the formation of the source region and the drain region can be precisely controlled in a self-aligned process.

[0094] With reference to all the drawings and according to various embodiments of the present invention, a thin film transistor (TFT) device is provided. The TFT includes: a word line 110 disposed on a substrate 100; a semiconductor layer 120 disposed on the substrate 100, the semiconductor layer 120 including a source region 120S, a drain region 120D and a channel region 120C, the channel region 120C being disposed between the source region 120S and the drain region 120D and overlapping the word line 110 in a vertical direction perpendicular to the plane of the substrate 100; a hydrogen diffusion barrier film 122 overlapping the channel region 120C in a vertical direction; a gate dielectric layer 116 disposed between the channel region 120C and the word line 110; and a source electrode 112 and a drain electrode 114 electrically coupled to the respective source region 120S and the drain region 120D.

[0095] In one embodiment, the source region 120S and the drain region 120D of the TFT 200 may have a higher hydrogen concentration than the channel region 120C. In another embodiment, the hydrogen diffusion barrier film 122 may have a thickness in a range of about 1 nm to about 200 nm. In another embodiment, the hydrogen diffusion barrier film 122 of the TFT 200 includes a dielectric material. In another embodiment, the hydrogen diffusion barrier film 122 of the TFT 200 includes Al2O3. In another embodiment, the first dielectric layer 102 of the TFT 200 may be disposed between the semiconductor layer 120 and the substrate 100; and the second dielectric layer 106 may be disposed on the first dielectric layer 102, thereby covering the semiconductor layer 120 and the hydrogen diffusion barrier film 122. In another embodiment, the source electrode 112 and the drain electrode 114 may be embedded in the second dielectric layer 106; and the word line 110 may be embedded in the first dielectric layer 102. In another embodiment, the source electrode 112 and the drain electrode 114 of the TFT 200 may overlap opposite portions of the word line 100 in the vertical direction. In another embodiment, the source electrode 112 and the drain electrode 114 may be spaced farther apart than the width W of the word line 110. In another embodiment, the hydrogen diffusion barrier film 122 may be disposed between the second dielectric layer 106 and the channel region 120C; and the gate dielectric layer 116 may be disposed between the semiconductor layer 120 and the word line 110. In another embodiment, the source electrode 112 and the drain electrode 114 may be embedded in the first dielectric layer 102; and the word line 110 may be embedded in the second dielectric layer 106. In another embodiment, the first dielectric layer 102 may include silicon dioxide; and the second dielectric layer 106 may include silicon dioxide or silicon nitride. In another embodiment, the TFT 200 may have a source region 120S and a drain region 120D formed by a thermal annealing process.

[0096] With reference to all the drawings and according to various embodiments of the present invention, a TFT 400 is provided. The TFT 400 includes: a word line 110 disposed on a substrate 100; a semiconductor layer 120 disposed on the substrate 100, the semiconductor layer 120 including a source region 120S, a drain region 120D and a channel region 120C, the channel region 120C being disposed between the source region 120S and the drain region 120D and overlapping the word line 110 in a vertical direction perpendicular to the plane of the substrate 100; a hydrogen diffusion barrier film 122 overlapping the channel region 120C in a vertical direction; a gate dielectric layer 116 disposed in the channel region 116; 20C and the word line 110; the source electrode 112 and the drain electrode 114 are electrically coupled to the corresponding source region 120S and the drain region 120D; the first dielectric layer 102 is arranged between the semiconductor layer 120 and the substrate 100; and the second dielectric layer 106 is arranged on the first dielectric layer 102, covering the semiconductor layer 120 and the hydrogen diffusion barrier film 122, wherein the source region 120S and the drain region 120D directly contact the second dielectric layer 106; and the channel region 120C directly contacts the hydrogen diffusion barrier film 122.

[0097] Various embodiments provide a method for forming a transistor, the method comprising: depositing a first dielectric layer 102 on a substrate 100; forming a semiconductor layer 120 on the first dielectric layer 102; forming a hydrogen diffusion barrier film 122 on a channel region 120C of the semiconductor layer 120; depositing a second dielectric layer 106 on the semiconductor layer 120 and the hydrogen diffusion barrier film 122; and performing a thermal annealing process to diffuse hydrogen into the semiconductor layer 120 to form a source region 120S and a drain region 120D on opposite sides of the channel region 120C.

[0098] Some embodiments of the present application provide a transistor, comprising: a word line, arranged on a substrate; a semiconductor layer, arranged on the substrate, the semiconductor layer having a source region, a drain region and a channel region, the channel region being arranged between the source region and the drain region and overlapping with the word line in a vertical direction perpendicular to the plane of the substrate; a hydrogen diffusion barrier film, overlapping with the channel region in a vertical direction; a gate dielectric layer, arranged between the channel region and the word line; and a source electrode and a drain electrode, electrically coupled to the corresponding source region and the drain region. In some embodiments, the source region and the drain region have a higher hydrogen concentration than the channel region. In some embodiments, the thickness of the hydrogen diffusion barrier film is in a range of about 1 nm to about 200 nm. In some embodiments, the hydrogen diffusion barrier film comprises a dielectric material. In some embodiments, the hydrogen diffusion barrier film comprises Al2O3. In some embodiments, the transistor further comprises: a first dielectric layer, arranged between the semiconductor layer and the substrate; and a second dielectric layer, arranged on the first dielectric layer, covering the semiconductor layer and the hydrogen diffusion barrier film. In some embodiments, the source electrode and the drain electrode are embedded in the second dielectric layer; and the word line is embedded in the first dielectric layer. In some embodiments, the source electrode and the drain electrode overlap with the opposite portion of the word line in the vertical direction. In some embodiments, the source electrode and the drain electrode are spaced farther apart than the width of the word line. In some embodiments, the hydrogen diffusion barrier film is disposed between the second dielectric layer and the channel region; and the gate insulating layer is disposed between the semiconductor layer and the word line. In some embodiments, the source electrode and the drain electrode are embedded in the first dielectric layer; and the word line is embedded in the second dielectric layer. In some embodiments, the hydrogen diffusion barrier film is disposed between the gate dielectric layer and the channel region; and the gate dielectric layer is disposed between the hydrogen diffusion barrier film and the word line. In some embodiments, the first dielectric layer includes silicon dioxide; and the second dielectric layer includes silicon dioxide or silicon nitride. In some embodiments, the semiconductor layer includes a metal oxide semiconductor material. In some embodiments, the source region and the drain region are formed by a thermal annealing process.

[0099] Some other embodiments of the present application provide a transistor, comprising: a word line, arranged on a substrate; a semiconductor layer, arranged on the substrate, the semiconductor layer comprising a source region, a drain region and a channel region, the channel region being arranged between the source region and the drain region and overlapping with the word line in a vertical direction perpendicular to the plane of the substrate; a hydrogen diffusion barrier film, overlapping with the channel region in a vertical direction; a gate dielectric layer, arranged between the channel region and the word line; a source electrode and a drain electrode, electrically coupled to the corresponding source region and the drain region; a first dielectric layer, arranged between the semiconductor layer and the substrate; a second dielectric layer, arranged on the first dielectric layer, covering the semiconductor layer and the hydrogen diffusion barrier film, wherein the source region and the drain region directly contact the second dielectric layer; and the channel region directly contacts the hydrogen diffusion barrier film. In some embodiments, the source region and the drain region have a higher hydrogen content than the channel region; and the hydrogen diffusion barrier film comprises a dielectric material; and the semiconductor layer comprises a metal oxide semiconductor material.

[0100] Some other embodiments of the present application provide a method for forming a transistor, comprising: depositing a first dielectric layer on a substrate; forming a semiconductor layer on the first dielectric layer; forming a hydrogen diffusion barrier film on a channel region of the semiconductor layer; depositing a second dielectric layer on the semiconductor layer and the hydrogen diffusion barrier film; and performing a thermal annealing process to diffuse hydrogen into the semiconductor layer to form a source region and a drain region on opposite sides of the channel region. In some embodiments, performing the thermal annealing process comprises heating the substrate at a temperature in a range of about 100° C. to about 300° C. in an atmosphere containing hydrogen (H2). In some embodiments, the method further comprises: forming a word line and a source electrode and a drain electrode in different first and second dielectric layers; and forming a gate dielectric layer between the word line and the channel region.

[0101] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A transistor, comprising: A word line is disposed on the substrate; A semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region and a channel region, the channel region being disposed between the source region and the drain region and overlapping the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier film overlapping the channel region in a vertical direction; a gate dielectric layer disposed between the channel region and the word line; as well as A source electrode and a drain electrode are electrically coupled to the corresponding source region and drain region, wherein the source electrode and the drain electrode are in physical contact with a portion of a top surface and a sidewall of the hydrogen diffusion barrier film, and a distance between the source electrode and the drain electrode is smaller than a width of the word line and a width of the channel region.

2. The transistor according to claim 1, wherein The source region and the drain region have a higher hydrogen concentration than the channel region.

3. The transistor according to claim 1, wherein The thickness of the hydrogen diffusion barrier film is in the range of 1 nm to 200 nm.

4. The transistor according to claim 1, wherein The hydrogen diffusion barrier film includes a dielectric material.

5. The transistor according to claim 1, wherein The hydrogen diffusion barrier film includes Al2O3.

6. The transistor according to claim 1, further comprising: A first dielectric layer disposed between the semiconductor layer and the substrate; as well as The second dielectric layer is disposed on the first dielectric layer and covers the semiconductor layer and the hydrogen diffusion barrier film.

7. The transistor according to claim 6, wherein: The source electrode and the drain electrode are embedded in the second dielectric layer; and The word lines are embedded in the first dielectric layer.

8. The transistor according to claim 7, wherein: The source electrode and the drain electrode overlap opposite portions of the word line in a vertical direction.

9. The transistor according to claim 7, wherein: The source electrode and the drain electrode are spaced farther apart than a width of the word line.

10. The transistor according to claim 7, wherein: The hydrogen diffusion barrier film is disposed between the second dielectric layer and the channel region; and The gate dielectric layer is disposed between the semiconductor layer and the word line.

11. The transistor according to claim 6, wherein: Top surfaces of the source electrode and the drain electrode are flush with a top surface of the second dielectric layer.

12. The transistor of claim 1, wherein: The hydrogen diffusion barrier film includes a dielectric material.

13. The transistor according to claim 6, wherein: The first dielectric layer comprises silicon dioxide; and The second dielectric layer includes silicon dioxide or silicon nitride.

14. The transistor according to claim 1, wherein The semiconductor layer includes a metal oxide semiconductor material.

15. The transistor according to claim 1, wherein The source region and the drain region are formed by a thermal annealing process.

16. A transistor comprising: A word line is disposed on the substrate; A semiconductor layer disposed on the substrate, the semiconductor layer comprising a source region, a drain region and a channel region, the channel region being disposed between the source region and the drain region and overlapping the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier film overlapping the channel region in a vertical direction; a gate dielectric layer disposed between the channel region and the word line; a source electrode and a drain electrode electrically coupled to the corresponding source region and the drain region; A first dielectric layer disposed between the semiconductor layer and the substrate; A second dielectric layer is disposed on the first dielectric layer and covers the semiconductor layer and the hydrogen diffusion barrier film, wherein: The source region and the drain region directly contact the second dielectric layer; and The channel region directly contacts the hydrogen diffusion barrier film, The source electrode and the drain electrode are in physical contact with a portion of a top surface and a sidewall of the hydrogen diffusion barrier film, and a distance between the source electrode and the drain electrode is smaller than a width of the word line and a width of the channel region.

17. The transistor of claim 16, wherein: The source region and the drain region have a higher hydrogen content than the channel region; and The hydrogen diffusion barrier film includes a dielectric material; and The semiconductor layer includes a metal oxide semiconductor material.

18. A method of forming a transistor, comprising: depositing a first dielectric layer on the substrate; forming a word line in the first dielectric layer; forming a semiconductor layer on the first dielectric layer; forming a hydrogen diffusion barrier film on a channel region of the semiconductor layer; depositing a second dielectric layer on the semiconductor layer and the hydrogen diffusion barrier film; performing a thermal annealing process to diffuse hydrogen into the semiconductor layer to form a source region and a drain region on opposite sides of the channel region; as well as forming a source electrode and a drain electrode in the second dielectric layer, The source electrode and the drain electrode are in physical contact with a portion of a top surface and a sidewall of the hydrogen diffusion barrier film, and a distance between the source electrode and the drain electrode is smaller than a width of the word line and a width of the channel region.

19. The method according to claim 18, wherein: Performing the thermal annealing process includes heating the substrate at a temperature ranging from 100° C. to 300° C. in an atmosphere containing hydrogen.

20. The method of claim 18, further comprising: A gate dielectric layer is formed between the word line and the channel region.

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