Image pickup device

Abstract

The present invention provides an image pickup device, comprising: a photodiode, which is configured to generate electric charges according to the amount of light received; a first transistor, which is connected to the photodiode and a power supply; a second transistor, which is connected to the photodiode and a capacitor, wherein the second transistor is configured to transfer a portion of the charge in the photodiode to the capacitor, and wherein the first transistor is configured to discharge the charge in the photodiode based on the amount of charge in the capacitor.

Description

[0001] This application is a divisional application of patent application No. 201780028797.8, whose application date is April 12, 2017 and whose invention name is “Image pickup device, solid-state image pickup element and control method of image pickup device”. Technical Field

[0002] The present technology relates to an image pickup device, a solid-state image pickup element, and a control method of the image pickup device. In particular, the present technology relates to an image pickup device, a solid-state image pickup element, and a control method of the image pickup device by which image data with an expanded dynamic range is generated. Background Art

[0003] In the past, in image pickup devices, solid-state image pickup elements for picking up image data have been used. The dynamic range of the ratio between the maximum value and the minimum value of the amount of light that can be photoelectrically converted by a single exposure by the solid-state image pickup element is generally narrower than the ratio between the maximum value and the minimum value of the amount of light of natural light. In the case where the dynamic range is narrow in this way, overexposure or underexposure sometimes occurs, and white jumps or blackouts are caused in the image data, resulting in deterioration of image quality. In order to suppress such deterioration of image quality, an image pickup device has been proposed, which performs multiple exposures for different exposure periods to generate multiple image data and synthesizes the image data, thereby generating image data having a dynamic range greater than the dynamic range before synthesis (for example, Patent Document 1).

[0004] [Citation list]

[0005] [Patent Document]

[0006] Patent Document 1: JP 2009-88927A Summary of the invention

[0007] [Technical issues]

[0008] With the above-mentioned prior art, since the dynamic range is expanded, it is possible to suppress the degradation of image quality caused by overexposure or underexposure. However, according to this configuration, since a plurality of image data having different exposure periods must be picked up each time synthesis is performed, there is a problem that the frame rate of the synthesized frame is reduced compared to an alternative case in which such synthesis is not performed. For example, in a case in which a frame is picked up at a frame rate of 60 Hz and two frames are synthesized to generate a synthesized frame with an increased dynamic range, the frame rate of the synthesized frame is reduced to 30 Hz.

[0009] The present technology has been made in view of the above-described circumstances, and an object of the present technology is to suppress a decrease in a frame rate in a solid-state image pickup element that generates a frame with an increased dynamic range.

[0010] [Solution to the problem]

[0011] The present technology has been made to eliminate the above-mentioned problems, and according to a first aspect of the present technology, there is provided an image pickup device and a control method of the image pickup device, the image pickup device including: a measuring section configured to measure the amount of light received in each of a plurality of regions to generate a measurement result; a selecting section configured to select one of a plurality of exposure periods different from each other based on the measurement result of each of the plurality of regions; a digital signal generating section configured to perform exposure within the selected exposure period for each of the plurality of regions to generate a digital signal; and an image processing section configured to adjust the value of the digital signal generated for each of the plurality of regions based on the measurement result. Thus, such an effect is produced that the exposure period is selected in response to the measurement result of the amount of light received in each of the plurality of regions, and the value of the digital signal is adjusted based on the measurement result.

[0012] In addition, in the first aspect, each of the plurality of regions may be constituted by one pixel. Thus, an effect is produced in which an exposure period is selected in response to a measurement result of a light reception amount of each of the plurality of pixels.

[0013] In addition, in the first aspect, each of the plurality of regions may be constituted by a plurality of pixels. Thus, an effect is produced in which an exposure period is selected in response to a measurement result of a received light amount in each of the regions each constituted by a plurality of pixels.

[0014] In addition, in the first aspect, the measuring unit may determine whether the received light amount is higher than a given value, generate a determination mark indicating the result of the determination, and store it as the measurement result. This produces an effect of determining whether the received light amount is higher than a given value.

[0015] In addition, in the first aspect, the image pickup device may further include: a counting section configured to count a count value in synchronization with a given clock signal; a photodiode configured to generate a charge according to the amount of received light; and a comparator configured to compare a given ramp signal and a voltage according to the amount of the charge with each other, and output the result of the comparison as a comparator output signal. In the case where the comparator output signal is inverted, the digital signal generating section maintains the count value as the digital signal, and the measuring section includes: a determination mark generating section configured to compare the count value and a given set value according to the given value with each other, and output the result of the comparison as a latch input signal; and a determination mark holding section configured to maintain the value of the latch input signal as the determination mark when the comparator output signal is inverted. Thus, an effect is produced in which the count value is maintained as a digital signal when the comparator output signal is inverted.

[0016] In the first aspect, the counting section may first perform one of the count value incrementing and decrementing processes and then perform the other process, thereby producing an effect that after performing one of the count value incrementing and decrementing processes, the other process is performed.

[0017] Furthermore, in the first aspect, the image processing section may perform at least one of a process of amplifying the digital signal in any region among the plurality of regions where the amount of received light is higher than the given value and another process of attenuating the digital signal in any region among the plurality of regions where the amount of received light does not exceed the given value, thereby producing an effect of amplifying or attenuating the digital signal.

[0018] Furthermore, in the first aspect, the measuring section may hold the measurement result whenever a given image pickup cycle passes, and the selecting section may select one of the plurality of exposure periods in each of the given image pickup cycles based on the measurement result held before the image pickup cycle. Thus, an effect is produced in which, in each image pickup cycle, an exposure period is selected based on the measurement result held before the image pickup cycle.

[0019] Furthermore, in the first aspect, the selection section may select one of the plurality of exposure periods in each of the given image pickup cycles based on the measurement result generated in the image pickup cycle. Thus, an effect is produced in which, in each image pickup cycle, an exposure period is selected based on the measurement result generated in the image pickup cycle.

[0020] Furthermore, in the first aspect, the measuring section, the selecting section, and the digital signal generating section may be provided in a solid-state image pickup element, and the circuit in the solid-state image pickup element may be dispersed over a plurality of stacked semiconductor substrates, thereby producing an effect in which a digital signal is generated by the circuit in the solid-state image pickup element provided over a plurality of stacked semiconductor substrates.

[0021] On the other hand, according to a second aspect of the present technology, there is provided a solid-state image pickup element, including: a measuring section configured to measure the amount of light received in each of a plurality of regions to generate a measurement result; a selecting section configured to select one of a plurality of exposure periods different from each other based on the measurement result of each of the plurality of regions; and a digital signal generating section configured to perform exposure in the selected exposure period for each of the plurality of regions to generate a digital signal indicating the exposure amount. Thus, an effect is produced in which the exposure period is selected in response to the measurement result of the amount of light received in each of the plurality of regions.

[0022] [Beneficial Effects of the Invention]

[0023] According to the present technology, an excellent effect of suppressing a decrease in frame rate in a solid-state image pickup element that generates frames with an expanded dynamic range is obtained. It should be noted that the effects described here are not necessarily restrictive and may be some of the effects described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 : is a block diagram showing a configuration example of an image pickup device in the first embodiment of the present technology.

[0025] Figure 2 : is a block diagram showing a configuration example of a solid-state image pickup element in the first embodiment of the present technology.

[0026] Figure 3 : is a block diagram showing an example of a pixel array section in the first embodiment of the present technology.

[0027] Figure 4 : is a circuit diagram showing a configuration example of a pixel circuit and a counting section in the first embodiment of the present technology.

[0028] Figure 5 2 is a view showing an example of the operation of the determination flag holding section in the first embodiment of the present technology.

[0029] Figure 6 : is a view showing an example of the operation of the determination flag generating section in the first embodiment of the present technology.

[0030] Figure 7is a timing chart showing an example of the operation of the solid-state image pickup element in the first embodiment of the present technology.

[0031] Figure 8 is a timing chart showing an example of the operation of the solid-state image pickup element according to the comparative example.

[0032] Fig. 9 is a timing chart showing an example of the operation in the determination period of the solid-state image pickup element in the first embodiment of the present technology.

[0033] Fig.10 : is a timing chart showing an example of the operation in the image pickup determination period of the solid-state image pickup element in the first embodiment of the present technology.

[0034] Fig.11 : is a block diagram showing an example of an image processing section in the first embodiment of the present technology.

[0035] Fig.12 is a flowchart showing an example of the operation of the image pickup device in the first embodiment of the present technology.

[0036] Fig.13 is a flowchart showing an example of image pickup processing in the first embodiment of the present technology.

[0037] Fig.14 : is a flowchart showing an example of HDR (High Dynamic Range) image generation processing in the first embodiment of the present technology.

[0038] Fig.15 : is a block diagram showing a configuration example of a solid-state image pickup element in a second embodiment of the present technology.

[0039] Fig.16 : is a circuit diagram showing a configuration example of a pixel circuit in a second embodiment of the present technology.

[0040] Fig.17 : is a timing chart showing an example of the operation in the determination period of the solid-state image pickup element in the second embodiment of the present technology.

[0041] Fig.18 1 is a flowchart showing an example of the operation during the image pickup determination period of the solid-state image pickup element in the second embodiment of the present technology.

[0042] Fig.19 It is a block diagram showing a configuration example of an image processing unit in the second embodiment of the present technology.

[0043] Fig. 20 It is a block diagram showing a configuration example of a pixel array unit in a third embodiment of the present technology.

[0044] Fig.21 : is a circuit diagram showing a configuration example of a pixel circuit in a third embodiment of the present technology.

[0045] Fig. 22 : is a perspective view showing a configuration example of a solid-state image pickup element in a fourth embodiment of the present technology.

[0046] Fig.23 : is a block diagram showing a configuration example of a solid-state image pickup element in a fourth embodiment of the present technology.

[0047] Fig.24 : is a circuit diagram showing a configuration example of a pixel circuit in a fifth embodiment of the present technology.

[0048] Fig.25 It is an example of a potential diagram up to an intermediate potential transfer of a pixel circuit in the fifth embodiment of the present technology.

[0049] Fig.26 This is an example of a potential diagram at the time of complete transfer of the pixel circuit in the fifth embodiment of the present technology.

[0050] Fig. 27 is a timing chart showing an example of the operation of the image pickup device in the fifth embodiment of the present technology.

[0051] Fig.28 1 is a timing chart showing an example of operation until intermediate potential transfer of a pixel circuit having a large amount of received light in the fifth embodiment of the present technology.

[0052] Fig.29 1 is a timing chart showing an example of operation until complete transfer of a pixel circuit having a large amount of received light in the fifth embodiment of the present technology.

[0053] Fig.30 1 is a timing chart showing an example of operation until intermediate potential transfer of a pixel circuit with a small amount of received light in the fifth embodiment of the present technology.

[0054] Fig.31 : is a timing chart showing an example of operation until complete transfer of a pixel circuit with a small amount of received light in the fifth embodiment of the present technology. DETAILED DESCRIPTION

[0055] Hereinafter, a mode for carrying out the present technology (hereinafter referred to as an embodiment) is described. Note that the description is given in the following order.

[0056] 1. First Embodiment (Example of Selecting Exposure Period for Each Pixel in Response to Light Received Amount)

[0057] 2. Second Embodiment (Example of Selecting an Exposure Period for Each Pixel in Response to the Light Received Amount and Generating a Digital Signal by an Up-Down Counter)

[0058] 3. Third Embodiment (Example of Selecting Exposure Period for Each Light Receiving Area in Response to Light Receiving Amount)

[0059] 4. Fourth Embodiment (Example of Selecting Exposure Period for Each Pixel in Responsive to the Quantity of Received Light in the Laminated Solid-State Image Pickup Element)

[0060] 5. Fifth Embodiment (Example of Selecting an Exposure Period for Each Pixel in Response to the Quantity of Received Light Measured in an Image Pickup Period)

[0061] <1. First Implementation Method>

[0062] [Configuration Example of Image Pickup Device]

[0063] Figure 1 1 is a block diagram showing a configuration example of the image pickup device 100 in the first embodiment. The image pickup device 100 is a device that picks up image data, and includes an image pickup lens 110, a solid-state image pickup element 200, an image processing section 120, an image pickup control section 130, and a recording section 140. For example, a digital camera, a smartphone or an information processing device having an image pickup function, or the like is assumed as the image pickup device 100.

[0064] The image pickup lens 110 condenses light and introduces the light to the solid-state image pickup element 200. The solid-state image pickup element 200 generates image data under the control of the image pickup control section 130. The solid-state image pickup element 200 supplies the generated image data to the image processing section 120 via the signal line 209.

[0065] The image processing section 120 performs various image processing on the image data under the control of the image pickup control section 130. The image processing includes a high dynamic range synthesis process for expanding the dynamic range of the image data compared with the previous process. The image processing section 120 supplies the image data after the image processing to the recording section 140 via the signal line 129. The recording section 140 records the image data.

[0066] The image pickup control section 130 controls the entire image pickup apparatus 100. The image pickup control section 130 supplies a vertical synchronization signal indicating image pickup timing and the like to the solid-state image pickup element 200 via a signal line 138. Furthermore, the image pickup control section 130 supplies a signal indicating timing to perform image processing to the image processing section 120 via a signal line 139.

[0067] It should be noted that although the image pickup lens 110, the solid-state image pickup element 200, the image processing section 120, the image pickup control section 130, and the recording section 140 are configured in the same device, they may be dispersed in a plurality of devices. For example, the image pickup lens 110 may be configured in a lens unit, the solid-state image pickup element 200 and the like may be configured in the image pickup device 100, and the image processing section 120 and the like may be configured in an information processing device.

[0068] Furthermore, although the image processing section 120 is provided outside the solid-state image pickup element 200 , their configuration is not limited thereto, and the image processing section 120 may be provided inside the solid-state image pickup element 200 .

[0069] [Configuration Example of Solid-State Image Pickup Element]

[0070] Figure 2 1 is a block diagram showing a configuration example of the solid-state image pickup element 200 in the first embodiment. The solid-state image pickup element 200 includes an interface 210, a driver 220, a pixel array section 230, a ramp signal generating section 250, a counting section 260, and a timing generating section 270. The circuits in the solid-state image pickup element 200 are provided on a single semiconductor substrate, for example.

[0071] The timing generation section 270 generates a timing signal indicating timing for the operation of the interface 210, the driver 220, the ramp signal generation section 250, and the counting section 260. The timing generation section 270 supplies the generated timing signal to a block corresponding to the signal.

[0072] The counting section 260 counts the count value in synchronization with a predetermined clock signal. The ramp signal generating section 250 generates a ramp signal in a sawtooth wave shape. The ramp signal generating section 250 supplies the generated ramp signal to the pixel array section 230 .

[0073] In the pixel array section 230, a plurality of pixel circuits are arranged in a two-dimensional grid. In the following description, a group of pixel circuits arranged in a predetermined direction (horizontal direction, etc.) is referred to as a "row", and a group of pixel circuits arranged in a direction perpendicular to the row is referred to as a "column". Each pixel circuit generates pixel data using a ramp signal and a count value of the counting section 260, and outputs the pixel data. Here, each such pixel data includes a digital signal indicating the exposure amount of the pixel and a determination mark indicating whether the light received by the pixel exceeds a predetermined value.

[0074] The driver 220 drives the pixel circuits to individually output pixel data. The interface 210 reads out pixel data from each pixel circuit. The interface 210 supplies image data in which the pixel data is arranged in a two-dimensional grid to the image processing section 120.

[0075] [Configuration Example of Pixel Array Section]

[0076] Figure 3 2 is a block diagram showing an example of the configuration of the pixel array section 230 in the first embodiment. In the pixel array section 230, the pixel circuits 240 are arranged in a two-dimensional grid. In addition, in the pixel array section 230, there are five horizontal signal lines for each row wiring along the row direction and one vertical signal line for each column wiring along the column direction. Each pixel circuit 240 is connected to the driver 220 via four of the five horizontal signal lines, and is connected to the ramp signal generating section 250 via the remaining one horizontal signal line. In addition, the pixel circuit 240 is connected to the interface 210 and the counting section 260 via the vertical signal line.

[0077] [Configuration Example of Pixel Circuit and Counting Section]

[0078] Figure 4 2 is a circuit diagram showing an example of the configuration of the pixel circuit 240 and the counting section 260 in the first embodiment. The pixel circuit 240 includes a switch 241, a PD (photodiode) reset transistor 242, a photodiode 243, a transfer transistor 244, a comparator 245, and an FD reset transistor 246. The pixel circuit 240 also includes a determination mark holding section 247 and a digital signal holding section 248. The counting section 260 includes an ascending counter 261 and a determination mark generating section 262 for each column of the pixel circuit 240. Figure 4 In FIG. 2 , a capacitor of a dotted line represents a floating diffusion layer. In addition, for the PD reset transistor 242 , the photodiode 243 , the transfer transistor 244 , and the FD reset transistor 246 , for example, an N-type MOS (Metal Oxide Semiconductor) transistor is used.

[0079] The switch 241 selects one of the control signals OFG (Over Flow Gate)_L and OFG_S in response to the value of the determination flag FLAG held in the determination flag holding unit 247. The switch 241 is implemented by an OR (logical AND) circuit, etc. The switch 241 supplies the selected signal to the gate of the PD reset transistor 242 as the control signal OFG.

[0080] Here, the control signals OFG_L and OFG_S are signals for controlling the PD reset transistor 242 used as an overflow gate, and are generated by the driver 220. It is assumed that the pulse width of the control signal OFG_L is greater than the pulse width of the control signal OFG_S. If the switch 241 selects the control signal OFG_S having a large pulse width, the timing of the start of exposure can be delayed to shorten the exposure period when the control signal OFG_L is selected. It should be noted that the switch 241 is an example of the selection unit described in the claims.

[0081] The PD reset transistor 242 discharges the charge of the photodiode 243 to the power source to initialize the photodiode 243. The PD reset transistor 242 is inserted between the photodiode 243 and the power source. The photodiode 243 performs photoelectric conversion on incident light to generate charge.

[0082] The transfer transistor 244 transfers the charge generated by the photodiode 243 to the floating diffusion layer according to the transfer signal TRG from the driver 220. The transfer signal TRG is a signal instructing the charge transfer. The transferred charge is accumulated in the floating diffusion layer, and a voltage according to the charge amount is input to the inverting input terminal (-) of the comparator 245.

[0083] The comparator 245 compares the input voltage FD, which is the voltage of the floating diffusion layer, with the reference voltage REF, which is the voltage of the ramp signal. The ramp signal from the ramp signal generating section 250 is input to the non-inverting input terminal (+) of the comparator 245. The comparator 245 outputs the comparison result as the comparator output signal VCO to the determination flag holding section 247 and the digital signal holding section 248. When the input voltage FD is equal to or lower than the reference voltage REF, the comparator output signal VCO of a high level is output, but when the input voltage FD is higher than the reference voltage REF, the comparator output signal VCO of a low level is output.

[0084] The FD (Floating Diffusion) reset transistor 246 initializes the charge amount of the floating diffusion layer according to the reset signal RST from the driver 220. The reset signal RST is a signal instructing the initialization of the floating diffusion layer. The FD reset transistor 246 is inserted between the inverting input terminal (-) and the output terminal of the comparator 245.

[0085] The up-counter 261 increments the count value in synchronization with the clock signal CLK from the timing generation section 270. It is assumed that the frequency of the clock signal CLK is higher than the frequency of the vertical synchronization signal. The up-counter 261 supplies the count value CNT of N bits (N is an integer equal to or greater than 1) to the determination mark generation section 262 and the digital signal holding section 248. In addition, the up-counter 261 initializes the count value CNT according to the reset signal rst from the timing generation section 270. It should be noted that a down-counter may be provided instead of the up-counter 261.

[0086] The determination flag generating section 262 compares the count value CNT with a predetermined set value, and generates a signal indicating the comparison result as a latch input signal LIN. For the latch input signal LIN, for example, when the count value CNT is equal to or lower than the set value, a value of "0" is set, but when the count value CNT is higher than the set value, a value of "1" is set. In addition, for the set value, for example, a value when the floating diffusion layer is saturated is set.

[0087] When the comparator output signal VCO is inverted from a high level to a low level (i.e., when the input voltage FD is higher than the reference voltage REF), the determination flag holding unit 247 holds the value of the latched input signal LIN as the determination flag FLAG. The determination flag holding unit 247 is implemented by, for example, a latch circuit. When the comparator output signal VCO indicates a high level, the determination flag holding unit 247 changes to a pass state and outputs the value of the latched input signal LIN as it is.

[0088] On the other hand, when the comparator output signal VCO is inverted from high level to low level, the determination flag holding unit 247 changes to the holding state and holds the value of the latch input signal LIN as the determination flag FLAG when inverted. The determination flag holding unit 247 outputs the held determination flag FLAG to the switch 241 and the interface 210.

[0089] When the comparator output signal VCO inverts from high level to low level (ie, when the input voltage FD is higher than the reference voltage REF), the digital signal holding unit 248 holds the count value CNT as the digital signal CODE. The value of the digital signal CODE indicates the exposure amount of the pixel circuit 240.

[0090] In addition, the digital signal holding section 248 is realized by, for example, a latch circuit. When the comparator output signal VCO indicates a high level, the digital signal holding section 248 transitions to a through state and outputs the count value CNT as it is.

[0091] On the other hand, when the comparator output signal VCO is inverted from a high level to a low level, the digital signal holding unit 248 changes to a holding state and holds the count value CNT as a digital signal CODE when inverted. The digital signal holding unit 248 outputs the held digital signal CODE to the interface 210. It should be noted that the digital signal holding unit 248 is an example of a digital signal generating unit described in the claims.

[0092] Furthermore, data including the determination flag FLAG from the determination flag holding section 247 and the digital signal CODE from the digital signal holding section 248 is output to the interface 210 as pixel data of the pixel circuit 240 .

[0093] With the above configuration, if the input voltage FD according to the amount of received light exceeds the saturation level of the floating diffusion layer, the high-level latch input signal LIN from the determination flag generation unit 262 is held as the determination flag FLAG in the determination flag holding unit 247. In particular, the determination flag FLAG indicates a measurement result of whether the amount of received light of the pixel circuit 240 exceeds a predetermined value (saturation level, etc.). It should be noted that the determination flag generation unit 262 and the determination flag holding unit 247 are examples of the measuring unit described in the claims.

[0094] Then, the switch 241 reads out the determination flag FLAG maintained in a certain frame in the next frame, and switches the exposure period in response to the determination flag FLAG. Because in the first frame, the determination flag FLAG maintains the initial value, the exposure period also maintains its initial value. However, in the second frame and subsequent frames, in response to the determination result (FLAG) of the amount of light received in the previous frame of each pixel circuit 240, long exposure and short exposure are switched. When the determination flag FLAG is "0" (that is, when the amount of light received greatly exceeds the predetermined value), short exposure is selected. On the other hand, when the determination flag FLAG is "1" (that is, when the amount of light received is equal to or lower than the predetermined value), long exposure is selected.

[0095] By determining whether the amount of received light exceeds a predetermined value for each pixel to switch the exposure period in this manner, the solid-state image pickup element 200 can generate short-time exposure pixel data and long-time exposure pixel data every time a fixed image pickup cycle passes.

[0096] Then, by adjusting (amplifying or attenuating) the pixel value of the corresponding pixel data in response to the determination flag FLAG, the image processing section 120 can generate image data with an expanded dynamic range in each image pickup cycle. In the following description, an image having a dynamic range with a predetermined value is referred to as a "normal image", and an image having a dynamic range expanded to a value higher than the predetermined value is referred to as an "HDR (High Dynamic Range) image".

[0097] It should be noted that although the switch 241 switches the exposure period between two exposure periods having different lengths, it can switch the exposure period between three or more exposure periods having different lengths from each other. When the exposure period is to be switched between M (M is an integer equal to or greater than 3) different exposure periods, the switch 241 is switched by M control signals having pulse widths different from each other. In addition, the determination flag generating section 262 generates a switching signal whose value is changed to the M level in response to an increase in the count value CNT, replacing the determination flag FLAG. In addition, when the comparator output signal is inverted, the determination flag holding section 247 holds the switching signal and supplies it to the switch 241.

[0098] In addition, although the solid-state image pickup element 200 measures the amount of light received for each pixel to generate a determination mark, the area of ​​the measurement unit of the amount of light received is not limited to pixels. As described below, the solid-state image pickup element 200 can measure the amount of light received for each area composed of a plurality of pixels.

[0099] Figure 5 is a view showing an example of the operation of the determination flag holding section 247 in the first embodiment. In the case where the comparator output signal VCO has a low level (i.e., in the case where the input voltage FD is higher than the reference voltage REF), the determination flag holding section 247 changes to a hold state and holds the value of the latch input signal LIN as the determination flag FLAG. On the other hand, in the case where the comparator output signal VCO has a high level, the determination flag holding section 247 changes to a pass state and outputs the latch input signal LIN as is. It should be noted that the operation of the digital signal holding section 248 is similar to that of the determination flag holding section 247 except that the number of bits to be retained is different.

[0100] Figure 6 2 is a diagram showing an example of the operation of the determination flag generating section 262 in the first embodiment. When the count value CNT is greater than the set value (that is, when the amount of received light is greater than the saturation level), the determination flag generating section 262 sets "1" as the latch input signal LIN. On the other hand, when the count value CNT is equal to or lower than the set value, the determination flag generating section 262 sets "0" as the latch input signal LIN.

[0101] Figure 7 : is a timing chart showing an example of the operation of the solid-state image pickup element 200 in the first embodiment. It is assumed that at time T1, image pickup of image data is started in synchronization with a vertical synchronization signal VSYNC of 60 Hz.

[0102] At the first moment T1, the determination flag FLAG maintains an initial value (e.g., "0") in all pixels. Therefore, all pixel circuits 240 are exposed during an exposure period of equal length to generate pixel data. In addition, each pixel circuit 240 determines whether the amount of received light exceeds a predetermined value to generate and maintain the determination flag FLAG. Then, the image processing unit 120 generates a normal image.

[0103] When time T2 after 1 / 60 seconds from time T1, each pixel circuit 240 selects an exposure period in response to the determination flag FLAG in the previous cycle, and performs exposure during the exposure period to generate pixel data. In addition, each pixel circuit 240 generates a determination flag FLAG. Then, the image processing unit 120 refers to the determination flag FLAG to generate an HDR image from two pixel data with different exposure periods.

[0104] After the above-mentioned time T1 until time T2, between the determination process of whether the amount of received light exceeds the predetermined value and the image pickup process of the HDR image, only the determination process is performed. Therefore, this period is hereinafter referred to as the "determination period". In addition, after time T2, the determination process and the image pickup process of the HDR image are performed in each image pickup cycle. Therefore, this period is hereinafter referred to as the "image pickup determination period".

[0105] It should be noted that although the image pickup cycle is 1 / 60 seconds, the cycle is not limited thereto. For example, the solid-state image pickup element 200 may perform image pickup after every 1 / 30 seconds.

[0106] Figure 8 1 is a timing chart showing an example of the operation of the solid-state image pickup element in the comparative example. It is assumed that the solid-state image pickup element of the comparative example does not measure the amount of received light for each pixel but performs image pickup with an exposure period of equal length applied to all pixels.

[0107] At the first moment T1, all pixel circuits in the solid-state image pickup element generate pixel data of short-time exposure. At the moment T2 after 1 / 60 seconds from the moment T1, all pixel circuits generate pixel data of long-time exposure. In addition, in the subsequent stage, the image processing unit synthesizes the image data of short-time exposure and the image data of long-time exposure to generate an HDR image. After the moment T3 after 1 / 60 seconds from the moment T2, the synthesis of the HDR image is performed after every 1 / 30 seconds.

[0108] In this way, in the comparative example, since a plurality of image data are synthesized to generate an HDR image (frame), the frame rate is reduced compared to an alternative case where such synthesis is not performed. For example, in the case where a normal image is picked up at a frame rate of 60 Hz and two normal normal images are synthesized to generate an HDR image, the frame rate of the HDR image is reduced to 30 Hz.

[0109] In contrast, Figure 7 As illustrated, since the solid-state image pickup element 200 measures the amount of light received for each pixel circuit 240 and switches the exposure period, an HDR image can be generated after each cycle (image pickup cycle) of the vertical synchronization signal VSYNC. For example, when the frequency of the vertical synchronization signal VSYNC is equal to the frequency in the comparative example, the solid-state image pickup element 200 can pick up an HDR image at a frame rate of 60 Hz. Therefore, the reduction in frame rate when picking up an HDR image can be suppressed.

[0110] Fig. 92 is a timing diagram showing an example of operation during the determination period of the solid-state image pickup element 200 according to the first embodiment. First, at time T1, the control signals OFG_L and OFG_S are controlled to be high level during pulses different from each other. If the initial value of the determination flag FLAG is set to a low level, for example, the switch 241 selects the control signal OFG_L based on the value of the determination flag FLAG, and outputs the control signal OFG_L as OFG. As a result, a long exposure of the exposure period t_LE is started.

[0111] Then, at time t2, a reset signal RST is supplied, and the voltage of the floating diffusion layer (FD) is initialized to its initial value (for example, initialized to a level equivalent to the reference voltage REF). If the reset signal RST drops, the voltage FD fluctuates due to feedthrough or charge injection. After time t3, the fluctuating component is counted as the reset level.

[0112] The reference voltage REF of the ramp signal gradually decreases during the period from time t3 to time t5. In addition, at time t3, the timing generation section 270 initializes the up-counter 261 and causes it to start counting.

[0113] When the input voltage FD becomes higher than the reference voltage REF at time t4 , the comparator output signal VCO is inverted to a low level. Also, at time t4 , the digital signal holding unit 248 holds the count value CNT as a reset level signal. This reset level is output to the interface 210 .

[0114] Then, at time t5 immediately before the end of the long exposure, the reference voltage REF rises until it becomes equal to or higher than the input voltage FD, and the comparator output signal VCO becomes high level. In addition, at time t5, the timing generation section 270 stops the clock signal CLK to the up counter 261 to stop its counting.

[0115] When the transfer signal TRG is supplied at time t6, the charge of the photodiode 243 is completely transferred to the floating diffusion layer, and its voltage (FD) drops. Therefore, the long exposure ends. After time t7, the reference voltage REF of the ramp signal gradually drops. In addition, at time t7, the timing generation section 270 initializes the up-counter 261 to start counting.

[0116] Since the count value CNT exceeds the set value at time t8, the determination flag generation unit 262 sets the latch input signal LIN to a high level. Then, when the input voltage FD becomes higher than the reference voltage REF at time t9, the comparator output signal VCO is inverted to a low level. At time t9 when the comparator output signal VCO is inverted, the determination flag holding unit 247 holds the high-level latch input signal LIN as the determination flag FLAG. In addition, the digital signal holding unit 248 holds the count value CNT at time t9 as a signal level. This signal level is output to the interface 210.

[0117] exist Fig. 9 In the example, since the comparator output signal VCO is inverted after the count value CNT exceeds the set value, the high-level determination flag FLAG is maintained. The high-level determination flag FLAG indicates that the light receiving amount exceeds the predetermined value Th (saturation level, etc.).

[0118] It should be noted that, in the case where the level of the input voltage FD is higher than the fluctuation amount of the ramp signal, the comparator output signal VCO is not inverted at the time t10 when the fluctuation of the ramp signal stops. In this case, at the time t10, the driver 220 forcibly inverts the comparator output signal VCO, so that the determination flag FLAG is held in the determination flag holding section 247.

[0119] Fig.10 2 is a timing diagram showing an example of operation during the image pickup determination period of the solid-state image pickup element 200 in the first embodiment. At time T2, the control signals OFG_L and OFG_S are controlled to be high level during different pulse periods. Since the determination flag FLAG maintained in the previous cycle is high level (i.e., since the amount of light received exceeds a predetermined value), the switch 241 selects and outputs the control signal OFG_S as OFG. Therefore, the short exposure of the exposure period t_SE is started.

[0120] Then, during a period from time t12 to time t15 , the reset level is AD-converted, and during a period from time t15 to time t20 , the signal level is AD-converted.

[0121] When the input voltage FD becomes higher than the reference voltage REF at time t18, the comparator output signal VCO is inverted to a low level. At time t18 when the comparator output signal VCO is inverted, the determination flag holding unit 247 holds the low-level latch input signal LIN as the determination flag FLAG.

[0122] Then, at the subsequent time t19, the count value CNT exceeds the set value, and therefore the determination flag generating section 262 sets the latch input signal LIN to the high level.

[0123] exist Fig.10 In the example, since the comparator output signal VCO is inverted before the count value CNT exceeds the set value, the low-level determination flag FLAG is maintained. The low-level determination flag FLAG indicates that the received light amount is equal to or lower than the predetermined value Th.

[0124] [Configuration Example of Image Processing Unit]

[0125] Fig.11 1 is a block diagram showing a configuration example of the image processing unit 120 in the first embodiment. The image processing unit 120 includes a correlated double sampling circuit 121 , a switch 122 , a multiplier 123 , and a post-processing unit 124 .

[0126] The correlated double sampling circuit 121 performs CDS (correlated double sampling) processing to calculate the difference between the reset level and the signal level in the digital signal CODE. Through the CDS processing, reset noise, threshold dispersion of transistors, etc. can be reduced. The correlated double sampling circuit 121 supplies the pixel value after the CDS processing to the switch 122.

[0127] In response to the determination flag FLAG, the switch 122 selects one of the multiplier 123 and the post-processing section 124 as an output destination, and outputs the pixel value from the correlated double sampling circuit 121 to the output destination. In the case where the determination flag FLAG has a high level (that is, in the case where the amount of received light exceeds a predetermined value), the switch 122 outputs the pixel value to the multiplier 123. On the other hand, in the case where the determination flag FLAG has a low level, the switch 122 outputs the pixel value to the post-processing section 124.

[0128] The multiplier 123 multiplies the pixel value from the switch 122 by t_LE / t_SE, which is an exposure ratio between the long exposure and the short exposure, and supplies the multiplied pixel value to the subsequent processing unit 124 .

[0129] The post-processing section 124 performs various image processing such as demosaic processing and white balance processing, and supplies the processing results to the recording section 140 .

[0130] The pixel values ​​of bright pixels whose light receiving amount exceeds a predetermined value are amplified by the multiplier 123. On the other hand, the pixel values ​​of dark pixels whose light receiving amount is lower than a predetermined value are not amplified. Therefore, the dynamic range of the image data is expanded by an amplification ratio equal to the exposure ratio, and an HDR image is obtained.

[0131] It should be noted that although the image processing unit 120 performs adjustment processing for amplifying only the pixel values ​​of bright pixels, if the dynamic range is expanded, adjustment processing other than this processing may be performed. For example, the image processing unit 120 may attenuate only the pixel values ​​of dark pixels without amplifying the pixel values ​​of bright pixels. In addition, the image processing unit 120 may amplify the pixel values ​​of bright pixels and attenuate the pixel values ​​of dark pixels.

[0132] [Example of Operation of Image Pickup Device]

[0133] Fig.12 1 is a flowchart showing an example of the operation of the image pickup apparatus 100 in the first embodiment. For example, when an operation for starting image pickup of an HDR image (pressing a shutter button or the like) is performed, the operation is started.

[0134] The solid-state image pickup element 200 performs an image pickup process for picking up image data (S910). In the first image pickup process, a normal image is picked up. Then, the solid-state image pickup element 200 performs the image pickup process again (step S910), and the image processing section 120 performs an HDR image generation process for generating an HDR image (step S920). Then, after step S920, in response to an operation such as stopping image pickup, the image pickup device 100 determines whether to end image pickup (step S930).

[0135] In the case where image pickup is not to be ended (step S930: No), the image pickup apparatus 100 repeats step S910 again. On the other hand, in the case where image pickup is to be ended (step S930: Yes), the image pickup apparatus 100 ends the operation for image pickup.

[0136] Fig.13 is a flowchart showing an example of image pickup processing in the first embodiment. The pixel circuit 240 in the solid-state image pickup element 200 determines whether the determination flag FLAG has a low level (i.e., whether the amount of light received in the previous cycle is equal to or lower than the predetermined value Th) (step S911). In the case where the determination flag FLAG has a low level (step S911: yes), the pixel circuit 240 performs a long time period exposure of t_LE (step S912). On the other hand, in the case where the determination flag FLAG has a high level (step S911: no), the pixel circuit 240 performs a short time period exposure of t_SE (step S913).

[0137] After step S912 or S913, the pixel circuit 240 determines whether the amount of light received in the current cycle is equal to or lower than the predetermined value Th (step S914). In the case where the amount of light received is equal to or lower than the predetermined value Th (step S914: Yes), the pixel circuit 240 sets the low level as the determination mark and maintains it therein (step S915). On the other hand, in the case where the amount of light received exceeds the predetermined value Th (step S914: No), the pixel circuit 240 sets the high level as the determination mark and maintains it therein (step S916). After step S915 or S916, the pixel circuit 240 generates and outputs pixel data (step S917).

[0138] Fig.14 1 is a flowchart showing an example of HDR image generation processing in the first embodiment. The image processing unit 120 performs correlated double sampling processing on the input pixel data (step S921). Then, the image processing unit 120 determines whether the determination flag FLAG of the pixel data has a high level (that is, whether the amount of received light exceeds a predetermined value Th) (step S922).

[0139] When it is determined that the flag FLAG has a high level (step S922: Yes), the image processing unit 120 multiplies the pixel value by the exposure ratio (t_LE / t_SE) (step S923). When it is determined that the flag FLAG has a low level (step S922: No), or after step S923, the image processing unit 120 determines whether the processing of all pixels is completed (step S924). When the processing of all pixels is not completed (step S924: No), the image processing unit 120 repeatedly executes the steps starting from step S921. On the other hand, when the processing of all pixels is completed (step S924: Yes), the image processing unit 120 ends the HDR image generation process.

[0140] In this way, according to the first embodiment of the present technology, each pixel circuit 240 measures the amount of received light and performs exposure during the exposure period selected in response to the measurement result to generate pixel data. Therefore, an HDR image can be generated from the image data of one image. As a result, the frame rate of the HDR image can be increased compared to the alternative case of synthesizing the image data of multiple images.

[0141] <2. Second Implementation Method>

[0142] In the above-mentioned first embodiment, the solid-state image pickup element 200 performs AD conversion on the reset level and the signal level in sequence through the ascending counter 261. However, in this configuration, when the reset noise or the like is to be reduced, the image processing section 120 needs to obtain the AD conversion values ​​of the reset level and the signal level to perform CDS processing, and therefore, the processing burden of the image processing section 120 increases. The solid-state image pickup element 200 in the second embodiment is different from the solid-state image pickup element in the first embodiment in that the processing amount of the image processing section 120 is reduced.

[0143] Fig.15 2 is a block diagram showing a configuration example of a solid-state image pickup element 200 in the second embodiment. The solid-state image pickup element 200 in the second embodiment is different from that in the first embodiment in that it does not include a counting section 260 .

[0144] Fig.16 2 is a circuit diagram showing a configuration example of a pixel circuit 240 in the second embodiment. The pixel circuit 240 in the second embodiment is different from the pixel circuit in the first embodiment in that it includes a determination flag generating section 301 and an up / down counter 302 instead of the digital signal holding section 248.

[0145] The up-down counter 302 increases or decreases its count value in synchronization with the clock signal CLK. The up-down counter 302 initializes its count value according to the reset signal rst from the timing generation section 270. In addition, the up-down counter 302 switches between the increment operation and the decrement operation according to the control signal UD from the timing generation section 270. In addition, when the comparator output signal VCO is reversed at each of the increment operation and the decrement operation, the up-down counter 302 stops its counting. Then, after the increment operation ends, the up-down counter 302 supplies its count value CNT to the determination flag generation section 301 and the interface 210.

[0146] The determination flag generation unit 301 compares the count value CNT and the set value with each other to generate a signal indicating the comparison result as a latch input signal LIN. The determination flag generation unit 301 supplies the latch input signal LIN to the determination flag holding unit 247 .

[0147] Fig.17 1 is a timing chart showing an example of operation during the determination period of the solid-state image pickup element in the second embodiment. Since the initial value of the determination flag FLAG is a low level, the control signal OFG_L is selected at time T1 and long exposure is started. When the reference voltage REF starts to decrease at time t3, the up-down counter 302 initializes its count value and starts to decrement the count value. Then, when the comparator output signal VCO is inverted at time t4, the up-down counter 302 stops its counting.

[0148] Then, when the reference voltage REF starts to decrease at time t7, the up-down counter 302 sets the value at the end of the decrement as the initial value and starts to increment the count value CNT. Then, when the comparator output signal VCO is inverted at time t9, the up-down counter 302 stops its counting. The count value CNT at this time represents the difference between the reset level and the signal level. In particular, the CDS process is performed by the up-down counter 302. Since the count value CNT is higher than the set value (that is, since the exposure amount exceeds the predetermined value Th), a high-level determination flag FLAG is generated at time t9.

[0149] It should be noted that although the up-down counter 302 is incremented after being decremented, it may be decremented after being incremented conversely.

[0150] Fig.18 1 is a timing diagram showing an example of operation during the image pickup determination period of the solid-state image pickup element in the second embodiment. Since the determination flag FLAG in the previous cycle is high level, the control signal OFG_S is selected at time T2 and the short exposure is started. Then, since the count value CNT after incrementing is equal to or lower than the set value (that is, since the exposure amount is equal to or lower than the predetermined value Th), a low level determination flag FLAG is generated at time t18.

[0151] Fig.19 1 is a block diagram showing a configuration example of the image processing section 120 in the second embodiment. The image processing section 120 in the second embodiment is similar to that in the first embodiment except that the correlated double sampling circuit 121 is not provided therein. As described above, since the CDS process is performed by the up-down counter 302, the correlated double sampling circuit 121 becomes unnecessary.

[0152] In this way, according to the second embodiment of the present technology, since the up / down counter 302 in the pixel circuit 240 performs CDS processing, the image processing section 120 at the subsequent stage does not need to perform CDS processing. As a result, the processing amount of the image processing section 120 can be reduced.

[0153] <3. Third Implementation Plan>

[0154] Although in the above-mentioned second embodiment, the solid-state image pickup element 200 measures the amount of light received for each pixel, the unit for measuring the amount of light received is not limited to one pixel, and the amount of light received can be measured for each area including a plurality of pixels. The solid-state image pickup element 200 in the third embodiment is different from the solid-state image pickup element in the second embodiment in that it measures the amount of light received for each light receiving area including a plurality of pixels.

[0155] Fig. 20 2 is a block diagram showing a configuration example of the pixel array section 230 in the third embodiment. The pixel array section 230 of the third embodiment is different from the pixel array section of the first embodiment in that it is divided into a plurality of light receiving regions 350. In each light receiving region 350, pixel circuits 360, 380, and 390 arranged in the column direction are provided.

[0156] It should be noted that, although the number of pixels in each light receiving area 350 is three, the number of pixels may be more than two and is not limited to three.

[0157] Fig.21 360 and 380 in the third embodiment. The pixel circuit 360 includes a switch 361, a PD reset transistor 362, a photodiode 363, a transfer transistor 364, a comparator 365, and an FD reset transistor 366. The pixel circuit 360 also includes a determination flag holding unit 367, a determination flag generating unit 368, an adder 369, and an up / down counter 370.

[0158] The configuration of the pixel circuit 360 is similar to that of Fig.16 The configuration of the pixel circuit 240 in the second embodiment is illustrated in FIG.

[0159] The pixel circuit 380 includes a switch 381 , a PD reset transistor 382 , a photodiode 383 , a transfer transistor 384 , a comparator 385 , and a FD reset transistor 386 . The pixel circuit 380 also includes an adder 388 and an up-down counter 389 .

[0160] The configuration of the pixel circuit 380 is similar to that of the pixel circuit 380 except that it includes an adder 388 instead of the determination flag generating unit 301 and the determination flag holding unit 247. Fig.16 The configuration of the pixel circuit 240 in the second embodiment is illustrated in FIG.

[0161] The up-down counter 389 supplies its count value CNT to the adder 388 and the interface 210 . The adder 388 adds the count value CNT of the pixel circuit 380 and the count value CNT of the pixel circuit 390 . The adder 388 supplies the addition result to the pixel circuit 360 .

[0162] The adder 369 adds the addition result from the pixel circuit 380 to the count value CNT of the pixel circuit 360. The adder 369 supplies the addition result to the determination flag generation section 368. The addition result is an integrated value of the count values ​​CNT of the pixel circuits 360, 380, and 390, and indicates the amount of light received by the light receiving area 350.

[0163] The determination flag generating section 368 generates a latch input signal LIN indicating whether the amount of light received by the light receiving area 350 exceeds a predetermined value, and supplies the latch input signal LIN to the determination flag holding section 367. When the comparator output signal VCO is inverted, the determination flag holding section 367 holds the latch input signal LIN as a determination flag FLAG, and supplies the held value to the switch 361 and the pixel circuits 380 and 390.

[0164] With the above configuration, the amount of received light is measured for each light receiving region 350 , and in response to the measurement result (determination flag FLAG), each pixel in the light receiving region 350 can select an exposure period.

[0165] In this way, according to the third embodiment of the present technology, the amount of light received is measured for each light receiving area 350 composed of a plurality of pixels, and exposure is performed during an exposure period selected according to the measurement result to generate image data. Therefore, an HDR image can be generated from the image data of one image.

[0166] <4. Fourth Implementation Plan>

[0167] Although each circuit in the solid-state image pickup element 200 is configured on a semiconductor substrate in the above-mentioned first embodiment, if it is assumed that the area of ​​the semiconductor substrate is constant, the pixels must be miniaturized as the number of pixels increases. Through this miniaturization, the area of ​​the photodiode in each pixel becomes smaller, which makes it difficult to maintain pixel characteristics such as sensitivity. The solid-state image pickup element 200 in the fourth embodiment is different from the solid-state image pickup element in the first embodiment in that the area of ​​the photodiode is increased.

[0168] Fig. 22 2 is a perspective view showing a configuration example of a solid-state image pickup element 200 in the fourth embodiment. The solid-state image pickup element 200 of the fourth embodiment includes a lower semiconductor substrate 202 and an upper semiconductor substrate 201 stacked on the substrate.

[0169] Fig.23 2 is a block diagram showing a configuration example of the solid-state image pickup element 200 in the fourth embodiment. On the lower semiconductor substrate 202, a plurality of latch circuits 410 are arranged in a two-dimensional grid, and on the upper semiconductor substrate 201, a plurality of pixel circuits 240 are arranged in a two-dimensional grid. In addition, the interface 210, the driver 220, the ramp signal generating section 250, the counting section 260, and the timing generating section 270 in the solid-state image pickup element 200 are arranged on the lower semiconductor substrate 202.

[0170] The configuration of the pixel circuit 240 in the fourth embodiment is similar to that in the first embodiment except that the switch 241, the determination flag holding section 247, and the digital signal holding section 248 are not provided thereon. The switch 241, the determination flag holding section 247, and the digital signal holding section 248 are provided in the latch circuit 410.

[0171] It should be noted that although the circuits in the solid-state image pickup element 200 are dispersed over two stacked semiconductor substrates, they may be dispersed over three or more semiconductor substrates. In addition, although the switch 241, the determination mark holding section 247, and the digital signal holding section 248 in the solid-state image pickup element 200 are provided on one substrate, and the remaining circuits are arranged on another substrate, their configuration is not limited to this configuration. For example, the switch 241 may be arranged on the substrate on the pixel circuit 240 side.

[0172] In this way, according to the fourth embodiment of the present technology, since the circuits within the solid-state image pickup element 200 are dispersed over the two semiconductor substrates stacked, the area of ​​the photodiode 243 can be increased compared to an alternative case where the two semiconductor substrates are not stacked. As a result, it is possible to suppress degradation of pixel characteristics (sensitivity, etc.) caused by miniaturization.

[0173] <5. Fifth Implementation Plan>

[0174] In the above-mentioned second embodiment, the solid-state image pickup element 200 selects an exposure period for exposure in response to the measurement result (determination mark FLAG) of the amount of light received measured in the previous frame when the image of each frame is picked up. However, according to this configuration, in the case where the amount of light received shows a large difference between the current frame and the previous frame, there is a possibility that the appropriate exposure period cannot be selected, resulting in deterioration of image quality. Therefore, it is preferred that, in each frame, the exposure period is selected in response to the amount of light received measured in the image pickup cycle of the frame. The solid-state image pickup element 200 in the fifth embodiment is different from the solid-state image pickup element of the second embodiment in that it selects an appropriate exposure period to improve image quality.

[0175] Fig.24 2 is a circuit diagram showing a configuration example of a pixel circuit 240 in the fifth embodiment. The pixel circuit 240 of the fifth embodiment is different from the pixel circuit of the second embodiment in that a transfer transistor 420 is included instead of the transfer transistor 244 .

[0176] The transfer transistor 420 is different from the transfer transistor 244 in the second embodiment in that the potential of its channel can be controlled to three levels. If the driver 220 supplies a low-level transfer signal TRG, the potential of the transfer transistor 420 becomes the highest potential. On the other hand, if the driver 220 supplies a high-level transfer signal TRG, the potential of the transfer transistor 420 becomes the lowest potential. If the driver 220 supplies an intermediate-level transfer signal TRG, the potential of the transfer transistor 420 becomes an intermediate potential between the high potential and the low potential.

[0177] With the intermediate potential, the charge in the photodiode 243 is not completely transferred, and the supernatant signal of the charge exceeding the intermediate potential is transferred to the floating diffusion layer. The charge transfer at the intermediate potential is hereinafter referred to as "intermediate potential transfer". Meanwhile, at the low potential, the charge in the photodiode 243 is completely transferred to the floating diffusion layer. The transfer at the low potential is hereinafter referred to as "complete transfer".

[0178] Fig.25 is an example of a potential diagram of intermediate potential transfer up to the pixel circuit 240 in the fifth embodiment. Fig.25 A in FIG. 4 shows a potential diagram of the pixel circuit 240 immediately before the intermediate potential is transferred. At this time, since the potential of the transfer transistor 420 is sufficiently high, the charge of the photodiode 243 is not transferred to the floating diffusion layer.

[0179] Fig.25 b shows the case where the amount of light received is greater than Fig.25 The potential diagram of the pixel circuit 240 when the intermediate potential of the received light amount in c is transferred. If the driver 220 supplies the intermediate level transfer signal TRG, the potential at the transfer transistor 420 becomes the intermediate potential. Then, the floating layer signal is transferred from the photodiode 243 to the floating diffusion layer.

[0180] Fig.25 c shows the case where the amount of light received is less than Fig.25 The potential diagram of the intermediate potential of the pixel circuit 240 in the light receiving amount in b is transferred. When the light receiving amount is small, the charge amount of the photodiode 243 is small and the floating layer signal is small. Fig.25 As illustrated in b and c in FIG. 1 , since the charge amount of the floating diffusion layer changes in response to the amount of received light when the intermediate potential is transferred, the pixel circuit 240 can generate the determination flag FLAG from the input voltage FD of the floating diffusion layer at this time.

[0181] Fig.262 is an example of a potential diagram at the time of complete transfer of the pixel circuit 240 in the fifth embodiment. If the driver 220 supplies a high-level transfer signal TRG, the potential of the transfer transistor 420 becomes a low potential. Then, all the charges in the photodiode 243 are transferred to the floating diffusion layer.

[0182] Fig. 27 1 is a timing chart showing an example of the operation of the image pickup device 100 in the fifth embodiment. When the first moment T1 passes, the pixel circuit 240 generates a determination flag FLAG when the intermediate potential is transmitted. Then, the pixel circuit 240 selects an exposure period in response to the determination flag, and performs exposure during the exposure period to generate pixel data. Then, the image processing section 120 refers to the determination flag FLAG to generate an HDR image from two different image data having different exposure periods.

[0183] Furthermore, at and after time T2 which is 1 / 60 seconds after time T1 , the pixel circuit 240 similarly generates the determination flag FLAG within the image pickup period to select the exposure period, and the image processing section 120 generates an HDR image.

[0184] Fig.28 1 is a timing diagram showing an example of the operation of the intermediate potential transfer of the pixel circuit 240 with a large amount of light received in the fifth embodiment. First, at time T1, the control signals OFG_L and OFG_S are controlled to a high level during the same pulse period. Then, during the period from time t12 to time t15, the reset level is counted. At time t16 thereafter, a transfer signal TRG of the intermediate level L1 is supplied, and the transfer transistor 420 performs the intermediate potential transfer. During the period from time t17 to time t19, a count value CNT representing the difference between the reset level and the signal level is counted. Since the count value CNT exceeds the set value (that is, since the amount of light received exceeds the predetermined value Th), a high-level determination flag FLAG is generated.

[0185] Fig.29 2 is a timing diagram showing an example of operation until the complete transfer of the pixel circuit 240 with a large amount of light received in the fifth embodiment. At time t22 immediately after the intermediate potential transfer, the control signal OFG_S is controlled to a high level during a predetermined pulse period. On the other hand, the control signal OFG_L remains at a low level. In addition, the switch 241 selects the control signal OFG_S according to the high-level determination flag FLAG, and outputs the control signal OFG_S as OFG. As a result, a short exposure of the exposure period t_SE is started.

[0186] Then, during the period from time t24 to time t27, the reset level is counted. At time t28 thereafter, the transmission signal TRG of the high level L2 is supplied, and the transmission transistor 420 performs complete transmission. The short-time exposure is then ended. During the period from time t29 to time t30, the count value CNT indicating the difference between the reset level and the signal level is counted. The count value CNT indicates the pixel value of the pixel subjected to the short-time exposure.

[0187] Fig.30 2 is a timing chart showing an example of the operation of transferring the intermediate potential of the pixel circuit 240 with a small amount of light received in the fifth embodiment. Since the control signals OFG_S and OFG_L are the same at time T2, the switch 241 outputs the control signal OFG with a fixed pulse width regardless of the value of the determination flag FLAG. The exposure of the pixel circuit 240 is started according to the control signal OFG.

[0188] Then, at time t28, the transfer transistor 420 performs intermediate potential transfer. During the period from time t29 to time t30, the count value CNT indicating the difference between the reset level and the signal level is counted. Then, since the count value CNT is equal to or lower than the set value (that is, since the amount of received light is equal to or lower than the predetermined value Th), a low-level determination flag FLAG is generated.

[0189] Fig.31 2 is a timing diagram showing an example of operation until complete transfer of the pixel circuit 240 with a small amount of light received in the fifth embodiment. At time t40 immediately after the intermediate potential transfer, according to the low-level determination flag FLAG, the switch 241 selects the control signal OFG_L and outputs the control signal OFG_L as OFG. As a result, at the time of the intermediate potential transfer, the floating layer signal is not reset and the accumulation of charge continues, and exposure is performed for a long period of the exposure period t_LE. Then, at time t46, the transfer signal TRG of the high level L2 is supplied, and the transfer transistor 420 performs complete transfer. The long exposure ends therewith.

[0190] In this way, according to the fifth embodiment of the present technology, since the pixel circuit 240 measures the amount of received light in the image pickup cycle and selects the exposure period in response to the measurement result, even in the case where the amount of received light changes greatly compared to the previous image pickup cycle, exposure can be performed within an appropriate exposure period after the change. As a result, the image quality of the image data can be improved.

[0191] It should be noted that the above-mentioned embodiments represent examples for implementing the present technology, and the matters in the embodiments and the specific matters of the present invention in the claims each have a corresponding relationship. Similarly, the specific matters of the present invention in the claims and the matters in the embodiments of the present invention to which the same names as the names in the claims are applied each have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the subject matter of the present technology.

[0192] In addition, the processing procedures described in the foregoing description of the embodiment may be understood as a method having such a series of processes, or may be understood as a program for causing a computer to execute such a series of processes or a recording medium storing the program. As the recording medium, for example, a CD (Compact Disc), an MD (Mini Disc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray Disc (registered trademark) Disc), etc. may be used.

[0193] It should be noted that the effects described herein are not necessarily restrictive, and may be some effects described in the present disclosure.

[0194] It should be noted that the present technology can adopt the following configurations.

[0195] (1) An image pickup device comprising:

[0196] a measuring section configured to measure an amount of received light in each of the plurality of regions to generate a measurement result;

[0197] a selection section configured to select one of a plurality of exposure periods different from each other based on a measurement result of each of the plurality of areas;

[0198] a digital signal generating section configured to perform exposure for each of the plurality of regions within a selected exposure period to generate a digital signal; and

[0199] An image processing section is configured to adjust a value of a digital signal generated for each of the plurality of areas based on the measurement result.

[0200] (2) The image pickup device according to (1), wherein

[0201] Each of the plurality of regions is composed of one pixel.

[0202] (3) The image pickup device according to (1), wherein

[0203] Each of the plurality of regions is composed of a plurality of pixels.

[0204] (4) The image pickup device according to any one of (1) to (3), wherein

[0205] The measuring unit determines whether the amount of received light is higher than a given value, generates a determination mark indicating a result of the determination, and stores the determined mark as the measurement result.

[0206] (5) The image pickup device according to (4), further comprising:

[0207] a counting section configured to count a count value in synchronization with a given clock signal;

[0208] a photodiode configured to generate electric charge according to the amount of received light; and

[0209] a comparator configured to compare a given ramp signal and a voltage according to the amount of the charge with each other and output a result of the comparison as a comparator output signal, wherein

[0210] When the comparator output signal is inverted, the digital signal generation section holds the count value as the digital signal, and

[0211] The measuring unit includes

[0212] a determination flag generating section configured to compare the count value and a given set value according to the given value with each other and output a result of the comparison as a latch input signal, and

[0213] A determination flag holding section is configured to hold the value of the latch input signal as the determination flag when the comparator output signal is inverted.

[0214] (6) The image pickup device according to (5), wherein

[0215] The counting section first performs one of a process of incrementing and a process of decrementing the count value, and then performs the other process.

[0216] (7) The image pickup device according to (5), wherein

[0217] The image processing section performs at least one of a process of amplifying the digital signal in any region among the multiple regions where the amount of received light is higher than the given value and another process of attenuating the digital signal in any region among the multiple regions where the amount of received light does not exceed the given value.

[0218] (8) The image pickup device according to any one of (1) to (7), wherein

[0219] The measuring section holds the measurement result every time a given image pickup period passes, and

[0220] The selection section selects one of the plurality of exposure periods in each of the given image pickup cycles based on a measurement result held before the image pickup cycle.

[0221] (9) The image pickup device according to any one of (1) to (7), wherein

[0222] The selection section selects, in each of the given image pickup cycles, one of the plurality of exposure periods based on a measurement result generated within the image pickup cycle.

[0223] (10) The image pickup device according to any one of (1) to (9), wherein

[0224] The measuring section, the selecting section, and the digital signal generating section are provided in a solid-state image pickup element, and

[0225] The circuits within the solid-state image pickup element are dispersed over a plurality of stacked semiconductor substrates.

[0226] (11) A solid-state image pickup element comprising:

[0227] a measuring section configured to measure an amount of received light in each of the plurality of regions to generate a measurement result;

[0228] a selection section configured to select one of a plurality of exposure periods different from each other based on a measurement result of each of the plurality of areas; and

[0229] A digital signal generating section is configured to perform exposure for each of the plurality of regions within the selected exposure period to generate a digital signal indicating an exposure amount.

[0230] (12) A control method for an image pickup device, comprising:

[0231] a measurement process for measuring the amount of light received in each of the plurality of areas to generate a measurement result;

[0232] a selection process for selecting one of a plurality of exposure periods that are different from each other based on the measurement result of each of the plurality of areas;

[0233] a digital signal generating process for performing exposure for each of the plurality of regions within a selected exposure period to generate a digital signal representing an exposure amount; and

[0234] An image processing process is used to adjust the value of the digital signal generated for each of the plurality of regions based on the measurement results.

[0235] Reference numerals list

[0236] 100 Image pickup device

[0237] 110 Image pickup lens

[0238] 120 Image Processing Unit

[0239] 121 Correlated Double Sampling Circuit

[0240] 122,241,361,381 Switches

[0241] 123 Multiplier

[0242] 124 Post-processing unit

[0243] 130 Image pickup control unit

[0244] 140 Records Department

[0245] 200 Solid-state image pickup element

[0246] 201 Upper semiconductor substrate

[0247] 202 lower semiconductor substrate

[0248] 210 Interface

[0249] 220 Driver

[0250] 230 Pixel array unit

[0251] 240,360,380,390 pixel circuit

[0252] 242,362,382 PD reset transistor

[0253] 243,363,383 Photodiode

[0254] 244,364,384,420 Pass transistors

[0255] 245,365,385 Comparators

[0256] 246,366,386 FD reset transistor

[0257] 247,367 Judgment mark holding unit

[0258] 248 Digital signal holding unit

[0259] 250 Ramp signal generating unit

[0260] 260 Counting Unit

[0261] 261 ascending counter

[0262] 262,301,368 Judgment mark generation unit

[0263] 270 Timing Generation Unit

[0264] 302,370,389 Up / Down Counter

[0265] 350 light receiving area

[0266] 369,388 Adder

[0267] 410 Latch Circuit

Claims

1. An image pickup device, comprising: a photodiode configured to generate electric charge according to the amount of received light; a first transistor connected to the photodiode and a power source; a second transistor connected to the photodiode and the capacitor; and a switch connected to a gate of the first transistor, wherein the second transistor is configured to transfer a portion of the charge in the photodiode to the capacitor, and The first transistor is configured to discharge charge in the photodiode based on an amount of charge in the capacitor.

2. The image pickup device according to claim 1, wherein The potential of the second transistor can be controlled to three levels, namely, a lowest potential, an intermediate potential and a highest potential.

3. The image pickup device according to claim 2, wherein When the second transistor is at the lowest potential, all the charges in the photodiode are transferred to the capacitor.

4. The image pickup device according to claim 2, wherein When the second transistor is at the intermediate potential, the charges in the photodiode are not completely transferred to the capacitor, and a floating layer signal of the portion of the charges exceeding the intermediate potential is transferred to the capacitor.

5. The image pickup device according to claim 2, wherein When the second transistor is at the highest potential, the charges in the photodiode are not transferred to the capacitor.

6. The image pickup device according to claim 1, wherein In each frame, one of a plurality of exposure periods different from each other is selected in response to the amount of received light measured in an image pickup period of the frame.

7. The image pickup device according to claim 2, wherein When the second transistor is at the intermediate potential, the charge amount of the capacitor changes in response to the amount of received light, so that one of a plurality of exposure periods different from each other can be selected according to the charge amount of the capacitor.

8. The image pickup device according to claim 1, The switch is used to select one of a plurality of exposure periods that are different from each other.

9. The image pickup device according to claim 1, wherein The capacitor constitutes a floating diffusion layer.

10. The image pickup device according to claim 1, wherein The first transistor is a reset transistor; and The second transistor is a transfer transistor.

Images