Semiconductor device with through hole having zinc-second metal-copper composite layer

Abstract

An integrated circuit (IC) includes a substrate (108) having a semiconductor surface layer comprising a circuit system (180) configured to implement at least one circuit function including a plurality of transistors (T1, T2), the semiconductor surface layer including at least one dielectric layer (133) having at least one through-hole (121 to 124) located above the plurality of transistors. A first top-level via and a second top-level via laterally to the first top-level via include a composite layer 168 comprising copper (Cu), a first metal including Zn, and a second metal, wherein the composite layer is located on a barrier layer 127 coupled to the through-hole. A first Cu top metal trace 141 is located on the first top-level via, and a second Cu metal trace 142 is located on the second top-level via.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and more specifically to through-holes for semiconductor devices. Background Technology

[0002] In integrated circuit (IC) design and fabrication, a via is a relatively small opening in a dielectric layer (e.g., a silicon oxide layer) that allows conductive connections between different stacked conductive layers, including adjacent metal layers. A via connecting the bottom layer of a stack of metal layers to a doped diffused or polysilicon layer is often specifically referred to as a "contact." A via level exists between a top metal layer and its topmost metal interconnect layer below it. The top metal layer provides bonding pads and typically includes some metal traces for some wiring, such as providing redistribution layer (RDL) arrangements.

[0003] The top layer metal typically includes aluminum or copper. Copper (Cu) offers higher speed and better electromigration resistance compared to aluminum. In the case of a Cu top metal, chemical mechanical planarization (CMP) is required for removal because, as is well known in the art, Cu cannot be removed by depositing a copper layer, forming a pattern using photoresist (PR), and then etching away unwanted portions of the Cu layer using reactive gases commonly used for etching aluminum layers. Summary of the Invention

[0004] This summary is provided to present a simplified selection of the disclosed concepts, which will be further described below in a detailed description including the accompanying drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0005] This disclosure recognizes that the required overlap (e.g., 5.5 μm) of the Cu or Cu alloy top metal layer above the topmost via (top-level via) can limit the number of top-level vias below the Cu traces conventionally formed on the Cu seed layer, which can limit current carrying capacity. The large overlap of Cu traces required above the top-level vias results in a potentially smaller area of ​​the top-level vias (within a fixed via area), leading to reduced current carrying capacity. This disclosure also recognizes that the requirement for a larger overlap of top Cu traces above the top-level vias is due to two main reasons. Etching the conventional Cu seed layer simultaneously etches the Cu traces on it, reducing the width of the Cu traces (e.g., a 20 μm wide line can become a 19 μm line, resulting in a 5% width reduction). Additionally, the Cu seed layer, typically a sputtered layer, is etched faster than the Cu top metal layer, typically an electroplated layer, resulting in undercutting in the Cu seed layer.

[0006] The disclosed approach addresses the aforementioned seed layer undercut problem below the Cu seed layer by forming a first metal seed layer comprising zinc (Zn) on top of a refractory metal barrier layer, instead of a conventional Cu seed layer. The second metal layer described herein is then formed on the first metal seed layer comprising Zn, on which Cu traces are present. Upon appropriate heating, a Zn-second metal-Cu composite layer is formed at the interface between the Cu traces and the barrier layer.

[0007] The disclosed aspects also address the problem that commercially available acidic copper plating solutions dissolve certain seed layers (such as the disclosed first metal seed layer containing Zn). Furthermore, conventional commercially available alkaline copper plating solutions can damage the PR (Potential Producer Layer). Therefore, the Cu plating method disclosed herein on a first metal seed layer containing Zn would not be considered feasible by those skilled in the art.

[0008] The disclosed aspect includes an IC comprising a substrate having a semiconductor surface layer, the semiconductor surface layer including a circuit system configured to implement at least one circuit function including a plurality of transistors, the semiconductor surface layer including at least one dielectric layer having a first through-hole and a second through-hole located above the plurality of transistors. The through-hole includes a first top-level via and at least a second top-level via transverse to the first top-level via. A composite layer operating as a via interface includes Cu, a first metal including Zn, and a second metal, wherein the composite layer is located above a barrier layer, the barrier layer being located above the first top-level via and the second top-level via. A first Cu top metal trace is located on the composite layer contacting the first top-level via, and a second Cu top metal trace is located on the composite layer contacting the second top-level via.

[0009] One disclosed aspect includes a method comprising forming a composite layer on a top-level via. This step involves forming a relatively thin second metal layer (e.g., Ni, Co, Fe, Cr) on a first metal layer comprising a Zn seed layer. The second metal layer can be electroplated from a chlorine-free, neutral or near-neutral pH second metal plating bath, avoiding removal of the seed layer. After electroplating the Cu top metal layer, heating is performed to allow diffusion of the first metal, the second metal, and Cu comprising Zn, thereby forming a Zn-second metal-Cu composite layer at the interface between the Cu trace and the barrier layer located above the top-level via. Because the Zn-second metal-Cu composite layer is resistant to common chemicals used for etching (typically including wet etching) the Zn-comprising first metal seed layer, the problem of seed layer undercutting below the Cu top metal trace is reduced or eliminated when etching the Zn-comprising first metal seed layer and then the barrier layer. Attached Figure Description

[0010] Now refer to the accompanying drawings, which are not necessarily drawn to scale. In the accompanying drawings:

[0011] Figure 1 This is a cross-sectional view of an exemplary IC device including a topmost via having a Zn-second metal-Cu composite layer at the interface between the top-level Cu trace and the barrier layer above the top-level via.

[0012] Figure 2 This is a flowchart illustrating steps in an exemplary method for forming a disclosed composite layer above a barrier layer above a top layer, according to an exemplary aspect, the composite layer having a Zn-second metal-Cu composite layer located at the interface between the Cu trace and the barrier layer.

[0013] Figures 3A to 3F According to the exemplary aspect, corresponding to Figure 2 A cross-sectional view of an intermediate process IC in the method shown, the intermediate process IC having a Zn-second metal-Cu composite layer at the interface between the Cu trace above the top-level via and the barrier layer. Detailed Implementation

[0014] Exemplary aspects have been described with reference to the accompanying drawings, wherein similar reference numerals are used to denote similar or equivalent elements. The illustrated order of actions or events should not be construed as limiting, as some actions or events may occur in a different order and / or in parallel with other actions or events. Furthermore, it is not required that some illustrated actions or events implement the methods according to this disclosure.

[0015] Furthermore, the terms “coupled to” or “coupled with” (etc.) as used herein are intended to describe indirect or direct electrical connections without further limitation. Thus, if a first device is “coupled” to a second device, the connection can be a direct electrical connection where parasitic phenomena exist only in the bypass, or an indirect electrical connection via an intermediate term that includes other devices and the connection. For indirect coupling, the intermediate term typically does not alter the information of the signal, but can regulate its current level, voltage level, and / or power level.

[0016] Figure 1This is a cross-sectional view of an exemplary IC device 100 including a top-level via (BV) according to an exemplary aspect. The BV has a disclosed Zn-second metal-Cu composite layer 168 located above the top-level via 124 at the interface between Cu traces 141, 142 and a barrier layer 127. The IC device 100 includes a metal stack illustrated by way of an example including three (3) layers of metal interconnects shown as metals 1 (M1), M2, and M3, which are shown as interlayer dielectric layers 1 (ILD1), ILD2, and ILD3 respectively embedded on a dielectric layer above a semiconductor top surface, which may be referred to as a pre-metal dielectric (PMD) 115, which may be located on another dielectric layer (such as a thermally grown silicon oxide layer) shown as 116. The top-level metal hierarchy including Cu shown as M4 includes Cu traces shown as 141 and 142 that can be used as RDLs and also provides a plurality of bonding pads. The dielectric layer shown as 133 is located at ILD3, which provides etch stop (such as silicon nitride).

[0017] Via 121 is shown coupling M3 to M2, via 122 is shown coupling M2 to M1, and via 123 is shown coupling M1 to the semiconductor surface of substrate 108. A small portion of circuit system 180 is shown, including node 109a, shown as a diffusion (e.g., n+ or p+) to the semiconductor surface of substrate 108, node 109b as the gate 112 of a MOS transistor shown as T1, and node 109c as the gate 112 of a MOS transistor shown as T2. Circuit system 180 includes circuit elements (including transistors such as T1 and T2) and generally also includes layers formed together in the semiconductor surface layer of substrate 108 configured to perform at least one circuit function such as analog (e.g., amplifier, power converter, or power field-effect transistor (FET)) function, radio frequency (RF) function, digital function, or memory function.

[0018] Vias 121 to 123 couple the M3 line to node 109a, and vias 121 to 124 (with top-level vias on top) couple the Cu trace 141 to node 109b, which is, as described above, a gate 112 of T1 located on a gate dielectric 111 on a semiconductor surface of substrate 108, such that, in one aspect, the semiconductor surface is, for example, a silicon-containing surface, wherein these gates are shown having sidewall spacers 113. Cu trace 142 is shown as coupling to node 109c, which is, as described above, a gate 112 of T2 located on a semiconductor surface of substrate 108. Sources, drains, and wells, which are typically present, are not shown for simplicity. Vias 121, 122, 123, and 124 may all comprise tungsten or another suitable conductive plug material.

[0019] As described above, M4 comprises Cu, such as pure Cu or a Cu alloy, surrounded by a dielectric layer shown as ILD4, wherein M4 is located on a disclosed Zn-second metal-Cu composite layer 168, which is located on a refractory metal barrier layer 127, which is located on a top-level via 124. The barrier layer 127 may comprise TiW, Ta, TaN, Ti, or TiN. Cu traces 141 and 142 are shown coupled to M3 via the top-level via 124 through the dielectric layer 133 and ILD3, and coupled from M3 all the way to features on the semiconductor surface of the substrate 108, such as coupling from Cu trace 141 to node 109b and from Cu trace 142 to node 109c.

[0020] IC device 100 typically includes at least one dielectric passivation layer located above Cu traces 141 and 142, wherein... Figure 1 The intermediate passivation layer is shown as a first passivation layer 147 (e.g., silicon oxide or silicon oxynitride) located on the second passivation layer 146 (e.g., silicon oxide or silicon oxynitride). Although not shown, an etch stop layer (e.g., silicon nitride) may be present beneath the second passivation layer 146.

[0021] Figure 2 This is a flowchart illustrating steps in an exemplary method 200 for forming a disclosed composite layer on a top-level via, according to an exemplary aspect. The composite layer has a Zn-second metal-Cu composite layer on a barrier layer, wherein the composite layer provides an interface between Cu traces and the barrier layer. Step 201 includes providing a substrate having a semiconductor surface layer comprising a circuit system configured to implement at least one circuit function including a plurality of transistors, the semiconductor surface layer including at least one dielectric layer having a through-via over the plurality of transistors. Step 202 includes depositing a refractory metal barrier layer on the dielectric layer. Step 203 includes forming (e.g., sputtering) a first metal layer comprising Zn on the refractory metal barrier layer.

[0022] Step 204 includes, for example, forming a PR layer on Figure 3C and Figure 3DThe patterned layer feature shown is a PR feature 163 having a patterned opening located above a through-hole. Step 205 includes forming (e.g., plating) a second metal layer 164 (e.g., Ni, Co, Fe, Cr) onto the first metal layer. Step 206 includes forming (e.g., plating) a Cu-containing layer onto the second metal layer to form a plurality of Cu traces within the patterned opening. Step 207 includes removing the patterned layer feature. Step 208 includes heat treatment to cause internal diffusion, thereby forming a Cu-first metal-second metal composite layer below the Cu traces. Step 209 includes etching laterally to the metal traces to remove the first metal layer and the refractory metal barrier layer. The composite layer is resistant to the etching.

[0023] Figures 3A to 3F The diagram shows the corresponding description above. Figure 2 A cross-sectional view of an intermediate process IC in step 200 of method 200, the intermediate process IC having a top-level via including a first metal-second metal-Cu composite layer 168 located on a barrier layer 127, such that the composite layer is located at the interface between the Cu traces 141, 142 and the barrier layer 127 above the top-level via 124. Zn can be used as the first metal layer 162, and TiW can be used as the barrier layer and can also be used as an adhesion-improving layer. The IC includes metal stacks thereon. Figure 3A The through holes shown are 121 to 124 (124 being the top-level through hole). These through holes can correspond to... Figure 1 The silicon wafer introduced through the vias of the ILD (Inter-Insulated Layer) can be coated with a refractory metal barrier layer 127, such as sputtered TiW of 2,000 Å to 4,000 Å. A first metal layer 162 comprising Zn is then sputtered, which serves as a seed layer for Cu plating. This seed layer can consist of a Zn layer of 0.8 to 1.2 μm thickness, resulting in… Figure 3B As shown in the diagram. Then it can be used with, for example, as... Figure 3C The wafer is patterned with a patterned layer for the patterned layer feature portion 163 shown to create an opening above the top-level via 124 of the through via between the PR feature portions 163, wherein a top metal Cu-containing trace will later be formed in this method.

[0024] Then, a relatively thin (e.g., about 0.5 to 2.0 μm thick) second metal layer 164, such as Ni or Co, is formed between the openings 163 of the PR features using a chlorine-free plating bath with a neutral or near-neutral pH, defined herein as 6 to 7.5, to avoid removing the first metal layer 162, which includes Zn. Subsequently, a top metal containing Cu, including Cu traces 141, 142, is electroplated using an acid Cu plating bath, resulting in… Figure 3D As shown in the image.

[0025] Cu traces 141 and 142 are shown above two through-holes 121 to 124 located laterally to each other. However, one or three or more through-holes may exist beneath each Cu trace 141 and 142. The maximum overlap of Cu traces 141 and 142 above their through-holes 121 to 124 is typically <2 μm, which can be close to zero overlap. This is achieved by reducing or eliminating undercutting because the composite layer 168 is resistant to common chemicals used for etching a first metal layer 162 comprising Zn, which serves as a seed layer for the copper traces. The wafer is then annealed, for example, at a temperature of 175°C to 300°C in air or a non-oxidizing environment (such as in a furnace) for 30 to 120 minutes to allow Cu to diffuse from the bottom of the copper traces, the first metal layer 162 comprising Zn, and the second metal layer 164, thereby forming a first metal-second metal-Cu composite layer, shown as composite layer 168, which is located beneath the first metal-second metal-Cu composite layer. Figure 3E The interface between the Cu traces 141 and 142 above the top-level vias 124 (121 to 124) and the barrier layer 127 is shown in the diagram.

[0026] The composite layer 168 is typically 100 nm to 3 μm thick. The composite layer 168 typically comprises an average of at least 30% by weight Cu, 10% by weight of a second metal (e.g., Ni), and a weighting of at least 40% by weight Zn across its thickness. The weight percentages of Zn, the second metal layer, and the Cu traces in the composite layer 168 typically depend on the heat treatment used for internal diffusion, including temperature and temperature rise rate, duration, and the thickness of the first metal layer, the second metal layer, and the Cu traces, wherein the thickness of the composite layer 168 typically increases with the thickness of the respective layer until saturation of the respective metal is achieved. The first metal layer 162 between the Cu traces 141 and 142 can then be etched away, followed by etching of the barrier layer 127, resulting in the structure shown below. Figure 3F As shown. Because composite layer 168 is resistant to common chemicals used to etch the first metal layer 162, the undercut of composite layer 168 cannot be detected below Cu traces 141 and 142, as shown. Figure 3F As shown.

[0027] Subsequent processing may include forming at least one dielectric layer between Cu traces 141, 142 (e.g., Figure 1 The ILD4 shown is then formed in Figure 1 At least one passivation layer, shown as 146 and 147, is then etched to expose the Cu bonding pads of the top Cu layer.

[0028] Example

[0029] The disclosed aspects are further illustrated by the following specific embodiments, which should not be construed as limiting the scope or content of this disclosure in any way.

[0030] A 200 mm Si wafer is sputtered with a 3,000 Å thick TiW layer as a barrier layer 127, followed by sputtering a 1 μm Zn layer as the first metal layer 162. A 17 μm PR spin-coated wafer is then patterned to form PR feature areas 163. A thin nickel layer is electroplated on top of the Zn layer 162 using a chlorine-free, neutral pH (approximately 7) nickel plating bath as the second metal layer 164. Cu plating is then performed to form Cu traces 141 and 142. The mixture is then heat-treated at 250°C for 1 hour to allow Cu, Ni, and Zn to diffuse together, thereby forming a Ni-Zn-Cu composite layer 168 at the interface between the Cu traces 141 and 142 and the barrier layer 127. The Ni-Zn-Cu composite layer has 30% to 40% by weight Cu, 10% to 15% by weight Ni, and a Zn counterweight. The thickness of the composite layer is 600 nm to 1 μm. The Ni-Zn-Cu composite layer 168 here is resistant to common chemicals used for etching the first metal layer 162 of Zn, which is used as a seed layer for Cu electroplating, resulting in the elimination of undercutting problems when using conventional Cu seed layers, and thereby reducing or eliminating the overlap of Cu traces above through-holes.

[0031] The aspects disclosed herein can be used to form semiconductor dies, which can be integrated into various assembly processes to form a variety of different devices and related products. A semiconductor die may include various elements therein and / or various layers thereon, including barrier layers, dielectric layers, device structures, active and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Furthermore, semiconductor dies can be formed using various processes including bipolar, insulated-gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0032] Those skilled in the art will understand that many other aspects are possible within the scope of the claimed invention, and that these aspects can be further added to, deleted from, substituted for, and modified without departing from the scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit, i.e., an IC, comprising: A substrate having a semiconductor surface layer is provided, the semiconductor surface layer including a circuit system configured to implement at least one circuit function including a plurality of transistors, the semiconductor surface layer including at least one dielectric layer having a through-hole located above the plurality of transistors; A barrier layer is deposited on the dielectric layer; A first metal layer comprising zinc is formed on the barrier layer; A patterned layer is formed, comprising patterned layer features, wherein the patterned layer features have patterned openings between the patterned layer features located above the through-hole; A second metal layer is formed on the first metal layer; A copper-containing layer, i.e. a Cu-containing layer, is formed on the second metal layer to form multiple Cu traces within the pattern opening; Remove the patterned layer; Heat treatment causes internal diffusion, thereby forming a Cu-first metal-second metal composite layer beneath the plurality of Cu traces, and Etching is performed laterally along the plurality of Cu traces to remove the first metal layer and the barrier layer.

2. The method according to claim 1, wherein, The first metal layer is composed of zinc, and the second metal layer includes nickel.

3. The method according to claim 1, wherein, The formation of the second metal layer includes electroplating using a chlorine-free electroplating bath with a pH of 6 to 7.

5.

4. The method according to claim 1, wherein, The heat treatment consumes all of the first metal layer to form the Cu-first metal-second metal composite layer.

5. The method according to claim 1, wherein, The patterning layer includes a photoresist layer.

6. The method according to claim 1, wherein, The formation of the second metal layer includes electroplating, and the thickness of the second metal layer is formed to be 500 Å to 2,000 Å.

7. The method according to claim 1, wherein, The heat treatment includes a temperature of 175°C to 300°C for 30 to 120 minutes.

8. The method according to claim 1, wherein, Each of the plurality of Cu traces is located above the plurality of through holes.

9. The method according to claim 1, wherein, The Cu-first metal-second metal composite layer has an average thickness of at least 30% by weight of Cu and at least 40% by weight of zinc, and wherein the thickness of the Cu-first metal-second metal composite layer is from 100 nm to 3 μm.

10. An integrated circuit, or IC, comprising: A substrate having a semiconductor surface layer, the semiconductor surface layer including a circuit system configured to implement at least one circuit function including a plurality of transistors, the semiconductor surface layer including at least one dielectric layer having a plurality of through-holes located above the plurality of transistors, the plurality of through-holes including a first top-level via and at least a second top-level via transverse to the first top-level via; A composite layer comprising copper (Cu), a zinc-containing first metal, and a second metal, wherein the composite layer is located on a barrier layer, and the barrier layer is located on a first top-level via and on a second top-level via. as well as Multiple Cu traces, including a first Cu top metal trace located on the composite layer that contacts the first top-level via and a second Cu top metal trace located on the composite layer that contacts the second top-level via.

11. The IC according to claim 10, wherein, The second metal includes nickel, iron, or cobalt.

12. The IC according to claim 11, wherein, The second metal includes nickel.

13. The IC according to claim 10, wherein, The at least one dielectric layer includes a metal stack located on the semiconductor surface layer, the semiconductor surface layer including a plurality of dielectric layers, the plurality of dielectric layers including a plurality of through-holes connecting the plurality of dielectric layers in the metal stack.

14. The IC according to claim 10, wherein, Each of the plurality of Cu traces is located above the plurality of through holes.

15. The IC according to claim 10, wherein, The composite layer is 100 nm to 3 μm thick.

16. The IC according to claim 10, wherein, The maximum overlap of the first Cu top metal trace on the first top layer via and the maximum overlap of the second Cu top metal trace on the second top layer via are both <2μm.

17. The IC according to claim 10, wherein, The composite layer is in direct contact with the barrier layer at its bottom and in direct contact with the first Cu top metal trace and the second Cu top metal trace at its top.

18. The IC according to claim 10, wherein, The composite layer has an average thickness of at least 30% by weight of Cu and at least 40% by weight of zinc, and the thickness of the composite layer is from 100 nm to 3 μm.

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