System, device and method for fingerprint sensing

Abstract

The present invention describes various aspects or embodiments of implementations of fingerprint sensing, for example, for fingerprint sensing on a portion or the entire screen of a computing device such as a smart phone, a tablet computer or other information processing device. The present invention discloses an electronic module, a computing device and a panel. The electronic module includes: a slope configuration circuit for generating at least one output signal and sending the at least one output signal to a gate-on-array (GOA) circuit of a panel; and a fingerprint sensing control circuit coupled to a plurality of fingerprint sensing elements of the panel to generate a plurality of control signals and transmit the plurality of control signals to the GOA circuit, wherein the fingerprint sensing control circuit controls the GOA circuit to generate a plurality of reset signals according to the at least one output signal, and the slope configuration circuit controls the slope of the falling edge of each reset signal, and the GOA circuit resets the plurality of fingerprint sensing elements respectively.

Description

Technical Field

[0001] The present invention relates to fingerprint sensing technology, and more particularly to a fingerprint sensing system, device and method used in a single chip of a computing device, as well as an electronic module, a computing device and a panel related to fingerprint sensing. Background Art

[0002] For computing devices such as smart phones, tablet computers or other information processing devices, touch screens have become an essential component of computing devices for user interaction. Users can input or control computing devices through single-touch or multi-touch gestures by touching the screen with one or more fingers or a special stylus.

[0003] Furthermore, the demand for fingerprint sensing on a portion of a touch screen or the entire touch screen continues to increase. Summary of the invention

[0004] Various aspects or embodiments are described regarding implementations of fingerprint sensing, for example, for fingerprint sensing on a portion or the entire screen of a computing device such as a smartphone, tablet computer, or other information processing device.

[0005] According to a first aspect of the present disclosure, a system, apparatus and method for a fingerprint sensing driver (or chip) to provide a pre-scanned fingerprint pattern to an application are introduced.

[0006] According to a second aspect of the present disclosure, a system, apparatus and method for adjusting the slew rate of a signal of a fingerprint sensing driver or FDTI chip are introduced.

[0007] According to a third aspect of the present disclosure, a system, apparatus and method for dynamic offset adjustment in a fingerprint sensor driver of an FTDI chip are introduced.

[0008] According to a fourth aspect of the present disclosure, a system, an apparatus and a method for adjusting a reference voltage in a fingerprint sensing driver or a FDTI chip are introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A It shows that the fingerprint sensing driver or chip captures the final average fingerprint image after multiple cycles to provide it to the application program (which can execute the corresponding algorithm) for use;

[0010] Figure 1BAn embodiment of capturing fingerprint images of each cycle in a pre-scan image process to provide the fingerprint images to an application program (which can execute a corresponding algorithm) for use;

[0011] Figure 1C An embodiment (fast version) of the FTDI application using the pre-scan image process is shown;

[0012] Figure 1D Another embodiment (no-truncate version) of the FTDI application using the pre-scanned image program is shown;

[0013] Figure 2A FIG. 1 is a diagram illustrating charge injection of a pixel reset switch in a pixel circuit;

[0014] Figure 2B is a schematic diagram of charge injection;

[0015] Figure 2C The control method of the previous panel reset signal is shown;

[0016] Figure 2D An embodiment of the FTDI constant slope pulse mechanism;

[0017] Figure 2E Example of a timing diagram showing the FTDI constant slope pulse mechanism;

[0018] Figure 2F An embodiment of a multi-segment slope constant slope pulse is shown;

[0019] Figure 2G is a schematic block diagram of an embodiment of a constant slope pulse generator;

[0020] Figure 2H It is a multi-stage slope control pulse generator and the corresponding control signal and output signal waveform diagram;

[0021] Fig.2I An embodiment of multi-stage discharge pulse control is shown;

[0022] Figure 2J An example of a multi-stage discharge pulse control system implemented on a panel is shown;

[0023] Figure 2K An embodiment of the impedance current limiting pulse generation mechanism is shown;

[0024] Figure 2L A schematic block diagram of an embodiment of implementing an impedance-limited current pulse generator on a panel;

[0025] Figure 3A Shows the unlocking process of display panel and FTDI fingerprint;

[0026] Figure 3B A schematic diagram of the sensor sensing the peak and valley signals of the finger;

[0027] Figure 3C is a schematic flow chart of an embodiment of a dynamic offset adjustment mechanism;

[0028] Figure 3D A schematic diagram of the DDAC switching action and digital operation time;

[0029] Figure 3E It shows that after compensation, the individual sensor output is subtracted from the DAC average voltage;

[0030] Figure 3F A schematic block diagram showing an embodiment of implementing a dynamic offset adjustment mechanism, wherein an analog module is required;

[0031] Figure 3G A schematic block diagram showing another embodiment of a dynamic offset adjustment mechanism, wherein an AFE2 analog module for amplifying the peak-to-valley signal phase difference is further added;

[0032] Figure 3H An embodiment showing another method of finding a DDAC;

[0033] Fig. 3I Indicates that when supporting multi-finger recognition and simultaneous reading, the DDAC needs to be adjusted accordingly to the different pressing areas of each finger

[0034] Figure 3J The sensor dark current and sensor power drop are different in different areas of the large screen.

[0035] Figure 4A Shows the unlocking process of display panel and FTDI fingerprint;

[0036] Figure 4B Schematic diagram of the panel and readout IC, showing the resetting of the panel photodiode voltage;

[0037] Figure 4C Schematic diagram of the panel and readout IC, showing the first sampling of CDS;

[0038] Figure 4DSchematic diagram of the panel and readout IC, which shows the second sampling and subtraction readout of the CDS;

[0039] Figure 4E is a schematic block diagram of the feedback loop during the second sampling;

[0040] Figure 4F Schematic diagram of the light and dark distribution of fingerprints;

[0041] Figure 4G Displays the relationship between the number of constants required for convergence (N) and the final value gap voltage (LSB), from which the convergence time required by the AFE for the difference between the fingerprint voltage and the reference voltage can be obtained;

[0042] Figure 4H An example showing the operation of the circuit during the reset phase;

[0043] Fig. 4I An example showing the operation of the circuit in readout phase 1;

[0044] Figure 4J An example showing the operation of the circuit in readout phase 2;

[0045] Figure 4K A schematic flow chart showing an embodiment of the FTDI CDS reference voltage adaptation mechanism process;

[0046] Figure 4L A schematic flow chart showing another embodiment of the FTDI CDS reference voltage adaptation mechanism process;

[0047] Figure 4M A schematic block diagram of an embodiment of a display panel and a readout IC readout architecture;

[0048] Figure 4N A schematic flow chart showing an embodiment of a multiple CDS reference voltage adaptation readout process;

[0049] Fig.4O is a schematic diagram of an embodiment of a pixel voltage prediction method;

[0050] Figure 4P An example showing the operation of the circuit in readout phase 1; and

[0051] Figure 4Q An example showing the operation of the circuit in readout phase 2.

[0052] Reference numerals

[0053] 1A, 1B, 1C, 1D Computing equipment

[0054] 10, 10C, 10D panels

[0055] 11, 11C, 11D Gate-on-array (GOA) circuit

[0056] 12 fingerprint sensor elements (pixels)

[0057] 20A, 20B Electronic Module

[0058] 21A, 21B, 21C, 21D Slope Configuration Circuit

[0059] 22A, 22B, 22C, 22D Fingerprint sensing control circuit

[0060] 110 Shift register

[0061] 112 Switch DETAILED DESCRIPTION

[0062] Embodiments of the present disclosure will be described below with reference to the drawings. Various modifications to the embodiments and features described herein will be apparent to those skilled in the art. Therefore, the present disclosure is not limited to the embodiments shown, but should be given the widest scope consistent with the principles and features described herein. Accordingly, some aspects of the present disclosure are described or depicted herein for the purpose of illustration and not limitation.

[0063] First, a system, device or method for a fingerprint sensing driver (or chip) to provide a pre-scanned fingerprint pattern to an application is introduced.

[0064] In some embodiments, a method for a fingerprint sensing driver (or chip) to provide a pre-scanned fingerprint pattern to an application (e.g., a program executed by an application processor) is provided, comprising the following steps:

[0065] (S10) performing a plurality of exposure cycles; and

[0066] (S20) After at least one exposure cycle and before the last exposure cycle, the pre-scanned fingerprint pattern is output to a memory.

[0067] In one embodiment, the method may further include: notifying the application to obtain a pre-scanned fingerprint image from a memory.

[0068] In one embodiment, the method may further include: after the last exposure cycle, outputting the final fingerprint state

[0069] In one embodiment, the exposure cycle includes: reset, exposure, and SMP (sampling).

[0070] In one embodiment, the notifying step includes: sending an interrupt to the application.

[0071] In one embodiment, the pre-scan fingerprint pattern includes measured light brightness average information.

[0072] In one embodiment, the pre-scan fingerprint pattern includes a truncated fingerprint image obtained through an exposure cycle.

[0073] In one embodiment, the memory is located in the fingerprint driver (or chip).

[0074] In some embodiments, after performing a second exposure cycle to obtain a second pre-scan fingerprint pattern, the second pattern may be averaged with the first pattern, or the first pattern may be directly replaced.

[0075] The following examples, embodiments or descriptions are related to a method for a fingerprint sensing driver (or chip) to provide a pre-scanned fingerprint pattern to an application.

[0076] The following describes a fingerprint sensing driver or chip (such as a computing device (such as a smart device)) that uses a pre-scan image process (pre-scan image process) to generate a pre-scan fingerprint data pattern or data set in an optical fingerprint recognition process, and provides it in advance to an application of a processor of the computing device (such as a smart device) that is communicatively connected to the fingerprint sensing driver in various ways such as the embodiments proposed below, wherein the application can use the pre-scan fingerprint data pattern (pre-scan fingerprint data pattern) or data set to perform fingerprint recognition functions, such as unlocking function algorithms in advance. In this way, the performance of large-area screen fingerprint recognition functions (such as unlocking functions) can be improved.

[0077] Regarding the basic architecture principle of optical fingerprint recognition, when the fingerprint sensing driver or chip receives the command from the host to capture the fingerprint, it will reset, expose, and then sample the captured data. When optical fingerprint recognition captures fingerprints, in order to reduce the excessive interference of noise on the fingerprint image and reduce the recognition rate, a common method is to average multiple fingerprint images for processing.

[0078] If the noise is processed by multi-cycle surface averaging, in order to obtain the final fingerprint image, it is necessary to wait until the set number of cycles is completed to obtain the best fingerprint image. However, the waiting time is:

[0079] (The set number of cycles) * (the total time to complete a frame including reset, exposure and then sampling and grabbing data).

[0080] In one embodiment, in the process of capturing data in multiple cycles, in addition to capturing the final fingerprint image of the surface average after the multiple cycles, after each cycle, the image information of the current cycle will be provided to the application (which can execute the corresponding algorithm) for pre-scanning processing, which is called the pre-scan image program.

[0081] For example, the content provided to the application (which can execute the corresponding algorithm) for pre-scanning processing includes image information, average information of the measured brightness of the entire frame, or other information.

[0082] For example Figure 1A As shown, assuming that the number of scan cycles in this example is 4 cycles (such as Figure 1A The data output of the final average image (FAI) will be performed after the fourth cycle (such as cycle 4) ends (in Figure 1A The FAI data is represented by a box containing the FAI data output, which is read by the application program and then performed by the application program (which can execute the corresponding algorithm) for subsequent comparison processing. Figure 1A In the example, the AlgorithmProcess box represents the processing of the application program, and the box containing R represents the reset period, the exposure box represents the exposure period, and the subsequent box containing S represents the sampling period; and in the Figure 1A The boxes representing consecutive reset, exposure, and sampling periods on the same row may represent the above reset, exposure, and sampling actions for the fingerprint sensing elements of a row in the fingerprint sensor (or fingerprint sensor). However, the implementation of the present disclosure is not limited to the above examples.

[0083] If the noise is processed by multi-cycle surface averaging, in order to obtain the final fingerprint image, it is necessary to wait until the set number of cycles is completed to obtain the best fingerprint image. However, the waiting time is:

[0084] (The set number of cycles) * (the total time to complete a frame including reset, exposure and then sampling and grabbing data).

[0085] In one embodiment, if Figure 1B As shown, in the process of capturing data in multiple cycles, in addition to capturing the final fingerprint image of the surface average after the end of multiple cycles, the image information of the current cycle will be provided after each cycle. Figure 1B The pre-scanning image process is referred to as the pre-scanning image process. The content provided to the application program (which can execute the corresponding algorithm) for pre-scanning processing includes: for example, image information, average brightness information of the entire screen, or other information. Figure 1B The algorithm blocks in the figure represent the processing steps of the application program and the subsequent processing is performed after the cycle 1 is completed.

[0086] In today's field of optical fingerprint recognition, it is integrated with the touch / driver into an IC, which we call fingerprint, display, touch IC (FDTI or FTDI).

[0087] In one embodiment, if Figure 1C As shown in the figure, it is an operation timing diagram of a single IC of FTDI. In the FTDI application, the action interval of fingerprint recognition is the finger-cycle in the figure (such as the boxes of F-cycle 1, F-cycle 2 to F-cycle 5 to represent the period of the cycle). In this embodiment, the pre-scanned image data (in Figure 1C The pre-scanned IDO box represents the time period required for outputting data) to the application program (which can execute the corresponding algorithm) for pre-comparison processing. Figure 1C The processing sequence of the application is represented by the blocks of the calculation program, and the subsequent processing is performed in advance after the end of F-cycle 2. Figure 1C In the example, D-cycle 1 indicates a display cycle; D-cycle and F-cycle appear alternately, indicating that in a single IC such as FTDI, the internal timing of the single IC processes display and fingerprint related work at different time periods, such as the timing of the interface of the single IC for display and fingerprint related data. However, the present disclosure is not limited to the above examples. In implementing Figure 1C Or other embodiments of outputting data in advance regarding fingerprint data may be configured not to be limited by the above-mentioned display cycle example.

[0088] For the current display frequency of 60hz, each cycle takes 16.6ms, and the transmission time of image data output is:

[0089] Interface transfer time * Panel X size * Panel Y size * Number of bits per pixel

[0090] If the fingerprint recognition application is displayed on a large screen, the increase in X / Y size will inevitably cause the transmission time to become longer, which will affect the working interval of the next finger-cycle, that is, greater than 16.6ms*2=33.2ms. In order to achieve the purpose of pre-scanning in this application, the number of bits per pixel transmitted will be processed. In this embodiment, assuming that the number of bits per pixel originally transmitted is 12 bits, in large-screen applications, in order not to prolong the transmission time, we will transmit truncated pixel information, such as 8 bits, 10 bits or other suitable bits, to achieve the pre-scan image process. With this embodiment (fast version), the processing efficiency can be improved.

[0091] In another embodiment, the original pixel image data may be transmitted without being truncated (for example, originally 12 bits) to an application (which may execute a corresponding algorithm) for processing. Figure 1D As shown, compared to Figure 1C If the number of data bits is reduced (e.g. 8 or 10 bits), the transmission time will be longer because the number of bits per pixel is the original number of bits (e.g. 12 bits), which will affect the time of the next finger-cycle interface capture and cause interface transmission interface control conflicts. Figure 1D As shown in , the image data transmission time of finger-cycle 1 is greater than 33.2ms, which affects the image data reading of finger-cycle 2. In this application, in order to prevent the conflict between finger-cycle 3 and finger-cycle 4, the pre-scanned image data (12 bits) of finger-cycle 1 will be provided to the application program (which can execute the corresponding algorithm) for processing in this embodiment (non-truncated version), and the data of finger-cycle 2 and finger-cycle 3 will not be provided to avoid interface conflicts, and finally the final average image will be provided to the application program (which can execute the corresponding algorithm).

[0092] The effects of the multiple embodiments disclosed above are that, in a multi-cycle processing program, the application (which can execute the corresponding algorithm) can first perform the corresponding algorithm executed by the application according to the pre-scan information provided by at least one cycle, such as the fingerprint comparison judgment program. If the application determines that the comparison is a match, the comparison can be completed in advance to save unlocking time and improve the user experience speed. The application (which can execute the corresponding algorithm) does not have to wait until the set number of multi-cycles is completed before performing the comparison and consuming unnecessary time. In this way, the overall performance can be improved, allowing users to obtain a better user experience.

[0093] Secondly, a system, an apparatus and a method for adjusting the slope of a signal of a fingerprint sensing driver or a FDTI chip are introduced.

[0094] In some embodiments, a device capable of facilitating reducing charge injection relative to a fingerprint sensor, the device for coupling to a fingerprint sensor having a plurality of fingerprint sensing elements associated with a display panel, the device comprising:

[0095] a signal generator circuit for generating a reset signal having a configurable falling edge; and

[0096] A fingerprint sensing control circuit is coupled to the fingerprint sensor and is used to selectively promote the signal generator circuit to output a reset signal to at least a portion of the fingerprint sensing element of the fingerprint sensor, and the fingerprint sensing control circuit outputs a clock signal to the fingerprint sensor so as to respectively reset a portion of the fingerprint sensing element during a reset phase of the fingerprint sensor.

[0097] The signal generator circuit is used to configure the reset signal with a falling edge to have a slope smaller than the slope of the clock signal, so as to reduce the charge injection in the fingerprint sensing element that has been reset.

[0098] In some embodiments, the signal generator circuit is operable to configure the reset signal to have a falling edge that includes a segment and falls substantially in a segmented manner.

[0099] In some embodiments, the signal generator circuit is operable to configure the reset signal to have a falling edge that includes a plurality of downward sloping segments and falls substantially in a stepwise manner.

[0100] In some embodiments, the signal generator circuit is operable to configure the reset signal to have a falling edge that includes a plurality of steps and falls substantially in a stepwise manner.

[0101] In some embodiments, the signal generator circuit is operable to configure the reset signal to have a falling edge that includes at least one step and at least one segment and falls substantially in a stepwise manner.

[0102] In some embodiments, the signal generator circuit comprises:

[0103] a first inverter having an input terminal and an output terminal for receiving the pulse signal, wherein when the pulse signal drops from a high voltage level to a low voltage level, the first inverter is powered by a current source; and

[0104] The second inverter has an input terminal coupled to the output terminal of the first inverter and has an output terminal for outputting a reset signal, wherein the input terminal and the output terminal of the second inverter are capacitively coupled.

[0105] In some embodiments, the signal generator circuit comprises:

[0106] a first inverter having an input terminal and an output terminal for receiving a pulse signal, wherein when the pulse signal drops from a high voltage level to a low voltage level, the first inverter is sequentially powered by a plurality of current sources; and

[0107] The second inverter has an input terminal coupled to the output terminal of the first inverter and has an output terminal for outputting a reset signal, wherein the input terminal and the output terminal of the second inverter are capacitively coupled.

[0108] In some embodiments, the device is implemented in a single chip and the signal generator circuit is located in the device.

[0109] In some embodiments, the device is implemented in a single die and the signal generator circuit is external to the device.

[0110] In some embodiments, a computing device is provided, comprising:

[0111] a display panel having a touch sensor and a fingerprint sensor;

[0112] a signal generator circuit for generating a reset signal with a configurable falling edge (as exemplified in one or a combination of the above embodiments, as appropriate); and

[0113] A fingerprint sensing control circuit coupled to a fingerprint sensor (as exemplified in one or a combination of the above embodiments, as appropriate).

[0114] The following describes a mechanism for adjusting the signal slope in a fingerprint sensing driver or chip (eg, disposed in a computing device (eg, a smart device)).

[0115] Before further providing embodiments of the second aspect of the present disclosure, the problem of charge injection of a pixel reset switch (or reset switch) in a pixel circuit is discussed. Figure 2A Schematic diagram of charge injection into a pixel reset switch in a pixel circuit. Figure 2B Figure 2 is a schematic diagram of charge injection. The optical fingerprint reading circuit needs to use the pixel circuit to expose and obtain the fingerprint image. In Figure 2, a pixel circuit PX for a pixel is shown, which includes a reset switch (for example, represented by MRST), a photodiode, a capacitor C1, and an additional switch for selecting a pixel (for example, represented by MSF and MSEL). In addition, RST_IN represents an input reset signal (or reset signal), RST represents a reset signal output by a buffer, VBIAS represents a signal for biasing, SEL represents a signal for selecting a pixel, and SOUT represents an output signal of a pixel. The fingerprint sensor may include, for example, a plurality of fingerprint sensing elements in the form of an array or matrix, each of which may be based on the pixel circuit PX. The MRST switch in the pixel will affect the voltage of the Q point (i.e., the node) after the reset due to the charge injection generated when the RST signal drops.

[0116] During reset, the Q point is reset to VDD, but when MRST is turned off, the channel electrons on the MRST switch (such as those caused by Q ch Express) release (such as Q ch Part of mQ ch or nQ ch ) to the Q point, causing charge injection and a voltage drop at the Q point.

[0117]

[0118] This effect is reduced by the slower drop of the MRST switch voltage.

[0119]

[0120] Figure 2C The figure shows the control method of the reset signal of the previous panel. The previous panel could not control the slew rate (SR) of the reset control signal because the panel used a shift register to control the signal generation of each row. After the RST pulse was generated from the shift register, the reset (RST) voltage level of the pixel was derived from VH and VL (such as RST pulses, RST1-RST4).

[0121] Under such conditions, if the buffer speed is to be fast, the fall time will be very short, so the charge injection will be very serious. If the buffer speed is too slow, the pixels in the entire row of the push panel will have different fall times, causing each pixel in a row to have a different charge injection amount, and thus reset to different voltages, causing noise to the image.

[0122] Therefore, the disadvantages of the prior art are: since the slope of the reset switch cannot be controlled, the buffering speed is fast, and the charge injection effect is severe and cannot be controlled.

[0123] Therefore, a second aspect of the present disclosure provides the following embodiments.

[0124] In some embodiments, an electronic module includes:

[0125] a slew rate (SR) configuration circuit for generating at least one output signal and sending the at least one output signal to a gate on array (GOA) circuit of the panel; and

[0126] A fingerprint sensing control circuit is coupled to the plurality of fingerprint sensing elements of the panel to generate a plurality of control signals and transmit the plurality of control signals to the GOA circuit, wherein the fingerprint sensing control circuit controls the GOA circuit to generate a plurality of reset signals according to the at least one output signal, and the slope configuration circuit controls the slope of the falling edge of each reset signal, and the GOA circuit resets the plurality of fingerprint sensing elements respectively.

[0127] In some embodiments, a computing device includes:

[0128] A panel including a gate-on-array (GOA) circuit and a plurality of fingerprint sensing elements;

[0129] a slope configuration circuit for generating at least one output signal and sending the at least one output signal to the GOA circuit; and

[0130] A fingerprint sensing control circuit is coupled to the plurality of fingerprint sensing elements to generate a plurality of control signals and transmit the plurality of control signals to the GOA circuit, wherein the fingerprint sensing control circuit controls the GOA circuit to generate a plurality of reset signals according to the at least one output signal, and the slope configuration circuit controls the slope of the falling edge of each reset signal, and the GOA circuit resets the plurality of fingerprint sensing elements respectively.

[0131] In some embodiments, a panel includes:

[0132] Panel body;

[0133] a gate-on-array (GOA) circuit disposed on the panel body; and

[0134] A plurality of fingerprint sensing elements are disposed on the panel body and coupled to the GOA circuit;

[0135] The GOA circuit is configured to receive multiple control signals provided by the fingerprint sensing control circuit, wherein the multiple control signals are used to control the GOA circuit to generate multiple reset signals according to at least one output signal provided by the slope configuration circuit, and the GOA circuit resets the multiple fingerprint sensing elements respectively, wherein the slope of the falling edge of each reset signal can be configured by the slope configuration circuit.

[0136] In one application scenario, an electronic module (e.g., an integrated circuit (IC) of fingerprint, touch, display integration (FTDI or FDTI)) is coupled to a panel of a computing device and drives the panel, and the panel can perform fingerprint sensing on a portion of the screen or the entire screen of the panel of a computing device (e.g., a smart phone, a tablet computer, or other information processing device). The following provides a variety of embodiments to illustrate the use of FTDI's IC to control the closing speed of a pulse signal, and the pulse signal can be sent to the panel to control the RST switch. For example, a fixed slope pulse generated by an IC terminal (such as FTDI's IC) is provided to the panel, so that the falling time / rising time of the RST switch can be appropriate (e.g., not too fast), so that the charge injection effect generated by the pixel during reset can be slowed down. And the closing speed of the RST switch is controlled so that the impact of the charge injection effect is the same and does not change due to the change of the buffer falling time / rising time. In this way, the closing speed of the reset switch is controlled, so that the occurrence of charge injection can be suppressed.

[0137] Figure 2D This is an example of the FTDI fixed slope pulse mechanism. Figure 2D As shown, a computing device 1A (such as a smart phone, a tablet computer or other information processing device) includes a panel 10, a slope configuration circuit (e.g., a fixed slope pulse generator 21A) and a fingerprint sensing control circuit (e.g., an FTDI IC 22A). The slope configuration circuit and the fingerprint sensing control circuit can be implemented and included in an electronic module such as a single chip (e.g., an FTDI IC; or any single chip including a fingerprint sensing control function or a fingerprint driver circuit). The panel 10 includes a gate-on-array (GOA) circuit 11 and a plurality of fingerprint sensing elements 12, each of which is based on, for example, a Figure 2AThe optical fingerprint sensing element of the pixel circuit PX in the embodiment of the present invention. The slope configuration circuit (e.g., 21A) is used to generate at least one output signal (e.g., a fixed slope pulse) and send it to the GOA circuit 11. The fingerprint sensing control circuit (e.g., 22A) is coupled to the fingerprint sensing element 12 to generate a plurality of control signals (e.g., a clock signal (CLK) and / or a start signal (STV)) and send them to the GOA circuit 11. The fingerprint sensing control circuit (e.g., 22A) controls the GOA circuit 11 to generate a plurality of reset signals (e.g., RST1, RST2, RST3, RST4) according to the at least one output signal. The slope configuration circuit (e.g., 21A) controls the slope of the falling edge of each reset signal (such as RST1-RST4), and the GOA circuit 11 resets the fingerprint sensing element 12 respectively.

[0138] exist Figure 2D In the embodiment, the GOA circuit 11 includes, for example, a plurality of shift registers 110 and a plurality of switches 112 (e.g., transmission gates). Each shift register 110 is configured to receive at least one of the control signals (e.g., a CLK signal and an STV signal), and is coupled to one of the plurality of switches 112 to generate one of the reset signals (e.g., RST1-RST4) according to at least one output signal (e.g., a constant slope (SR) pulse). Figure 2D In the example shown, the shift register 110 outputs a plurality of switch control signals (eg, SW1 , SW2 , SW3 , SW4 ) to a plurality of switches 112 to generate respective reset signals (eg, RST1 - RST4 ).

[0139] In one example, the shift register 110 of the panel 10 outputs switch control signals (e.g., SW1-SW4) to the switches 112 (e.g., transmission gates) that control the pixels, so that the switches 112 (e.g., transmission gates) can be turned on at different times. The signals of these transmission gates are provided by a constant slew rate pulse generator 21A on the FTDI, so that the constant slew rate pulse can be turned on at the time point of each column, and the pulse is input to each pixel for reset. And the charge injection effect of each pixel can be slowed down and approached to the same through the controlled fall time.

[0140] In one embodiment, a FTDI constant slope pulse mechanism timing is provided. Figure 2D Under the circuit architecture, Figure 2EAn example of a timing diagram of the FTDI constant slope pulse mechanism is shown. In terms of the clock, the clock is generated by CLK to the shift register 110, and the first pulse is generated by the first STV. While the CLK pulse is in progress, the switches 112 corresponding to the switch control signals SW1, SW2, SW3, and SW4 are turned on in sequence.

[0141] In coordination with the timing of CLK, the fixed falling time pulse generated by the CSR pulse generator 21A, under the control of the shift register, sequentially inputs the pulses to each pixel to control their reset, so that the reset switch (such as reset MOS) can be closed slowly to reduce the occurrence of charge injection.

[0142] In some embodiments, the multiple control signals (such as CLK, STV) generated by the fingerprint sensing control circuit (such as 20A) include a clock signal (such as CLK), and the multiple reset signals (such as RST1-RST4) are synchronized with the clock signal. Figure 2E shown.

[0143] In some embodiments, the slope of the falling edge of each of the reset signals (such as RST1-RST4) is reduced to be less than the slope of the falling edge of the clock signal (such as CLK), such as Figure 2E shown.

[0144] In some embodiments, the slope configuration circuit (eg, 20A) configures one of the plurality of reset signals (eg, RST1 - RST4 ) to have a falling edge including a downward slope segment.

[0145] like Figure 2E As shown in the above embodiments, the time sequence of the control signal and the reset signal etc. can be applied to other embodiments (eg Figure 2H-2L one or a combination thereof or related examples), and apply with modification as appropriate.

[0146] In some embodiments, the slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes a plurality of downward sloping segments and falls in a segmented manner, such as Figure 2F shown.

[0147] In one embodiment, a multi-stage slope control is utilized. Figure 2F An embodiment of a multi-slope fixed slope pulse is shown. The slower the pulse slope, the smaller the charge injection effect, but the voltage conversion process takes longer. Since the section where charge injection is sensitive to the pulse slope is when the switch is close to closing, the pulse drop can be divided into multiple sections, and the slope is slower when it is close to closing.

[0148] like Figure 2FAs shown, at t1, the fastest slope SR1 is used to speed up the time required for pulse conversion. When it is close to closing tn, it is most sensitive to charge injection, and the slowest slope SRn is used to reduce the impact of charge injection.

[0149] Various embodiments for implementing a slope configuration circuit are provided below.

[0150] In some embodiments, the slope configuration circuit (e.g., 21A) includes a pulse generator circuit, which is configured to generate a pulse signal used as the at least one output signal and provide the pulse signal to the GOA circuit (e.g., 11), wherein the pulse generator circuit is operable to configure the slope of the falling edge of each reset signal.

[0151] In one embodiment, a constant slope pulse generator is proposed as a pulse generator circuit, such as Figure 2G Please refer to Figure 2G The pulse generator circuit includes: a first inverter (such as Mp1 and Mn1) and a second inverter (such as Mp2 and Mn2). The first inverter, for example, includes transistors Mp1 and Mn1, which have input terminals for receiving input signals (such as Figure 2G The first inverter is powered by one or more current sources. The second inverter includes transistors Mp2 and Mn2, for example, whose input terminals are coupled to the output terminals of the first inverter and have output terminals for outputting the pulse signal (e.g., Figure 2G denoted by point “out” (node ​​“output”) in FIG. 1 ), wherein the input and output of the second inverter are capacitively coupled. For example, the input and output of the second inverter are coupled via at least one capacitor (eg, Co).

[0152] like Figure 2G As shown, this is one of the constant SR pulse generators. A fixed current source Is is used. When the "in" point turns low, Is is used to make the capacitor voltage of capacitor Co rise at a fixed slope, thereby controlling the falling slew rate of the "out" point, SR = Is / Co (that is, the falling slope is equal to the current of the current source divided by the capacitance of capacitor Co). Because the current source Is controls the change in charge of capacitor Co, the slope of this circuit is not affected by the output point load.

[0153] When the in-point voltage changes from low to high, it is used to turn on the pixel reset switch. The output rise time does not need to control the slope, and there is no current limit. It operates in a similar way to the output buffer.

[0154] Furthermore, the slope configuration circuit may be implemented to configure one of the reset signals to have a falling edge that includes a plurality of downward sloping segments and falls in a segmented manner.

[0155] like Figure 2H To achieve multi-stage slope control, just change the Is current at the selected time. The larger the Is, the higher the slope. In other words, the slope configuration circuit can be based on Figure 2G The circuit architecture shown is implemented in that the current source is replaced by a current source circuit capable of outputting a current that changes at a selected time to the first inverter (e.g., Mp1 and Mn1) to configure the falling edge of the pulse at the "output" point (or node) with a multi-stage conversion slope (e.g., Figure 2H In one embodiment, as shown on the left side Figure 2H As shown, the current source circuit includes a plurality of current sources (e.g., two or more current sources, such as Is1, Is2, Is3) and a plurality of switches (e.g., two or more switches, such as Is1SW, Is2SW, Is3SW). Figure 2H As shown, for example, the switches Is1SW, Is2SW, and Is3SW are turned on in sequence, because Is1>Is2>Is3 (for example, the currents of the current sources are different), a gradually slowing down signal can be generated. For example, the switches (for example, Is1SW, Is2SW, Is3SW) sequentially and respectively output currents of different magnitudes in corresponding time periods (for example, t1, t2, t3), and these time periods are controlled by multiple control signals (for example, Is1_EN, Is2_EN, Is3_EN). Therefore, as Figure 2H As shown, a slope configuration circuit capable of configuring the falling edge of a pulse with multiple slopes can be implemented by using a first inverter, a second inverter, and a current source circuit. Optionally, the slope configuration circuit may include a control circuit for generating a control signal (e.g., Is1_EN, Is2_EN, Is3_EN). Figure 2H As shown, the slope configuration circuit can be replaced Figure 2D The constant slope pulse generator 21A in.

[0156] In addition, the slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes at least one step and at least one segment and falls in a segmented manner (for example, as shown in FIG. Fig.2I multi-segment pulse shown on the left).

[0157] Fig.2IAn embodiment of multi-stage discharge pulse control is shown. In addition to directly using a constant slope circuit to control the rise time / fall time of the panel, a multi-stage discharge method can also be used to reduce the occurrence of charge injection. Fig.2I As shown, in one embodiment, when a multi-stage discharge method (greater than two stages) is manufactured at the IC end, the time for VRST (for example, the voltage of a reset signal such as RST1-RST4) to drop directly from VGH to VGL can be slowed down, so that the instantaneous voltage difference seen is reduced, and the occurrence of charge injection is alleviated.

[0158] like Fig.2I As shown, the computing device 1B includes a panel 10 and an electronic module 20B, and the electronic module 20B includes a slope configuration circuit (e.g., 21B) and a fingerprint sensing control circuit (e.g., 22B). The computing device 1B is different from the computing device 1A in that the computing device 1B uses the slope configuration circuit to implement the following Fig.2I The multi-stage discharge pulse control (e.g., multi-stage pulse generator 21B) shown in FIG. Fig.2I The fixed slope pulse generator 21A shown. In some embodiments, the multi-segment pulse generator 21B includes a voltage level generator circuit, which is configured to generate a plurality of output signals having a plurality of predetermined voltage levels (e.g., V1, V2, ..., Vn, n>1), and provides the plurality of output signals to the GOA circuit so that each reset signal transitions based on the predetermined voltage level during the falling edge. The voltage level generator circuit can be implemented to output a multi-segment pulse having a falling edge, which has a plurality of voltage levels (or steps). For example, the voltage level generator circuit can be implemented by using a selection circuit (e.g., a multiplexer or a plurality of switches) coupled to a plurality of power supplies (e.g., voltage or current sources) and selecting some or all of them in turn. In corresponding time periods (e.g., t1, t2, ..., tn), a multi-stage pulse having a falling edge of a plurality of voltage levels (or voltage steps) is outputted by the selection circuit according to a plurality of voltages (e.g., VGH, V1, V2, ..., Vn, VGL) generated by the power supply.

[0159] In some embodiments, the GOA circuit (such as 11) of the panel (such as 10) is Figure 2D or 2I, configured to be coupled to the slope configuration circuit (such as 21A or 21B) implemented in a single chip; Figure 2G or 2H) and the fingerprint sensing control circuit (such as 22A or 22B).

[0160] In some embodiments, the GOA circuit (such as 11C or 11D) of the panel (such as 10C or 10D) is Figure 2JAs shown in or 2L, it is configured to be coupled to the fingerprint sensing control circuit (such as 22C or 22D) implemented in a single chip, and the slope configuration circuit (such as 21A, 21B, 21C or 21D; Figure 2G or 2H) is arranged outside the single chip and located on the panel.

[0161] like Figure 2J As shown in 2L or 21C, a slope configuration circuit (e.g., 21C or 21D) can be implemented on a panel (e.g., 1C or 1D). In this way, for example, the slope configuration circuit can be considered to be included in a gate-on-array (GOA) circuit of the panel. In these embodiments, the panel (e.g., 1C or 1D) includes a panel body (e.g., a body of 1C or 1D), a gate-on-array (GOA) circuit (e.g., 11C or 11D) disposed on the panel body, and a plurality of fingerprint sensing elements (e.g., 12) disposed on the panel body and coupled to the GOA circuit. The GOA circuit (e.g., 11C or 11D) is configured to receive multiple control signals (e.g., CLK and STV) provided by a fingerprint sensing control circuit (e.g., 22C or 22D), wherein the provided control signals are used to control the GOA circuit to generate multiple reset signals (e.g., RST1-RST4) according to at least one output signal provided by a slope configuration circuit (e.g., 21C or 21D), and the GOA circuit (e.g., 11C or 11D) resets the fingerprint sensing element (e.g., 12), wherein the slope of the falling edge of each of the reset signals can be configured by the slope configuration circuit.

[0162] In some embodiments, Figure 2J As shown in FIG. 2 or 2L, the GOA circuit (e.g., 11C or 11D) includes a plurality of shift registers 110. Each shift register 110 is configured to receive at least one of the control signals (e.g., CLK or STV), and is coupled to a slope configuration circuit (e.g., 21C or 21D) to generate a plurality of reset signals (e.g., RST1-RST4) having a plurality of predetermined voltage levels (e.g., VGH, V1, V2, ..., Vn, VGL, n>1 or VH and VL), so that each reset signal transitions based on the plurality of predetermined voltage levels during a falling edge. The output of the shift register 110 can be used to enable or trigger the slope configuration circuit (e.g., 21C or 21D) to generate a reset signal (e.g., RST1-RST4), for example, according to the following. Figure 2E The timing of the control signals and reset signals may be as shown in or similar to that shown in FIG.

[0163] Figure 2J An embodiment of a multi-stage discharge pulse control system on a panel is shown. Figure 2JAs shown, the computing device (e.g., 1C) includes a panel 10C, a slope configuration circuit (e.g., 21C), and a fingerprint sensing control circuit (e.g., 22C). The computing device 1C differs from the computing device 1A or 1B in that the slope configuration circuit (e.g., 21C) is located on the panel (e.g., 1C) of the computing device 1C, rather than being implemented in a single chip with the fingerprint sensing control circuit (e.g., 22C or 22D). For example, the slope configuration circuit (e.g., 21C) can be a pulse controller implemented according to a voltage level generator circuit (e.g., as described above), and is configured to generate multiple reset signals according to multiple predetermined voltages (e.g., VGH, V1, V2, ..., Vn, VGL; n>1). As Figure 2J As shown, the fingerprint detection control circuit (eg, 22C) may be implemented to output control signals (eg, CLK and STV) and a plurality of predetermined voltages to the GOA circuit 11C and the pulse controller 21C, respectively.

[0164] like Figure 2J As shown, the multi-stage discharge generation method, in addition to directly generating pulses at the IC end (such as FTDIIC 22C), can also generate multiple voltages from the IC end. Through the selection of logic on the panel, different voltages can be generated at different times to achieve the same effect. It can slow down the time for VRST (for example, the voltage of the reset signal, such as RST1-RST4; or represented by RSTx; x>1) to drop directly from VGH to VGL, so that the instantaneous voltage difference seen is reduced, and the occurrence of charge injection is alleviated.

[0165] In accordance with Figure 2J In another embodiment, in addition to multiple circuits (such as power supply loops), multiple predetermined voltages (such as VGH, V1, V2, ..., Vn, VGL; n>1) can also be provided by the FTDI IC 22C.

[0166] Furthermore, the slope configuration circuit may be implemented to configure one of the reset signals to have a falling edge that includes at least one step and at least one segment and falls in a segmented manner. Figure 2K An embodiment of the impedance current limiting pulse generation mechanism is shown. Figure 2K As shown, to control the closing speed of the reset switch, in addition to setting the slope, impedance current limiting can also be used. Figure 2D In the embodiment, a pulse is generated at the IC end and injected into the panel, and the rise / fall time of the switch is controlled in this way to reduce the occurrence of charge injection.

[0167] Figure 2L FIG. 1 is a schematic block diagram of an embodiment of implementing an impedance-limited current pulse generator on a panel. Figure 2LAs shown in the figure, to control the closing speed of the reset switch, in addition to controlling the fall time from the IC, you can also use impedance current limiting on the panel to prevent the RST signal from closing too quickly. Figure 2L In the embodiment, a slope configuration circuit (eg, 21C) is implemented by using a plurality of buffer circuits and resistors coupled to the buffer circuits.

[0168] In other embodiments, Figure 2D The slope configuration circuit in or 2I (e.g., 21A or 21B) can be implemented on the panel and considered as part of the GOA circuit 11.

[0169] The effects of the above-disclosed embodiments are that the falling time / rising time of the RST switch can be appropriate (e.g., not too fast), so that the charge injection effect generated by the pixel during the reset can be slowed down. The closing speed of the RST switch is controlled so that the impact of the charge injection effect is the same and does not change due to the change of the falling time / rising time of the buffer. In this way, the closing speed of the reset switch is controlled, so that the occurrence of charge injection can be suppressed.

[0170] Third, a system, apparatus and method for dynamic offset adjustment in a fingerprint sensing driver of an FTDI chip are introduced.

[0171] The following describes a mechanism for dynamic signal offset adjustment in a fingerprint sensing driver or a FDTI chip (eg, disposed in a computing device (eg, a smart device)).

[0172] In FTDI, the fingerprint sensor is implemented on the display panel. It is limited by the dark current of the sensor itself and the offset caused by the non-fingerprint reflected light signal. It is also unable to amplify the fingerprint reflected light signal at an abnormal level of offset. Otherwise, part of the signal will be cut off, thereby sacrificing the usable dynamic range of the signal, resulting in the signal amount and noise difference of the fingerprint peaks and valleys being unable to be widened, which increases the difficulty of back-end algorithm recognition.

[0173] The so-called offset, for the fingerprint reflected light signal, refers to the offset in the signal level caused by various factors. Generally speaking, the offset can be summarized as being related to the finger position and the sensing area.

[0174] The following proposes multiple implementations of a dynamic offset adjustment mechanism to correct the offset caused by the sensor dark current and non-fingerprint reflected light signal in different finger pressing areas.

[0175] In one embodiment, FTDI is used for a large screen, and the fingerprint detection position can be applicable to a full screen. Different pressing positions correspond to different dark currents of the sensor itself and the offsets caused by non-fingerprint reflected light signals.

[0176] In one embodiment, a dynamic offset adjustment mechanism is proposed to correct the offset caused by the sensor dark current and non-fingerprint reflected light signal in different finger pressing areas.

[0177] In one embodiment, the input code of the DAC can be dynamically adapted according to the finger pattern and the selected zone.

[0178] In one embodiment, the input code of the DAC can be an average value or a relatively small value in a specific area within the reporting point area (ZONE).

[0179] In one embodiment, the calibration mechanism can also adjust the corresponding offset compensation according to the different finger peak and valley signals sensed by the sensor, and after compensation, the average value of the finger peak and valley signals can be located at the center of the ADC input full scale. The finger peak and valley signals can enjoy the maximum dynamic range by making a voltage swing relative to their average value.

[0180] Figure 3A To illustrate the display panel & FTDI fingerprint unlocking process. The FTDI fingerprint recognition action, the touch screen reports the fingerprint pressing position, notifies the fingerprint detection area to start the fingerprint recognition action and enters the recognition process, including the panel emitting light to the finger pressing point, the light is reflected by the peaks and valleys of the fingerprint wave, and then converted into a voltage signal by the TFT sensor on the panel and then transmitted to the FTDI, after the analog signal amplification and A / D conversion in the IC, the whole image data is finally output to the back-end algorithm for recognition, completing the fingerprint unlocking process, refer to Figure 3A , the TFT sensor array can be spread across the entire display panel, facilitating fingerprint unlocking actions at any position.

[0181] In large-screen applications, the large screen can be divided into different fingerprint detection areas (zone, Zone(1,1)~Zone(M,N)), so that fingerprint recognition can be performed in the detection area where the finger is placed. Different fingerprint detection areas are used according to the different fingerprint pressing positions, but the dark current of the sensor itself and the offset caused by the non-fingerprint reflected light signal are different for each fingerprint detection area, and dynamic adjustments are required for different fingerprint detection areas. Taking a fingerprint detection area as an example, the sensor senses the peak and valley signals of the finger as shown by the red / green cylinder, which includes the dark current and the offset caused by the non-fingerprint reflected light signal. The phase difference value of the peak and valley signal is the effective information required for identification rather than other offsets. Refer to Figure 3B, the offsets of different zones are different (offset(1,1)≠offset(M,N)), that is, the average values ​​are also different (avg(1,1)≠avg(M,N)), so fixed offset correction cannot be applied and corresponding adjustments are required.

[0182] Figure 3C FIG. 1 is a schematic flow chart of an embodiment of a dynamic offset adjustment mechanism. Figure 3C As shown, the dynamic offset adjustment mechanism (or method) includes the following steps:

[0183] (S110) selecting the fingerprint detection area by touching the point;

[0184] (S120) capturing outputs of multiple sensor groups in the detection area, including peak and valley signals, dark current, and other environmental deviations;

[0185] (S130) Averaging is performed in the digital domain to obtain an average code, which is transmitted to the DAC to generate a corresponding voltage ex:avg(1,1);

[0186] (S140) Subtracting the voltage between the individual sensor output and the average voltage generated by the DAC;

[0187] (S150) Enter ADC conversion.

[0188] Figure 3D D DAC Schematic diagram of switching action and digital operation time. Figure 3D It indicates that there are multiple operation cycles in the fingerprint sensor driver or FDTI chip, such as the first readout frame indicates the time interval for resetting the fingerprint sensor, the second display frame corresponds to the exposure time interval, and the second readout frame indicates the time interval for capturing multiple sensor outputs in the detection area. DAC1 In the first readout frame, a preset value is used; in the second display frame, multiple sensor outputs in the detection area are captured, and a preliminary capture (or pre-scan) is first performed and digital operations (such as Figure 3D The time interval shown by the frame line of the digital operation) and obtain an average code (D DAC2 ), in the second readout frame, the DAC is fed back to generate a corresponding average voltage V DAC , and in this code (D DAC2 ) and capture the outputs of multiple sensor groups in the detection area again. Figure 3D In, D DAC The corresponding curves are for illustration only. DAC The value of D DAC The implementation of this embodiment is not limited to this example.

[0189] Figure 3E It shows that after compensation, the output of individual sensors is subtracted from the DAC average voltage. After compensation, the offset can be removed in the subtraction of the DAC average voltage, so that the average value of the finger peak and valley signal is located at the center of the ADC input full scale. The finger peak and valley signal read by individual sensors can swing the voltage value relative to its average value, and can enjoy the largest dynamic range. Although the avg(1,1)~avg(m,n) of different fingerprint patterns and different fingerprint detection areas are different, the fingerprint center can be located at 0.5FS after closed-loop correction, such as Figure 3E As shown, where FS stands for full-scale.

[0190] Figure 3F A schematic block diagram showing an embodiment of a dynamic offset adjustment mechanism is shown, wherein an analog module is required. Figure 3F As shown, a digital averaging module is required to average the CODEs converted from the outputs of multiple sets of sensors in the selected detection area and obtain an average code (D DAC ), a DAC analog module generates V DAC For voltage output, the individual sensor output is subtracted from the average voltage generated by the DAC, V ADC =(G AFE1 V sensor -V DAC ), and then enter the ADC.

[0191] Figure 3G A schematic block diagram showing another embodiment of the dynamic offset adjustment mechanism is shown, wherein an AFE2 analog module is further added to amplify the peak-to-valley signal phase difference. In this embodiment, after the dynamic offset adjustment mechanism is implemented, the finger peak-to-valley signal read by each sensor can swing in voltage relative to its average value, and its center value falls at 0.5FS. Therefore, an additional AFE2 can be placed in front of the ADC to further amplify the peak-to-valley signal phase difference of the effective data sensor. ADC =[(G AFE1 V sensor -V DAC )G AFE2 ] to facilitate algorithm identification.

[0192] For example, the digital averaging module in the above implementation can average the codes converted from the outputs of multiple sets of sensors in the selected detection area according to the following steps to obtain an average code (D DAC ).

[0193] (S210) activating the selected fingerprint detection area by touching the point;

[0194] (S220) determining whether to perform translation processing on the position of the reported point, so that the individual pixel positions required for averaging can be located in the selected ZONE area to avoid taking empty pixel outputs resulting in a low average value, the required number of pixels and columns can be adjusted;

[0195] (S230) Observe the histogram of the data, filter the data to be included in the sample space for averaging, set two thresholds (for example, Vth_l and Vth_h are adjustable), collect the pixel outputs that fall within the corresponding limits, and ensure the accuracy of the average value of the fingerprint peaks and valleys;

[0196] (S240) Averaging the data in the filtered sample space to obtain a DAC code for generating an analog voltage output representing the average value of the fingerprint peaks and valleys.

[0197] When individual pixels in the selected ZONE area enter the average sample interval, several pixels above, below, left, and right of the touch point can be selected according to the touch point, wherein the number of pixels and the number of columns can be adjusted. However, the implementation of this embodiment is not limited to the above example.

[0198] Figure 3H Indicates to find D DAC In this embodiment, it is also possible to find V in the signal output by the sensor. sensor The relatively small value of D DAC , and then fed back to the DAC to generate a corresponding voltage, retaining the effective peak and valley signal difference value.

[0199] Fig. 3I When supporting multi-finger recognition and simultaneous reading, the pressing area of ​​each finger is different, D DAC In this embodiment, when multiple fingers are supported for simultaneous reading, fingerprint signals of multiple ZONE zones are read out in sequence according to the different pressing areas of each finger. The DDAC used in the process needs to be adjusted accordingly (ex: DAC1 & DAC2). Here, two fingers are used as an illustration, and it can also be extended to multiple fingers.

[0200] Figure 3J This shows that the dark current and power drop of the sensor are different in different areas of the large screen. In this embodiment, the dark current (Idark) and the offset (dV) caused by the power drop of the sensor are different in different areas of the large screen, which can also be eliminated by this method.

[0201] The multiple embodiments disclosed above can achieve the effect of dynamic signal offset adjustment, so that the finger peak and valley signals can swing in voltage relative to their average value, thereby enjoying the largest dynamic range.

[0202] Fourth, a system, device and method for adjusting the reference voltage in a fingerprint sensing driver of an FTDI chip are introduced.

[0203] The following describes a FTDI CDS (correlated double sampling) reference voltage adaptation mechanism in a fingerprint sensing driver or FDTI chip (eg, disposed in a computing device (eg, a smart device)).

[0204] Figure 4A The schematic diagram shows the process of display panel and FTDI fingerprint unlocking. The FTDI fingerprint recognition action includes the panel emitting light to the finger pressing point. After the light is reflected by the peaks and valleys of the fingerprint wave, it is converted into a voltage signal by the TFT sensor on the panel and then transmitted to FTDI. After analog signal amplification and A / D conversion in the IC, the entire image data is finally output to the back-end algorithm for recognition, completing the fingerprint unlocking process. Refer to Figure 4A , the TFT sensor array can be spread across the entire display panel, facilitating fingerprint unlocking actions at any position.

[0205] Because the fingerprint sensor is implemented on the entire panel, the readout signal line must run through the entire panel. This readout signal line is long and has a large parasitic capacitance, which will cause a delay in the induced current of the AFE's readout photodiode.

[0206] Currently, the reading method of the passive optical fingerprint sensor on the panel is to use the CDS method to read the voltage. The CDS can be divided into or include four phases (or steps).

[0207] 1. (e.g. Figure 4B As shown in the figure, each pixel on the panel is reset first. There is a front-end amplifier on the IC corresponding to each column of the panel. The feedback switch of the front-end amplifier is short-circuited, so that the OP output voltage will be locked at the Vrst reset voltage. The switches s1, s2... to sY are controlled to be turned on one by one in sequence, and closed after the reset voltage. The sensing array voltage of the entire panel will be reset to the Vrst voltage.

[0208] 2. After the voltage of the photodiode is reset to Vrst, due to the irradiation of light, the refractive index at the contact surface between the finger and the panel glass is different, and the reflected light is different, causing the photodiode to generate different photocurrents, which are stored in the capacitors of each pixel.

[0209] 3. (such as Figure 4C As shown in the figure, the front-end amplifier feedback is short-circuited, but the pixel is not turned on. At this time, Cpar is charged to Vrst, and Cf1~CfX are discharged until there is no voltage difference. At this time, the first sampling Vo1p~Voxp is performed, and the offset voltage of Vrst+OP will be sampled.

[0210] 4. (such as Figure 4D As shown in the figure, the pixel switch is turned on. Since the Vsout voltage will be locked at Vrst+OP offset voltage by the OP feedback loop, the pixel exposure charge will be amplified to the AFE output end. At this time, the second sampling Vo1n~Voxn will sample Vrst plus OP offset voltage + Qlight / Cf.

[0211] By subtracting the offset and rst voltage from the first sampling, Qlight / Cf can be obtained as Vo1~Vox. Repeat steps 3~4 to complete the reading of the entire panel image.

[0212] Figure 4E This is a schematic block diagram of the feedback loop during the second sampling. Since the Cpar of the Sout line running through the display panel is very large (about 50pF level), but in order to sense the charge-to-voltage conversion, the feedback capacitance on the OP is small (about 0.1pF level), and the feedback of Cpar to Cf will cause the OP bandwidth to be attenuated by about 500 times relative to the unity gain bandwidth, requiring a longer stabilization time for the two samplings of the CDS.

[0213] It can be seen that in the above-mentioned situation where the parasitic capacitance of Cpar is large, the AFE requires a long stabilization time. Therefore, in the multiple embodiments provided below, the reference voltage of CDS is adjusted with each exposure voltage, so that the two readout voltages of CDS are close. By reducing the difference between the two output voltages of AFE, the required stabilization time is reduced. Therefore, the embodiment can reduce the voltage difference between the two samplings of CDS by adjusting the CDS reference voltage, reduce the stabilization time required for the AFE output between sampling, and thus improve the efficiency of signal acquisition.

[0214] The Cpar of the Sout line that runs through the display panel is very large (about 50pF level). However, in order to sense the conversion of charge to voltage, the feedback capacitance on the OP is small (about 0.1pF level). The feedback of Cpar to Cf will cause the OP bandwidth to be attenuated by about 500 times relative to the unity gain bandwidth, and a longer stabilization time is required for the two samplings of CDS.

[0215] Figure 4F This is a schematic diagram of the light and dark distribution of fingerprints. Figure 4F As shown, the difference between the brightness of the peak and valley is very small (about 10mV), but the overall environment difference is large (1V level).

[0216] Figure 4G The relationship between the number of constants required for convergence (N) and the final value difference voltage (LSB) is shown, from which the convergence time required by the AFE for the difference between the fingerprint voltage and the reference voltage can be obtained. Figure 4G As shown, if the average voltage of the finger is used as a reference value when the CDS is read, the voltage difference that needs to be changed in the output when the AFE is read can be reduced, and the convergence time required for the brightness difference of the finger pixel can be reduced. The reading accuracy can also be improved under a fixed convergence time.

[0217] Figure 4H An example showing the operation of the circuit during the reset phase. Figure 4H , the required reset voltage is output to the photodiode through OP. Since OP has an offset voltage, the voltage will be reset to Vrst+Vofs.

[0218] After exposure, the exposure signal at the center of the finger is pre-read as the reference value for the entire finger reading signal. Vexpa is the average exposure voltage at the center of the finger, and Vexpd is the difference between the finger pixel and the average value at the center of the finger. Exposure starts from Vrst, and the finger reference voltage is Vrst-Vexpa. Fig. 4I An example showing the operation of the circuit in readout phase 1. Fig. 4I For example, when CDS is in phase 1, Vrst-Vexpa (a preset value is used) is applied to the positive terminal of OP, so after feedback, the first CDS reading can obtain Vrst+Vofs-Vexpa as the first reading voltage.

[0219] Figure 4J An example of the operation of the display circuit in the readout stage 2. The second readout of the CDS reads out the exposure voltage Vrst+Vofs-Vexpa-Vexpd. The part of Vexpd that is fed back by the OP will be read out and amplified to the OP output. The second sampling voltage of the CDS is Vrst+Vofs-Vexpa+Vexpd(Cd / Cf). Between the two samplings, the voltage difference of the OP output is Vexpd(Cd / Cf). Since the voltage difference between the mean value of the finger center and the fingerprint pixel is very small, Vexpd(Cd / Cf) only needs a short time to stabilize.

[0220] Figure 4K A schematic flow chart showing an embodiment of the FTDI CDS reference voltage adaptation mechanism process. Figure 4KAs shown, the embodiment of this process includes a pre-scan step and a normal reading step. In this embodiment, after the panel touch unit reports the finger position, the finger center position or the position sufficient to represent the finger exposure position is first read out and sampled. After the voltage is calculated, the voltage is provided to the positive end of the OP as a reference voltage. This voltage is used as a setting to sequentially read the entire finger image, shortening the AFE reading convergence time.

[0221] Figure 4L A schematic flow chart showing another embodiment of the FTDI CDS reference voltage adaptation mechanism process. Figure 4L As shown, the embodiment of this process includes a first image reading step (first image reading) and a second image reading step (second image reading). In this embodiment, a finger image reading (first image reading) is performed first, and the appropriate CDS reference voltage is calculated by the operation unit. After the voltage is calculated, the voltage is provided to the OP positive terminal as a reference voltage. This voltage is used as a setting to sequentially read the entire finger image (second image reading), thereby reducing the time required for convergence and improving the AFE image reading quality.

[0222] Figure 4M A schematic block diagram of an embodiment of a display panel and a readout IC readout architecture. Figure 4M It is the circuit architecture of the panel CDS reference voltage adaptation mechanism. First, the center position of the finger is selected and read out. The CDS reference level process unit of the readout IC generates the required reference voltage after calculation. When reading out, it is used as the reference voltage for the AFE, which accelerates the convergence time required for the AFE to perform CDS.

[0223] Figure 4N A schematic flow chart showing an embodiment of a multiple CDS reference voltage adaptation readout process. Figure 4N As shown, the embodiment of this process includes a pre-scan step and an image reading step. In this embodiment, as Figure 4N As shown, in order to avoid the interference of some dirt or noise on the finger, which affects the accuracy of pre-reading, the best fingerprint image can be obtained by adjusting Vref multiple times (such as pre-scan) and then exposing and reading, or the fingerprint features of multiple images can be combined to piece together a better fingerprint pattern.

[0224] like Figure 4N As shown, after the fingerprint center is read out, the fingerprint center brightness is used to generate the first Vref and then the image is read. Then, Vref is added to Vd and the image is re-exposed and read to obtain the read image after the Vref reference voltage is modulated, and the image is handed over to the computing unit for judgment and adjustment.

[0225] For example, Vd is not limited to positive or negative, and can have multiple values ​​for multiple exposure readings. The size of Vd and the number of times it needs to be adjusted can also be determined after the first pre-scan.

[0226] exist Figure 4N In the process, for example, the judgment condition of the step "OP positive end Vref needs to be adjusted" can be determined according to conditions related to image quality, or the number of reads can be used as a judgment condition, for example, whether the number of reads has reached a threshold value (for example, a value of 2 or more) as a judgment condition.

[0227] In some embodiments or the aforementioned embodiments, a pixel voltage prediction method may be used. When pre-scanning the voltage, a voltage representing the finger voltage needs to be found to adjust the CDS reference voltage. Fig.4O For example, after the touch panel reports the finger center, a representative area such as 16 pixels (4x4) of the estimated fingerprint center (or finger center) is pre-read after exposure to obtain the voltages of these 16 pixels, where the representative area can be any suitable area smaller than the original fingerprint image area, such as an area of ​​4x4, 6x6, 8x8 pixels or any other area.

[0228] Then, the CDS reference level processing unit of the readout IC as mentioned above calculates the average value (or median or any value that can characterize this representative area) of this representative area to obtain the representative voltage representing the exposure voltage of the entire finger, and generates a new CDS reference voltage and outputs it to the positive end of OP, which is the CDS reference voltage for the next "normal reading" (such as the entire area, such as the original fingerprint image area). In this way, the efficiency of adjustment can be improved.

[0229] In one embodiment, a prescan voltage acquisition method is disclosed. By pre-reading the voltage of a few pixels, a representative voltage value of the center of the finger can be obtained. Figure 4P As shown, in the readout phase 1, the CDS1 voltage generated by Vrst (or other reference voltage) is first read; Figure 4Q As shown, in the readout phase 2, the voltage of CDS2 is read to obtain the difference of Vx(Cd / Cf), wherein since Vrst, Cd, and Cf are known parameters, and Vofs is relatively small and negligible, the voltage value of Vrst+Vofs-Vx can be inferred from Vx(Cd / Cf). The above-mentioned embodiment of the method for obtaining the prescan voltage can be applied to any of the above-mentioned embodiments requiring the prescan voltage.

[0230] The above-disclosed embodiments can reduce the voltage difference between two CDS samples by adjusting the CDS reference voltage, and reduce the stabilization time required for the AFE output between samples, thereby improving the efficiency of signal acquisition.

[0231] In addition, in some of the aforementioned embodiments, whether the reset, sampling and readout (or selection, or sensing, in short, readout) actions can be completed in one fingerprint (FPR) FRAME (called a readout frame in the figure), or whether it will take at least one display frame so that the reset and readout are achieved in different FPR FRAMEs. This involves the operating speed of the FPR module itself, relative to the time length of the FPR FRAME. Therefore, the implementation of the present disclosure is not limited to these examples.

[0232] There are different implementation methods in actual applications. For example, even if the FPR module does not operate fast enough, the FPR module can be designed so that the time of the FPR FRAME is sufficient to complete the reset, sampling or readout operation of one FPR FRAME.

[0233] For another example, in an integrated IC (such as a fingerprint, display, touch IC (FDTI), or other ICs including fingerprint processing), a display frame (display frame) is inserted between multiple FPR frames (frames) (even mixed with touch). In addition, there are various time-sharing methods for display and FPR modules or frames, and the implementation of the present disclosure is not limited to these examples.

[0234] Although the present disclosure has been described through specific embodiments, those skilled in the art may make various modifications and variations thereto or any combination thereof where appropriate without departing from the scope and spirit of the present disclosure.

Claims

1. An electronic module, characterized in that: include: a slope configuration circuit for generating at least one output signal and transmitting the at least one output signal to an array upper gate circuit of the panel; and A fingerprint sensing control circuit is coupled to the plurality of fingerprint sensing elements of the panel to generate a plurality of control signals and transmit the plurality of control signals to the array upper gate circuit, wherein the fingerprint sensing control circuit controls the array upper gate circuit to generate a plurality of reset signals according to the at least one output signal, and the slope configuration circuit controls the slope of the falling edge of each reset signal, the array upper gate circuit resets the plurality of fingerprint sensing elements respectively, the plurality of control signals generated by the fingerprint sensing control circuit include a clock signal, the plurality of reset signals are synchronized with the clock signal, and the slope configuration circuit also reduces the slope of the falling edge of each of the reset signals to be less than the slope of the falling edge of the clock signal.

2. The electronic module according to claim 1, characterized in that: The slope configuration circuit includes a pulse generator circuit configured to generate a pulse signal used as the at least one output signal and provide the pulse signal to the array upper gate circuit, wherein the pulse generator circuit is operable to configure the slope of the falling edge of each reset signal.

3. The electronic module according to claim 1, characterized in that: The slope configuration circuit includes a voltage level generator circuit configured to generate the plurality of output signals having a plurality of predetermined voltage levels and provide the plurality of output signals to the array upper gate circuit so that each reset signal transitions based on the plurality of predetermined voltage levels during a falling edge.

4. The electronic module according to claim 1, characterized in that: The slope configuration circuit configures one of the plurality of reset signals to have a falling edge including a downward slope segment.

5. The electronic module according to claim 1, characterized in that: The slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes a plurality of downward sloping segments and falls in a segmented manner.

6. The electronic module according to claim 1, characterized in that: The slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes at least one step and at least one segment and falls in a segmented manner.

7. The electronic module according to claim 2, characterized in that: The pulse generator circuit comprises: a first inverter having an input for receiving an input signal and an output, wherein the first inverter is powered by one or more current sources; and The second inverter has an input terminal coupled to the output terminal of the first inverter and has an output terminal for outputting the pulse signal, wherein the input terminal and the output terminal of the second inverter are capacitively coupled.

8. A computing device, characterized in that include: A panel, the panel comprising an array gate circuit and a plurality of fingerprint sensing elements; a slope configuration circuit for generating at least one output signal and sending the at least one output signal to the array upper gate circuit; and A fingerprint sensing control circuit is coupled to the plurality of fingerprint sensing elements to generate a plurality of control signals and transmit the plurality of control signals to the array upper gate circuit, wherein the fingerprint sensing control circuit controls the array upper gate circuit to generate a plurality of reset signals according to the at least one output signal, and the slope configuration circuit controls the slope of the falling edge of each reset signal, the array upper gate circuit resets the plurality of fingerprint sensing elements respectively, the plurality of control signals generated by the fingerprint sensing control circuit include a clock signal, the plurality of reset signals are synchronized with the clock signal, and the slope configuration circuit further reduces the slope of the falling edge of each of the reset signals to be less than the slope of the falling edge of the clock signal.

9. The computing device according to claim 8, characterized in that The slope configuration circuit includes a pulse generator circuit configured to generate a pulse signal used as the at least one output signal and provide the pulse signal to the array upper gate circuit, wherein the pulse generator circuit is operable to configure the slope of the falling edge of each reset signal.

10. The computing device according to claim 8, characterized in that The slope configuration circuit includes a voltage level generator circuit configured to generate the plurality of output signals having a plurality of predetermined voltage levels and provide the plurality of output signals to the array upper gate circuit so that each reset signal transitions based on the plurality of predetermined voltage levels during a falling edge.

11. The computing device according to claim 8, characterized in that The slope configuration circuit configures one of the plurality of reset signals to have a falling edge including a downward slope segment.

12. The computing device according to claim 8, characterized in that The slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes a plurality of downward sloping segments and falls in a segmented manner.

13. The computing device according to claim 8, characterized in that The slope configuration circuit configures one of the plurality of reset signals to have a falling edge that includes at least one step and at least one segment and falls in a segmented manner.

14. The computing device according to claim 9, characterized in that The pulse generator circuit comprises: a first inverter having an input for receiving an input signal and an output, wherein the first inverter is powered by one or more current sources; and The second inverter has an input terminal coupled to the output terminal of the first inverter and has an output terminal for outputting the pulse signal, wherein the input terminal and the output terminal of the second inverter are capacitively coupled.

15. The computing device according to claim 8, characterized in that The slope configuration circuit and the fingerprint sensing control circuit are implemented in a single chip.

16. The computing device according to claim 8, characterized in that The fingerprint sensing control circuit is implemented in a single chip, and the slope configuration circuit is arranged outside the single chip and on the panel.

17. The computing device according to claim 8, characterized in that The array upper gate circuit includes a plurality of shift registers and a plurality of switches, each of the shift registers being configured to receive at least one of the control signals and coupled to a corresponding one of the plurality of switches to generate a corresponding reset signal according to the at least one output signal.

18. The computing device according to claim 8, characterized in that The array upper gate circuit includes a plurality of shift registers, each of the shift registers being configured to receive at least one of the control signals and being coupled to the slope configuration circuit to generate a plurality of reset signals having a plurality of predetermined voltage levels, so that each reset signal transitions based on the plurality of predetermined voltage levels during a falling edge.

19. A panel, characterized in that: include: Panel body; An array grid circuit is arranged on the panel body; and A plurality of fingerprint sensing elements are disposed on the panel body and coupled to the array upper gate circuit; The array gate circuit is configured to receive a plurality of control signals provided by a fingerprint sensing control circuit, wherein the plurality of control signals are used to control the array gate circuit to generate a plurality of reset signals according to at least one output signal provided by a slope configuration circuit, and the array gate circuit resets the plurality of fingerprint sensing elements respectively, wherein the slope of the falling edge of each reset signal can be configured by the slope configuration circuit, the plurality of control signals generated by the fingerprint sensing control circuit include a clock signal, the plurality of reset signals are synchronized with the clock signal, and the slope configuration circuit also reduces the slope of the falling edge of each of the reset signals to be less than the slope of the falling edge of the clock signal.

20. The panel according to claim 19, characterized in that The array top gate circuit is configured to receive the at least one output signal, the at least one output signal having a falling edge including a downward slope segment.

21. The panel according to claim 19, characterized in that The array upper gate circuit is configured to receive the at least one output signal having a falling edge including a plurality of downward sloping segments and falling in a segmented manner.

22. The panel according to claim 19, characterized in that The array upper gate circuit is configured to receive the at least one output signal having a falling edge including at least one step and at least one segment and falling in a segmented manner.

23. The panel according to claim 19, characterized in that The array-on-gate circuit is configured to be coupled to the slope configuration circuit and the fingerprint sensing control circuit implemented in a single chip.

24. The panel according to claim 19, characterized in that The on-array gate circuit is configured to be coupled to the fingerprint sensing control circuit implemented in a single chip, and the slope configuration circuit is arranged outside the single chip and located on the panel.

25. The panel according to claim 19, characterized in that The array upper gate circuit includes a plurality of shift registers and a plurality of switches, each of the shift registers being configured to receive at least one of the control signals and coupled to a corresponding one of the plurality of switches to generate a corresponding reset signal according to the at least one output signal.

26. The panel according to claim 19, characterized in that The array upper gate circuit includes a plurality of shift registers, each of the shift registers being configured to receive at least one of the control signals and being coupled to the slope configuration circuit to generate a plurality of reset signals having a plurality of predetermined voltage levels, so that each reset signal transitions based on the plurality of predetermined voltage levels during a falling edge.

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