Display device and method for manufacturing a display device

Abstract

A display device and a method for manufacturing the display device, the display device including a substrate, a first conductive layer on the substrate and including a lower light-blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light-blocking pattern through the anode electrode, and at least a portion of the second semiconductor pattern is insulated from and overlaps each of the first signal line and the second signal line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all rights arising therefrom of Korean Patent Application No. 10-2020-0043332, filed on April 9, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device and a method for manufacturing a display device. Background Technology

[0004] Electronic devices that provide images to users, such as televisions, smartphones, tablet PCs, digital cameras, laptops, and navigation systems, include display devices for displaying images.

[0005] A display device is a means for displaying images and includes a display panel such as a light-emitting display panel or a liquid crystal display panel. In the aforementioned panel, the light-emitting display panel may include light-emitting elements. Examples of light-emitting diodes (“LEDs”) include organic light-emitting diodes (“OLEDs”) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0006] The display device may include multiple pixels and pixel circuitry for driving each pixel. Each pixel circuitry includes a thin-film transistor and wiring formed on an insulating substrate. Summary of the Invention

[0007] Within each pixel, parasitic capacitors may be generated in the overlapping portions of the wiring. Aspects of this disclosure provide a display device capable of suppressing or preventing the formation of parasitic capacitors.

[0008] Various aspects of this disclosure also provide methods for manufacturing display devices capable of suppressing or preventing the formation of parasitic capacitors.

[0009] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0010] An embodiment of the display device includes: a substrate; a first conductive layer disposed on the substrate and including a lower light-blocking pattern and a first signal line; a buffer layer disposed on the first conductive layer; a semiconductor layer disposed on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separate from the first semiconductor pattern, the first semiconductor pattern including a channel region of a transistor; an insulating layer disposed on the semiconductor layer and including an insulating layer pattern; a second conductive layer disposed on the insulating layer and including a second signal line; a planarization layer disposed on the second conductive layer; and a third conductive layer disposed on the planarization layer and including an anode electrode, wherein the first semiconductor pattern is electrically connected to the lower light-blocking pattern through the anode electrode, and wherein at least a portion of the second semiconductor pattern is insulated from and overlaps each of the first signal line and the second signal line in the thickness direction.

[0011] In an embodiment of a display device including a storage capacitor and at least one transistor, the at least one transistor includes a first semiconductor pattern. The display device includes: a substrate; a first conductive layer disposed on the substrate and including a first electrode of the storage capacitor and a first signal line; a buffer layer disposed on the first conductive layer; a semiconductor layer disposed on the buffer layer and including the first semiconductor pattern and a second semiconductor pattern separate from the first semiconductor pattern; an insulating layer disposed on the semiconductor layer; and a second conductive layer disposed on the insulating layer and including a gate electrode of the transistor, a second electrode of the storage capacitor, and a second signal line, wherein the first signal line and the second signal line overlap each other in at least a portion of a region in the thickness direction, wherein at least a portion of the second semiconductor pattern is disposed in the overlapping region where the first signal line and the second signal line overlap, and wherein, in the overlapping region, the distance between the first signal line and the second signal line in the thickness direction is greater than the distance between the first electrode and the second electrode of the storage capacitor in the thickness direction.

[0012] In an embodiment of a method for manufacturing a display device, the method includes: forming a first conductive layer on a substrate, comprising a first signal line and a first electrode of a storage capacitor; forming a buffer layer on the substrate to cover the first conductive layer; depositing a semiconductor layer material and an insulating layer material over the entire buffer layer; etching the semiconductor layer material and the insulating layer material respectively to form an insulating layer and a semiconductor layer, wherein the semiconductor layer comprises a first semiconductor pattern of a transistor and a second semiconductor pattern separate from the first semiconductor pattern; and forming a second conductive layer on the insulating layer, comprising a gate electrode of the transistor, a second electrode of the storage capacitor, and a second signal line, wherein the first signal line and the second signal line overlap each other in at least a portion of a region in a thickness direction, wherein at least a portion of the second semiconductor pattern is disposed in the overlapping region where the first signal line and the second signal line overlap each other in the thickness direction, and wherein, in the overlapping region, the distance between the first signal line and the second signal line in the thickness direction is greater than the distance between the first electrode and the second electrode of the storage capacitor in the thickness direction.

[0013] According to the display device and the method of manufacturing the display device in accordance with exemplary embodiments, the formation of parasitic capacitors can be suppressed or prevented, and the reliability of the product can be improved.

[0014] The effects of this disclosure are not limited to those described above, and various other effects are included in this specification. Attached Figure Description

[0015] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0016] Figure 1 This is a plan view of a display device according to an exemplary embodiment;

[0017] Figure 2 This is a block diagram schematically illustrating a display device according to an exemplary embodiment;

[0018] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment;

[0019] Figure 4 This is a layout diagram of a pixel of a display device according to an exemplary embodiment;

[0020] Figure 5 yes Figure 4 An enlarged view of the outer region of the first semiconductor dummy pattern;

[0021] Figure 6 It is along Figure 4 A cross-sectional view taken from lines A-A' and B-B';

[0022] Figure 7 This is a flowchart of a method for manufacturing a display device according to an exemplary embodiment;

[0023] Figures 8 to 19 It shows the manufacturing process. Figure 6 A cross-sectional view of the steps of a method for displaying one pixel of the device shown;

[0024] Figure 20 This is an enlarged view of the peripheral region of the first semiconductor dummy pattern according to another embodiment;

[0025] Figure 21 It is along Figure 20 A cross-sectional view taken from line XXI-XXI';

[0026] Figure 22 This is an enlarged view of the peripheral region of a first semiconductor dummy pattern according to yet another embodiment; and

[0027] Figure 23 It is along Figure 22 The cross-sectional view taken from line XXIII-XXIII'. Detailed Implementation

[0028] The invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0029] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0030] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Therefore, a first element discussed below may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “At least one” is not to be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” or “containing” and / or “having” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof. Exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a plan view of a display device according to an exemplary embodiment.

[0033] Reference Figure 1 Display device 1 is a device for displaying moving or still images. Display device 1 can be used as a display screen for various products and portable electronic devices, such as televisions, laptops, monitors, billboards, and the Internet of Things, and portable electronic devices such as mobile phones, smartphones, tablet PCs (“Tablet PCs”), smartwatches, watch phones, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (“PMPs”), navigation systems, and ultra-mobile PCs (“UMPCs”).

[0034] The display device 1 according to an exemplary embodiment may have a substantially rectangular shape in a plan view. The display device 1 may also have a rectangular shape with right-angled corners in a plan view. However, it is not limited thereto; in another exemplary embodiment, the display device 1 may have a rectangular shape with rounded corners in a plan view.

[0035] In the accompanying drawings, the first direction DR1 represents the horizontal direction (e.g., the direction of the long side) of the display device 1 in a plan view, and the second direction DR2 represents the vertical direction (e.g., the direction of the short side) of the display device 1 in a plan view. Furthermore, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly. The third direction DR3 is the direction that intersects with the plane on which the first direction DR1 and the second direction DR2 are positioned, and intersects both the first direction DR1 and the second direction DR2 perpendicularly. However, it should be understood that the directions mentioned in the embodiments refer to relative directions, and the embodiments are not limited to the mentioned directions.

[0036] Unless otherwise defined, the terms “above,” “top surface,” and “upper side” as used herein refer to the display surface side of the display device 1, and the terms “below,” “bottom surface,” and “lower side” as used herein refer to the side opposite to the display surface of the display device 1.

[0037] Figure 2 This is a block diagram schematically illustrating a display device according to an exemplary embodiment.

[0038] Reference Figure 1 and Figure 2 The display device 1 according to an exemplary embodiment may include a display panel 10, a timing controller 21, a data driver 22, and a scan driver 30.

[0039] Display panel 10 may be an organic light-emitting display panel. In the following embodiments, the case in which an organic light-emitting display panel is used as display panel 10 is described as an example, but the present disclosure is not limited thereto, and in another exemplary embodiment, other types of display panels such as liquid crystal display (“LCD”) panels, quantum dot display (“QD-Display”) panels and micro LED panels may be used as display panel 10.

[0040] Display panel 10 may include a display area DA for displaying images and a non-display area NDA in which no images are displayed. In a plan view, display panel 10 may be divided into display area DA and non-display area NDA. Non-display area NDA may be configured to surround display area DA. Non-display area NDA may form a border.

[0041] The display area DA in a planar drawing can be a rectangle with right angles or rounded corners. However, the planar shape of the display area DA is not limited to a rectangle, but can be a circle, an ellipse, or various other shapes.

[0042] The display area DA may include multiple pixels PX. The pixels PX may be arranged in a matrix. Each pixel PX may include an emissive layer and a circuit layer for controlling the amount of light emitted by the emissive layer. The circuit layer may include wiring, electrodes, and at least one transistor. The emissive layer may include an organic light-emitting material. The emissive layer may be encapsulated by an encapsulation layer. The following description will focus on the case where the emissive layer is an organic light-emitting layer, but this disclosure is not limited thereto. A detailed configuration of the pixels PX will be described later.

[0043] The non-display area NDA can be configured to be adjacent to the two short sides and two long sides of the display area DA. In this case, the non-display area NDA can surround all the sides of the display area DA and form the edge of the display area DA. However, this disclosure is not limited to this, and the non-display area NDA can be configured to be adjacent to the two short sides or the two long sides of the display area DA, rather than being adjacent to all the short sides and long sides of the display area DA.

[0044] Within the display area DA, not only can pixel PX be configured, but also multiple scan lines SL1, SL2, ..., to SLk (k is an integer of 2 or greater) (hereinafter referred to as "SL1 to SLk"), multiple data lines DL1, DL2, ..., to DLj (j is an integer of 2 or greater) (hereinafter referred to as "DL1 to DLj"), and multiple power lines (not shown) connected to pixel PX can be configured. Scan lines SL can extend along a first direction DR1 and can be arranged along a second direction DR2. Data lines DL can extend along the second direction DR2 and can be arranged along the first direction DR1.

[0045] The display panel 10 includes a plurality of pixels PX positioned at the intersection of a plurality of scan lines SL1 to SLk (k is an integer of 2 or greater) and a plurality of data lines DL1 to DLj (j is an integer of 2 or greater) and arranged in a matrix. Each pixel PX can be connected to at least one of the scan lines SL and one of the data lines DL.

[0046] The timing controller 21 receives image signals RGB and timing signals CS from the host system. The timing signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The host system may be an application processor of a smartphone or tablet PC, a system-on-a-chip of a monitor or TV, etc.

[0047] The timing controller 21 generates control signals for controlling the operating timing of the data driver 22 and the scan driver 30. The control signals may include a source control signal CONT2 for controlling the operating timing of the data driver 22 and a scan control signal CONT1 for controlling the operating timing of the scan driver 30.

[0048] The scan driver 30 receives a scan control signal CONT1 from the timing controller 21. The scan driver 30 generates scan signals S1, S2, ..., Sk (k is an integer of 2 or greater) based on the scan control signal CONT1 (hereinafter referred to as "S1 to Sk"), and supplies the scan signals S1 to Sk to the scan lines SL1 to SLk of the display panel 10. The scan driver 30 may include multiple transistors and may be disposed in the non-display area NDA of the display panel 10. Alternatively, the scan driver 30 may be formed as an integrated circuit, and in this case, the scan driver 30 may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0049] Data driver 22 receives digital video data DATA and source control signal CONT2 from timing controller 21. Data driver 22 converts the digital video data DATA into analog data voltage according to the source control signal CONT2 and supplies the analog data voltage to the data lines DL1 to DLj of display panel 10. Each pixel PX emits light with a predetermined brightness according to the data signals D1, D2, ..., Dj (j is an integer of 2 or greater) transmitted through data lines DL1 to DLj, through the driving current supplied to the light-emitting element.

[0050] A power supply circuit (not shown) can generate the voltage required to drive the display panel 10 from the main power supply applied from the system board, and can supply said voltage to the display panel 10. For example, the power supply circuit (not shown) can supply the light-emitting element OLED (see [link to relevant documentation]) for driving the display panel 10 from the main power supply. Figure 3 The first power supply voltage ELVDD( Figure 3 (as shown) and the second power supply voltage ELVSS ( Figure 3 As shown in the diagram, the first power supply voltage ELVDD and the second power supply voltage ELVSS can be supplied to the first power line ELVDL of the display panel 10, respectively. Figure 3 (as shown) and the second power line ELVSL ( Figure 3 (As shown in the diagram). Furthermore, a power supply circuit (not shown) can generate and supply drive voltages from the main power supply for driving the timing controller 21, data driver 22, and scan driver 30, etc. The power supply circuit (not shown) can be formed as an integrated circuit and mounted on a circuit board, but the present disclosure according to the invention is not limited thereto.

[0051] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0052] Reference Figure 3A pixel PX may include a first transistor TR1, a second transistor TR2, a light-emitting element OLED, and a storage capacitor Cst. Although Figure 3 The illustration shows a 2-transistor-1-capacitor (“2T1C”) structure for each pixel PX, comprising two transistors TR1 and TR2 and a storage capacitor Cst; however, this disclosure is not limited thereto. Each pixel PX may include multiple transistors and multiple capacitors. For example, in another exemplary embodiment, various modified pixel structures, such as 3T1C, 6T1C, and 7T1C structures, may be applied to each pixel PX.

[0053] Each of the first transistor TR1 and the second transistor TR2 may include a first source / drain electrode, a second source / drain electrode, and a gate electrode. One of the first source / drain electrode and the second source / drain electrode may be a source electrode, and the other may be a drain electrode.

[0054] Each of the first transistor TR1 and the second transistor TR2 can be formed by a thin-film transistor. Furthermore, although... Figure 3 The illustration shows that each of the first transistor TR1 and the second transistor TR2 is formed of an N-type metal-oxide-semiconductor field-effect transistor (“MOSFET”), but this disclosure is not limited thereto. In another exemplary embodiment, each of the first transistor TR1 and the second transistor TR2 may be formed of a P-type MOSFET. In this case, the positions of the source and drain electrodes of each of the first transistor TR1 and the second transistor TR2 may be interchanged. In the following description, it is assumed that the first transistor TR1 and the second transistor TR2 are N-type MOSFETs.

[0055] The first transistor TR1 can be a driving transistor. Specifically, the gate electrode of the first transistor TR1 is connected to the second source / drain electrode of the second transistor TR2 and the second electrode of the storage capacitor Cst. The first source / drain electrode of the first transistor TR1 is connected to the first power supply line ELVDL. The second source / drain electrode of the first transistor TR1 is connected to the anode (or pixel electrode) of the light-emitting element OLED. The first transistor TR1 receives a data signal Dj (j is an integer of 1 or greater) according to the switching operation of the second transistor TR2 (see...). Figure 2 This allows the driving current to be supplied to the light-emitting element OLED.

[0056] The gate electrode of the second transistor TR2 is connected to the scan line SL. The first source / drain electrode of the second transistor TR2 is connected to the data line DL. The second source / drain electrode of the second transistor TR2 is connected to the gate electrode of the first transistor TR1 and the second electrode of the storage capacitor Cst. The second transistor TR2 is connected according to the scan signal Sk (k is an integer of 1 or greater) (see...). Figure 2 And then turn on to execute the transfer of data signal Dj (j is an integer of 1 or greater) (see...) Figure 2 The switching operation transmitted to the gate electrode of the first transistor TR1.

[0057] The first electrode of the storage capacitor Cst can be connected to the first power line ELVDL and the first source / drain electrode of the first transistor TR1, and the second electrode of the storage capacitor Cst can be connected to the gate electrode of the first transistor TR1 and the second source / drain electrode of the second transistor TR2. The storage capacitor Cst can be used to keep the data voltage applied to the gate electrode of the first transistor TR1 constant.

[0058] The OLED light-emitting element can emit light according to the driving current of the first transistor TR1. The OLED light-emitting element can be an organic light-emitting diode comprising an anode electrode (or a first electrode), an organic light-emitting layer, and a cathode electrode (or a second electrode). However, the type of OLED light-emitting element according to the present invention is not limited thereto. The anode electrode of the OLED light-emitting element can be connected to the second source / drain electrode of the first transistor TR1, and the cathode electrode of the OLED light-emitting element can be connected to the second power supply line ELVSL, which is subjected to a second power supply voltage ELVSS lower than the first power supply voltage ELVDD.

[0059] The planar arrangement and cross-sectional structure of the aforementioned pixel PX will be described in detail below.

[0060] Figure 4 This is a layout diagram of a pixel of a display device according to an exemplary embodiment. Figure 5 yes Figure 4 An enlarged view of the outer region of the first semiconductor dummy pattern. Figure 6 It is along Figure 4 The cross-sectional view taken from lines A-A' and B-B'.

[0061] In the following embodiments, even if some elements are related to the reference Figures 1 to 3 The components mentioned are essentially the same, but some of them are still indicated by new reference numerals to facilitate the description of the arrangement and coupling between the components.

[0062] Reference Figures 4 to 6A pixel PX can include a light-emitting region EA and a circuit region CA. The light-emitting region EA is the area in which a light-emitting element OLED is disposed to emit light. The circuit region CA includes a first transistor (…). Figure 3 "TR1" (the same below), the second transistor ( Figure 3 "TR2" (the same applies below) and capacitors ( Figure 3 The first transistor is electrically connected to the first power supply line (Cst, as used below). Figure 3 The “ELVDL” (hereinafter referred to as “112”), data cable ( Figure 3 The “DL” (hereinafter referred to as “114”) and scan lines ( Figure 3 (SL in the text, referred to as "144" below).

[0063] Each of transistors TR1 and TR2 includes a conductive layer forming electrodes, a semiconductor pattern forming a channel, and an insulating layer. The storage capacitor Cst includes a conductive layer forming electrodes and an insulating layer disposed between the conductive layers. Specifically, the storage capacitor Cst includes a first electrode 113 (or the lower electrode of the capacitor) and a second electrode 143 (or the upper electrode of the capacitor), and an insulating layer disposed between the first electrode 113 and the second electrode 143 of the storage capacitor Cst. The aforementioned conductive material, conductive layer, semiconductor layer, and insulating layer are disposed on the substrate 101.

[0064] Display panel 10 according to an exemplary embodiment (see Figure 2 The display panel 10 includes a semiconductor layer 130, multiple conductive layers, and multiple insulating layers disposed on a substrate 101. The multiple conductive layers may include a first conductive layer 110, a second conductive layer 140, and a third conductive layer 150. The multiple insulating layers may include a buffer layer 120, a gate insulating layer GI, a passivation layer PVX, and a via layer VIA. Each layer of the display panel 10 may include a barrier layer 102, a first conductive layer 110, a buffer layer 120, a semiconductor layer 130, a gate insulating layer GI, a second conductive layer 140, a passivation layer PVX, a via layer VIA, a third conductive layer 150, and a pixel defining layer PDL, disposed sequentially on the substrate 101. Each of the above layers may consist of a single layer or a stack of multiple layers. Other layers may be further disposed between these layers.

[0065] The substrate 101 supports various layers disposed on the substrate 101. For example, the substrate 101 may be made of an insulating material such as a polymer resin. Examples of insulating materials may include polyethersulfone (“PES”), polyacrylate (“PA”), polyarylate (“PAR”), polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyallylate, polyimide (“PI”), polycarbonate (“PC”), cellulose triacetate (“CAT”), cellulose acetate propionate (“CAP”), or combinations thereof. The substrate 101 may include a metallic material.

[0066] The substrate 101 can be a flexible substrate that can be bent, folded, or rolled. Examples of materials for the flexible substrate include polyimide (PI), but the invention is not limited thereto.

[0067] When the organic light-emitting display device is bottom-emitting or double-sided-emitting, a transparent substrate can be used. When the organic light-emitting display device is top-emitting, in addition to a transparent substrate, a translucent or opaque substrate can also be used.

[0068] A barrier layer 102 may be disposed on the substrate 101. The barrier layer 102 can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform surface planarization. The barrier layer 102 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. The barrier layer 102 may be omitted depending on the type of substrate 101 and process conditions.

[0069] The first conductive layer 110 is disposed on the barrier layer 102. However, it is not limited thereto; when the barrier layer 102 is omitted, the first conductive layer 110 can be directly disposed on the substrate 101.

[0070] The first conductive layer 110 includes a first lower light-blocking pattern 111, a first power line 112, a first electrode 113 of a storage capacitor Cst, a data line 114, and a second lower light-blocking pattern 115.

[0071] The first lower light-blocking pattern 111 can be used to prevent light incident from the bottom side of the display panel 10 from entering the semiconductor pattern 131 (specifically, the channel region 131c of the semiconductor pattern 131) of the first transistor TR1 disposed above the first lower light-blocking pattern 111. The first lower light-blocking pattern 111 can be configured to cover the semiconductor pattern 131 of the first transistor TR1 disposed above the first lower light-blocking pattern 111. In a plan view, the first lower light-blocking pattern 111 can be larger than the semiconductor pattern 131 of the first transistor TR1, and the entire area of ​​the semiconductor pattern 131 of the first transistor TR1 can overlap with the first lower light-blocking pattern 111 in the thickness direction (third direction DR3). However, it is not limited to this, the first lower light-blocking pattern 111 can be configured to at least cover the channel region 131c of the semiconductor pattern 131 of the first transistor TR1, and can at least overlap with the channel region 131c of the semiconductor pattern 131 of the first transistor TR1. Furthermore, in another exemplary embodiment, the first lower light-blocking pattern 111 may be smaller than the semiconductor pattern 131 of the first transistor TR1.

[0072] In the plan view, the first lower light-blocking pattern 111 is disposed between the first power line 112 and the data line 114, and may have an island shape. That is, the first lower light-blocking pattern 111 may be spaced apart from the second lower light-blocking pattern 115, the first power line 112, the first electrode 113 of the storage capacitor Cst, and the data line 114.

[0073] In the plan view, the first power line 112 can be positioned to the right of a pixel PX. The first power line 112 can extend in the second direction DR2. The first power line 112 can extend to another pixel PX, which is positioned adjacent to a pixel PX in the second direction DR2.

[0074] The first electrode 113 of the storage capacitor Cst can protrude from one side of the first power line 112 in the first direction DR1. That is, the first electrode 113 of the storage capacitor Cst can branch from the first power line 112 and can extend in the first direction DR1 (more precisely, in the direction opposite to the arrow direction of the first direction DR1). The first electrode 113 of the storage capacitor Cst can be disposed near the center of the circuit region CA. The first electrode 113 of the storage capacitor Cst can be disposed between the first lower light-blocking pattern 111 and the second lower light-blocking pattern 115 (see...). Figure 4 However, the arrangement of the first electrode 113 of the storage capacitor Cst according to the present invention is not limited thereto.

[0075] In the plan view, data line 114 is positioned to the left of pixel PX and can extend in the second direction DR2. Data line 114 can extend to another pixel PX, which is adjacent to pixel PX in the second direction DR2. Data line 114 can be positioned to the left of the first power line 112, while being spaced apart from the first power line 112.

[0076] The second lower light-blocking pattern 115 can be used to prevent light incident from the bottom side of the display panel 10 from entering the semiconductor pattern 132 (specifically, the channel region of the semiconductor pattern (not shown)) of the second transistor TR2 disposed above the second lower light-blocking pattern 115. The second lower light-blocking pattern 115 can be configured to cover the semiconductor pattern 132 of the second transistor TR2 disposed above the second lower light-blocking pattern 115. In a plan view, the second lower light-blocking pattern 115 can be larger than the semiconductor pattern 132 of the second transistor TR2, and the entire area of ​​the semiconductor pattern 132 of the second transistor TR2 can overlap with the second lower light-blocking pattern 115 in the thickness direction (third direction DR3). However, this disclosure is not limited to this, and the second lower light-blocking pattern 115 can be configured to at least cover the channel region (not shown) of the semiconductor pattern 132 of the second transistor TR2, and can at least overlap with the channel region (not shown) of the semiconductor pattern 132 of the second transistor TR2. Furthermore, in another exemplary embodiment, the second lower light-blocking pattern 115 can be smaller than the semiconductor pattern 132 of the second transistor TR2.

[0077] The second lower light-blocking pattern 115 can protrude from one side of the data line 114 in the first direction DR1. That is, the second lower light-blocking pattern 115 can branch from the data line 114 and extend in the first direction DR1.

[0078] The first conductive layer 110 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single layer or multiple layers.

[0079] A buffer layer 120 is disposed on the first conductive layer 110. The buffer layer 120 can serve as an interlayer insulating layer that insulates the first conductive layer 110 from the semiconductor layer 130. The buffer layer 120 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The buffer layer 120 may be omitted depending on the type of substrate 101 and process conditions, etc.

[0080] Semiconductor layer 130 may be disposed on buffer layer 120. Semiconductor layer 130 may include semiconductor pattern 131 of first transistor TR1, semiconductor pattern 132 of second transistor TR2, first semiconductor dummy pattern SD1 and second semiconductor dummy pattern SD2.

[0081] The semiconductor pattern 131 of the first transistor TR1 can be the active layer of the first transistor TR1, and the semiconductor pattern 132 of the second transistor TR2 can be the active layer of the second transistor TR2. The semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 can be arranged for each pixel PX.

[0082] The semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 may extend in the first direction DR1 and may be spaced apart from each other. The semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2 may have an island shape. However, not limited thereto, in another exemplary embodiment, the semiconductor pattern 131 of the first transistor TR1 and / or the semiconductor pattern 132 of the second transistor TR2 may extend in the second direction DR2.

[0083] The semiconductor pattern 131 of the first transistor TR1 may include a channel region 131c of the first transistor TR1, a first source / drain region 131a located on one side of the channel region 131c, and a second source / drain region 131b located on the other side of the channel region 131c. The channel region 131c of the first transistor TR1 is configured to overlap with the gate electrode 141 of the first transistor TR1 located above the channel region 131c in the thickness direction. The first source / drain region 131a and the second source / drain region 131b of the first transistor TR1 are conductive regions and may have greater conductivity and lower resistance than the channel region 131c of the first transistor TR1.

[0084] The first semiconductor dummy pattern SD1 can be disposed in the region where the first power line 112 and the scan line 144 intersect and overlap (hereinafter referred to as the overlapping region OA). The second semiconductor dummy pattern SD2 can be disposed in the region where the data line 114 and the scan line 144 intersect and overlap (overlapping region OA). In the following description, the first semiconductor dummy pattern SD1, the first power line 112, and the scan line 144 will be given in part, but the above description also applies to the second semiconductor dummy pattern SD2, the data line 114, and the scan line 144.

[0085] The first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 can be island-shaped. That is, the first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 can be set to be separate from each other, and can be set to be separate from the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2.

[0086] The first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 can be dummy semiconductor patterns isolated from signal lines (e.g., the first power line 112, data line 114, and scan line 144) or electrodes. That is, separate voltages can be applied to the first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2.

[0087] The overlapping region OA refers to the area in which the first power line 112 extending in the second direction DR2 and the scan line 144 extending in the first direction DR1 overlap each other. The first power line 112 and the scan line 144 extending in different directions in the overlapping region OA may intersect each other. However, not limited thereto, in another exemplary embodiment, the first power line 112 and the scan line 144 may overlap each other in the thickness direction (third direction DR3) while not intersecting each other, or may extend in the same direction in the overlapping region OA.

[0088] Figure 5 The overlapping region OA is shown inside the area where the first power line 112 and the scan line 144 actually overlap, but this is for illustrative purposes. The overlapping region OA is the area where the first power line 112 and the scan line 144 overlap each other in the thickness direction (third direction DR3). Furthermore, although not shown in the figures, the overlapping region OA can refer not only to the area where the first power line 112 and the scan line 144 overlap in the thickness direction (third direction DR3), but also to the area where the data line 114 and the scan line 144 overlap in the thickness direction (third direction DR3).

[0089] Since the first semiconductor dummy pattern SD1 is disposed in the overlapping region OA, the capacitance of parasitic capacitors that may appear in the aforementioned region can be reduced. The parasitic capacitor may include a first power line 112 as a first electrode and a scan line 144 as a second electrode. Furthermore, the parasitic capacitor may include a buffer layer 120 located between the first power line 112 and the scan line 144, the first semiconductor dummy pattern SD1, and the second gate insulating layer pattern GI2 as dielectrics. Because the first semiconductor dummy pattern SD1 is disposed in the overlapping region OA, the distance d2 between the first power line 112 and the scan line 144 in the thickness direction (third direction DR3) can be increased compared to the case where the first semiconductor dummy pattern SD1 is not present.

[0090] When a parasitic capacitor is formed between the first power line 112 and the scan line 144, the dielectric of the parasitic capacitor and the dielectric of the storage capacitor Cst share the same configuration, but the dielectric (or dielectric layer) of the parasitic capacitor may include more layers than the dielectric (or dielectric layer) of the storage capacitor Cst. However, as an example, the dielectric of the storage capacitor Cst may include a buffer layer 120. But when a parasitic capacitor is formed between the first power line 112 and the scan line 144 in the overlap region OA, the dielectric of the parasitic capacitor may further include a first semiconductor dummy pattern SD1 and a second gate insulating layer pattern GI2, as well as the buffer layer 120. That is, when a parasitic capacitor is formed in the overlap region OA, the dielectric of the storage capacitor Cst and the dielectric of the parasitic capacitor share the buffer layer 120, but the dielectric of the parasitic capacitor may further include the first semiconductor dummy pattern SD1 and the second gate insulating layer pattern GI2.

[0091] In this case, by arranging the first semiconductor dummy pattern SD1 and / or the second gate insulating layer pattern GI2 in the overlapping region OA, the capacitance of the parasitic capacitor can be adjusted independently of the capacitance of the storage capacitor Cst. That is, by further setting the first semiconductor dummy pattern SD1 and / or the second gate insulating layer pattern GI2 in the overlapping region OA, the dielectric constant ε of the dielectric of the parasitic capacitor and the distance d (or the thickness of the dielectric) between each conductor (not shown) can be adjusted independently of the storage capacitor Cst (see equation (1) below).

[0092] The thickness of the dielectric of the storage capacitor Cst can be substantially the same as the thickness d1 of the buffer layer 120 (i.e., the length on the third direction DR3) (also referred to as "the distance d1 between the first electrode 113 and the second electrode 143 of the storage capacitor Cst"), and the thickness of the dielectric of the parasitic capacitor can be substantially the same as the distance d2 between the first power line 112 and the scan line 144 in the overlapping region OA (i.e., the length on the third direction DR3) (also referred to as "the thickness d2 of the dielectric of the parasitic capacitor"). Therefore, by setting the first semiconductor dummy pattern SD1 and / or the second gate insulating layer pattern GI2 in the overlapping region OA, the thickness d2 of the dielectric of the parasitic capacitor can be greater than the thickness d1 of the dielectric of the storage capacitor Cst.

[0093] In addition, by setting a first semiconductor dummy pattern SD1 and / or a second gate insulating layer pattern GI2 in the overlapping region OA, the dielectric constant of the dielectric of the parasitic capacitor can be less than the dielectric constant of the dielectric of the storage capacitor Cst.

[0094] The capacitance C of a capacitor can be inversely proportional to the distance d between the conductors (or the thickness of the dielectric), and can be directly proportional to the dielectric constant ε of the dielectric and the overlapping area S between the conductors, as expressed in equation (1) below:

[0095]

[0096] Therefore, in the overlapping region OA, by further arranging the first semiconductor dummy pattern SD1 and / or the second gate insulating layer pattern GI2 in the thickness direction (third direction DR3) between the first power line 112 and the scan line 144, the thickness of the dielectric of the parasitic capacitor can be increased, and / or the dielectric constant of the dielectric of the parasitic capacitor can be decreased. Thus, the capacitance of the parasitic capacitor can be reduced.

[0097] Since the first semiconductor dummy pattern SD1 and the second gate insulating layer pattern GI2 are only further disposed in the overlapping region OA and the nearby region, and not in the region of the storage capacitor Cst, the distance d1 between the first electrode 113 and the second electrode 143 of the storage capacitor Cst (or the thickness of the dielectric of the storage capacitor Cst) and the dielectric constant of the dielectric in the storage capacitor Cst can be maintained. Therefore, the capacitance of the storage capacitor Cst can be kept at a sufficient level without decreasing, but the capacitance of the parasitic capacitor can be reduced.

[0098] The first semiconductor dummy pattern SD1 may cover at least a portion of the overlapping region OA. However, not limited thereto, according to an exemplary embodiment, the first semiconductor dummy pattern SD1 may cover the entire overlapping region OA in which the first power line 112 and scan line 144 overlap each other. In other words, the first semiconductor dummy pattern SD1 may cover the entire area of ​​the overlapping region OA. The entire area of ​​the overlapping region OA may overlap with the first semiconductor dummy pattern SD1 in the thickness direction (third direction DR3), but only a portion of the first semiconductor dummy pattern SD1 may overlap with the overlapping region OA in the thickness direction (third direction DR3).

[0099] The first semiconductor dummy pattern SD1 can have a shape extending from the overlapping region OA. In other words, in a planar view, the first semiconductor dummy pattern SD1 can have a larger size and area than the overlapping region OA. Additionally, as... Figure 5As shown, a first semiconductor dummy pattern SD1 covering the entire area of ​​the overlapping region OA can partially protrude outward from the overlapping region OA. The first semiconductor dummy pattern SD1, overlapping the entire area of ​​the overlapping region OA in the thickness direction (third direction DR3), can extend in the first direction DR1 and / or the second direction DR2 to protrude from the overlapping region OA. The length of the first semiconductor dummy pattern SD1 in the first direction DR1 can be greater than or equal to the width of the first power line 112 in the first direction DR1. The length of the first semiconductor dummy pattern SD1 in the second direction DR2 can be greater than or equal to the width of the scan line 144 in the second direction DR2.

[0100] The planar shape of the first semiconductor dummy pattern SD1 can be a shape corresponding to the planar shape of the overlapping region OA. The overlapping region OA can be set in a rectangular shape in the planar view, and the first semiconductor dummy pattern SD1 can have a rectangular shape in the planar view. However, it is not limited to this; although the overlapping region OA has a rectangular shape in the planar view, in another exemplary embodiment, the first semiconductor dummy pattern SD1 can have a polygonal shape such as a triangle or pentagon, or a circular or elliptical shape while covering the entire area of ​​the overlapping region OA.

[0101] Additionally, as will be described later, the first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 can be formed together in the process of forming semiconductor layer 130. Therefore, the process for forming the first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 will not be further described.

[0102] Semiconductor layer 130 may include an oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (AB) comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). x ), ternary compounds (AB) x C y ) or quaternary compounds (AB) x C y D z In an exemplary embodiment, the semiconductor layer 130 may include indium tin zinc oxide (“IGZO”). However, it is not limited thereto, and the semiconductor layer 130 may be made of polycrystalline silicon, monocrystalline silicon, or amorphous silicon.

[0103] A gate insulating layer GI is disposed on the semiconductor layer 130. The gate insulating layer GI may include a first gate insulating layer pattern GI1 and a second gate insulating layer pattern GI2. The first gate insulating layer pattern GI1 may cover the channel region 131c of the semiconductor layer 130 and may expose the first source / drain region 131a and the second source / drain region 131b as well as the side surface of the semiconductor layer 130. The first gate insulating layer pattern GI1 may be used as the gate insulating layer of the first transistor TR1 in certain regions. The second gate insulating layer pattern GI2 may be used as the dielectric of the parasitic capacitor in the overlapping region OA. In addition, although not shown, a third gate insulating layer pattern (not shown) may be used as the gate insulating layer of the transistor TR2.

[0104] The first gate insulating layer pattern GI1 can overlap with the gate electrode 141 of the first transistor TR1 located above the first gate insulating layer pattern GI1. The second gate insulating layer pattern GI2 can overlap with the scan line 144 located above the second gate insulating layer pattern GI2, and can overlap with the first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 located below the second gate insulating layer pattern GI2. The gate insulating layer GI may not be disposed between the first electrode 113 and the second electrode 143 of the storage capacitor Cst. Therefore, the distance d1 between the first electrode 113 and the second electrode 143 of the storage capacitor Cst can be reduced, and the capacitance of the storage capacitor Cst can be increased.

[0105] By providing a second gate insulating layer pattern GI2 in the overlap region OA, the capacitance of the parasitic capacitor can be reduced when it is formed between the first power line 112 and the scan line 144 in the overlap region OA. Since the second gate insulating layer pattern GI2 is only provided in the overlap region OA and its vicinity, and not in the region of the storage capacitor Cst, the distance d1 (or the thickness of the dielectric of the storage capacitor Cst) between the first electrode 113 and the second electrode 143 of the storage capacitor Cst can be maintained, thus preventing a decrease in the capacitance of the storage capacitor Cst. In other words, by further arranging the second gate insulating layer pattern GI2 between the first power line 112 and the scan line 144 in the overlap region OA, the capacitance of the parasitic capacitor can be reduced while maintaining the capacitance of the storage capacitor Cst.

[0106] The second gate insulating layer pattern GI2 can be formed simultaneously with the process of forming the gate insulating layer GI. Therefore, the process for forming the second gate insulating layer pattern GI2 is not described separately.

[0107] The gate insulating layer GI can include silicon compounds or metal oxides. For example, the gate insulating layer GI can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used alone or in combination with each other.

[0108] The second conductive layer 140 is disposed on the gate insulating layer GI. The second conductive layer 140 may include the gate electrode 141 of the first transistor TR1, the gate electrode 142 of the second transistor TR2, the second electrode 143 (or the upper electrode) of the storage capacitor Cst, and the scan line ( Figure 3 (SL in this context, referred to as "144" below).

[0109] Although not limited thereto, the gate electrode 141 of the first transistor TR1 may protrude from one side of the second electrode 143 of the storage capacitor Cst in the second direction DR2 (see...). Figure 4 The gate electrode 141 of the first transistor TR1 can branch off from the second electrode 143 of the storage capacitor Cst in the second direction DR2, and can be configured to overlap with the channel region 131c of the semiconductor pattern 131 of the first transistor TR1. The gate electrode 142 of the second transistor TR2 can protrude from one side of the scan line 144. The gate electrode 142 of the second transistor TR2 can branch off from the scan line 144 in the second direction DR2, and can be configured to overlap with the channel region (not shown) of the semiconductor pattern 132 of the second transistor TR2.

[0110] The second electrode 143 of the storage capacitor Cst can be disposed at the center of the circuit region CA, can be positioned in the plan view between the first lower light-blocking pattern 111 and the second lower light-blocking pattern 115, and can be partially extended to connect to the gate electrode 141 of the first transistor TR1.

[0111] The second electrode 143 of the storage capacitor Cst may be disposed on the first electrode 113 of the storage capacitor Cst, overlapping at least a portion of the first electrode 113 of the storage capacitor Cst. The shape of the second electrode 143 of the storage capacitor Cst may be substantially similar to the shape of the first electrode 113 of the storage capacitor Cst. In a plan view, the second electrode 143 of the storage capacitor Cst may have an area smaller than that of the first electrode 113 of the storage capacitor Cst, thereby exposing a portion of the first electrode 113 of the storage capacitor Cst.

[0112] The second electrode 143 of the storage capacitor Cst can be configured to overlap with the first electrode 113 of the storage capacitor Cst, and a buffer layer 120 is located between the second electrode 143 and the first electrode 113, thereby forming the storage capacitor Cst. The buffer layer 120 located between the first electrode 113 and the second electrode 143 of the storage capacitor Cst can be the dielectric of the storage capacitor Cst.

[0113] However, not limited to this, the second electrode 143 of the storage capacitor Cst and the gate electrode 141 of the first transistor TR1 can be integrally patterned to serve as the second conductive layer 140.

[0114] In the plan view, scan line 144 can be positioned below a pixel PX (or below the circuit region CA). Scan line 144 can extend in the first direction DR1. Scan line 144 can extend to another pixel PX, which is positioned adjacent to a pixel PX in the first direction DR1. Scan line 144 can be positioned on a different layer than the first power line 112 and data line 114, and can be positioned above the first power line 112 and data line 114. Scan line 144 can extend in the first direction DR1 and can intersect with the first power line 112 and data line 114 extending in the second direction DR2.

[0115] The second conductive layer 140 may be made of a low-resistance material. The second conductive layer 140 may include, but is not limited to, at least one metal selected from the group consisting of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0116] A passivation layer PVX is disposed on the second conductive layer 140. The passivation layer PVX can cover and protect the second conductive layer 140. The passivation layer PVX can cover the top surface and / or side surface of the gate insulating layer GI and the top surface and side surface of the second conductive layer 140.

[0117] The passivation layer PVX may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. Although not shown, the passivation layer PVX may be disposed in the display area DA, but may not be disposed in at least a portion of the non-display area NDA.

[0118] A via layer (VIA, i.e., planarization layer) is disposed on the passivation layer PVX. The via layer VIA can be disposed on the passivation layer PVX to completely cover the top surface of the passivation layer PVX. When the via layer VIA is made of an organic layer, the upper surface of the via layer VIA can be flat regardless of the step on the lower surface.

[0119] The via layer VIA may comprise an inorganic insulating material or an organic insulating material selected from the group consisting of acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, and benzocyclobutene (“BCB”). The via layer VIA may further comprise a photosensitive material, but the present disclosure according to the invention is not limited thereto.

[0120] The third conductive layer 150 is disposed on the via layer VIA. The third conductive layer 150 may include a first conductive pattern 151, a second conductive pattern 152, a third conductive pattern 153, and a fourth conductive pattern 154. The conductive patterns 151, 152, 153, and 154 may be physically spaced apart from each other, but may be electrically connected to each other.

[0121] The first conductive pattern 151 may include a light-emitting element ( Figure 3 The anode electrode of the OLED (as defined in the image). The first conductive pattern 151 can be set individually for each pixel PX. At least a portion of the first conductive pattern 151 can overlap with the first lower light-blocking pattern 111 and with the semiconductor pattern 131 of the first transistor TR1.

[0122] The first conductive pattern 151 can pass through the via layer VIA, the passivation layer PVX, and the buffer layer 120, and can contact the first lower light-blocking pattern 111 through the first contact hole CNT1 that exposes a portion of the first lower light-blocking pattern 111. Furthermore, the first conductive pattern 151 can pass through the via layer VIA and the passivation layer PVX, and can contact the second source / drain region 131b of the first transistor TR1 through the second contact hole CNT2 that exposes a portion of the second source / drain region 131b of the first transistor TR1. Therefore, the first conductive pattern 151 itself can become the second source / drain electrode of the first transistor TR1, or at least a portion of the first conductive pattern 151 can become the second source / drain electrode of the first transistor TR1. Additionally, the second source / drain region 131b of the first transistor TR1 and the first lower light-blocking pattern 111 can be electrically connected to each other through the first conductive pattern 151.

[0123] The second conductive pattern 152 can overlap with the semiconductor pattern 131 of the first power line 112 and the first transistor TR1. The second conductive pattern 152 can pass through the via layer VIA and the passivation layer PVX, and can contact the first source / drain region 131a of the first transistor TR1 through a third contact hole CNT3 that exposes a portion of the first source / drain region 131a of the first transistor TR1. Therefore, the second conductive pattern 152 itself can become the first source / drain electrode of the first transistor TR1, or at least a portion of the second conductive pattern 152 can become the first source / drain electrode of the first transistor TR1. Additionally, the second conductive pattern 152 can pass through the via layer VIA, the passivation layer PVX, and the buffer layer 120, and can contact the first power line 112 through a fourth contact hole CNT4 that exposes a portion of the first power line 112. Therefore, the first source / drain region 131a of the first transistor TR1 and the first power line 112 can be electrically connected to each other through the second conductive pattern 152.

[0124] The third conductive pattern 153 can overlap with the first electrode 113 of the storage capacitor Cst, the second electrode 143 of the storage capacitor Cst, the semiconductor pattern 132 of the second transistor TR2, and the second lower light-blocking pattern 115. The third conductive pattern 153 can contact the second electrode 143 of the storage capacitor Cst through the fifth contact hole CNT5. Furthermore, the third conductive pattern 153 can contact the second source / drain region of the second transistor TR2 through the sixth contact hole CNT6. Therefore, the third conductive pattern 153 itself can become the second source / drain electrode of the second transistor TR2, or at least a portion of the third conductive pattern 153 can become the second source / drain electrode of the second transistor TR2. Additionally, the second electrode 143 of the storage capacitor Cst and the second source / drain region (not shown) of the second transistor TR2 can be electrically connected to each other through the third conductive pattern 153.

[0125] The fourth conductive pattern 154 can overlap with the second lower light-blocking pattern 115 and the semiconductor pattern 132 of the second transistor TR2. The fourth conductive pattern 154 can contact the first source / drain region of the second transistor TR2 through the seventh contact hole CNT7. Therefore, the fourth conductive pattern 154 itself can become the first source / drain electrode of the second transistor TR2, or at least a portion of the fourth conductive pattern 154 can become the first source / drain electrode of the second transistor TR2. Furthermore, the fourth conductive pattern 154 can contact the second lower light-blocking pattern 115 through the eighth contact hole CNT8. Therefore, the first source / drain region of the second transistor TR2 and the second lower light-blocking pattern 115 can be electrically connected to each other through the fourth conductive pattern 154.

[0126] The third conductive layer 150 may have a stacked structure formed by stacking a material layer with a high work function and a reflective material layer. The material layer with a high work function may be such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), and indium oxide (In₂O₃). The reflective material layer may be such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof, but the invention is not limited thereto. The material layer with a high work function may be disposed above the reflective material layer and positioned closer to the light-emitting layer EL. The third conductive layer 150 may have a multilayer structure such as ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but the invention is not limited thereto.

[0127] A pixel defining layer (PDL) may be disposed on the third conductive layer 150. The PDL may define an opening that partially exposes the first conductive pattern 151 of the third conductive layer 150. The PDL may be formed of, or may include, an organic insulating material or an inorganic insulating material. For example, the PDL may include at least one of polyimide resin, acrylic resin, silicone compound, and polyacrylic resin.

[0128] The light-emitting layer EL, the cathode electrode CAT, and the thin-film encapsulation layer 160 may be further disposed on the first conductive pattern 151 exposed by the pixel-defining layer PDL.

[0129] The light-emitting layer (EL) may include an organic material layer. The organic material layer of the light-emitting layer (EL) may include an organic light-emitting layer, and may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0130] The cathode electrode CAT can be disposed on the light-emitting layer EL. The cathode electrode CAT can be a common electrode disposed on all pixels PX, without distinguishing between pixels PX. The first conductive pattern 151 (i.e., the anode electrode), the light-emitting layer EL, and the cathode electrode CAT can constitute an organic light-emitting element OLED.

[0131] The cathode electrode CAT may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode electrode CAT may further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0132] A thin-film encapsulation layer 160 is disposed on the cathode electrode CAT. The thin-film encapsulation layer 160 may include a first inorganic layer 161, a first organic layer 162, and a second inorganic layer 163. Although not shown, the first inorganic layer 161 and the second inorganic layer 163 may be in contact with each other at the ends of the thin-film encapsulation layer 160. The first organic layer 162 may be encapsulated by the first inorganic layer 161 and the second inorganic layer 163.

[0133] Each of the first inorganic layer 161 and the second inorganic layer 163 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. The first organic layer 162 may include an organic insulating material.

[0134] Hereinafter, a method for manufacturing a display device 1 according to an exemplary embodiment will be described.

[0135] Figure 7 This is a flowchart of a method for manufacturing a display device according to an exemplary embodiment. Figures 8 to 19 It shows the manufacturing process. Figure 6 A cross-sectional view of the steps of a method for displaying one pixel of the device.

[0136] First, refer to Figure 7 and Figure 8 A barrier layer 102 is formed on the entire surface of the substrate 101, and a first conductive layer 110 is formed on the barrier layer 102 and the first conductive layer 110 is patterned (step S01).

[0137] Specifically, a first conductive layer material (not shown) can be coated onto the entire surface of the barrier layer 102, and the first conductive layer material (not shown) can be patterned using a photolithography process to form a shape such as... Figure 6 The first conductive layer 110 is shown in the figure. In another exemplary embodiment, when the barrier layer 102 is omitted, the first conductive layer material (not shown) can be directly coated onto the substrate 101.

[0138] Subsequently, referring to Figures 9 to 12 A buffer layer 120 is formed on the entire surface of the barrier layer 102, and the buffer layer 120 covers the first conductive layer 110. A semiconductor layer 130 and a gate insulating layer GI are formed on the buffer layer 120 and the semiconductor layer 130 and the gate insulating layer GI are patterned (step S02).

[0139] Specifically, a patterned semiconductor layer 130 and gate insulating layer GI can be formed using a masking process. Semiconductor layer material 130a is deposited on the entire surface of buffer layer 120, and subsequently, gate insulating layer material GIa is deposited on the entire surface of semiconductor layer material 130a. Then, after coating the gate insulating layer material GIa with a photoresist layer PR, a photoresist pattern is formed by exposure and development. Then, the gate insulating layer material GIa and semiconductor layer material 130a are sequentially etched using the photoresist layer PR as an etch mask. Thus, the gate insulating layer GI, including a first gate insulating layer pattern GI1 and a second gate insulating layer pattern GI2, is patterned. Additionally, the semiconductor layer 130, including a semiconductor pattern 131 of a first transistor TR1, a semiconductor pattern 132 of a second transistor TR2, a first semiconductor dummy pattern SD1, and a second semiconductor dummy pattern SD2, is patterned. Subsequently, the photoresist layer PR is removed by a stripping or ashing process.

[0140] In the process of patterning semiconductor layer 130, a step is taken in the overlapping region ( Figure 5 and Figure 6 The first semiconductor dummy pattern SD1 and the second semiconductor dummy pattern SD2 of the semiconductor layer 130 in “OA” can be formed together with the semiconductor pattern 131 of the first transistor TR1 and the semiconductor pattern 132 of the second transistor TR2. Additionally, in the process of patterning the gate insulating layer GI, a dummy pattern SD2 is provided in the overlapping region (…). Figure 5 and Figure 6 The second gate insulating layer pattern GI2 in the gate insulating layer GI of “OA” can be formed together with the first gate insulating layer pattern GI1. Therefore, it is not necessary to add a pattern for forming the gate insulating layer GI located in the overlapping region ( Figure 5 and Figure 6 The first semiconductor dummy pattern SD1, the second semiconductor dummy pattern SD2, and the second gate insulating layer pattern GI2 are separate masks in “OA”. That is, even if the first semiconductor dummy pattern SD1, the second semiconductor dummy pattern SD2, and the second gate insulating layer pattern GI2 are further formed, no additional process is required.

[0141] Next, refer to Figures 13 to 16 A second conductive layer 140 is formed on the gate insulating layer GI (step S03).

[0142] Specifically, the second conductive layer 140 can be formed using a mask process. The second conductive layer material 140a is deposited on the entire surface of the buffer layer 120 on which the semiconductor layer 130 and the gate insulating layer GI are formed. Subsequently, after coating the second conductive layer material 140a with a photoresist layer PR, a photoresist pattern is formed by exposure and development. Then, the second conductive layer material 140a and the gate insulating layer GI are sequentially etched using the photoresist layer PR as an etching mask. Although the accompanying drawings show that in the process of etching the second conductive layer material 140a, a portion of the gate insulating layer GI is etched such that a portion of the side surface of the second conductive layer 140a is aligned with a portion of the side surface of the gate insulating layer GI, the present disclosure according to the invention is not limited thereto.

[0143] Therefore, it will include the gate electrode 141 of the first transistor TR1 and the gate electrode of the second transistor TR2 (see...). Figure 4 The second conductive layer 140, including the second electrode 143 of the storage capacitor Cst and the scan line 144, is patterned. Furthermore, the gate insulating layer GI, comprising the first gate insulating layer pattern GI1 and the second gate insulating layer pattern GI2, is patterned. Then, the photoresist layer PR is removed by a stripping or ashing process.

[0144] Although not limited to this, the first source / drain region 131a, the second source / drain region 131b, and the channel region 131c of the first transistor TR1 can be formed by the above process. Furthermore, although not shown, the first source / drain region (not shown), the second source / drain region (not shown), and the channel region (not shown) of the second transistor TR2 can be formed by the above process.

[0145] In the above description, as an example, the photoresist layer PR is used as an etch mask until the gate insulating layer GI is patterned. However, the patterned upper layer can be used as a hard mask for etching the lower layer. In this case, the photoresist layer PR can be used together with the hard mask as an etch mask. As another example, after forming the hard mask, the photoresist layer PR can be removed, and the hard mask can be used as an etch mask to etch the lower layer.

[0146] Then, refer to Figure 17 A passivation layer PVX and a via layer VIA are formed on the second conductive layer 140, and a contact hole is formed (see [link]). Figure 4 (CNT1 to CNT8) (step S04). Although only the first contact holes CNT1 to the fourth contact holes CNT4 are shown in the figures, the fifth to eighth contact holes can also be formed in step S04 (see... Figure 4 (CNT5 to CNT8).

[0147] Specifically, a passivation layer PVX is deposited on the buffer layer 120 to cover the second conductive layer 140, the gate insulating layer GI, and the semiconductor layer 130. After depositing the passivation layer PVX, a via layer VIA is formed by coating a material layer for the via layer VIA onto the passivation layer PVX. Subsequently, by etching the via layer VIA, the passivation layer PVX, and / or the buffer layer 120, first contact holes CNT1 to eighth contact holes CNT8 can be formed to expose any one of the first conductive layer 110, the semiconductor layer 130, and the second conductive layer 140, thus penetrating the via layer VIA, the passivation layer PVX, and / or the buffer layer 120.

[0148] Then, refer to Figure 18 A third conductive layer 150 is formed on the via layer VIA (step S05). Although only the first conductive pattern 151 and the second conductive pattern 152 are shown in the figures, a third conductive pattern can also be formed in step S05 (see [reference]). Figure 4 (153 in the text) and the fourth conductive pattern (see Figure 4 (154 in the text).

[0149] Specifically, the third conductive layer 150 can be formed using a masking process. A material layer (not shown) for the third conductive layer 150 is completely deposited on the via layer VIA. In the deposition process, the material layer (not shown) for the third conductive layer 150 can be deposited inside the first contact holes CNT1 to the eighth contact holes CNT8. Therefore, the third conductive layer 150 can be connected to at least one of the first conductive layer 110, the semiconductor layer 130, and the second conductive layer 140. Subsequently, a photoresist layer is coated on the material layer (not shown) for the third conductive layer 150, a photoresist pattern is formed by exposure and development, and then the material layer for the third conductive layer 150 is etched using the photoresist layer as an etching mask. Thereafter, as... Figure 4 and Figure 18 As shown, the photoresist layer is removed by a stripping or ashing process to complete the patterned third conductive layer 150.

[0150] Then, refer to Figure 19 A patterned pixel definition layer (PDL) is formed on the via layer (VIA) to cover the third conductive layer 150 (step S06).

[0151] Specifically, the pixel-defining layer (PDL) may include, for example, an organic material having a photosensitive component. In this case, a patterned pixel-defining layer (PDL) can be formed by coating an organic material layer onto the PDL and then exposing and developing it.

[0152] The pixel defining layer PDL can be formed along the boundary of pixel PX and can partially overlap with the third conductive layer 150. The pixel defining layer PDL can be formed to overlap with the first contact holes CNT1 to the eighth contact holes CNT8. When the third conductive layer 150 fails to completely fill the internal space of the first contact holes CNT1 to the eighth contact holes CNT8 and only partially fills the internal space of the first contact holes CNT1 to the eighth contact holes CNT8, the pixel defining layer PDL can completely fill the internal space of the first contact holes CNT1 to the eighth contact holes CNT8.

[0153] The light-emitting layer EL, the cathode electrode CAT, and the thin film encapsulation layer 160 may be further disposed on the pixel defining layer PDL, but the method of manufacturing the light-emitting layer EL, the cathode electrode CAT, and the thin film encapsulation layer 160 is a well-known technology, and therefore its detailed description is omitted.

[0154] Other embodiments will be described below. In the following embodiments, descriptions of components identical to those in the above embodiments will be omitted or simplified to avoid repetition, and the differences will be mainly described.

[0155] Figure 20 This is an enlarged view of the outer region of the first semiconductor dummy pattern according to another embodiment. Figure 21 It is along Figure 20 The cross-sectional view taken from line XXI-XXI'.

[0156] Reference Figure 20 and Figure 21 This embodiment and Figure 5 The difference in the embodiment is that the first semiconductor dummy pattern SD1_1 is set in the overlapping region OA.

[0157] Specifically, according to this embodiment, the entire area of ​​the first semiconductor dummy pattern SD1_1 can be disposed in the overlapping area OA to cover the entire area of ​​the overlapping area OA. The first semiconductor dummy pattern SD1_1 can completely overlap with the overlapping area OA. In other words, the entire area of ​​the first semiconductor dummy pattern SD1_1 can overlap with the overlapping area OA in the thickness direction (third direction DR3), and the entire area of ​​the overlapping area OA can overlap with the first semiconductor dummy pattern SD1_1 in the thickness direction (third direction DR3). The length of the first semiconductor dummy pattern SD1_1 in the first direction DR1 can be the same as the width of the first power line 112 in the first direction DR1, and the length of the first semiconductor dummy pattern SD1_1 in the second direction DR2 can be the same as the width of the scan line 144 in the second direction DR2. Therefore, a portion of the side surface of the first semiconductor dummy pattern SD1_1 can be aligned with a portion of the side surface of the first power line 112, and another portion of the side surface of the first semiconductor dummy pattern SD1_1 can be aligned with a portion of the side surface of the scan line 144.

[0158] Furthermore, in this case, since the first semiconductor dummy pattern SD1_1 is set in the overlapping region OA, the distance between the first power line 112 and the scan line 144 in the thickness direction (third direction DR3) can be increased, and the capacitance of parasitic capacitors that may appear in the above region can be reduced.

[0159] Figure 22 This is an enlarged view of the outer region of the first semiconductor dummy pattern according to yet another embodiment. Figure 23 It is along Figure 22 The cross-sectional view taken from line XXIII-XXIII'.

[0160] Reference Figure 22 and Figure 23 This embodiment and Figure 5 The difference in the embodiment is that the first semiconductor dummy pattern SD1_2 covers a portion of the overlapping region OA.

[0161] Specifically, according to this embodiment, the first semiconductor dummy pattern SD1_2 can be disposed in the overlapping region OA to cover only a portion of the overlapping region OA. The first semiconductor dummy pattern SD1_2 can overlap with a portion of the overlapping region OA in the thickness direction (third direction DR3), rather than overlapping the entire overlapping region OA. Although the figures show that the length of the first semiconductor dummy pattern SD1_2 in the second direction DR2 is less than the width of the scan line 144 in the second direction DR2, the present disclosure according to the present invention is not limited thereto, and in another exemplary embodiment, the length of the first semiconductor dummy pattern SD1_2 in the first direction DR1 can be less than the width of the first power line 112 in the first direction DR1.

[0162] Therefore, the scan line 144 can be disposed on the side surface of the first semiconductor dummy pattern SD1_2 and / or the side surface of the second gate insulating layer pattern GI2 while being in direct contact with the side surface of the first semiconductor dummy pattern SD1_2 and / or the side surface of the second gate insulating layer pattern GI2.

[0163] In this case, since the first semiconductor dummy pattern SD1_2 is set in the overlapping region OA, the distance between the first power line 112 and the scan line 144 in the thickness direction (third direction DR3) can be increased in the region in which the first semiconductor dummy pattern SD1_2 is set, and the capacitance of the parasitic capacitor that may appear in the overlapping region OA can be reduced.

[0164] Although preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the invention as disclosed in the appended claims.

Claims

1. A display device, wherein, The display device includes: a substrate; a first conductive layer provided over the substrate and including a lower light-blocking pattern and a first signal line; a buffer layer provided over the first conductive layer; a semiconductor layer provided over the buffer layer and including a first semiconductor pattern including a channel region of a transistor and a second semiconductor pattern separated from the first semiconductor pattern; an insulating layer provided over the semiconductor layer and including an insulating layer pattern; a second conductive layer provided over the insulating layer and including a second signal line; a planarization layer provided over the second conductive layer; and a third conductive layer provided over the planarization layer and including an anode electrode, wherein the first semiconductor pattern is electrically connected to the lower light-blocking pattern through the anode electrode, and wherein at least a portion of the second semiconductor pattern is insulated from and overlaps each of the first signal line and the second signal line in a thickness direction.

2. The display device according to claim 1, wherein The display device further includes: a storage capacitor including a first electrode and a second electrode, wherein the first conductive layer includes the first electrode of the storage capacitor, wherein the second conductive layer includes the second electrode of the storage capacitor, and wherein a distance between the first signal line and the second signal line in the thickness direction is greater than a distance between the first electrode and the second electrode of the storage capacitor in the thickness direction.

3. The display device according to claim 1, wherein The anode electrode is connected to the lower light-blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and is connected to the first semiconductor pattern of the transistor through a second contact hole passing through the planarization layer.

4. The display device according to claim 1, wherein The third conductive layer further includes a sub-conductive pattern separated from the anode electrode, and the sub-conductive pattern electrically connects the first signal line to the first semiconductor pattern of the transistor.

5. The display device of claim 4, wherein, The sub-conductive pattern contacts the first signal line through a third contact hole passing through the planarization layer and the buffer layer, and contacts the first semiconductor pattern of the transistor through a fourth contact hole passing through the planarization layer.

6. The display device according to claim 1, wherein The first signal line is one of a first power supply line and a data line, and the second signal line is a scan line.

7. The display device of claim 6, wherein, The second signal line extends in a first direction, the first signal line extends in a second direction intersecting the first direction, and the first signal line and the second signal line intersect each other in an overlapping region.

8. The display device of claim 7, wherein, A length of the second semiconductor pattern in the first direction is equal to or greater than a width of the first signal line in the first direction, and wherein a length of the second semiconductor pattern in the second direction is equal to or greater than a width of the second signal line in the second direction.

9. The display device according to claim 1, wherein The overlapping region in which the first signal line and the second signal line overlap each other completely overlaps the second semiconductor pattern in the thickness direction.

10. The display device of claim 9, wherein, At least a part of the insulating layer is provided in the overlapping region and overlaps the second semiconductor pattern in the thickness direction.

11. A display device comprising a storage capacitor and at least one transistor comprising a first semiconductor pattern, wherein, The display device includes: a substrate; a first conductive layer provided over the substrate and including a first electrode of the storage capacitor and a first signal line; a buffer layer provided over the first conductive layer; a semiconductor layer provided over the buffer layer and including the first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern; an insulating layer provided over the semiconductor layer; and a second conductive layer provided over the insulating layer and including a gate electrode of the transistor, a second electrode of the storage capacitor, and a second signal line, wherein the first signal line and the second signal line overlap each other in at least a part of a region in a thickness direction, wherein at least a part of the second semiconductor pattern is provided in an overlapping region where the first signal line and the second signal line overlap each other, and wherein in the overlapping region, a distance between the first signal line and the second signal line in the thickness direction is greater than a distance between the first electrode and the second electrode of the storage capacitor in the thickness direction.

12. The display device of claim 11, wherein, The second semiconductor pattern is a dummy semiconductor pattern insulated from the first signal line and the second signal line.

13. The display device of claim 12, wherein, At least a part of the insulating layer is provided in the overlapping region and overlaps the second semiconductor pattern in the thickness direction.

14. The display device of claim 13, wherein, The second semiconductor pattern and the insulating layer are not provided between the first electrode and the second electrode of the storage capacitor in the thickness direction.

15. The display device of claim 11, wherein, The first signal line is one of a first power line and a data line, and the second signal line is a scan line.

16. The display device of claim 15, wherein, The second signal line extends in a first direction, the first signal line extends in a second direction intersecting the first direction, and the first signal line and the second signal line intersect each other in an overlapping region.

17. A method for manufacturing a display device, wherein, The method includes: forming a first conductive layer including a first signal line and a first electrode of a storage capacitor over a substrate; forming a buffer layer over the substrate to cover the first conductive layer; depositing a semiconductor layer material and an insulating layer material over the entire buffer layer; etching the semiconductor layer material and the insulating layer material to form an insulating layer and a semiconductor layer including a first semiconductor pattern of a transistor and a second semiconductor pattern separated from the first semiconductor pattern, respectively; and forming a second conductive layer including a gate electrode of the transistor, a second electrode of the storage capacitor, and a second signal line over the insulating layer, wherein the first signal line and the second signal line overlap each other in at least a part of a region in a thickness direction, wherein at least a part of the second semiconductor pattern is provided in an overlapping region where the first signal line and the second signal line overlap each other in the thickness direction, and wherein in the overlapping region, a distance between the first signal line and the second signal line in the thickness direction is greater than a distance between the first electrode and the second electrode of the storage capacitor in the thickness direction. In the overlapping region, a distance between the first signal line and the second signal line in the thickness direction is greater than a distance between the first electrode and the second electrode of the storage capacitor in the thickness direction.

18. The method of claim 17, wherein, The second semiconductor pattern is a dummy semiconductor pattern that is insulated from the first signal line, the second signal line, the first electrode and the second electrode of the storage capacitor, and the gate electrode of the transistor.

19. The method of claim 18, wherein, At least a portion of the insulating layer is provided in the overlapping region and overlaps the second semiconductor pattern in the thickness direction, and The second semiconductor pattern and the insulating layer are not provided between the first electrode and the second electrode of the storage capacitor in the thickness direction.

20. The method of claim 19, wherein, The first signal line is one of a first power supply line and a data line, and the second signal line is a scan line, and In which the second signal line extends in a first direction, the first signal line extends in a second direction intersecting the first direction, and the first signal line and the second signal line intersect each other in the overlapping region.

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