Isolation of integrated waveguide detectors using back-end processing

Abstract

An optical device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, a photosensitive component (e.g., a photodetector) within the dielectric layer and coupled to the waveguide, and a plurality of optical isolation structures within at least one of the substrate or the dielectric layer and configured to prevent stray light from reaching the photosensitive component. In some embodiments, an optical isolation structure of the plurality of optical isolation structures includes two opposing sidewalls and a filler material between the two opposing sidewalls. The two opposing sidewalls include the optical isolation layer. The filler material is characterized by a thermal expansion coefficient that matches the thermal expansion coefficient of at least one of the substrate or the dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 751,447, filed on October 26, 2018, entitled “Isolation of Waveguide-Integrated Detectors Using a Back End of Line Process,” and U.S. Provisional Patent Application No. 62 / 887,364, filed on August 15, 2019, entitled “Coefficient of Thermal Expansion-Matched Trench Fill For Scatter Mitigation in Linear Optical Quantum Computer,” the disclosures of which are incorporated herein by reference in their entirety for all purposes. Background Art

[0003] Optoelectronic devices with high sensitivity (such as single-photon detectors) can be used in many photonic quantum technologies, such as quantum encryption and quantum computing. Due to the high sensitivity of photodetectors, they are very sensitive to noise (such as unwanted ambient light or stray light that can reach the photodetector through direct or indirect paths). Summary of the Invention

[0004] The present disclosure generally relates to photodetectors. More specifically, the present disclosure relates to techniques for preventing background light from reaching highly sensitive photodetectors (e.g., superconducting nanowire single photon detectors) in photonic integrated circuits (PICs) to achieve high sensitivity and high signal-to-noise ratio (SNR). According to certain embodiments, the photonic integrated circuit may include an optical isolation structure manufactured using a CMOS back-end-of-line (BEOL) process to prevent ambient light or stray light from reaching the photodetector directly or indirectly. The optical isolation structure may include, for example, a metal layer, an array of vias, an air gap, a trench filled with a reflective or absorptive material, and the like. The optical isolation structure may provide local and / or global isolation to the photodetector and / or waveguide at different locations (e.g., the input and output ports of the photonic integrated circuit and the photodetector) such that any scattered, reflected, diffused, or otherwise leaked light from the light source or the photonic integrated circuit is partially or completely blocked, thereby preventing it from reaching the photodetector.

[0005] According to some embodiments, a device may include: a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, a photosensitive component in the dielectric layer and coupled to the waveguide, and a plurality of optical isolation structures in at least one of the substrate or the dielectric layer and adjacent to the photosensitive component. The plurality of optical isolation structures may be configured to reflect or absorb stray light to prevent stray light from reaching the photosensitive component. In various embodiments, the plurality of optical isolation structures may include, for example: a metal trench in the dielectric layer, an array of metal vias in the dielectric layer, a metal cover in the dielectric layer and on top of the photosensitive component, a deep trench in the substrate that includes an air gap or is filled with a light-reflective material, a light-absorbing material, or any combination thereof. In some embodiments, the metal cover may be in the metal layer and may be aligned with or coupled to the metal trench or metal via array to form a continuous structure surrounding the photosensitive component. In some embodiments, the waveguide may include an input port, wherein the metal trench or metal via array may be located at the region including the input port. The photosensitive component may include a single-photon detector, such as a superconducting nanowire single-photon detector. The dielectric layer may, for example, include an oxide layer.

[0006] In some embodiments, the optical isolation structure in the plurality of optical isolation structures may include two opposing sidewalls (each sidewall including an optical isolation layer), and a filling material between the two opposing sidewalls, and the filling material is characterized by a coefficient of thermal expansion (CTE) that matches the CTE of at least one of the substrate or the dielectric layer. The filling material may be, for example, polysilicon or silicon dioxide. In some embodiments, the optical isolation layer may be characterized by a thickness greater than a value that makes the combined two opposing sidewalls optically opaque. In some embodiments, the thickness may be less than 60 nm. In some embodiments, the optical isolation layer may include a metal nitride, such as TiN, TaN, ZrN, or WN.

[0007] In some embodiments, the plurality of optical isolation structures may include: a first optical isolation structure in a substrate and a second optical isolation structure in a dielectric layer. The CTE of the filler material in the first optical isolation structure may match the CTE of the substrate, and the CTE of the filler material in the second optical isolation structure may match the CTE of the dielectric layer. The first optical isolation structure may be aligned with or offset from the second optical isolation structure.

[0008] In some embodiments, each of the two opposing sidewalls may further include a first adhesive layer between the optical isolation layer and at least one of the dielectric layer or the substrate. The first adhesive layer may be characterized by a thickness of less than 20 nm. The first adhesive layer may include, for example, a titanium layer. In some embodiments, each of the two opposing sidewalls may further include a second adhesive layer between the optical isolation layer and the filler material. The second adhesive layer may be characterized by a thickness of less than 20 nm and may, for example, include a titanium layer. In some embodiments, the device may further include an unfilled trench in the substrate or dielectric layer, wherein the sidewalls of the unfilled trench may be optically opaque.

[0009] According to some embodiments, a method may include receiving a photonic integrated circuit, the photonic integrated circuit including a substrate, a dielectric layer on the substrate, a waveguide, and a photosensitive component coupled to the waveguide, wherein the waveguide and the photosensitive component are located in the dielectric layer. The method may also include etching a via or a trench in the dielectric layer surrounding the photosensitive component to expose a portion of the substrate, filling the via or the trench with a light-reflective or light-absorbing material, forming a top metal cap on the dielectric layer and on top of the photosensitive component, and etching the substrate from a backside of the substrate opposite the dielectric layer to form a deep trench in the substrate.

[0010] In some embodiments, the method may further include filling the deep trench with a light reflective or light absorbing material. In some embodiments, the method may further include depositing a thin adhesive layer on the exposed surface of the deep trench, depositing a thin optical isolation layer on the thin adhesive layer, and depositing a filling material layer on the thin optical isolation layer, wherein the filling material layer can fill the deep trench and can be characterized by a coefficient of thermal expansion (CTE) that matches the CTE of the substrate. In some embodiments, the top metal cover is in the metal 1 layer. In some embodiments, the method may further include forming additional dielectric layers and metal layers on the dielectric layer. In some embodiments, the method may further include etching additional vias or trenches in the dielectric layer at an area including the input port of the waveguide, filling the additional vias or trenches with a light reflective or light absorbing material, and etching the substrate from the back side of the substrate opposite the dielectric layer to form additional deep trenches in the substrate at an area including the input port of the waveguide.

[0011] According to some embodiments, a method may include: receiving a photonic integrated circuit, the photonic integrated circuit including a substrate and a dielectric layer on the substrate, wherein the dielectric layer may include a photosensitive component. The method may also include: etching a trench adjacent to the photosensitive component and in at least one of the dielectric layer or the substrate, depositing a thin adhesive layer on an exposed surface of the trench, depositing a thin optical isolation layer on the thin adhesive layer, and depositing a first filler material layer on the thin optical isolation layer. The first filler material layer may fill the trench and may have a coefficient of thermal expansion (CTE) that matches a CTE of at least one of the substrate or the dielectric layer. In some embodiments, the method may also include: depositing a second adhesive layer on the thin optical isolation layer before depositing the first filler material layer. In some embodiments, the method may also include planarizing the first filler material layer.

[0012] In some embodiments, the trench may be in both the substrate and the dielectric layer, and the CTE of the first filler material layer may match the CTE of the substrate. The method may further include etching a portion of the first filler material layer that fills the trench so that the top surface of the first filler material layer in the trench is aligned with the interface between the substrate and the dielectric layer, depositing a second filler material layer in the trench, and planarizing the second filler material layer. The second filler material layer may be characterized by a CTE that matches the CTE of the dielectric layer. In some embodiments, etching the portion of the first filler material layer may include etching the first filler material layer, a thin adhesive layer, and a thin optical isolation layer using a dry etching process, and the method may further include depositing a second adhesive layer on the exposed surface of the trench before depositing the second filler material layer, and depositing a second optical isolation layer on the second adhesive layer.

[0013] The systems, devices and methods disclosed herein can improve the signal-to-noise ratio of a photodetector by preventing unwanted light from reaching a highly sensitive photodetector. As a result, the photodetector can achieve high sensitivity and can have a minimal amount of dead time. The optical isolation structure can be manufactured using a standard CMOS middle-of-line (MOL) process or a back-end-of-line (BEOL) process or a CMOS-compatible BEOL process. Some isolations can be local and do not require additional global layers or materials in the stack, thereby not applying additional thermal loads to the circuits and devices. In addition, the optical isolation structure can include a thin optical isolation layer and a material having a coefficient of thermal expansion (CTE) that matches the CTE of the material forming the optical isolation structure. Therefore, the overall CTE of the optical isolation structure can match the CTE of other parts of the photonic integrated circuit, thereby reducing or minimizing internal stresses caused by thermal expansion mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various aspects of the present disclosure are illustrated by way of example.Non-limiting and non-exhaustive aspects are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified.

[0015] Figure 1 is a simplified block diagram illustrating an example of an optical device including a photonic integrated circuit (PIC) and a high-sensitivity photodetector in accordance with certain embodiments.

[0016] Figure 2 Examples of stray light isolation at input ports and / or output ports of a photonic integrated circuit, according to certain embodiments, are illustrated.

[0017] Figure 3 Examples of locally isolating photodetectors using various oxide layer isolation structures according to certain embodiments are illustrated.

[0018] Figures 4A to 4D Another example of utilizing various isolation structures to locally isolate photodetectors in an optical device according to certain embodiments is illustrated. Figure 4A is a cross-sectional view of an optical device including a photodetector and an optical isolation structure. Figure 4B yes Figure 4A A stereogram of the optical device in FIG. Figure 4C yes Figure 4A Top view of the optical device in . Figure 4D yes Figure 4A A top view of a cross section of the optical device.

[0019] Figure 5 is a flow chart illustrating an exemplary method for fabricating various optical isolation structures in a photonic integrated circuit, according to certain embodiments.

[0020] Figure 6 is a cross-sectional view of an example of a photonic integrated circuit including a photodetector and manufactured using a front-end process according to some embodiments.

[0021] Figure 7 is a cross-sectional view of an example of a photonic integrated circuit having vias or trenches etched in an oxide layer using a back-end process, according to some embodiments.

[0022] Figure 8 is a cross-sectional view of an example of a photonic integrated circuit having vias or trenches etched in an oxide layer and filled with a reflective or absorptive material (eg, metal), in accordance with certain embodiments.

[0023] Figure 9is a cross-sectional view of an example of a photonic integrated circuit having a metal cover fabricated on a metal layer for locally isolating photodetectors, in accordance with certain embodiments.

[0024] Figure 10 is a cross-sectional view of an example of a photonic integrated circuit after additional back-end processing, according to some embodiments.

[0025] Figure 11 is a cross-sectional view of an example of a photonic integrated circuit including deep trenches etched in a substrate of the photonic integrated circuit, according to some embodiments.

[0026] Figure 12 is a cross-sectional view of an example of a photonic integrated circuit including a deep trench filled with a reflective or absorptive material in a substrate of the photonic integrated circuit, according to some embodiments.

[0027] Figure 13 is a cross-sectional view of an example of a photonic integrated circuit illustrating optical isolation formed by various isolation structures in the photonic integrated circuit, according to some embodiments.

[0028] Figure 14A The coefficient of thermal expansion (CTE) mismatch between silicon and copper is illustrated.

[0029] Figure 14B The thermal expansion coefficient of silicon oxide is exemplified.

[0030] Figure 15A is a cross-sectional view of an example of a photonic integrated circuit including trenches filled with a reflective or absorptive optical isolation material, according to some embodiments.

[0031] Figure 15B is a cross-sectional view of an example of a photonic integrated circuit including a trench filled with a thin layer of optical isolation material and a CTE matching material, according to some embodiments.

[0032] Figure 15C is a cross-sectional view of an example of a photonic integrated circuit including a trench filled with a thin layer of optical isolation material and a CTE matching material, according to some embodiments.

[0033] Figures 16A to 16G An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated.

[0034] 17A to 17H An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated.

[0035] Figures 18A to 18G An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated.

[0036] Figures 19A to 19H An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated.

[0037] Figure 20 is a cross-sectional view of an example of a photonic integrated circuit including a deep trench in a substrate filled with a thin optical isolation layer and a substrate matching material, in accordance with certain embodiments.

[0038] Figure 21 is a flow chart illustrating an exemplary method of fabricating an optical isolation structure in a photonic integrated circuit, according to certain embodiments. DETAILED DESCRIPTION

[0039] The technology disclosed herein generally relates to highly sensitive photodetectors. More specifically, the technology disclosed herein relates to techniques for preventing unwanted background light (e.g., stray light or ambient light) from reaching highly sensitive photodetectors (e.g., superconducting nanowire single-photon detectors) in photonic integrated circuits (PICs) to achieve high sensitivity and high signal-to-noise ratio (SNR). Various innovative embodiments, including methods, processes, systems, and devices, are described herein.

[0040] Photodetectors with high light sensitivity used in many photonic quantum technologies, such as single-photon detectors (SPDs)—for example, superconducting nanowire SPDs (SNSPDs)—can be very sensitive to a variety of optical radiation. In many cases, these highly sensitive photodetectors will not achieve their potential sensitivity or SNR due to various noise sources (e.g., background light including stray light in the system or ambient light entering the system).

[0041] According to certain embodiments, to improve the sensitivity and SNR of a photodetector, an optical isolation structure surrounding the photodetector can be used to optically isolate the photodetector (e.g., an SNSPD) from background radiation (e.g., ambient light or stray light). The optical isolation structure can include a light-reflective or light-absorbing material, such that the optical isolation structure can be optically opaque. In some embodiments, additional isolation structures can be added at any other locations in the PIC where background light might otherwise propagate and reach the photodetector to reduce the number of stray photons that might reach the photodetector region. For example, because a major source of background or stray light in a photonic integrated circuit is light that is reflected, scattered, or diffused at the optical input and / or output ports of the PIC (e.g., input or output waveguide couplers) due to incomplete coupling of light into or out of the PIC, isolation structures can be used at the optical input and / or output ports to prevent stray light from entering the interior of the PIC. In this way, the probability that any stray or ambient light can enter the waveguide or reach the photodetector region can be significantly reduced. Furthermore, if any background light can reach the area where the photodetectors are located, the local optical isolation structure surrounding the photodetectors can block the background light to prevent the background light from being detected by the photodetectors. In various embodiments, the optical isolation structure can be fabricated using a standard CMOS back-end-of-line (BEOL) process or other CMOS-compatible manufacturing process.

[0042] According to certain embodiments, when the processing temperature of the PIC (e.g., greater than approximately 700K) cools to the operating temperature (e.g., less than approximately 4K), to reduce stress or damage caused by the mismatch in thermal expansion coefficients between the light-reflective or light-absorbing material in the light-isolating structure and the rest of the light-isolating structure, one or more thin opaque layers and an adhesive layer may be deposited on the inner surface of the trench in the PIC for light isolation. The trench may then be filled with a transparent or non-transparent material whose CTE substantially matches the CTE of the material forming the trench. Consequently, the light-isolating structure can expand or contract at approximately the same rate as the rest of the PIC, reducing internal stress and potential damage or defects in the PIC.

[0043] Some illustrative embodiments will now be described with reference to the accompanying drawings, which form a part of this document. The subsequent description provides only one or more embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the subsequent description of one or more embodiments will provide those skilled in the art with a description of possibilities for implementing one or more embodiments. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the spirit and scope of the present disclosure. In the following description, specific details are provided for the purpose of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it is apparent that various embodiments may be practiced without these specific details. These drawings and descriptions are not intended to be limiting. The words "example" or "exemplary" as used herein are used to mean "serving as an example, instance or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be construed as being more preferred or more advantageous than other embodiments or designs.

[0044] Figure 11 is a simplified block diagram illustrating an example of an optical device 100 including a photonic integrated circuit (PIC) 120 and a high-sensitivity photodetector 130, according to certain embodiments. PIC 120 may include a photonic circuit formed from waveguides and other active or passive optical components (e.g., filters, resonators, splitters, optical amplifiers, etc.). The optical device may include a light source, such as a laser 110, which may be an ultrafast (e.g., picosecond or femtosecond) pulsed laser. In some embodiments, the light source may be an external source and may be connected to PIC 120 via, for example, one or more optical fibers. Light from the light source may be coupled into the waveguides in PIC 120 via a coupler (e.g., a grating coupler, an edge coupler, etc.). However, achieving very high coupling efficiency may be difficult. For example, in many cases, the coupling efficiency may be less than 90%, less than 75%, less than 60%, or less than 50%. Consequently, a significant amount of light from the light source may not enter the waveguides in PIC 120, but may be reflected, scattered, or diffused, and become stray light 140. Stray light 140 will be reflected, refracted, diffracted, or otherwise deflected by structures or components in optical device 100 (e.g., metal layers, interfaces between different materials, etc.). As a result, a portion of stray light 140 will ultimately reach photodetector 130. Furthermore, some portions of PIC 120 will also leak light away from the intended path. For example, when a waveguide has sharp turns or there are defects in the waveguide or other photonic circuits, light will couple out of the waveguide rather than being guided within the photonic circuit to reach photodetector 130. Light that leaks from the photonic circuit will become stray light 150, which will also be at least partially deflected toward photodetector 130. In some embodiments, ambient light may also enter PIC 120, for example, through oxide layers and / or be reflected by metal layers.

[0045] The photodetector 130 can be a highly sensitive photodetector, such as a single photon detector. For example, in some embodiments, the photodetector 130 can include a superconducting nanowire single photon detector that can detect a single photon. In one embodiment, the photodetector 130 can include a waveguide coupled to a superconducting nanowire (e.g., a niobium germanium nanowire), which can have an ultra-low resistance in a superconducting state. The superconducting nanowire can be photosensitive or photoactive, for example, absorptive to photons. For example, a photon passing through the waveguide can be absorbed by the superconducting nanowire and cause the superconducting nanowire to become non-superconducting (i.e., change resistance or impedance). The resistance or impedance change in the nanowire can be converted into an electrical detection signal (e.g., a current or voltage signal) indicating that one or more photons have been detected.

[0046] When at least a portion of the stray light 140 and 150 reaches the photodetector 130, this will cause the superconducting nanowire to change state, and the photodetector 130 will generate a detection signal indicating that one or more photons have been detected, even if no photons have reached the superconducting nanowire from the waveguide, or the magnitude of the detection signal may incorrectly indicate the number of photons reaching the photodetector from the waveguide. As a result, an erroneous detection signal or an incorrect (e.g., noisy) detection signal may be generated by the photodetector 130, which will reduce the effective sensitivity or signal-to-noise ratio of the photodetector 130.

[0047] According to certain embodiments, optical isolation structures may be added at various locations within optical device 100 to prevent stray or ambient light from reaching photodetector 130. For example, isolation structure 160 may be added at the input port of PIC 120; isolation structure 170 may be fabricated to surround photodetector 130; and isolation structure 180 may be added anywhere within optical device 100 that would otherwise propagate ambient light. Further details of some embodiments of optical isolation structures and their fabrication processes are described in the following examples.

[0048] Figure 2 An example of stray light isolation at input and / or output ports of a photonic integrated circuit 200 is shown, in accordance with certain embodiments. Figure 2 A cross-sectional view of a PIC 200 is shown, which may include a waveguide 210 fabricated on a substrate 205 (e.g., a silicon handle wafer). The PIC 200 may also include an input port 220 for the waveguide 210 and an output port 230 for the waveguide 210. The waveguide 210 may guide light from the input port 220 into the interior of the PIC 200 or may guide light out of the PIC 200 through the output port 230, where some light-sensitive components may be located.

[0049] As described above, light may not be fully coupled into or out of waveguide 210 at input port 220 or output port 230. A significant portion of the input light or output light will enter PIC 200 through paths other than waveguide 210. In some cases, approximately 1012 photons will enter PIC 200 as stray light in each laser pulse. To prevent these photons from reaching the interior of PIC 200, one or more optical isolation structures may be fabricated at the input port and / or output port. For example, Figure 2 As shown, PIC 200 may include a Figure 12. The isolation structure 160 shown in FIG. 1 includes one or more metal trenches 240 and one or more deep trenches 260. The metal trenches 240 may include a metal layer that is sufficiently thick to block (e.g., reflect or absorb) incident photons. The metal trenches 240 may function as a mirror-like barrier and may extend from, for example, a metal 1 layer (M1, which may be located approximately 1 m above the waveguide 210) down to the substrate 205 (which may be located approximately 2 to 3 m below the waveguide 210) to block light that would propagate in the cladding of the waveguide 210 from reaching the interior of the PIC 200. The deep trenches 260 may extend through the substrate 205 of the PIC 200 and may be empty (i.e., an air gap) or may be filled with a reflective or absorptive material to at least partially reflect or absorb incident photons that would propagate in or scatter from the substrate 205 so that the photons do not enter the cladding of the waveguide.

[0050] There may be gaps 250 between adjacent metal trenches 240, so that the waveguide 210 can pass through the gaps between the metal trenches 240. There may be gaps 270 between adjacent deep trenches 260, so that the waveguide 210 can be supported by the substrate at the gaps 270. Figure 2 As shown, gap 250 and gap 270 may be misaligned and may be offset from each other by a certain distance so that gap 250 may not be in the line of sight of stray photons from input port 220 and thus stray photons from input port 220 may not pass through gap 250 and may be blocked by metal trench 240.

[0051] Figure 3 An example of utilizing various isolation structures to locally isolate a photodetector 350 in a photonic integrated circuit 300 according to certain embodiments is illustrated. PIC 300 may include a substrate 305 (e.g., a silicon handle wafer). A waveguide 310 may be formed on substrate 305, wherein waveguide 310 may include multiple turns to change direction. Optical isolation structures, such as a top metal cap 320, a metal trench 330, and a deep trench 340, may be fabricated in PIC 300 to surround and isolate waveguide 310 and photodetector 350. Figure 3 The optical isolation structure shown can be Figure 1 The isolation structure 170 is a specific embodiment of the present invention, and can be formed into an isolation structure similar to a castle-like structure.

[0052] like Figure 3As illustrated, waveguide 310 can guide signal light from the photonic circuit in PIC 300 to photodetector 350 (e.g., SNSPD), where the signal light can be detected. Similar to deep trench 260, deep trench 340 can include an air gap that passes completely through substrate 305, or can be filled with a reflective or absorptive material. In some embodiments, deep trench 340 can partially pass through substrate 305. The deep trench can isolate photodetector 350 from light that will propagate in or be scattered from substrate 305. Metal trench 330 can be similar to metal trench 240 and can form a mirror barrier that can extend from M1 down to substrate 305, as described above with respect to Figure 2 As described. In some embodiments, the metal trench 330 may include a plurality of nested rings centered on the photodetector 350, wherein an inner ring may be surrounded by one or more outer rings. Each ring may include an opening through which the waveguide 310 may pass. The opening in each ring may be located on a different side (e.g., an opposite side or an adjacent side) relative to the opening in the adjacent ring. The metal trench 330 may block light propagating in the cladding of the waveguide 310 from reaching the photodetector 350. The top metal cover 320 may serve as a top of the optical isolation structure (which may be similar to a castellated structure) and may prevent light from reaching the photodetector 350 from the top of the photodetector 350 and the PIC 300.

[0053] Figures 4A to 4D Another example of utilizing various isolation structures to locally isolate the photodetector 470 in the optical device 400 according to certain embodiments is illustrated. Figure 4A is a cross-sectional view of an optical device 400 including a photodetector 470 and an optical isolation structure surrounding the photodetector 470 . Figure 4B yes Figure 4A , which is a perspective view of an optical device 400 shown in FIG. The optical device 400 may include a substrate 410 (e.g., a silicon handle wafer), a barrier oxide (BOX) layer 420 (e.g., silicon dioxide), a waveguide 440 formed on top of the BOX layer 420, and a low temperature oxide (LTO) layer 430 covering the waveguide 440. The optical device 400 may also include an array of vias 450 and a top metal cap 460 that may be formed on the Metal 1 layer.

[0054] Figure 4C yes Figure 4A A top view of the optical device 400 in FIG. Figure 4C A top metal cover 460 is shown covering the photodetector 470 from the top so that background light will not reach the photodetector 470 from the top, wherein the top metal cover 460 may be part of the Metal 1 layer.

[0055] Figure 4D yes Figure 4A A top view of a cross section of the optical device 400 in FIG. Figure 4D The arrangement of a via array 450 and a photodetector 470 is shown. As illustrated, the via array 450 can be arranged in a two-dimensional array, where the vias in a row (or column) can be offset from the vias in an adjacent row (or column) so that the via array can effectively form a wall. The photodetector 470 can include a photoactive nanowire 480 (e.g., niobium germanium nanowire) on the waveguide 440.

[0056] Figure 5 is a flowchart 500 illustrating an exemplary method for fabricating various optical isolation structures in a photonic integrated circuit according to certain embodiments. Figure 5 Operations are described in a sequential flow, but some operations may be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may have additional steps not included in the diagram. Some operations are optional and therefore may be omitted in various embodiments. Some operations may be performed in conjunction with other operations.

[0057] Optionally, at block 510, a barrier oxide layer (e.g., Figure 4A and Figure 4B A waveguide layer is formed on the BOX layer 420 shown in FIG. The waveguide layer can be patterned and etched using, for example, photolithography techniques to form a waveguide core and / or input / output couplers. At block 520, a photoactive layer (e.g., a niobium germanium layer) can be deposited on top of the waveguide layer. The photoactive layer can be patterned and etched to form nanowires in the region of the waveguide core. The processing at blocks 510 and 520 can be part of a front-end of line process in a CMOS process.

[0058] Figure 6 FIG2 is a cross-sectional view of an example of a photonic integrated circuit 600 including a photodetector fabricated using front-end processes at blocks 510 and 520, according to some embodiments. The PIC 600 may include a substrate 610 (e.g., a silicon handle wafer), a BOX layer 620 formed on the substrate 610, various devices on the device layer (e.g., an optical input / output coupler 640, a waveguide 650, and a photodetector including a waveguide 660 and nanowires 670 containing a photoactive material), and an oxide layer 630 covering the device layer. The optical input / output coupler 640 may include a grating coupler. The oxide layer 630 and the BOX layer 620 may serve as cladding layers for the waveguide 650. In one example, the oxide layer 630 may have a thickness of approximately 1 μm.

[0059] At block 530, vias or trenches may be etched down through the oxide layer to the substrate. For example, a patterned mask layer may be formed on the oxide layer (e.g., LTO layer and BOX layer), and a wet or dry etching technique may be selectively used to etch the vias (holes) or trenches through the oxide layer. The patterned mask layer may have a total thickness of, for example, 3 μm to 4 μm.

[0060] Figure 7 is a cross-sectional view of an example of a photonic integrated circuit 700 having vias or trenches 710 etched in an oxide layer using a back-end-of-line (BEOL) process at block 530, according to some embodiments. PIC 700 may be fabricated from PIC 600. Vias or trenches 710 may be etched through oxide layer 630 and BOX layer 620 down to substrate 610.

[0061] At block 540, the via or trench may be filled with a reflective or absorptive material, such as a metal material. For example, a metal layer may be deposited on the oxide layer and selectively etched in one or more cycles to form a metal plug in the via or trench.

[0062] Figure 8 is a cross-sectional view of an example of a photonic integrated circuit 800 having vias or trenches filled with a reflective or absorptive material (e.g., a metal such as copper, aluminum, cobalt, tungsten, etc.) etched in an oxide layer using a BEOL process at block 540, in accordance with certain embodiments. PIC 800 may be fabricated from PIC 700, where vias or trenches 710 may be filled with metal plugs 810.

[0063] At block 550, a metal 1 layer can be deposited on the oxide layer and etched using standard CMOS BEOL processing techniques to leave a top metal cap in the region of the top of the photodetector. The top metal cap can be aligned with a via or trench filled with a reflective or absorptive material (e.g., metal). Thus, the top metal cap and the via or trench can block background light from at least three directions (e.g., top, left, and right) or five directions (e.g., top, left, right, front, and back).

[0064] Figure 9is a cross-sectional view of an example of a photonic integrated circuit 900 having a top metal cap 910 fabricated as part of a metal layer for locally isolating a photodetector fabricated using a BEOL process at block 550, in accordance with certain embodiments. PIC 900 may be fabricated from PIC 800 and may include an additional top metal cap 910 formed as part of a metal 1 layer. Top metal cap 910 may be located above (e.g., on top of) a photodetector including waveguides 660 and nanowires 670. Top metal cap 910 may contact metal plugs 810 in vias or trenches 710 to block light from above, to the left, and to the right in the two-dimensional cross-sectional view.

[0065] Optionally, other BEOL processes may be performed to form, for example, additional dielectric (eg, oxide) layers and upper metal layers (eg, metal 2, metal 3, etc.) at block 560. These BEOL processes may include standard CMOS BEOL processes.

[0066] Figure 10 is a cross-sectional view of an example of a photonic integrated circuit 1000 after additional BEOL processing at block 560 in accordance with certain embodiments. PIC 1000 may be fabricated from PIC 900 and may include additional metal layers 1010 and upper-level metal layers, such as metal layer 1020 .

[0067] At block 570, the substrate may be etched from the back side to form deep trenches in the substrate from the back side. The deep trenches may reflect photons propagating within the substrate at the interface between the substrate material and the air gap. For example, total internal reflection may occur when photons are incident at an angle on the interface from the substrate material to the air gap.

[0068] Figure 11 is a cross-sectional view of an example of a photonic integrated circuit 1100 according to some embodiments, the photonic integrated circuit 1100 including a trench 1110 etched in a substrate of the photonic integrated circuit using a BEOL process at block 570. The PIC 1100 can be fabricated from the PIC 1000 and can include the trench 1110 in the substrate 610. The trench 1110 can be offset from the metal plug 810. For example, the trench 1110 can be slightly further away from the photodetector than the metal plug 810 to prevent light from the bottom side of the substrate 610 and the BOX layer 620 from bypassing the metal plug 810 and reaching the photodetector.

[0069] Optionally, at block 580 , the deep trenches may be filled with a reflective or absorptive material (eg, a metallic material) that may block light.

[0070] Figure 12is a cross-sectional view of an example of a photonic integrated circuit 1200 including a deep trench in a substrate filled with a reflective or absorptive material using a process at block 580, in accordance with some embodiments. PIC 1200 may be fabricated from PIC 1100 and may include a reflective or absorptive material 1210 (e.g., a metal material) filled in trench 1110.

[0071] Figure 13 is a cross-sectional view of a photonic integrated circuit 1200, illustrating optical isolation formed by various isolation structures in a photonic integrated circuit, according to certain embodiments. Light from a laser can be sent to the PIC 1200 via an input fiber 1310, which can include a collimator, such as a GRIN lens or a microlens. Input light 1320 from the input fiber 1310 can propagate through the oxide layer and can be partially coupled into a waveguide in the PIC 1200 by means of an optical input / output coupler 640, which in some embodiments can include a tilted grating.

[0072] Light not coupled into the waveguide by means of the optical input / output coupler 640 will be scattered in various directions. For example, a portion of the input light 1320 may be reflected at the interface between the substrate 610 and the BOX layer 620 as light 1330, which may be further reflected by the metal layer 1020 as light 1370, which may be blocked by one of the metal plugs 810. A portion of the input light 1320 may be scattered as light 1335, which may propagate toward the metal plug 810 and be blocked by it. A portion of the input light 1320 may be scattered at the bottom surface of the substrate 610, where a portion of the scattered light 1350 may be blocked by the reflective or absorptive material 1210 in the trench 1110, while another portion of the scattered light 1340 may be blocked by the metal plug 810.

[0073] Light 1360 that scatters or otherwise leaks from waveguide 650 can also be blocked by metal plug 810 from reaching the photodetector. Ambient light 1380 that may enter the oxide layer from the top or stray light reflected by various metal layers can be blocked by top metal cover 910 on top of the photodetector and thus also does not reach the photodetector. In this way, only photons guided within waveguide 660 can reach the photodetector, significantly reducing or essentially eliminating background noise. Consequently, high sensitivity and a high signal-to-noise ratio (SNR) can be achieved by the photodetector.

[0074] In various embodiments, other dielectric layers used in CMOS processing may be used to replace one or more of the above-mentioned oxide layers (e.g., silicon dioxide layers). For example, the dielectric layer may include silicon nitride, alkali halides, barium titanate, lead titanate, tantalum oxide, tungsten oxide, zirconium oxide, etc.

[0075] Some of the above processes, such as oxide and metal deposition processes, may need to be performed at elevated temperatures (e.g., 700K or higher). In addition, it may be necessary to bond the PIC to an electronic integrated circuit and / or printed circuit board at elevated temperatures. However, in order to be in a superconducting state, the superconducting nanowires in the single-photon detector may need to be operated at low temperatures (e.g., less than or equal to about 4K). Therefore, at least the area surrounding the superconducting nanowires may need to be cooled to cryogenic temperatures during normal operation. Therefore, the optical isolation structure adjacent to the superconducting nanowires may experience large temperature changes from the manufacturing environment to the operating environment.

[0076] As described above, reflective or absorptive materials such as metals (including copper, aluminum, cobalt, tungsten, etc.) can be used to fill trenches (e.g., trench 1110) to block stray light or ambient light from reaching the sensitive single-photon detector. However, most metals, such as copper and tungsten, may have a much higher coefficient of thermal expansion (CTE) than silicon and SiO2. Consequently, when the PIC is cooled from a processing temperature (e.g., greater than or equal to 4K) to an operating temperature (e.g., less than or equal to 4K), there may be a significant difference between the amount of thermal contraction of the filling material in the trench and the amount of thermal contraction of the other materials of the PIC. Consequently, a significant amount of induced strain may occur near the trench, potentially affecting the mechanical stability and performance of the PIC.

[0077] Figure 14A The CTE mismatch between silicon and copper is shown. Curve 1410 shows the CTE mismatch between silicon and copper as the temperature varies from approximately 0K to approximately 273K. Figure 13 The total percentage of thermal expansion (or contraction) of silicon for a particular temperature change (e.g., between 0K and 273K) may be the area below curve 1410. Curve 1420 shows the CTE of copper, which may be used as a substrate, as the temperature changes from 0K to about 273K. Figure 13 The total percentage of thermal expansion (or contraction) of copper for a particular temperature change (e.g., between 0K and 10K) may be the area under curve 1420. Figure 14AAs shown, at a given temperature, copper has a much higher coefficient of thermal expansion than silicon. Therefore, for the same temperature change, the total percentage of thermal expansion (or contraction) of copper will be much greater than the total percentage of thermal expansion (or contraction) of silicon. Tungsten has a smaller CTE than copper but much larger than silicon, so for the same temperature change, the total percentage of thermal expansion (or contraction) of tungsten will be much greater than the total percentage of thermal expansion (or contraction) of silicon. Therefore, if the size of the trench, and therefore the size of the metal material filling the trench, is relatively large, the difference between the overall thermal expansion of the metal material in the trench and the overall thermal expansion of the adjacent silicon material will be significant. Consequently, large stresses will be induced around the trench, which can lead to damage or defects in the PIC and / or alter the optical properties (e.g., optical loss, guided modes, polarization properties, etc.) of the waveguides and other components in the PIC.

[0078] Figure 14B The coefficient of thermal expansion of silicon oxide is shown. Curve 1430 shows the CTE of silicon oxide (e.g., BOX layer 620 or oxide layer 630 described above) as the temperature varies from 0 K to approximately 300 K. As illustrated, the CTE of silicon oxide at a certain temperature will be lower than the CTE of silicon at the same temperature, and will be much lower than the CTE of copper or tungsten at the same temperature. Therefore, the CTE mismatch between copper, tungsten, and silicon oxide can be even greater than the CTE mismatch between copper and silicon.

[0079] Figure 15A is a cross-sectional view of an example of a photonic integrated circuit 1500 including a trench filled with a reflective or absorptive optical isolation material, according to certain embodiments. As described above, the photonic integrated circuit 1500 may include a silicon substrate 1510, a BOX layer 1520, and a cladding layer 1530 (e.g., a silicon oxide layer). A superconducting nanowire single-photon detector (SNSPD) 1540 may be formed in the BOX layer 1520 and the cladding layer 1530. To isolate the SNSPD 1540, a metal plug 1550 (similar to, for example, metal plug 810) may be formed in the BOX layer 1520 and the cladding layer 1530 adjacent to the SNSPD 1540. The metal plug 1550 may include, for example, a via or trench filled with tungsten or other metal, metal alloy, or metal compound. An additional optical isolation structure 1560 may be formed in the silicon substrate 1510, the BOX layer 1520, and the cladding layer 1530 to prevent stray light from reaching the SNSPD 1540 in various directions and passing through various material layers (e.g., the silicon substrate 1510). The optical isolation structure 1560 may be filled with a reflective or absorptive optical isolation material, such as a metal (e.g., copper or tungsten), a metal alloy, or a metal compound (e.g., a metal nitride).

[0080] As described above, since the size of the optical isolation structure 1560 can be relatively large, when the temperature of the photonic integrated circuit 1500 changes significantly, the thermal expansion of the metal in the optical isolation structure 1560 will be much greater than the thermal expansion of the silicon in the silicon substrate 1510 and the silicon oxide in the BOX layer 1520 and the cladding layer 1530. Therefore, large mechanical stress will be introduced into the photonic integrated circuit 1500.

[0081] According to certain embodiments, when the PIC 1500 is cooled from a processing temperature (e.g., greater than 700 K) to an operating temperature (e.g., less than or equal to about 4 K), to reduce stress and potential damage caused by the CTE mismatch between the optical isolation structure 1560 and other portions of the PIC 1500, one or more thin optical isolation layers (e.g., having a thickness of less than 100 nm (nanometers), such as less than or equal to about 50 nm, about 60 nm, or about 70 nm) can be deposited on the inner surfaces of the trenches for the optical isolation structure 1560 (which can have linear dimensions of several micrometers or tens of micrometers). The trenches can then be filled with a material having a CTE that approximately matches the CTE of the substrate or other layer in which the trenches are formed. The combination of the optical isolation layers in the optical isolation structure can be optically opaque. Thus, the optical isolation structure 1560, including the thin optical isolation layers and the CTE-matching filler material, can expand at approximately the same rate as the rest of the PIC, reducing internal stress and potential damage or defects in the PIC.

[0082] Figure 15B is a cross-sectional view of an example of a photonic integrated circuit 1502 including trenches filled with thin layers of optical isolation material and CTE matching material, according to certain embodiments. As the photonic integrated circuit 1500, the photonic integrated circuit 1502 may include a silicon substrate 1512, a BOX layer 1522, and a cladding layer 1532 (e.g., a silicon oxide layer). A superconducting nanowire single-photon detector 1542 may be formed in the BOX layer 1522 and the cladding layer 1532. To isolate the SNSPD 1542, a metal plug 1552 (similar to, for example, metal plug 810) may be formed in the BOX layer 1522 and the cladding layer 1532 adjacent to the SNSPD 1542. The metal plug 1552 may include, for example, a via or trench filled with tungsten or other metal, metal alloy, or metal compound. Additional light isolation structures 1562 may be formed in the silicon substrate 1512 , the BOX layer 1522 , and the cladding layer 1532 to prevent stray light or ambient light from reaching the SNSPD 1542 in various directions and passing through various material layers (eg, the silicon substrate 1512 ).

[0083] Each optical isolation structure 1562 may include an adhesion layer 1582 (e.g., a Ti layer having a thickness of about 2 nm to about 10 nm) and an optical isolation layer 1592 (e.g., a TiN, TaN, ZrN, or WN layer having a thickness of about 25 nm to about 60 nm) on each sidewall and bottom surface of the trench forming the optical isolation structure 1562. The total thickness of the two optical isolation layers 1592 in two opposing sidewalls in the optical isolation structure 1562 may be, for example, about 50 nm to about 120 nm. Thus, the combination of the two optical isolation layers 1592 may be optically opaque. The adhesion layer 1582 may help improve the adhesion between the optical isolation layer 1592 and the silicon substrate 1512 and the oxide layer (e.g., the BOX layer 1522 and the cladding layer 1532). A portion 1563 of the optical isolation structure 1562 within the silicon substrate 1512 can be filled with polysilicon, and a portion 1572 of the optical isolation structure 1562 within the BOX layer 1522 and the cladding layer 1532 can be filled with silicon oxide. Thus, a portion of the optical isolation structure 1562 within the silicon substrate 1512 (including the adhesive layer 1582, the optical isolation layer 1592, and the portion 1563) can have a CTE that approximately matches the CTE of silicon, while a portion of the optical isolation structure 1562 within the BOX layer 1522 and the cladding layer 1532 (including the adhesive layer 1582, the optical isolation layer 1592, and the portion 1572) can have a CTE that approximately matches the CTE of silicon oxide. Consequently, the optical isolation structure 1562 can expand at approximately the same rate as the silicon substrate 1512, the BOX layer 1522, and the cladding layer 1532, thereby reducing internal stress and potential damage or defects in the PIC.

[0084] Figure 15C is a cross-sectional view of an example of a photonic integrated circuit 1504 including trenches filled with thin layers of optical isolation material and CTE matching material, according to certain embodiments. As with photonic integrated circuit 1502, photonic integrated circuit 1504 may include a silicon substrate 1514, a BOX layer 1524, and a cladding layer 1534 (e.g., a silicon oxide layer). A superconducting nanowire single-photon detector 1544 may be formed in the BOX layer 1524 and the cladding layer 1534. To isolate the SNSPD 1544, a metal plug 1554 (similar to, for example, metal plug 810) may be formed in the BOX layer 1524 and the cladding layer 1534 adjacent to the SNSPD 1544. The metal plug 1554 may include, for example, a via or trench filled with tungsten or other metal, metal alloy, or metal compound. Additional light isolation structures 1564 may be formed in the silicon substrate 1514 , the BOX layer 1524 , and the cladding layer 1534 to prevent stray light or ambient light from reaching the SNSPD 1544 in various directions and passing through various material layers (eg, of the silicon substrate 1514 ).

[0085] Each optical isolation structure 1564 may include a first adhesive layer 1584 (e.g., a Ti layer having a thickness of about 2 nm to about 10 nm), an optical isolation layer 1594 (e.g., a TiN, TaN, ZrN, or WN layer having a thickness of about 25 nm to about 60 nm), and a second adhesive layer 1586 on each sidewall and bottom surface of the trench forming the optical isolation structure 1564. The total thickness of the two optical isolation layers 1592 in two opposing sidewalls in the optical isolation structure 1562 may be, for example, about 50 nm to about 120 nm. Thus, the two optical isolation layers 1594, alone or in combination, may be optically opaque. The first adhesive layer 1584 may help improve the adhesion between the optical isolation layer 1594 and the silicon substrate 1514 or the oxide layer (e.g., the BOX layer 1524 and the cladding layer 1534). A portion 1565 of the optical isolation structure 1564 within the silicon substrate 1514 can be filled with polysilicon, and a portion 1574 of the optical isolation structure 1564 within the BOX layer 1524 and the cladding layer 1534 can be filled with silicon oxide. The second adhesive layer 1586 can help improve the adhesion between the optical isolation layer 1594 in the trench and the polysilicon (portion 1565) and silicon dioxide (portion 1574). Therefore, the portion of the optical isolation structure 1564 within the silicon substrate 1514 (including the adhesive layer 1586, the optical isolation layer 1594, and the portion 1565) can have a CTE that approximately matches the CTE of silicon, and the portion of the optical isolation structure 1564 within the BOX layer 1524 and the cladding layer 1534 (including the adhesive layer 1586, the optical isolation layer 1594, and the portion 1574) can have a CTE that approximately matches the CTE of silicon oxide. Thus, the light isolation structure 1564 can expand at approximately the same rate as the silicon substrate 1514 , the BOX layer 1524 , and the cladding layer 1534 to reduce internal stress and potential damage or defects in the PIC.

[0086] Figures 16A to 16G An example of a method of fabricating an optical isolation structure (eg, optical isolation structure 1562 ) including a thin optical isolation layer and a CTE matching material in accordance with certain embodiments is illustrated. Figure 16A A trench 1650 formed in a photonic integrated circuit is shown. The photonic integrated circuit includes a silicon oxide layer 1620 on a silicon substrate 1610, wherein a superconducting nanowire single-photon detector 1630 and a metal plug 1640 are fabricated in the silicon oxide layer 1620. The trench 1650 can be formed using various selective etching techniques, such as photolithography and dry etching techniques. The trench 1650 can be etched from either the silicon oxide layer 1620 side or the silicon substrate 1610 side. In some embodiments, the trench 1650 can be etched through both the silicon oxide layer 1620 and the silicon substrate 1610.

[0087] Figure 16BA photonic integrated circuit is illustrated having a thin adhesion layer 1660 and a thin optical isolation layer 1662 conformally deposited on the exposed surface of the trench 1650 and on the top surface of the silicon oxide layer 1620. As described above, the adhesion layer 1660 can help improve the adhesion of the optical isolation layer 1662 to the sidewalls and bottom surface of the trench 1650. The adhesion layer 1660 can include, for example, a titanium (Ti) layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). The adhesion layer 1660 can be deposited on the exposed surface of the trench 1650 and on the top surface of the silicon oxide layer 1620 using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Optical isolation layer 1662 may include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and may have a thickness of approximately several tens of nanometers (e.g., approximately 25 nm to approximately 60 nm). Optical isolation layer 1662 may be deposited on adhesion layer 1660 using, for example, ALD, CVD, PVD, or the like.

[0088] Figure 16C A polysilicon layer 1670 is illustrated deposited on the photonic integrated circuit and filling the trench 1650. The polysilicon layer 1670 may be deposited on the photonic integrated circuit, for example, by CVD or PVD. Figure 16D The polysilicon layer 1670 is shown having been planarized, for example, by chemical mechanical polishing (CMP), to expose the optical isolation layer 1662 , which can subsequently be removed along with the adhesion layer 1660 , for example, by selective wet etching.

[0089] Figure 16E A portion of the polysilicon layer 1670 filling the trench 1650 is illustrated, and this portion can be selectively etched by a wet etching process to a level substantially aligned with the interface between the silicon substrate 1610 and the silicon oxide layer 1620. Therefore, a portion of the polysilicon layer 1670 can remain in the trench 1650, while the top surface of the remaining portion of the polysilicon layer 1670 can be substantially aligned with the interface between the silicon substrate 1610 and the silicon oxide layer 1620.

[0090] Figure 16F A silicon oxide layer 1680 is shown deposited on the silicon oxide layer 1620. The silicon oxide layer 1680 may again fill the trench 1650. The silicon oxide layer 1680 may be deposited on the photonic integrated circuit using, for example, CVD or PVD.

[0091] Figure 16G A silicon oxide layer 1680 is shown that has been planarized by, for example, chemical mechanical polishing. Thus, the photonic integrated circuit can include optical isolation structures 1664 similar to optical isolation structures 1562, with each optical isolation structure 1664 including a portion of a polysilicon layer 1670 and a portion of a silicon oxide layer 1680 surrounded by sidewalls including the adhesion layer 1660 and the optical isolation layer 1662.

[0092] 17A to 17H An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated. Figure 17A A trench 1750 formed in a photonic integrated circuit is shown. The photonic integrated circuit includes a silicon oxide layer 1720 on a silicon substrate 1710, wherein a superconducting nanowire single-photon detector 1730 and a metal plug 1740 are fabricated in the silicon oxide layer 1720. The trench 1750 can be formed using various selective etching techniques, such as photolithography and dry or wet etching techniques. The trench 1750 can be etched from either the silicon oxide layer 1720 side or the silicon substrate 1710 side. In some embodiments, the trench 1750 can be etched through both the silicon oxide layer 1720 and the silicon substrate 1710.

[0093] Figure 17B A photonic integrated circuit is illustrated having a thin adhesion layer 1760 and a thin optical isolation layer 1762 conformally deposited on the exposed surface of the trench 1750 and on the top surface of the silicon oxide layer 1720. As described above, the adhesion layer 1760 can help improve the adhesion of the optical isolation layer 1762 to the sidewalls and bottom surface of the trench 1750. The adhesion layer 1760 can include, for example, a titanium layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). The adhesion layer 1760 can be deposited on the exposed surface of the trench 1750 and on the top surface of the silicon oxide layer 1720 using, for example, ALD, CVD, PVD, etc. The optical isolation layer 1762 can include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and can have a thickness of approximately tens of nanometers (e.g., approximately 25 nm to approximately 60 nm). Optical isolation layer 1762 may be deposited on adhesion layer 1760 using, for example, ALD, CVD, PVD, or the like.

[0094] Figure 17C A polysilicon layer 1770 is illustrated as being deposited on the photonic integrated circuit and filling the trench 1750. The polysilicon layer 1770 may be deposited on the photonic integrated circuit by, for example, CVD or PVD. Figure 17DPolysilicon layer 1770 is shown having been planarized, for example, by chemical mechanical polishing, to expose optical isolation layer 1762, which may subsequently be removed along with adhesion layer 1760, for example, by selective wet etching.

[0095] Figure 17E A portion of the polysilicon layer 1770 filling the trench 1750 is illustrated, which is a portion that can be selectively etched by a dry etching process (e.g., plasma etching (such as RIE)) to a level that is more accurately aligned with the interface between the silicon substrate 1710 and the silicon oxide layer 1720. Therefore, the trench 1752 can be formed in the silicon oxide layer 1720, and a portion of the polysilicon layer 1770 can remain in the trench 1750, while the top surface of the remaining portion of the polysilicon layer 1770 can be aligned with the interface between the silicon substrate 1710 and the silicon oxide layer 1720.

[0096] Figure 17F A thin adhesion layer 1764 and a thin optical isolation layer 1766 are shown, which can be conformally deposited on the exposed surfaces of trench 1752 and on the top surface of silicon oxide layer 1720. As described above, adhesion layer 1764 can help improve the adhesion of optical isolation layer 1766 to the sidewalls and bottom surface of trench 1752. Adhesion layer 1764 can include, for example, a titanium layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). Adhesion layer 1764 can have a thickness similar to that of adhesion layer 1760. Adhesion layer 1764 can be deposited on the exposed surfaces of trench 1752 and on the top surface of silicon oxide layer 1720 using ALD, CVD, PVD, or the like. Optical isolation layer 1766 can include a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and can have a thickness similar to that of optical isolation layer 1762. For example, the thickness of optical isolation layer 1766 can be on the order of tens of nanometers, e.g., approximately 25 nm to approximately 60 nm. Optical isolation layer 1766 may be deposited on adhesion layer 1764 using, for example, ALD, CVD, PVD, or the like.

[0097] Figure 17G A silicon oxide layer 1780 is shown deposited on the silicon oxide layer 1720. The silicon oxide layer 1780 may fill the trench 1752. The silicon oxide layer 1780 may be deposited on the photonic integrated circuit by, for example, CVD or PVD.

[0098] Figure 17HA silicon oxide layer 1780 is shown that has been planarized, for example, by chemical mechanical polishing. Adhesion layer 1764 and optical isolation layer 1766 can be removed, for example, by selective dry etching or wet etching. Thus, the photonic integrated circuit can include optical isolation structures 1768, each of which includes a portion of silicon oxide layer 1780 and a portion of polysilicon layer 1770 surrounded by sidewalls, wherein the sidewalls include adhesion layer 1760 or 1764 and optical isolation layer 1762 or 1766.

[0099] As mentioned above about Figure 15C As described above, in order to improve the adhesion between the optical isolation layer 1594 and the polysilicon or silicon oxide filling the deep trench to form the optical isolation structure, a second adhesion layer 1586 may be used between the optical isolation layer 1594 and the polysilicon or silicon oxide filling the deep trench.

[0100] Figures 18A to 18G An example of a method of fabricating an optical isolation structure (eg, optical isolation structure 1564 ) including a thin optical isolation layer and a CTE matching material is shown in accordance with certain embodiments. Figure 18A A trench 1850 formed in a photonic integrated circuit is shown. The photonic integrated circuit includes a silicon oxide layer 1820 on a silicon substrate 1810, wherein a superconducting nanowire single-photon detector 1830 and a metal plug 1840 are fabricated in the silicon oxide layer 1820. The trench 1850 can be formed using various etching techniques, such as photolithography and dry or wet etching techniques. The trench 1850 can be etched from either the silicon oxide layer 1820 side or the silicon substrate 1810 side. In some embodiments, the trench 1850 can be etched through both the silicon oxide layer 1820 and the silicon substrate 1810.

[0101] Figure 18BA photonic integrated circuit is illustrated having a first adhesion layer 1860, a thin optical isolation layer 1862, and a second adhesion layer 1864 conformally deposited on the exposed surface of trench 1850 and on the top surface of silicon oxide layer 1820. As described above, first adhesion layer 1860 can help improve the adhesion of optical isolation layer 1862 to the sidewalls and bottom surface of trench 1850. First adhesion layer 1860 can include, for example, a titanium layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). First adhesion layer 1860 can be deposited on the exposed surface of trench 1850 and on the top surface of silicon oxide layer 1820 using, for example, ALD, CVD, PVD, etc. Optical isolation layer 1862 can include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and can have a thickness of approximately tens of nanometers (e.g., approximately 25 nm to approximately 60 nm). Optical isolation layer 1862 can be deposited on first adhesive layer 1860 using, for example, ALD, CVD, PVD, etc. Second adhesive layer 1864 can help improve the adhesion of optical isolation layer 1862 to the material in trench 1850. Second adhesive layer 1864 can include, for example, a titanium layer having a thickness of several nanometers (e.g., about 2 nm to about 10 nm). Second adhesive layer 1864 can be deposited on optical isolation layer 1862 using, for example, ALD, CVD, PVD, etc.

[0102] Figure 18C A polysilicon layer 1870 is illustrated as being deposited on the photonic integrated circuit and filling the trench 1850. The polysilicon layer 1870 may be deposited on the photonic integrated circuit by, for example, CVD or PVD.

[0103] Figure 18D Polysilicon layer 1870 is shown having been planarized, for example by chemical mechanical polishing, to expose second adhesion layer 1864 or optical isolation layer 1862, which can subsequently be removed along with first adhesion layer 1860, for example by selective wet etching.

[0104] Figure 18E A portion of the polysilicon layer 1870 filling the trench 1850 is illustrated, and this portion is a portion that can be selectively etched, for example, by a wet etching process to a level approximately aligned with the interface between the silicon substrate 1810 and the silicon oxide layer 1820. Therefore, a portion of the polysilicon layer 1870 can remain in the trench 1850, while the top surface of the remaining portion of the polysilicon layer 1870 can be approximately aligned with the interface between the silicon substrate 1810 and the silicon oxide layer 1820.

[0105] Figure 18FA silicon oxide layer 1880 is shown deposited on the silicon oxide layer 1820. The silicon oxide layer 1880 may again fill the trench 1850. The silicon oxide layer 1880 may be deposited on the photonic integrated circuit by, for example, CVD or PVD.

[0106] Figure 18G The silicon oxide layer 1880 is shown planarized by, for example, chemical mechanical polishing. The third adhesion layer 1966, the optical isolation layer 1968, and the fourth adhesion layer 1972 can be removed, for example, by selective dry etching or wet etching. Thus, the photonic integrated circuit can include optical isolation structures 1866 similar to the optical isolation structures 1564, each of which includes a portion of the polysilicon layer 1870 and a portion of the silicon oxide layer 1880 surrounded by sidewalls, wherein the sidewalls include the first adhesion layer 1860, the optical isolation layer 1862, and the second adhesion layer 1864.

[0107] Figures 19A to 19H An example of a method of fabricating an optical isolation structure including a thin optical isolation layer and a CTE matching material according to certain embodiments is illustrated. Figure 19A A trench 1950 formed in a photonic integrated circuit is shown. The photonic integrated circuit includes a silicon oxide layer 1920 on a silicon substrate 1910, wherein a superconducting nanowire single-photon detector 1930 and a metal plug 1940 are formed in the silicon oxide layer 1920. The trench 1950 can be formed using various etching techniques, such as photolithography and selective dry or wet etching techniques. The trench 1950 can be etched from either the silicon oxide layer 1920 side or the silicon substrate 1910 side. In some embodiments, the trench 1950 can be etched through both the silicon oxide layer 1920 and the silicon substrate 1910.

[0108] Figure 19BA photonic integrated circuit is illustrated having a first adhesion layer 1960, a thin optical isolation layer 1962, and a second adhesion layer 1964 conformally deposited on the exposed surface of trench 1950 and on the top surface of silicon oxide layer 1920. As described above, first adhesion layer 1960 can help improve the adhesion of optical isolation layer 1962 to the sidewalls and bottom surface of trench 1950. First adhesion layer 1960 can include, for example, a titanium layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). First adhesion layer 1960 can be deposited on the exposed surface of trench 1950 and on the top surface of silicon oxide layer 1920 using, for example, ALD, CVD, PVD, etc. Optical isolation layer 1962 can include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and can have a thickness of approximately tens of nanometers (e.g., approximately 25 nm to approximately 60 nm). Optical isolation layer 1962 can be deposited on first adhesion layer 1960 using, for example, ALD, CVD, PVD, etc. Second adhesion layer 1964 can help improve the adhesion of optical isolation layer 1962 to the material in trench 1950. Second adhesion layer 1964 can include, for example, a titanium layer having a thickness of several nanometers (e.g., about 2 nm to about 10 nm). Second adhesion layer 1964 can be deposited on optical isolation layer 1962 using, for example, ALD, CVD, PVD, etc.

[0109] Figure 19C A polysilicon layer 1970 is illustrated as being deposited on the photonic integrated circuit and filling the trench 1950. The polysilicon layer 1970 may be deposited on the photonic integrated circuit by, for example, CVD or PVD.

[0110] Figure 19D Polysilicon layer 1970 is shown having been planarized, for example by chemical mechanical polishing, to expose second adhesion layer 1964 or optical isolation layer 1962, which can subsequently be removed along with first adhesion layer 1960, for example by selective wet etching.

[0111] Figure 19E A portion of the polysilicon layer 1970 filling the trench 1950 is illustrated, and this portion can be selectively etched by a dry etching process (e.g., plasma etching (such as RIE)) to a portion at a level more accurately aligned with the interface between the silicon substrate 1910 and the silicon oxide layer 1920. Thus, a trench 1952 can be formed in the silicon oxide layer 1920, and a portion of the polysilicon layer 1970 can remain in the trench 1950, while the top surface of the remaining portion of the polysilicon layer 1970 can be aligned with the interface between the silicon substrate 1910 and the silicon oxide layer 1920.

[0112] Figure 19F A third adhesion layer 1966, a thin optical isolation layer 1968, and a fourth adhesion layer 1972 are shown, which can be conformally deposited on the exposed surfaces of trench 1952 and on the top surface of silicon oxide layer 1920. As described above, third adhesion layer 1966 can help improve the adhesion of optical isolation layer 1968 to the sidewalls and bottom surface of trench 1952. Third adhesion layer 1966 can have a thickness similar to that of first adhesion layer 1960. For example, third adhesion layer 1966 can include a titanium layer having a thickness of several nanometers (e.g., approximately 2 nm to approximately 10 nm). Third adhesion layer 1966 can be deposited on the exposed surfaces of trench 1952 and on the top surface of silicon oxide layer 1920 using, for example, ALD, CVD, PVD, etc. Optical isolation layer 1968 can include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof) and can have a thickness similar to that of optical isolation layer 1962. For example, the thickness of optical isolation layer 1968 can be about several tens of nanometers, for example, about 25 nanometers to about 60 nanometers. Optical isolation layer 1968 can be deposited on third adhesion layer 1966 using, for example, ALD, CVD, PVD, etc. Fourth adhesion layer 1972 can help improve the adhesion of optical isolation layer 1968 to the material in trench 1952. Fourth adhesion layer 1972 can include, for example, a titanium layer having a thickness of several nanometers (for example, about 2 nm to about 10 nm). Fourth adhesion layer 1972 can be deposited on optical isolation layer 1968 using, for example, ALD, CVD, PVD, etc.

[0113] Figure 19G A silicon oxide layer 1980 is shown deposited on the silicon oxide layer 1920. The silicon oxide layer 1980 may fill the trench 1952. The silicon oxide layer 1980 may be deposited on the photonic integrated circuit using, for example, CVD or PVD.

[0114] Figure 19H A silicon oxide layer 1980 is shown that has been planarized, for example, by chemical mechanical polishing. Third adhesion layer 1966, optical isolation layer 1968, and fourth adhesion layer 1972 can be removed, for example, by selective dry etching or wet etching. Thus, the photonic integrated circuit can include optical isolation structures 1974, each of which includes a portion of polysilicon layer 1970 and a portion of silicon oxide layer 1980 surrounded by sidewalls, wherein the sidewalls include adhesion layers 1960 and 1964 or adhesion layers 1966 and 1972 and optical isolation layer 1962 or 1966.

[0115] The above technology can also be used to form other optical isolation structures for optical isolation in photonic integrated circuits. Figure 7 The groove 710 shown in FIG. Figure 11The trenches 1110 shown in FIG can be filled with a thin optical isolation layer and a CTE matching material, wherein the trenches 1110 in the silicon substrate 610 and the trenches 710 in the BOX layer 620 and the oxide layer 630 can be misaligned and can be formed (e.g., etched) and filled separately. For example, the trenches 710 in the BOX layer 620 or the oxide layer 630 can be filled from the top of the oxide layer 630, while the trenches 1110 in the silicon substrate 610 can be filled from the bottom surface of the silicon substrate 610.

[0116] Figure 20 is a cross-sectional view of an example of a photonic integrated circuit 2000 including a deep trench in a substrate filled with a thin optical isolation layer and a CTE matching material, according to certain embodiments. Photonic integrated circuit 2000 can be fabricated from photonic integrated circuit 1100. For example, a thin adhesion layer 2010 can be deposited on exposed surfaces of silicon substrate 610 (including the inner surfaces of trench 1110 and the bottom surface of silicon substrate 610), and a thin optical isolation layer 2020 can be deposited on thin adhesion layer 2010. Adhesion layer 2010 can be similar to, for example, adhesion layers 1660, 1760, 1860, or 1960, and can include, for example, a titanium layer having a thickness of several nanometers (e.g., about 2 nm to about 10 nm). Optical isolation layer 2020 can be similar to, for example, optical isolation layers 1662, 1762, 1862, or 1962, and can include, for example, a metal nitride (e.g., TiN, TaN, ZrN, WN, or any combination thereof), and can have a thickness of about tens of nanometers (e.g., about 25 nm to about 60 nm). Adhesion layer 2010 and optical isolation layer 2020 can be deposited by, for example, ALD, CVD, PVD, etc. In some embodiments, another adhesion layer (similar to, for example, adhesion layer 1864 or 1964, Figure 20 (not shown). In some embodiments, a polysilicon layer 2030 may be deposited on the silicon substrate 610 and may fill the trench 1110. The polysilicon layer 2030 may be planarized by CMP to expose the optical isolation layer 2020 or the adhesion layer 2010, and the optical isolation layer 2020 or the adhesion layer 2010 may be removed by, for example, selective dry etching or wet etching.

[0117] In some embodiments, the trench may not be filled with a CTE matching material, and the optical isolation structure may include an air gap surrounded by a thin optical isolation layer and / or adhesive layer. This air gap allows the surrounding material to expand or contract without constraint, thereby helping to reduce thermally induced stress.

[0118] Figure 21 is a flowchart 2100 illustrating an example method for fabricating an optical isolation structure in a photonic integrated circuit according to certain embodiments. Figure 21Operations are described in a sequential flow, but some operations may be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may have additional steps not included in the diagram. Some operations are optional and therefore may be omitted in various embodiments. Some operations may be performed in conjunction with other operations.

[0119] At block 2105, a photonic integrated circuit may be obtained that includes a substrate, a dielectric layer on the substrate, and a photosensitive component in the dielectric layer. The photosensitive component may include a single-photon detector, such as a superconducting nanowire single-photon detector. The photonic integrated circuit may also include a waveguide connected to the photosensitive component and an input coupler or input port for the waveguide, such as a grating coupler.

[0120] At block 2110, a trench may be etched in at least one of the dielectric layer or the substrate adjacent to a photosensitive component or input port (or input coupler) for a waveguide. The trench may be drilled, dry etched, or wet etched. The trench may be in the substrate, the dielectric layer, or both.

[0121] At block 2115, a thin adhesion layer can be deposited on the exposed surfaces of the trench, including the sidewalls and bottom of the trench. The thickness of the thin adhesion layer can be less than 20 nm, for example, between about 2 nm and about 10 nm. The first adhesion layer can include, for example, a titanium layer. As described above, the thin adhesion layer can be deposited on the exposed surfaces of the trench by, for example, ALD, CVD, PVD, etc. The thin adhesion layer can help improve adhesion between the optical isolation material and the substrate or dielectric layer.

[0122] At block 2120, a thin optical isolation layer may be deposited on the thin adhesion layer by, for example, ALD, CVD, PVD, or the like as described above. The optical isolation layer may have a thickness greater than a certain value such that the two combined opposing sidewalls are optically opaque. The thickness may be less than 60 nm, for example, between about 25 nm and about 60 nm. The optical isolation layer may include, for example, a metal nitride, such as TiN, TaN, ZrN, WN, or the like. The total thickness of the two optical isolation layers on the two opposing sidewalls of the trench may be, for example, about 50 nm to about 120 nm. Thus, the two optical isolation layers, alone or in combination, may be optically opaque.

[0123] Optionally, at block 2125, a second adhesive layer can be deposited on the thin optical isolation layer. The second adhesive layer can have a thickness of less than 20 nm, for example, between about 2 nm and about 10 nm. As a thin adhesive layer, the second adhesive layer can include, for example, a titanium layer. The second adhesive layer can be deposited on the thin optical isolation layer by, for example, ALD, CVD, PVD, etc., as described above. The second adhesive layer can help improve adhesion between the optical isolation material and the filler material.

[0124] At block 2130, a first filler material layer may be deposited on the thin optical isolation layer. The first filler material layer may have a CTE that matches the CTE of the substrate or dielectric layer. The first filler material layer may include, for example, polysilicon. The first filler material layer may be deposited by, for example, CVD or PVD.

[0125] Optionally, at block 2135, the first filler material layer may be planarized, for example using CMP, which may expose the thin optical isolation layer and / or the second adhesion layer. The exposed thin optical isolation layer and / or one or more adhesion layers on the dielectric layer may be removed, for example, by selective wet etching.

[0126] Optionally, at block 2140, a portion of the first filler material layer can be etched using a wet etching or dry etching technique as described above. The wet etching can remove a portion of the first filler material in the trench until the top surface of the remaining first filler material is substantially aligned with the interface between the substrate and the dielectric layer. A dry etch, such as a plasma etch (such as RIE), can more precisely etch the first filler material so that the top surface of the remaining first filler material can be more precisely aligned with the interface between the substrate and the dielectric layer. The dry etch can also etch one or more adhesion layers and thin optical isolation layers.

[0127] Optionally, a third adhesion layer can be deposited on the exposed surface of the trench at block 2145. The third adhesion layer can help improve adhesion between the optical isolation material and the dielectric layer. The third adhesion layer can be similar to the thin adhesion layer described above and can be deposited using techniques similar to those used to deposit the thin adhesion layer described above.

[0128] Optionally, a second optical isolation layer can be deposited on the third adhesive layer at block 2150. The second optical isolation layer can be similar to the thin second optical isolation layer and can be deposited using techniques similar to those used to deposit the thin optical isolation layer described above.

[0129] Optionally, a fourth adhesive layer may be deposited on the second optical isolation layer at block 2155. The fourth adhesive layer may help improve adhesion between the second optical isolation material and the filler material. The fourth adhesive layer may be similar to the second adhesive layer described above and may be deposited using techniques similar to those used to deposit the second adhesive layer described above.

[0130] Optionally, at block 2160, a second filler material layer having a CTE matching the CTE of the dielectric layer may be deposited on the second optical isolation layer or the fourth adhesive layer. The second filler material layer may include, for example, silicon dioxide. The second filler material layer may be deposited by, for example, CVD or PVD.

[0131] Optionally, at block 2165, the second filler material layer may be planarized, for example using CMP, which may expose the second optical isolation layer and / or the fourth adhesive layer. The exposed second optical isolation layer and / or one or more adhesive layers on the dielectric layer may be removed, for example, by selective wet etching.

[0132] The highly sensitive photodetectors described above can be used to detect single photons in quantum computing or quantum encryption. For example, single-photon sources can be used in many photon quantum technologies. An ideal single-photon source will deterministically generate single photons. One method of achieving a deterministic single-photon source is to use a cascade (or multiplexed) heralded photon source (HPS) based on, for example, spontaneous four-wave mixing (SFWM) or spontaneous parametric down-conversion (SPDC) in a passive nonlinear optical medium. In each heralded photon source, photons (including signal photons and inert photons) are generated in pairs with uncertainty, where one photon (e.g., a signal photon) predicts the existence of the other photon in the pair (e.g., an inert photon). Therefore, if a signal photon is detected by a highly sensitive photodetector (e.g., a single photon detector as described above) at one prediction photon source, the corresponding inert photon can be used as the output of the single photon source, while other prediction photon sources in the cascade (or multiplexed) prediction photon source of the single photon source can be bypassed or turned off.

[0133] It will be appreciated by those skilled in the art that substantial variations may be made depending on the specific implementation. For example, customized hardware may be used, and / or specific elements may be implemented in hardware, software (including portable software, such as applets), or both. Furthermore, connections to other computing devices, such as network input / output devices, may be employed.

[0134] With reference to the accompanying drawings, the components that may include memory may include non-transient machine-readable media. The terms "machine-readable medium" and "computer-readable medium" used herein refer to any storage medium that participates in providing data that causes a machine to operate in a specific manner. In the embodiments provided above, various machine-readable media may be related to providing instructions / codes for execution to a processor and / or other one or more devices. Additionally or alternatively, machine-readable media can be used to store and / or carry such instructions / codes. In many embodiments, computer-readable media is a physical and / or tangible storage medium. Such media can take a variety of forms, including but not limited to non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example: magnetic and / or optical media, punch cards, paper tape, any other physical media with a pattern of holes, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), FLASH-EPROM, any other memory chip or tape, a carrier wave as described below, or any other medium from which a computer can read instructions and / or code.

[0135] The methods, systems, and devices discussed herein are exemplary. Various embodiments may appropriately omit, substitute, or add various processes or components. For example, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. The various components shown in the figures provided herein may be implemented in hardware and / or software. Furthermore, technological advancements and many elements are examples that do not limit the scope of the disclosure to these specific examples.

[0136] Sometimes, for convenience, primarily for reasons of common usage, signals are referred to as bits, information, values, elements, symbols, characters, variables, terms, serial numbers, numbers, etc. However, it will be understood that all of these or similar terms will be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise specifically stated, as will be apparent from the above discussion, it will be understood that terms such as "process," "estimate," "calculate," "determine," "ascertain," "identify," "correlate," "measure," "perform," etc., used throughout this specification, refer to the actions or processes of a specific apparatus (e.g., a specific purpose computer or similar specific purpose electronic computing device). Thus, in the context of this specification, a specific purpose computer or similar specific purpose electronic computing device is capable of manipulating or converting signals, which are typically represented as physical electronic, electrical, or magnetic quantities in a memory, register, or other information storage device, transmission device, or display device of the specific purpose computer or similar specific purpose electronic computing device.

[0137] Those skilled in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals used to convey the messages described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0138] As used herein, the terms "and", "or" and " / or" may include and are intended to include a variety of meanings that depend, at least in part, on the context in which the terms are used. Typically, "or", if used in conjunction with a list of items (e.g., A, B, or C), means A, B, and C (used herein in an inclusive sense) as well as A, B, or C (used herein in an exclusive sense). In addition, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. In addition, the term "at least one", if used in conjunction with a list of items (e.g., A, B, or C), may be interpreted to refer to any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0139] References throughout this specification to "one example," "an example," "a specific example," or "an exemplary embodiment" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Thus, appearances of the phrases "in one example," "in an example," "in some examples," "in some embodiments," or other similar phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and / or limitation. Furthermore, particular features, structures, or characteristics may be combined in one or more examples and / or features.

[0140] In some embodiments, operation or processing can involve the physical operation of physical quantity. Typically, although not necessarily, these quantities can take the form of electrical or magnetic signals that can be stored, transferred, combined, compared or otherwise manipulated. Sometimes for convenience, mainly for the reason of common use, the signal is referred to as a bit, information, value, element, symbol, character, variable, term, sequence number, number, etc. However, it should be understood that all of these or similar terms will be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise specifically stated, as will be apparent from the above discussion, it should be understood that terms such as "processing", "estimation", "calculation", "determination" used in the discussion of the entire specification refer to the action or process of a specific device (such as a specific purpose computer, a specific purpose computing device, or a similar specific purpose electronic computing device). Therefore, in the context of the present specification, a specific purpose computer or a similar specific purpose electronic computing device can manipulate or convert a signal, which is generally represented as a physical electronic quantity, electrical quantity or magnetic quantity in a memory, register or other information storage device, transmission device or display device of a specific purpose computer or a similar specific purpose electronic computing device.

[0141] In the foregoing detailed description, numerous specific details are set forth to provide a comprehensive understanding of the claimed subject matter. However, those skilled in the art will appreciate that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Accordingly, the claimed subject matter is not limited to the specific examples disclosed, but rather, the claimed subject matter may encompass all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A photonic integrated circuit device, comprising: substrate; a dielectric layer on the substrate; a waveguide within the dielectric layer; a photosensitive component in the dielectric layer and coupled to the waveguide; and a plurality of light isolation structures in the substrate and the dielectric layer and adjacent to the photosensitive component, the plurality of light isolation structures being configured to reflect or absorb stray light to prevent the stray light from reaching the photosensitive component; and The plurality of optical isolation structures include: a first optical isolation structure in the substrate and a second optical isolation structure in the dielectric layer; The filler material in the first light isolation structure is characterized by a thermal expansion coefficient that matches the thermal expansion coefficient of the substrate; The thermal expansion coefficient of the filling material in the second light isolation structure matches the thermal expansion coefficient of the dielectric layer; and The first light isolation structure is aligned with or offset from the second light isolation structure.

2. The device according to claim 1, wherein The plurality of optical isolation structures include at least one of the following: a metal trench in the dielectric layer; an array of metal vias in the dielectric layer; a metal cover in the dielectric layer and on top of the photosensitive component; or A deep trench in the substrate, the deep trench including an air gap or filled with a light reflective or light absorbing material.

3. The device according to claim 2, wherein The metal cover is in a metal layer and is aligned with or coupled to the metal trenches or the metal via array to form a continuous structure surrounding the photosensitive component.

4. The device according to claim 2, wherein The waveguide includes an input port; and The metal trench or the metal via array is located at a region including the input port.

5. The device according to claim 1, wherein The photosensitive component includes a single photon detector.

6. The device according to claim 5, wherein The single-photon detector comprises a superconducting nanowire single-photon detector.

7. The device according to claim 1, wherein The dielectric layer includes an oxide layer.

8. The device according to claim 1, wherein The optical isolation structure of the plurality of optical isolation structures comprises: two opposing sidewalls, each sidewall comprising an optical isolation layer; and A fill material between the two opposing sidewalls has a thermal expansion coefficient that matches a thermal expansion coefficient of at least one of the substrate or the dielectric layer.

9. The device according to claim 8, wherein The optical isolation layer is characterized by a thickness greater than a value such that the two opposing sidewalls combined are optically opaque.

10. The device according to claim 9, wherein The thickness is less than 60 nm.

11. The device according to claim 8, wherein The optical isolation layer includes metal nitride.

12. The device according to claim 11, wherein The metal nitride includes TiN, TaN, ZrN or WN.

13. The device according to claim 8, wherein The filling material includes polysilicon or silicon dioxide.

14. The device according to claim 8, wherein Each of the two opposing sidewalls further includes a first adhesive layer between the optical isolation layer and at least one of the dielectric layer or the substrate.

15. The device according to claim 14, wherein The first adhesion layer is characterized by a thickness of less than 20 nm.

16. The device according to claim 14, wherein The first adhesion layer includes a titanium layer.

17. The device according to claim 14, wherein Each of the two opposing sidewalls further includes a second adhesive layer between the optical isolation layer and the filling material.

18. The device according to claim 17, wherein The second adhesion layer is characterized by a thickness of less than 20 nm.

19. The device according to claim 17, wherein The second adhesion layer includes a titanium layer.

20. The device of claim 8, further comprising an unfilled trench in the substrate or the dielectric layer, wherein The sidewalls of the unfilled trench are optically opaque.

21. A method for manufacturing a photonic integrated circuit, comprising: receiving a photonic integrated circuit comprising a substrate, a dielectric layer on the substrate, and a photosensitive component in the dielectric layer; etching a trench in the substrate, the trench being adjacent to the photosensitive component; depositing a thin adhesion layer on the exposed surface of the trench; depositing a thin optical isolation layer on the thin adhesive layer; depositing a first filler material layer on the thin optical isolation layer, the first filler material layer filling the trench and characterized by a coefficient of thermal expansion that matches the coefficient of thermal expansion of the substrate; etching a portion of the first filling material layer filling the trench so that a top surface of the first filling material layer remaining in the trench is aligned with an interface between the substrate and the dielectric layer; A second fill material layer is deposited in the trench, the second fill material layer being characterized by a coefficient of thermal expansion that matches the coefficient of thermal expansion of the dielectric layer.

22. The method according to claim 21, further comprising: Before depositing the first filling material layer, a second adhesive layer is deposited on the thin optical isolation layer.

23. The method of claim 21, further comprising: The first filling material layer is planarized.

24. The method according to claim 23, further comprising: The second filling material layer is planarized.

25. The method according to claim 24, wherein Etching the portion of the first filling material layer includes: etching the first filling material layer, the thin adhesive layer, and the thin optical isolation layer using a dry etching process; and The method further comprises, before depositing the second filling material layer: depositing a second adhesion layer on the exposed surface of the trench; and A second optical isolation layer is deposited on the second adhesive layer.

Images