Data driving device and method for driving the data driving device

Abstract

The present invention relates to a data driving device and a method of driving the data driving device, and more particularly, to a data driving device and a method of driving the data driving device for automatically tuning a setting value of an internal circuit.

Description

Technical Field

[0001] The present invention relates to a technique for driving a data driven device. Background Art

[0002] Generally, a display panel of a display device includes a plurality of pixels arranged in a matrix, and each pixel includes sub-pixels such as a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, etc. Each sub-pixel emits light according to a grayscale included in image data, so that an image is displayed in the display panel.

[0003] The display device may include a data processing device called a timing controller and a data driving device called a source driver. Image data may be sent from the data processing device to the data driving device. The image data is sent in the form of a digital signal, and the data driving device converts the image data in the form of a digital signal into an analog voltage to drive each pixel.

[0004] Thus, in order to drive the display panel, the data processing device and the data driving device must communicate with each other. Generally, the frequency for communication between the data processing device and the data driving device is predetermined according to the type of the display device.

[0005] In other words, the frequency for communication of the data processing device may be determined differently according to the type of display device, and the communication circuit of the data driving device connected to the data processing device through the communication line must be tuned according to the frequency for communication of the data processing device.

[0006] Typically, tuning of the data driving device according to the frequency used for communication of the data processing device is performed manually.

[0007] Recently, as the specifications of display devices change more frequently for image quality improvement, etc., the frequency of communication of a data processing device for driving the display device may change frequently. Manual tuning of the data driving device may result in an increase in the time and manpower required for tuning. Summary of the invention

[0008] Against this background, one aspect of the present invention provides a technique for automatically tuning a data driving device in a display device.

[0009] To this end, on one hand, the present invention provides a data driving device, comprising: a clock recovery circuit for performing clock training using a communication signal received during multiple time intervals; and a control circuit for changing the setting value of a circuit in the clock recovery circuit that is affected by the frequency of the communication signal in each time interval, checking the result of the clock training in the clock recovery circuit according to the change of the setting value in each time interval, and determining the optimal value for the setting value.

[0010] The circuit affected by the frequency of the communication signal may include an oscillator, which is a current controlled oscillator or a voltage controlled oscillator.

[0011] The set value may include a value of a reference current input to the current controlled oscillator or a value of a reference voltage input to the voltage controlled oscillator.

[0012] The setting value may include a gain adjustment value for adjusting a gain of the oscillator.

[0013] The frequency of the communication signal can be set within a predetermined range, the control circuit can gradually increase the set value in each time interval and send the set value to the clock recovery circuit, and then the clock recovery circuit can increase the oscillation frequency of the oscillator in each time interval according to the set value, wherein the oscillation frequency in the first time interval of the multiple time intervals can belong to the lowest frequency range within the predetermined range and the oscillation frequency in the last time interval can belong to the highest frequency range within the predetermined range.

[0014] The frequency of the communication signal can be set within a predetermined range, the control circuit can gradually reduce the set value in each time interval and send the set value to the clock recovery circuit, and then the clock recovery circuit can reduce the oscillation frequency of the oscillator in each time interval according to the set value, wherein the oscillation frequency in the first time interval of the multiple time intervals can belong to the highest frequency range within the predetermined range and the oscillation frequency in the last time interval can belong to the lowest frequency range within the predetermined range.

[0015] The setting value may further include a value of a driving current supplied to the oscillator, and when the gain adjustment value is increased or decreased in each time interval, the control circuit may increase or decrease the value of the driving current according to the gain adjustment value.

[0016] The control circuit may receive a lock signal for clock training from the clock recovery circuit during the plurality of time intervals, and check a result of the clock training in each time interval using the lock signal.

[0017] In a case where the lock signal received in one of the plurality of time intervals has a first level and the lock signal received in the other time intervals has a second level, the control circuit may determine the setting value corresponding to the one time interval as an optimal value.

[0018] When the locking signals received in at least two consecutive time intervals among the multiple time intervals have a first level and the locking signals received in other time intervals have a second level, the control circuit can determine the intermediate value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

[0019] The data driving device may further include a receiving circuit configured to receive the clock recovered by clock training from the clock recovery circuit, and to recover data from the communication signal according to the recovered clock to output the data.

[0020] The control circuit may receive data output from the receiving circuit during the plurality of time intervals and check a result of clock training in each time interval using the data.

[0021] In a case where data output in one of the plurality of time intervals has regular changes and data output in other time intervals has irregular changes, the control circuit may determine a setting value corresponding to the one time interval as an optimal value.

[0022] When the data output in at least two consecutive time intervals among the multiple time intervals have regular changes and the data output in other time intervals have irregular changes, the control circuit can determine the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

[0023] On the other hand, the present invention provides a method for driving a data driving device, comprising: receiving a communication signal having a frequency within a predetermined range during multiple time intervals; training a clock included in the communication signal by changing a setting value of an internal circuit affected by the frequency of the communication signal in each time interval; and determining an optimal value of the setting value based on a result of the clock training.

[0024] When training the clock, the internal circuit may include a current-controlled oscillator or a voltage-controlled oscillator, the set value may include the value of a reference current input to the current-controlled oscillator or the value of a reference voltage input to the voltage-controlled oscillator, and the data driving device may gradually increase or decrease the value of the reference current or the value of the reference voltage in each time interval.

[0025] When training the clock, the internal circuit may include a current-controlled oscillator or a voltage-controlled oscillator, the setting value may include a gain adjustment value for adjusting the gain of the current-controlled oscillator or the voltage-controlled oscillator, and the data driving device may gradually increase or decrease the gain adjustment value in each time interval.

[0026] When determining the optimal value, when the locking signal output in one of the multiple time intervals has a first level and the locking signal output in the other time intervals has a second level, the data driving device can determine the setting value corresponding to the one time interval as the optimal value.

[0027] When determining the optimal value, when the locking signal output in at least two consecutive time intervals among the multiple time intervals has a first level and the locking signal output in other time intervals has a second level, the data driving device can determine the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

[0028] When determining the optimal value, the data driving device can recover data from the communication signal based on the clock recovered through clock training, and when the data recovered in one time interval of the multiple time intervals has regular changes and the data recovered in other time intervals has irregular changes, the data driving device can determine the setting value corresponding to the one time interval as the optimal value.

[0029] When determining the optimal value, the data driving device can recover data from the communication signal based on the clock recovered through clock training, and when the data recovered in at least two consecutive time intervals has regular changes and the data recovered in other time intervals has irregular changes, the data driving device can determine the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

[0030] As described above, according to the present invention, the data driving device can automatically tune the setting value of the internal circuit according to the communication frequency of the data processing device, and thus, the time and manpower required for tuning can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a structural diagram of a display device according to an embodiment;

[0033] Figure 2is a block diagram of a system according to an embodiment;

[0034] Figure 3 is a diagram showing a sequence of signals between a data processing device and a data driving device according to an embodiment;

[0035] Figure 4 is a structural diagram of a data driving device according to an embodiment;

[0036] Figure 5 and Figure 6 is a structural diagram of a clock recovery circuit according to an embodiment;

[0037] Figure 7 and Figures 8A to 8C is a diagram showing optimization of setting values ​​of a clock recovery circuit in a data driving device according to an embodiment;

[0038] Fig. 9 is a diagram illustrating determination of an optimum value for a setting value according to an embodiment; and

[0039] Fig.10 is a flowchart illustrating a process of determining an optimal value regarding a setting value in a data driving device according to an embodiment. DETAILED DESCRIPTION

[0040] Figure 1 is a structural diagram of a display device according to an embodiment.

[0041] refer to Figure 1 The display device 100 may include a display panel 110 , a data driving device 120 , a gate driving device 130 , and a data processing device 140 .

[0042] On the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of pixels P may also be arranged. The pixel P may include a plurality of sub-pixels. Here, the sub-pixel may be a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, or a white (W) sub-pixel. The pixel may include an RGB sub-pixel SP, an RGBG sub-pixel SP, or an RGBW sub-pixel SP. Hereinafter, for ease of description, it will be assumed that the pixel P includes an RGB sub-pixel for description.

[0043] The data driving device 120 , the gate driving device 130 , and the data processing device 140 are used to generate signals for displaying an image on the display panel 110 .

[0044] The gate driving device 130 may supply a gate driving signal, such as a turn-on voltage or a turn-off voltage, through the gate line GL. When the gate driving signal of the turn-on voltage is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. When the gate driving signal of the turn-off voltage is supplied to the sub-pixel SP, the sub-pixel SP is disconnected from the data line DL. The gate driving device 130 may be referred to as a gate driver.

[0045] The data driving device 120 can drive the data voltage V p The data voltage V supplied through the data line can be supplied to the sub-pixel SP according to the gate driving signal. p The data driving device 120 may be referred to as a source driver.

[0046] The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type, directly formed on the display panel 110, or integrated on the display panel 110 as the case may be. In addition, the data driving device 120 may be formed in a chip on film (COG) type.

[0047] The data processing device 140 may supply control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS to the gate driving device 130 to start scanning, output image data to the data driving device 120, and send a data control signal DCS to control the data driving device 120 to increase the data voltage V p The data processing device 140 may be referred to as a timing controller.

[0048] Figure 2 is a structural diagram of a system according to an embodiment.

[0049] refer to Figure 2 The system may include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c and 120d.

[0050] The data processing device 140 may be disposed on the first printed circuit board PCB1. The data processing device 140 may be connected to the plurality of data driving devices 120a, 120b, 120c, and 120d through the first and second communication lines LN1 and LN2.

[0051] The first communication line LN1 and the second communication line LN2 may reach the plurality of data driving devices 120a, 120b, 120c, and 120d via the first PCB PCB1 and the second PCB PCB2. The first PCB PCB1 and the second PCB PCB2 may be connected to a first film FL1 made of a flexible material. The first communication line LN1 and the second communication line LN2 may extend from the first PCB PCB1 to the second PCB PCB2 via such a first film FL1.

[0052] The respective data driving devices 120a, 120b, 120c, and 120d may be arranged on the second film FL2 in the form of a COF. The second film FL2 may be a support substrate made of a flexible material connecting the second PCB PCB2 and the display panel 110. The first communication line LN1 and the second communication line LN2 may extend from the second PCB PCB2 to the respective data driving devices 120a, 120b, 120c, and 120d via the second film FL2.

[0053] The first communication line LN1 may be connected one-to-one between the data processing device 140 and the data driving devices 120 a , 120 b , 120 c , and 120 d .

[0054] The second communication line LN2 may be connected between the respective data driving devices 120a, 120b, 120c, and 120d, or between the data driving device 120d and the data processing device 140, so that the second communication line LN2 does not overlap with the first communication line LN1 in a plan view. For example, the first data driving device 120a may be connected to the second data driving device 120b through the second communication line LN2, and the second data driving device 120b may be connected to the third data driving device 120c through the second communication line LN2. Here, the second data driving device 120b and the third data driving device 120c may be connected to different second PCBs PCB2, respectively. Therefore, the second communication line LN2 arranged therebetween may connect the second data driving device 120b and the third data driving device 120c via the second PCB PCB2, the first film FL1, the first PCB PCB1, another first film FL1, and another second PCB PCB2. The third data driving device 120 c may be connected to the fourth data driving device 120 d through the second communication line LN2 , and the fourth data driving device 120 d may be connected to the data processing device 140 through the second communication line LN2 .

[0055] As described above, the data processing device 140 and the data driving devices 120 a , 120 b , 120 c , and 120 d may communicate with each other through the first communication line LN1 and the second communication line LN2 .

[0056] Here, the frequency for communication between the data processing device 140 and the data driving devices 120a, 120b, 120c, and 120d may not be predetermined.

[0057] In other words, the communication circuits of the data driving devices 120 a , 120 b , 120 c , and 120 d may not be tuned in unison with the frequency used for communications of the data processing device 140 .

[0058] According to an embodiment, the process to be described below may be performed so that the data driving devices 120a, 120b, 120c, and 120d adjust the setting value of the internal circuit according to the communication frequency of the data processing device 140. Here, the communication frequency may be referred to as a communication clock frequency, and the internal circuit of the data driving devices 120a, 120b, 120c, and 120d may be a circuit whose characteristics change according to the communication frequency.

[0059] Figure 3 is a diagram showing a sequence of signals between a data processing device and a data driving device according to an embodiment.

[0060] refer to Figure 3 When the driving voltage VCC is supplied to the data processing device 140 and the data driving device 120, the data processing device 140 may Figure 3 The data processing device 140 may send the first protocol PS1 after sending the second protocol PS2. The first protocol PS1 and the second protocol PS2 may be connected by Figure 2 It is sent via the first communication line LN1.

[0061] Here, the second protocol PS2 as a rule system established between the data processing device 140 and the data driving device 120 may be a low-speed data communication protocol.

[0062] The first protocol PS1 as an algorithm system established between the data processing device 140 and the data driving device 120 may be a high-speed data communication protocol.

[0063] The communication frequency of the first protocol PS1 can be higher than (10 times) the communication frequency of the second protocol PS2. Under such characteristics, the first protocol PS1 can be classified as a high-speed data communication protocol, and the second protocol PS2 can be classified as a low-speed data communication protocol. In order to distinguish between the communication frequency of the first protocol PS1 and the communication frequency of the second protocol PS2, hereinafter, the communication frequency of the first protocol PS1 will be referred to as the first communication frequency, and the communication frequency of the second protocol PS2 will be referred to as the second communication frequency. In high-speed data communication, according to the setting of the receiving circuit, the data loss rate may be greatly different, or the communication may not be smooth. For this reason, in the display device 100 according to the embodiment, the sending circuit can send the setting data to the receiving circuit before the high-speed data communication for smooth high-speed data communication is performed. Here, the setting data can be sent or received by low-speed data communication. Since the data loss rate will not be greatly different according to the setting of the receiving circuit in low-speed data communication, the setting value can be sent to the receiving circuit relatively correctly.

[0064] The data processing device 140 can transmit the setting data required for high-speed data communication by transmitting the second protocol PS2 associated with low-speed data communication before transmitting the first protocol PS1 associated with high-speed data communication.

[0065] The second protocol PS2 may include a preamble interval, a CFG data interval, and a CFG done interval.

[0066] In the preamble section, the second protocol PS2 may include a low-speed data communication clock signal. The data driver 120 may train a clock using the low-speed data communication clock signal and receive low-speed data using the trained clock.

[0067] In the CFG data interval, the second protocol PS2 may include low-speed data. The data driver 120 may receive low-speed data using a trained clock (low-speed data communication clock). The low-speed data may include clock data for high-speed data communication of the data driver 120, that is, a gain setting value of an equalizer, scrambling information, line polarity information, etc. The data driver 120 may use the setting data to set a circuit for high-speed data communication. Here, the scrambling information may include information related to whether the data is scrambled when the data processing device 140 sends data to the data driver 120, and the line polarity information may include information indicating the polarity of the first line of pixels.

[0068] In the CFG completion section, the second protocol PS2 may include a message indicating the end of communication. The data driving device 120 may terminate the communication according to the second protocol PS2 by checking the message.

[0069] The auxiliary communication signal ALP may initially maintain a low level and change to a high level when the training of the low-speed data communication clock is completed. When the driving voltage is supplied to the data driving device 120, the data driving device 120 may maintain the auxiliary communication signal ALP at a low level, and then change the auxiliary communication signal ALP to a high level when the training of the low-speed data communication clock is completed in the leading interval. After the level of the auxiliary communication signal ALP has been changed to high, the data processing device 140 may send low-speed data using the second protocol PS2. Here, the auxiliary communication signal ALP may be referred to as a locking signal LOCK and is transmitted through Figure 2 The second communication line LN2 in is sent to the data processing device 140.

[0070] In the case where there is an abnormality in the internal state or an unexpected communication error occurs after the level of the auxiliary communication signal ALP is changed to high, the data driving device 120 may change the level of the auxiliary communication signal ALP to low. For example, in the case where low-speed data cannot be received or the clock crashes in the CFG data interval or the CFG completion interval, the data driving device 120 may change the level of the auxiliary communication signal ALP to low.

[0071] In an embodiment, the second communication frequency, ie, the frequency for low-speed data communication may be a predetermined frequency.

[0072] In other words, the second communication frequency may be a frequency commonly used in the display device 100 regardless of the specification of the display device 100. The data driving device 120 may set an internal circuit in accordance with the predetermined second communication frequency to perform low-speed data communication with the data processing device 140.

[0073] On the other hand, the first communication frequency, ie, the frequency for high-speed data communication is not predetermined. Therefore, the data processing device 140 and the data driving device 120 may further include a pre-clock training interval in the first protocol PS1 to set the internal circuits in accordance with the first communication frequency.

[0074] Specifically, in the pre-clock training section, the data processing device 140 may send the first protocol PS1 including the training clock pattern TR_CLK to the data driving device 120. Hereinafter, the signal of the first protocol PS1 sent to the data driving device 120 in the pre-clock training section will be referred to as a communication signal.

[0075] The data driving device 120 may divide the pre-clock training section into a plurality of time sections, and train the clock in accordance with the training clock pattern TR_CLK included in the communication signal by changing the setting value of the internal circuit in each time section.

[0076] The data driving device 120 may determine an optimal setting value according to a result of training consistent with the training clock pattern TR_CLK, and set an internal circuit using the optimal setting value.

[0077] A detailed description of this is as follows.

[0078] Figure 4 is a structural diagram of a data driving device according to an embodiment.

[0079] refer to Figure 4 , the data driving device 120 may include a clock recovery circuit (CDR) 410 , a control circuit 420 , and a receiving circuit 430 .

[0080] The clock recovery circuit 410 can perform clock training using the communication signal received during the multiple time intervals. Here, the communication signal can have a frequency within a predetermined frequency range. In other words, the frequency of the communication signal can be a first communication frequency included in the frequency range of high-speed data communication. The frequency range of high-speed data communication can be divided into N (N is a natural number equal to or greater than 1) ranges.

[0081] Clock recovery circuit 410 may include circuitry that is affected by the frequency of the communication signal. The circuitry may include Figure 5 An oscillator 520 is shown. The oscillator 520 may be a current controlled oscillator (CCO) or a voltage controlled oscillator (VCO).

[0082] The setting value CTR (described in detail below) sent by the control circuit 420 to the clock recovery circuit 410 in each time interval may include a reference current value input to a current controlled oscillator or a reference voltage value input to a voltage controlled oscillator.

[0083] The setting value CTR may include a gain adjustment value for the oscillator.

[0084] The clock recovery circuit 410 may receive a setting value CTR that is gradually increased in each time interval from the control circuit 420. In this case, the clock recovery circuit 410 may increase the oscillation frequency of the oscillator 520 in each time interval according to the setting value CTR. Here, the oscillation frequency in the first time interval among the multiple time intervals may be included in the lowest frequency range in the predetermined frequency range, and the oscillation frequency in the last time interval may be included in the highest frequency range in the predetermined frequency range. In other words, the reference current and the oscillation frequency, the reference voltage and the oscillation frequency, or the gain and the oscillation frequency of the oscillator may be proportional to each other.

[0085] For example, when the clock recovery circuit 410 receives Figure 7As shown in the case where the voltage values ​​V1→V2→V3→V4 gradually increase in each time interval, the reference frequency in the first time interval can be included in the first range f1~f2 (i.e., the lowest frequency range within the predetermined frequency range f1~f5), and the reference frequency in the last time interval can be included in the fourth range f4~f5 (i.e., the highest frequency range within the predetermined frequency range f1~f5).

[0086] On the other hand, the clock recovery circuit 410 may receive the setting value CTR that is gradually reduced in each time interval from the control circuit 420. In this case, the clock recovery circuit 410 may reduce the oscillation frequency of the oscillator 520 in each time interval according to the setting value CTR. Here, the oscillation frequency in the first time interval among the plurality of time intervals may be included in the highest frequency range f4 to f5 in the predetermined frequency range, and the oscillation frequency in the last time interval may be included in the lowest frequency range f1 to f2 in the predetermined frequency range.

[0087] According to an embodiment, the setting value CTR may also include a value of a driving current supplied to the oscillator 520. In the case where the driving current value is included in the setting value CTR, the clock recovery circuit 410 may receive a current value or a voltage value that gradually increases in each time interval together with the driving current value, or may receive a current value or a voltage value that gradually decreases in each time interval together with the driving current value from the control circuit 420.

[0088] The clock recovery circuit 410 may also receive from the control circuit 420 a gain adjustment value that gradually increases in each time interval together with the driving current value, or receive a gain adjustment value that gradually decreases in each time interval together with the driving current value.

[0089] For example, in the case where the driving current of the oscillator 520 is the first reference current or the first reference voltage, since Fig. 8A The actual waveform of the oscillator 520 is shown ( Fig. 8A The dotted line in the figure shows the increase time t R and reduce time t F can be adjusted to an ideal waveform with the first oscillation frequency ( Fig. 8A The increase time and decrease time of the solid line in the figure are consistent, so the waveform output from the oscillator 520 can be formed in a normal state. When the first reference current or the first reference voltage increases to the second reference current or the second reference voltage under the condition of a fixed driving current, due to Figure 8B The actual waveform of the second reference frequency (which is higher than the first reference frequency) is shown ( Figure 8B The increase and decrease time of the second reference frequency waveform ( Figure 8BThe increase time and decrease time of the oscillator 520 are shown in FIG. 5 , and thus the waveform output from the oscillator 520 may be formed in an abnormal state.

[0090] Here, if the driving current increases according to the increase of the reference current, the reference voltage or the gain, then Figure 8C The actual waveform shown ( Figure 8C The increase time and decrease time of the dotted line in the figure can be shortened.

[0091] As described above, since the value of the driving current may affect the output of the oscillator 520 , the value of the driving current may also be included in the setting value CTR.

[0092] On the other hand, the clock recovery circuit 410 may receive different setting values ​​CTR from the control circuit 420 in each time interval.

[0093] The setting of the circuit can be changed according to different setting values ​​CTR in each time interval, and clock training for the communication signal can be performed according to the changed setting. Here, the communication signal can include a training clock pattern TR_CLK.

[0094] In other words, the clock recovery circuit 410 can receive different setting values ​​of the oscillator 520 affected by the frequency of the communication signal in each time interval, change the oscillation frequency of the oscillator 520 according to the setting value CTR received in the time interval (which is different from the setting value CTR received in other time intervals), and perform clock training in accordance with the changed oscillation frequency and the training clock pattern TR_CLK. Here, in the case where the setting value CTR includes the value of the drive current, the clock recovery circuit 410 can change the drive current together with the oscillation frequency of the oscillator 520.

[0095] The clock recovery circuit 410 can generate an auxiliary communication signal ALP (ie, a lock signal LOCK indicating the clock training result in each time interval) and send it to the control circuit 420. The clock recovery circuit 410 can also send the lock signal LOCK to the data processing device 140 through the second communication line.

[0096] The clock recovery circuit 410 may change the level of the lock signal LOCK according to the clock training result in each time interval, and output the lock signal LOCK.

[0097] For example, in the case where the pre-clock training interval is divided into four time intervals, if the clock recovery circuit 410 completes the clock training in the first time interval and does not complete the clock training in the other three time intervals, the clock recovery circuit 410 may output a lock signal LOCK of a first level in the first time interval, and output a lock signal LOCK of a second level changed from the first level in the other three time intervals. Here, the first level may be high, and the second level may be low.

[0098] The clock recovery circuit 410 may recover the training clock pattern TR_CLK included in the communication signal through clock training, and transmit the recovered clock to the receiving circuit 430 to be described below.

[0099] When the pre-clock training interval, which may be divided into a plurality of time intervals, starts, the control circuit 420 may send different setting values ​​CTR to the clock recovery circuit 410 in each time interval.

[0100] In other words, when the pre-clock training interval starts, the control circuit 420 may send different setting values ​​CTR to the clock recovery circuit 410 at the start time points of each time interval.

[0101] The control circuit 420 may receive a message indicating the end of the low-speed data communication from the data processing device 140 in the CFG completion interval before the pre-clock training interval, and terminate the low-speed data communication, i.e., the communication based on the second protocol PS2, by checking the message. Subsequently, the control circuit 420 may start the high-speed data communication, i.e., the communication based on the first protocol PS1, so that the pre-clock training interval begins.

[0102] According to an embodiment, the control circuit 420 may store time interval information for dividing the pre-clock training interval into a plurality of time intervals and time information for the pre-clock training interval. In addition, the control circuit 420 may store a number of setting values ​​CTR corresponding to the number of the plurality of time intervals.

[0103] The control circuit 420 may send the setting value CTR that gradually increases or decreases in each time interval to the clock recovery circuit 410 .

[0104] For example, when the setting value CTR includes the value of the reference voltage and the control circuit 420 stores the voltage values ​​V1, V2, V3 and V4 in sequence from the lowest voltage value V1 according to their sizes, in the first time interval starting from the pre-clock training interval, the control circuit 420 can send the lowest voltage value V1 to the clock recovery circuit 410, and then send the increasing voltage values ​​V2→V3→V4 in each time interval to the clock recovery circuit 410 in sequence.

[0105] Otherwise, the control circuit 420 may send the highest voltage value V4 to the clock recovery circuit 410, and then sequentially send the voltage values ​​V3→V2→V1 that decrease in each time interval to the clock recovery circuit 410. In the case where the setting value CTR also includes the value of the driving current of the oscillator 520, the control circuit 420 may also increase or decrease the value of the driving current and send the value of the driving current to the clock recovery circuit 410 when the current value, voltage value, or gain adjustment value is increased or decreased in each time interval.

[0106] After sending the changed setting value CTR in each time interval to the clock recovery circuit 410, the control circuit 420 may receive a lock signal LOCK related to clock training from the clock recovery circuit 410 and check the result of the clock training in each time interval using the lock signal LOCK.

[0107] If the lock signal LOCK received in one of the multiple time intervals has a first level and the lock signal LOCK received in the other time intervals has a second level, the control circuit 420 may determine the setting value CTR corresponding to the one time interval as an optimal value. Subsequently, the control circuit 420 may set the circuit of the clock recovery circuit 410 using the setting value CTR corresponding to the one time interval.

[0108] In other words, the control circuit 420 may set a reference current or a reference voltage of the oscillator 520 included in the clock recovery circuit 410 , and may also set a driving current of the oscillator 520 using a setting value CTR corresponding to one time interval.

[0109] For example, if the number of time intervals is 4, Figure 7 When the setting values ​​CTR corresponding to the respective time intervals are V1, V2, V3 and V4, and the locking signal LOCK received by the control circuit 420 in the third time interval has a first level, and the locking signal LOCK received by the control circuit 420 in other time intervals has a second level, the control circuit 420 can use V3 (which is the setting value corresponding to the third time interval) to set the reference voltage of the oscillator 520.

[0110] On the other hand, when the lock signal LOCK received in at least two consecutive time intervals has a first level and the lock signal LOCK received in other time intervals has a second level, the control circuit 420 can determine the middle value of at least two setting values ​​CTR corresponding to the at least two time intervals as the optimal value.

[0111] Then, the control circuit 420 may use the intermediate value to set the circuit of the clock recovery circuit 410. Here, the first level may be high and the second level may be low.

[0112] For example, when the lock signal LOCK received by the control circuit 420 in the second time interval and the third time interval has a first level, and the lock signal LOCK received by the control circuit 420 in other time intervals has a second level, the control circuit 420 can use the middle value Vm of the setting values ​​V2 and V3 corresponding to the second time interval and the third time interval to set the reference voltage of the oscillator 520.

[0113] When receiving the clock recovered through clock training from the clock recovery circuit 410 , the receiving circuit 430 may recover data from the communication signal according to the recovered clock and output the data.

[0114] Here, if Figure 3 As shown, the communication signal may include a training clock pattern TR_CLK with regular changes. When clock training is completed in the clock recovery circuit 410, the receiving circuit 430 may recover data in a normal state from the communication signal according to a normal clock and output the data. In this case, the data output from the receiving circuit 430 may also have regular changes.

[0115] For example, in the receiving circuit 430, according to Figure 3 When the training clock pattern TR_CLK shown in the figure restores data in a normal state, the receiving circuit 430 can output data in which “0” and “1” appear alternately (for example, 0101010 . . . ).

[0116] However, in the case where clock training is not completed in the clock recovery circuit 410, the receiving circuit 430 may recover data in an abnormal state from the communication signal according to the abnormal clock and output the data. In this case, the data output from the receiving circuit 430 may have irregular changes.

[0117] For example, in the receiving circuit 430, according to Figure 3 In the case where the training clock pattern TR_CLK shown recovers data but the recovery is abnormal, the receiving circuit 430 may output data in which “0” and “1” appear irregularly (eg, 0011101011 . . . ) instead of data in which “0” and “1” appear alternately.

[0118] The receiving circuit 430 may transmit data having regular changes or irregular changes to the control circuit 420. The control circuit 420 may check the result of the clock training in each time interval using the data transmitted from the receiving circuit 430 in each time interval.

[0119] In the case where data output in one of the multiple time intervals has regular changes and data output in the other time intervals has irregular changes, the control circuit 420 may determine the setting value CTR corresponding to the one time interval as the optimal value.

[0120] Then, the control circuit 420 may set the circuit of the clock recovery circuit 410 using the setting value CTR corresponding to this one time interval.

[0121] On the other hand, in the case where the data output in at least two consecutive time intervals has a regular change and the data output in the other time intervals has an irregular change, the control circuit 420 may determine the middle value of at least two setting values ​​CTR corresponding to the at least two time intervals as the optimal value. Subsequently, the control circuit 420 may set the circuit of the clock recovery circuit 410 using the middle value.

[0122] Hereinafter, the structure of the clock recovery circuit 410 will be described in detail.

[0123] Figure 5 and Figure 6 is a structural diagram of a clock recovery circuit according to an embodiment.

[0124] refer to Figure 5 The clock recovery circuit 410 may include a reference source generation circuit (Ref Gen) 510, an oscillator (VCO / CCO) 520, a divider 530, a phase detector (PD) 540, a charge pump (CP) 550, a loop filter (LF) 560 and a lock detector 570.

[0125] The reference source generation circuit 510 may generate a reference current or a reference voltage for determining an oscillation frequency of the oscillator 520 , and provide it to the oscillator 520 .

[0126] In a plurality of time intervals corresponding to the pre-clock training interval, the reference source generation circuit 510 may change the reference current I according to the setting value CTR sent from the control circuit 420 in each time interval. dc Or reference voltage V dc .

[0127] For example, when the number of the plurality of time intervals is 4 and the setting values ​​CTR corresponding to the respective time intervals are voltage values ​​V1, V2, V3, and V4, the reference source generating circuit 510 may generate a reference voltage V1 having a value V1 in the first time interval according to the setting value CTR transmitted in the first time interval. dc , the reference voltage V can be set in the second time interval according to the setting value CTR of the second time interval. dcis changed to have a value V2, and in this way, the reference voltage V can be finally set in the fourth time interval according to the set value CTR of the fourth time interval. dc Change to have a value of V4.

[0128] According to an embodiment, the clock recovery circuit 410 may include a gain adjustment circuit 610 instead of the reference source generation circuit 510, such as Figure 6 shown.

[0129] The gain adjustment circuit 610 can adjust the gain K of the oscillator 520 used to determine the oscillation frequency of the oscillator 520. vco .

[0130] In a plurality of time intervals corresponding to the pre-clock training interval, the gain adjustment circuit 610 may adjust the gain K according to the setting value CTR sent from the control circuit 420 in each time interval. vco .

[0131] The oscillator 520 can be classified into an oscillator that outputs a sine waveform and an oscillator that outputs a square wave. The oscillator that outputs a sine waveform may include an RC element, an LC element, a crystal element, etc. that selectively operates with respect to a frequency in a feedback loop, and the oscillator that outputs a square wave may be a ring oscillator or a relaxation oscillator.

[0132] The oscillator may be a current controlled oscillator CCO or a voltage controlled oscillator VCO. In the case where the oscillator 520 is a current controlled oscillator CCO, the control voltage V c A voltage-to-current converter (not shown) that converts a voltage into a current may be disposed at a front end of the oscillator 520 .

[0133] The oscillator 520 can use the reference current I dc Or reference voltage V dc , gain and control voltage V c To output an oscillation signal including an oscillation clock pattern OSC_CLK.

[0134] In the case where the oscillator 520 is a voltage controlled oscillator VCO, the oscillation frequency ω of the oscillation signal fb It can be determined by the following equation.

[0135] [Equation 1]

[0136] ω fb =ω 0 +K vco (V c -V dc )

[0137] In Equation 1, ω fb is the frequency of the oscillating signal, ω0 is the reference frequency of the voltage controlled oscillator VCO, K vco is the gain of the voltage controlled oscillator VCO, V c is the control voltage and V dc Here, the reference frequency of the oscillator 520 may represent the frequency of a signal oscillating in the oscillator 520 before the input clock pattern IN_CLK is input to the phase detector 540, and the level of the reference frequency may be related to the reference current I dc The level or reference voltage V dc The level or gain K vco proportional to the level.

[0138] The reference frequency of oscillator 520 may be referred to as a free-running frequency.

[0139] In a plurality of time intervals corresponding to the pre-clock training interval, the oscillator 520 may be configured to generate a reference current I dc , reference voltage V dc or gain K vco In each time interval, the output has an oscillation frequency ω different from the oscillation frequency of other signals. fb oscillation signal.

[0140] In other words, the reference current I can be changed in each time interval. dc , reference voltage V dc or gain K vco The reference frequency ω of the oscillator 520 is determined differently 0 .

[0141] In this way, the oscillator 520 can output oscillation frequencies ω with different time intervals. fb Here, when the reference current I dc , reference voltage V dc or gain K vco When increasing or decreasing in each time interval, the reference frequency ω 0 It can also be based on the reference current I dc , reference voltage V dc or gain K vco In addition, the oscillation frequency ω fb It can also be based on the reference frequency ω 0 The divider 530 can divide the oscillation frequency ω of the oscillation signal including the oscillation clock mode OSC_CLK by fb Divide by a predetermined ratio N.

[0142] In this way, the divider 530 can output an output having an oscillation frequency ω by dividing the oscillation frequency ω by fbThe frequency ω obtained by dividing by the predetermined ratio N fb The feedback signal may include a feedback clock pattern FEB_CLK. The period of the feedback clock pattern FEB_CLK may be determined by a value obtained by multiplying the period of the oscillation clock pattern OSC_CLK by a predetermined ratio N.

[0143] The phase detector 540 may detect a phase difference between the input signal and the feedback signal and output an up signal Up or a down signal Down. Here, the output signal may include an input clock pattern IN_CLK having a period obtained by multiplying a period of the training clock pattern TR_CLK by a predetermined ratio N.

[0144] When the phase difference between the input signal and the feedback signal decreases, the frequency of the up signal Up or the down signal Down output by the phase detector 540 and their pulse widths may also decrease.

[0145] The charge pump 550 may store or release charges in the capacitor of the loop filter 560 according to the pulse width of the up signal Up or the down signal Down of the phase detector 540 .

[0146] The charge pump 550 may store charges in the capacitor of the loop filter 560 using the up signal Up, and may release charges from the capacitor of the loop filter 560 using the down signal Down.

[0147] By storing charge in or releasing charge from the capacitor by the charge pump 550, the loop filter 560 can increase or decrease the control voltage V c In addition, the loop filter can output a control voltage V c Here, the loop filter 560 may remove unnecessary elements such as harmonics from the up signal Up or the down signal Down.

[0148] The lock detector 570 can compare the phases of the input clock mode IN_CLK and the feedback clock mode FEB_CLK. If there is no phase difference between the input clock mode IN_CLK and the feedback clock mode FEB_CLK, the lock detector 570 can output a lock signal LOCK of a first level, and if there is a phase difference between the input clock mode IN_CLK and the feedback clock mode FEB_CLK, the lock detector 570 can output a lock signal LOCK of a second level. Here, the first level can be a high level indicating that the phases of the input signal and the feedback signal (i.e., the phases of the communication signal and the oscillation signal) are fixed, and the second level can be a low level indicating that the phases of the input signal and the feedback signal (i.e., the phases of the communication signal and the oscillation signal) are not fixed.

[0149] In other words, the lock detector 570 may output a lock signal LOCK of a first level if there is no phase difference between the communication signal and the oscillation signal, and may output a lock signal LOCK of a second level if there is a phase difference between the communication signal and the oscillation signal.

[0150] On the other hand, the lock detector 570 may also output a lock signal LOCK of the first level or the second level after checking the data restored in the receiving circuit 430 .

[0151] For example, if the data recovered in the receiving circuit 430 includes "0" and "1" alternating with each other (e.g., 0101010 ...), the lock detector 570 can output a lock signal LOCK of a first level, and if the data recovered in the receiving circuit 430 includes "0" and "1" appearing irregularly (e.g., 0011101011 ...), the lock detector 570 can output a lock signal LOCK of a second level. With the aforementioned components, the clock recovery circuit 410 can perform clock training in accordance with the training clock pattern TR_CLK of the communication signal.

[0152] On the other hand, the phase detector 540 of the clock recovery circuit 410 may have a limited detection range (eg, -π to +π).

[0153] When determining the oscillation frequency ω fb The reference frequency ω 0 When the difference between the level of and the level of the first communication frequency as the frequency of the communication signal is greater than a predetermined degree, the oscillation frequency ω fb0 The difference between the level of the input signal frequency and the level of the first communication frequency may also be greater than a predetermined degree. fb The difference between the levels of / N may also be greater than a predetermined degree.

[0154] In this case, the phase difference between the input signal and the feedback signal, that is, the phase difference between the input clock pattern IN_CLK and the feedback clock pattern FEB_CLK may exceed the detection range of the phase detector 540, and therefore, the phase detector 540 may not detect the phase difference between the input signal and the feedback signal.

[0155] According to an embodiment, when performing clock training associated with a communication signal, the clock recovery circuit 410 may change the reference current I of the oscillator 520 at predetermined time intervals. dc , reference voltage V dc or gain K vco , find an oscillation frequency ω whose level difference with the first communication frequency relative to the communication signal is less than a predetermined degree FBThe corresponding setting value (reference current I dc The value of the reference voltage V dc The value or gain K vco adjustment value).

[0156] For example, at the time T corresponding to the pre-clock training interval tot Divided into multiple time intervals T s1 To T s4 , and the clock mode IN_CLK of the input signal input to the phase detector 540 and the clock mode FEB_CLK of the feedback signal are as follows: Fig. 9 In the case shown, the phase detector 540 cannot detect the phase difference between the input signal and the feedback signal because in the first time interval T s1 and the second time interval T s2 Medium feedback signal frequency ω Fb The level of the feedback signal frequency ω is lower than the level of the input signal frequency by more than a predetermined degree, and in the fourth time interval Ts4, the feedback signal frequency ω is Fb The level of / N is higher than the level of the input signal frequency by more than a predetermined degree.

[0157] On the contrary, due to the feedback signal frequency ω FB The level of / N is lower than the level of the input signal frequency by less than a predetermined level, so the phase detector 540 can detect the phase difference between the input signal and the feedback signal. In this case, the clock recovery circuit 410 can complete the clock training associated with the communication signal.

[0158] The control circuit 420 may check the clock training results in each time interval, and after a plurality of time intervals have elapsed, set the circuit of the clock recovery circuit 410 using the setting value CTR corresponding to the third time interval.

[0159] As described above, according to the embodiment, the data driving device can perform clock training when changing the setting value CTR of the circuit affected by the communication frequency among the circuits of the clock recovery circuit 410 at predetermined time intervals, determine the optimal setting value in consideration of the result of the clock training, and automatically change the setting of the circuit. Therefore, the time and manpower required for the tuning of the data driving device can be minimized.

[0160] Hereinafter, a process of determining an optimum setting value of a first communication frequency of a communication signal in a data driving device will be described.

[0161] Fig.10 is a flowchart illustrating a process of determining an optimal value regarding a setting value in a data driving device according to an embodiment.

[0162] Reference Fig.10 , when the driving voltage is supplied to the data processing device and the data driving device, the data driving device may receive a communication signal from the data driving device (S1010). Here, the communication signal may have one of the frequencies within a predetermined range, and the predetermined range may be a communication frequency range for high-speed data communication. The data driving device may perform clock training using the communication signal by changing the setting value of the internal circuit affected by the communication frequency in each predetermined time interval, and checking the clock training results in each time interval (S1020, S1030).

[0163] Here, the internal circuit may include an oscillator of a clock recovery circuit, and the setting value may include a reference current value for determining a reference frequency of a current-controlled oscillator, a reference voltage value for determining a reference frequency of a voltage-controlled oscillator, or a gain adjustment value for adjusting a gain of the oscillator. The setting value may also include a value of a drive current supplied to the oscillator.

[0164] The data driving device may repeat the step of S1030 until the reception of the communication signal is completed (S1040). Here, the time for receiving the communication signal may be predetermined (eg, Figure 3 The data driving device may store information of time intervals for dividing the reception time of the communication signal into a plurality of time intervals and information of the reception time. In addition, the driving device may also store a setting value of a number corresponding to the number of the plurality of time intervals.

[0165] When the reception of the communication signal is completed, the data driving device may determine the optimal setting value according to the clock training results in each time interval (S1050).

[0166] In step S1050, if the lock signal output in one of the multiple time intervals has a first level and the lock signal output in the other time intervals has a second level, the data driving device may determine the setting value corresponding to the one time interval as the optimal value.

[0167] Otherwise, if the lock signal output in at least two consecutive time intervals has a first level and the lock signal output in other time intervals has a second level, the data driving device can determine the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value (S1060).

[0168] Before step S1050, the data driving device may recover data from the communication signal according to the clock recovered through clock training. In step S1050, if the data recovered in one of the multiple time intervals has a regular change, while the data recovered in other time intervals has an irregular change, the data driving device may determine the setting value corresponding to the one time interval as the optimal value.

[0169] Otherwise, in step S1060, if the data recovered in at least two consecutive time intervals has a regular change, while the data recovered in other time intervals has an irregular change, the data driving device may determine the median value of at least two setting values corresponding to the at least two time intervals as the optimal value.

[0170] Cross - reference to related applications

[0171] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0047117, filed on April 20, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A data driving device, include: A clock recovery circuit is configured to: receiving a setting value in each of a plurality of time intervals; changing the oscillation frequency according to the setting value; performing clock training using the communication signal received in each of the plurality of time intervals according to the oscillation frequency; detecting a phase difference between the training clock pattern and the feedback clock pattern by comparing a training clock pattern included in the communication signal with a feedback clock pattern obtained from the oscillation frequency; as well as restoring the training clock mode according to the clock training; as well as A control circuit is configured to: send the setting value to the clock recovery circuit, change the setting value of the circuit among the circuits of the clock recovery circuit that is affected by the frequency of the communication signal in the respective time intervals, check the result of the clock training in the clock recovery circuit according to the change of the setting value in the respective time intervals, and determine the optimal value for the setting value.

2. The data driving device according to claim 1, in, The circuit affected by the frequency of the communication signal comprises an oscillator, which is a current controlled oscillator or a voltage controlled oscillator.

3. The data driving device according to claim 2, in, The set value includes a value of a reference current input to the current controlled oscillator or a value of a reference voltage input to the voltage controlled oscillator.

4. The data driving device according to claim 2, in, The setting value includes a gain adjustment value for adjusting a gain of the oscillator.

5. The data driving device according to claim 2, in, The frequency of the communication signal is set within a predetermined range, the control circuit gradually increases the set value in each time interval and sends the set value to the clock recovery circuit, and then the clock recovery circuit increases the oscillation frequency of the oscillator in each time interval according to the set value, wherein the oscillation frequency in the first time interval of the multiple time intervals belongs to the lowest frequency range within the predetermined range and the oscillation frequency in the last time interval belongs to the highest frequency range within the predetermined range.

6. The data driving device according to claim 2, in, The frequency of the communication signal is set within a predetermined range, the control circuit gradually reduces the set value in each time interval and sends the set value to the clock recovery circuit, and then the clock recovery circuit reduces the oscillation frequency of the oscillator in each time interval according to the set value, wherein the oscillation frequency in the first time interval of the multiple time intervals belongs to the highest frequency range within the predetermined range and the oscillation frequency in the last time interval belongs to the lowest frequency range within the predetermined range.

7. The data driving device according to claim 4, in, The setting value also includes a value of a driving current supplied to the oscillator, and when the gain adjustment value is increased or decreased in each time interval, the control circuit increases or decreases the value of the driving current according to the gain adjustment value.

8. The data driving device according to claim 1, in, The clock recovery circuit outputs a lock signal according to the phase difference, and The control circuit receives the lock signal from the clock recovery circuit during each of the plurality of time intervals, and uses the lock signal to check a result of the clock training in each of the time intervals.

9. The data driving device according to claim 8, in, In a case where the lock signal received in one of the plurality of time intervals has a first level and the lock signal received in the other time intervals has a second level, the control circuit determines a setting value corresponding to the one time interval as an optimal value.

10. The data driving device according to claim 8, in, When the locking signals received in at least two consecutive time intervals among the multiple time intervals have a first level and the locking signals received in other time intervals have a second level, the control circuit determines the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

11. The data driving device according to claim 1, further comprising a receiving circuit, the receiving circuit being configured to receive the clock recovered by clock training from the clock recovery circuit, and recover data from the communication signal according to the recovered clock to output the data.

12. The data driving device according to claim 11, in, The control circuit receives data output from the receiving circuit during the plurality of time intervals, and uses the data to check results of the clock training in the respective time intervals.

13. The data driving device according to claim 12, in, In a case where data output in one of the plurality of time intervals has a regular change and data output in the other time intervals has an irregular change, the control circuit determines a setting value corresponding to the one time interval as an optimal value.

14. The data driving device according to claim 12, in, When the data output in at least two consecutive time intervals among the multiple time intervals have regular changes and the data output in other time intervals have irregular changes, the control circuit determines the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

15. A method for driving a data driving device, wherein include: receiving a communication signal having a frequency within a predetermined range during a plurality of time intervals; receiving a setting value in each time interval of the plurality of time intervals; changing the oscillation frequency of the clock recovery circuit according to the setting value; training a clock using the communication signals received in the respective time intervals of the plurality of time intervals according to the oscillation frequency; detecting a phase difference between the training clock pattern and the feedback clock pattern by comparing a training clock pattern included in the communication signal with a feedback clock pattern obtained from the oscillation frequency; restoring the training clock mode according to clock training; as well as An optimal value of the setting value is determined according to a result of the clock training.

16. The method according to claim 15, in, When training the clock, the internal circuit includes a current-controlled oscillator or a voltage-controlled oscillator, the setting value includes the value of a reference current input to the current-controlled oscillator or the value of a reference voltage input to the voltage-controlled oscillator, and the data driving device gradually increases or decreases the value of the reference current or the value of the reference voltage in each time interval.

17. The method according to claim 15, in, When training the clock, the internal circuit includes a current controlled oscillator or a voltage controlled oscillator, the setting value includes a gain adjustment value for adjusting the gain of the current controlled oscillator or the voltage controlled oscillator, and the data driving device gradually increases or decreases the gain adjustment value in each time interval.

18. The method according to claim 15, in, When determining the optimal value, when the locking signal output in one of the multiple time intervals has a first level and the locking signal output in the other time intervals has a second level, the data driving device determines the setting value corresponding to the one time interval as the optimal value.

19. The method according to claim 15, in, When determining the optimal value, when the locking signal output in at least two consecutive time intervals among the multiple time intervals has a first level and the locking signal output in other time intervals has a second level, the data driving device determines the middle value of at least two setting values ​​corresponding to the at least two time intervals as the optimal value.

20. The method according to claim 15, in, When determining the optimal value, the data driving device recovers data from the communication signal according to the clock recovered through clock training, and when the data recovered in one time interval among the multiple time intervals has regular changes and the data recovered in other time intervals has irregular changes, the data driving device determines the setting value corresponding to the one time interval as the optimal value.

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