Method for manufacturing semiconductor device

Abstract

In a method for manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer and the first dielectric layer are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed, while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth dielectric layer and the third dielectric layer are planarized, and the sacrificial gate electrode is exposed, and a portion of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of manufacturing semiconductor devices. Background Art

[0002] As the semiconductor industry moves into nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, the challenges posed by manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including fin-type FETs (FinFETs) and gate-all-around (GAA) FETs. In FinFETs, the gate electrode is adjacent to three sides of the channel region, with a gate dielectric layer in between. The gate electrode of a FinFET includes one or more layers of metal material formed by gate replacement technology. Summary of the invention

[0003] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a sacrificial gate structure above a substrate, the sacrificial gate structure including a sacrificial gate electrode; forming a first dielectric layer above the sacrificial gate structure; forming a second dielectric layer above the first dielectric layer; planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer so that an upper portion of the sacrificial gate structure is exposed and a lower portion of the sacrificial gate structure is embedded in the first dielectric layer; forming a third dielectric layer above the exposed sacrificial gate structure and above the first dielectric layer; forming a fourth dielectric layer above the third dielectric layer; planarizing the fourth dielectric layer and the third dielectric layer so that the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer; and removing the sacrificial gate electrode.

[0004] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a sacrificial gate structure above a substrate, wherein each of the sacrificial gate structures includes a sacrificial gate electrode, and an upper portion of each of the sacrificial gate structures is exposed, while a lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer; forming a second dielectric layer above the exposed sacrificial gate structure and above the first dielectric layer; forming a third dielectric layer above the second dielectric layer; planarizing the third dielectric layer and the second dielectric layer so that the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer; and removing the sacrificial gate electrode from each of the sacrificial gate structures to form a gate spacer, wherein the amount of depression at the rough pattern area is 1 nm to 5 nm, and wherein in the rough pattern area, the distance between adjacent sacrificial gate structures is 50 nm or greater.

[0005] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming underlying structures above a substrate, wherein an upper portion of each of the underlying structures is exposed and a lower portion of each of the underlying structures is embedded in a first dielectric layer; forming a second dielectric layer above the exposed underlying structures and above the first dielectric layer; forming a third dielectric layer above the second dielectric layer; and planarizing the third dielectric layer and the second dielectric layer so that the underlying structures are exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer, wherein planarizing the third dielectric layer and the second dielectric layer comprises: a first chemical mechanical polishing (CMP) process for etching the third dielectric layer; a second chemical mechanical polishing process for etching the second dielectric layer, ending when a portion of the underlying structures is exposed; and a third chemical mechanical polishing process for recessing the second dielectric layer and the underlying structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components can be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0008] Figure 2 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0009] Figure 3 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0010] Figure 4 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0011] Figure 5 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0012] Figure 6 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0013] Figure 7 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0014] Figure 8 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0015] Fig. 9 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0016] Fig.10 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0017] Fig.11 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0018] Fig.12 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0019] Fig.13 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0020] Fig.14 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0021] Fig.15 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0022] Fig.16 One of the stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0023] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D Various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention are shown.

[0024] Fig.18A , Fig.18B , Fig.18C , Fig.18D and Fig.18E Various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention are shown.

[0025] Fig.19A , Fig.19B , Fig.19C and Fig.19D One of the various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0026] Fig. 20A , Fig. 20B and Fig. 20C One of the various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0027] Fig.21A , Fig. 21B and Fig. 21C One of the various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0028] Fig.22A , Fig. 22B and Fig. 22C One of the various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0029] Fig.23A , Fig. 23B and Fig.23C Various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention are shown.

[0030] Fig.24A , Fig. 24B and Fig.24C Various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present invention are shown. DETAILED DESCRIPTION

[0031] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or desired characteristics of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For simplicity and clarity, each component may be arbitrarily drawn in different proportions.

[0032] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Additionally, the term "made of" may mean "including" or "consisting of."

[0033] In the gate replacement technique, a sacrificial gate structure (e.g., made of polysilicon) including a sacrificial gate electrode is first formed over a channel region and then replaced with a metal gate structure. In the gate replacement technique, various planarization operations (such as chemical mechanical polishing processes) are used to planarize dielectric layers, polysilicon layers, and / or metal layers. In addition, in some FinFET devices, after the gate replacement process to form a metal gate structure, the upper portion of the metal gate structure is recessed, and a capping insulating layer is formed over the recessed gate structure to ensure isolation between the metal gate electrode and adjacent conductive contacts. In the present invention, a method is provided to suppress the recess problem in a CMP operation and to improve the isolation characteristics of the capping insulating layer.

[0034] Figures 1 to 16 1 shows a sequential process for manufacturing a FET device according to an embodiment of the present invention. It should be understood that for other embodiments of the method, Figures 1 to 16 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0035] like Figure 1 As shown, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region. The ion implantation is performed to prevent punch-through effects.

[0036] In one embodiment, the substrate 10 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 10 may include a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In this embodiment, the substrate 10 is made of Si.

[0037] The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from that of the substrate to that of the source / drain region. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer may increase from 30 atomic % germanium in the bottommost buffer layer to 70 atomic % germanium in the topmost buffer layer.

[0038] Substrate 10 may include various regions that have been appropriately doped with impurities (eg, p-type or n-type conductivity).Dopant 12 is, for example, boron (BF2) for n-type Fin FETs and phosphorus for p-type Fin FETs.

[0039] exist Figure 2 In the embodiment of the present invention, a mask layer 15 is formed over the substrate 10. In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A is made of silicon nitride and the second mask layer 15B is made of silicon oxide. In other embodiments, the first mask layer 15A is made of silicon oxide and the second mask layer 15B is made of silicon nitride (SiN). The first mask layer and the second mask layer are formed by chemical vapor deposition (CVD) including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. The mask layer 15 is patterned into a mask pattern using a patterning operation including photolithography and etching.

[0040] Next, if Figure 3 As shown, the substrate 10 is patterned into a fin structure 20 extending in the X direction by using a patterned mask layer 15. Figure 3 In the embodiment, two fin structures 20 are arranged in the Y direction. However, the number of fin structures is not limited to two and can be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 20 to improve pattern fidelity in the patterning operation.

[0041] The fin structure 20 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0042] After forming the fin structure, an insulating material layer including one or more insulating materials is formed over the substrate so that the fin structure is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the fin structure 20 is exposed from the insulating material layer 30, such as Figure 4 shown.

[0043] In some embodiments, before forming the insulating material layer 30, Figure 3 One or more liner layers 22 are formed on the structure, such as Figure 4 The liner layer 22 includes one or more of silicon nitride, SiON, SiCN, SiOCN and silicon oxide.

[0044] Then, if Figure 5 As shown, the insulating material layer 30 is recessed to form an isolation insulating layer 30 so that the upper portion of the fin structure 20 is exposed. With this operation, the fin structures 20 are electrically isolated from each other by the isolation insulating layer 30, also known as shallow trench isolation (STI). The lower portion 11 of the fin structure is embedded in the isolation insulating layer 30.

[0045] After forming the isolation insulating layer 30, a sacrificial gate dielectric layer 42 is formed. Figure 6 As shown. Sacrificial gate dielectric layer 42 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of sacrificial gate dielectric layer 42 is in the range of about 1 nm to about 5 nm.

[0046] Figure 7The structure after forming a sacrificial gate structure 40 above the exposed fin structure 20 is shown. The sacrificial gate structure includes a sacrificial gate electrode 44 and a sacrificial gate dielectric layer 42. The sacrificial gate structure 40 is formed on the portion of the fin structure that will become the channel region. The sacrificial gate structure 40 is formed by first blanket depositing a sacrificial gate dielectric layer 42 above the fin structure. Then a sacrificial gate electrode layer is blanket deposited on the sacrificial gate dielectric layer and above the fin structure so that the fin structure is completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD or other suitable processes including LPCVD and PECVD. Subsequently, a mask layer is formed above the sacrificial gate electrode layer. The mask layer includes a pad SiN layer 46 and a silicon oxide mask layer 48.

[0047] Next, the mask layer is patterned, and the sacrificial gate electrode layer is patterned into a sacrificial gate structure 40, such as Figure 7 The patterning operation of the sacrificial gate structure 40 will be explained in more detail below.

[0048] In some embodiments, the sacrificial gate structure 40 includes a sacrificial gate dielectric layer 42, a sacrificial gate electrode layer 44 (e.g., polysilicon), a pad SiN layer 46, and a silicon oxide mask layer 48. By patterning the sacrificial gate structure 40, the upper portion of the fin structure 20 is partially exposed on opposite sides of the sacrificial gate structure 40, thereby defining a source / drain (S / D) region, such as Figure 7 As shown. In the present invention, the source and drain can be used interchangeably, and their structures are basically the same. Figure 7 In the embodiment, a sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0049] After forming the sacrificial gate structure 40, a blanket layer 45 of insulating material for sidewall spacers 45 is conformally formed by using CVD or other suitable methods, such as Figure 8 As shown. Blanket layer 45 is deposited in a conformal manner so that it is formed to have substantially equal thickness on vertical surfaces, such as the sidewalls, horizontal surfaces, and top of the sacrificial gate structure. In some embodiments, blanket layer 45 is deposited to a thickness in the range of about 2 nm to about 10 nm. In one embodiment, the insulating material of blanket layer 45 is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN and combinations thereof.

[0050] In addition, if Fig. 9As shown, sidewall spacers 45 are formed on opposite sidewalls of the sacrificial gate structure, and then the fin structure of the S / D region is recessed downward below the upper surface of the isolation insulating layer 30. After the blanket layer 45 is formed, an anisotropic etching is performed on the blanket layer 45 using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from the horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces such as the sidewalls of the sacrificial gate structure and the sidewalls of the exposed fin structure. The mask layer 48 can be exposed from the sidewall spacers. In some embodiments, an isotropic etching can then be performed to remove the insulating material from the upper portion of the S / D region of the exposed fin structure 20.

[0051] Subsequently, the fin structure of the S / D region is recessed downward below the upper surface of the isolation insulating layer 30 by using dry etching and / or wet etching. Fig. 9 As shown, the sidewall spacers 45 formed on the S / D regions of the exposed fin structure (fin sidewalls) partially remain. However, in other embodiments, the sidewall spacers 45 formed on the S / D regions of the exposed fin structure are completely removed. In the case of GAA FET, the internal spacers are formed after the S / D regions are recessed.

[0052] Then, if Fig.10 As shown, a source / drain (S / D) epitaxial layer 50 is formed. The S / D epitaxial layer 50 includes one or more layers of Si, SiP, SiC and SiCP for n-channel FET or Si, SiGe, Ge, GeSn and SiGeSn for p-channel FET. The S / D layer 50 is formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE).

[0053] like Fig.10 As shown, the S / D epitaxial layers are grown from the recessed fin structures, respectively. In some embodiments, the grown epitaxial layers merge over the isolation insulating layer and form a void 52 .

[0054] Subsequently, an insulating liner layer 60 is formed as an etch stop layer, and then an interlayer dielectric (ILD) layer 65 is formed, such as Fig.11 As shown. The insulating liner layer 60 is made of a silicon nitride-based material such as SiN and is used as a contact etch stop layer in a subsequent etching operation. Materials for the ILD layer 65 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the ILD layer 65. After forming the ILD layer 65, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer 44 is exposed, as shown in FIG. Fig.11 shown.

[0055] Next, if Fig.12As shown, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed, thereby exposing the fin structure in the gate spacer 49. During the removal of the sacrificial gate structure, the ILD layer 65 protects the S / D structure 50. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 44 is polysilicon and the ILD layer 65 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 54. Thereafter, the sacrificial gate dielectric layer 42 is removed using plasma dry etching and / or wet etching.

[0056] After removing the sacrificial gate structure, a gate dielectric layer 82 is formed around the exposed fin structure 20, and a gate electrode layer 88 is formed on the gate dielectric layer 82, as shown in FIG. Fig.13 shown.

[0057] In some embodiments, the gate dielectric layer 82 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer formed between the channel layer and the dielectric material.

[0058] The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed over the channel region. In some embodiments, the thickness of the gate dielectric layer 82 is in a range of about 1 nm to about 6 nm.

[0059] A gate electrode layer 88 is formed on the gate dielectric layer 82. The gate electrode 88 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0060] The gate electrode layer 88 may be formed by CVD, ALD, electroplating or other suitable methods. The gate electrode layer is also deposited over the upper surface of the ILD layer 65. The gate dielectric layer and the gate electrode layer formed over the ILD layer 65 are then planarized by using, for example, CMP until the top surface of the ILD layer 65 is exposed.

[0061] After the planarization operation, the gate electrode layer 88 is recessed and a gate cap insulating layer 90 is formed over the recessed gate electrode 88. Fig.13 In some embodiments, the gate capping insulating layer 90 includes one or more layers of silicon nitride-based materials, such as SiN. The gate capping insulating layer 90 may be formed by depositing an insulating material and then performing a planarization operation.

[0062] In some embodiments of the present invention, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 82 and the gate electrode 88. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as work function adjustment layers, and for p-channel FETs, one or more of WN, WCN, W, Ru, Co, TiN or TiSiN are used as work function adjustment layers. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer can be formed separately for n-channel FETs and p-channel FETs, which can use different metal layers.

[0063] Subsequently, a contact hole 110 is formed in the ILD layer 65 by using dry etching, as shown in FIG. Fig.14 In some embodiments, the upper portion of the S / D epitaxial layer 50 is etched.

[0064] A silicide layer 120 is formed on the S / D epitaxial layer 50. Fig.15 As shown. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi. Then, a conductive material 130 is formed in the contact hole, such as Fig.16 The conductive material 130 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN.

[0065] It should be understood that the FinFET undergoes further CMOS processing to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

[0066] FIG. 17A to FIG. 18E The embodiment according to the present invention is shown Figure 11 to Figure 12 It should be understood that for other embodiments of the method, FIG. 17A to FIG. 18EAdditional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, processes, methods, dimensions, and / or configurations explained using the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0067] In the formation corresponding to Fig.10 After forming one or more sacrificial gate structures, a first dielectric layer 62 is formed to completely cover the sacrificial gate structures, and a second dielectric layer 64 made of a material different from the first dielectric layer 62 is further formed on the first dielectric layer 62, such as Fig.17A In some embodiments, Fig.17A As shown, the sacrificial gate structure includes a fine pattern corresponding to a short channel FET (e.g., gate length Lg≤20nm) and a coarse or larger pattern corresponding to a long channel FET (e.g., 50nm≤Lg≤500nm). In addition, in some embodiments, the spacing between adjacent sacrificial gate structures varies between the same width as the fine pattern and about 2-5 times the width of the fine pattern, between 50nm and about 500nm.

[0068] In some embodiments, the first dielectric layer 62 is made of a silicon oxide-based material, such as silicon oxide, SiON, and SiOC. In some embodiments, the second dielectric layer 64 is made of a silicon nitride-based material, such as silicon nitride, SiON, and SiCN. In some embodiments, the thickness of the second dielectric layer 64 is less than the thickness of the first dielectric layer 62. The first dielectric layer and the second dielectric layer are formed by LPCVD, plasma CVD, ALD, or any other suitable film formation method. In some embodiments, the second dielectric layer is not formed.

[0069] Then, if Fig. 17B As shown, one or more planarization operations are performed on the first dielectric layer and the second dielectric layer to expose the sacrificial gate electrode 44 (polysilicon layer) of the sacrificial gate structure. In some embodiments, the planarization operation includes a CMP operation. During the planarization operation, the hard mask layers 46 and 48 are also removed.

[0070] In some embodiments, the planarization operation includes a first CMP process for mainly etching the second dielectric layer 64 and then a second CMP process for etching the first dielectric layer 62 , ending when the polysilicon layer of the sacrificial gate electrode is exposed.

[0071] Next, if Fig. 17CAs shown, the remaining first dielectric layer 62 is recessed to expose the upper portion of the sacrificial gate structure by one or more etching (e.g., plasma dry etching) operations. In some embodiments, after the planarization operation, the amount of recess D11 is about 10% to about 30% of the original depth D10 of the first dielectric layer 62, which is also measured from the top of the sacrificial gate structure. In some embodiments, D10 is in the range of about 100nm to about 200nm. In some embodiments, D11 is in the range of about 10nm to about 60nm, and in other embodiments is in the range of about 20nm to about 35nm.

[0072] Then, if Fig.17D As shown, a third dielectric layer 66 is formed to completely cover the sacrificial gate structure, and a fourth dielectric layer 68 made of a material different from that of the third dielectric layer 66 is further formed over the third dielectric layer 66 .

[0073] In some embodiments, the third dielectric layer 66 is made of a silicon nitride-based material, such as silicon nitride, SiON, and SiCN. In some embodiments, the silicon nitride layer is doped with some impurities (diffused silicon nitride film). In some embodiments, the fourth dielectric layer 68 is made of a silicon oxide-based material, such as silicon oxide, SiON, TEOS, and SiOC. The third and fourth dielectric layers are formed by LPCVD, plasma CVD, ALD, flowable CVD, or any other suitable film formation method.

[0074] In some embodiments, the deposition temperature is in a range from about 400°C to about 600°C.

[0075] In some embodiments, the thickness of the third dielectric layer 66 is less than the thickness of the fourth dielectric layer 68 .

[0076] In some embodiments, the thickness of the third dielectric layer 66 is in the range of about 50 nm to about 100 nm. In some embodiments, the thickness of the third dielectric layer 66 is 2-3 times the depth of the depth D11. When the thickness is less than this range, the flatness of the dielectric layer after the subsequent planarization operation (CMP) may be insufficient, and when the thickness is greater than this range, some patterns of lower pattern density may have a recess problem, and the deposition and / or polishing time may increase, which will increase the manufacturing cost. In some embodiments, the thickness of the fourth dielectric layer 68 is in the range of from about 100 nm to about 200 nm to improve the flatness after the subsequent planarization (CMP) process.

[0077] Then, if 18A to 18CAs shown, a planarization operation is performed on the first dielectric layer and the second dielectric layer to expose the sacrificial gate electrode 44 of the sacrificial gate structure. In some embodiments, the planarization operation includes a first CMP process, a second CMP process, and a third CMP process performed sequentially in this order. Different slurries and / or CMP pads are used in the first CMP operation to the third CMP operation.

[0078] In the first CMP operation, the fourth dielectric layer 68 is mainly etched. The first CMP operation stops at the surface of the third dielectric layer 66 by using an endpoint detection technique. In some embodiments, the downward force of the CMP head is relatively low in the range of about greater than 0.1 to up to about 2 psi for all regions to detect the endpoint and stop on the third dielectric layer 66 to suppress the dishing problem. When the downward pressure is above this range, the dishing problem may occur in the oxide-rich region. In some embodiments, the slurry used in the first CMP operation includes an abrasive containing CeO2, which etches silicon oxide at a high etch rate (e.g., 30-160 nm / min) and does not substantially etch silicon nitride.

[0079] In some embodiments, after detecting the endpoint, additional over-polishing (over-etching) is performed for about 10-30 seconds. Fig.18A As shown, in some embodiments, due to the topography of the upper surface of the third dielectric layer 66 , a remaining portion of the fourth dielectric layer remains.

[0080] The second CMP operation mainly etches the third dielectric layer 66 by using an endpoint detection technique and stops on the sacrificial gate electrode layer 44 (polysilicon layer). In some embodiments, the downward force of the CMP head is relatively low in the range of about greater than zero to up to about 3 psi. In some embodiments, after detecting the endpoint, additional over-polishing is performed for about 5-15 seconds (or about 3-9% of the main etching time). When the over-polishing time is too short, the third dielectric layer 66 may remain on the sacrificial gate electrode 44, and when the over-polishing time is too long, a recess problem at a large spaced portion may occur (see Fig.18D In some embodiments, in the second CMP operation, the sacrificial gate electrode layer 44 is lightly etched by an amount of 0.5 nm to about 2.5 nm.

[0081] In some embodiments, the third CMP operation etches the third dielectric layer 66 and the sacrificial gate electrode layer 44. The third CMP operation is controlled by time. In some embodiments, the etching time of the third CMP operation is in the range of about 5 seconds to about 15 seconds. In some embodiments, in the second CMP operation, the sacrificial gate electrode layer 44 is etched by an amount of 0.5 nm to about 5 nm. In some embodiments, after the third CMP process, the remaining third dielectric layer 66 is in the range of about 15 nm to about 30 nm. Fig.18C The structure corresponds to Fig.11 The structure of the present invention is a structure in which the ILD layer 65 includes the first dielectric layer 62 and the remaining third dielectric layer 66. In some embodiments, the slurry used in the third CMP has a relatively high silicon nitride etching rate (e.g., 20-50 nm / min) and a relatively low polysilicon etching rate. In some embodiments, the thickness D12 of the remaining third dielectric layer is about 10% to about 30% of the height D13 of the sacrificial gate structure from the upper surface of the isolation insulating layer, and in some embodiments, is about 90 nm to about 180 nm. In some embodiments, D12 is in the range of about 9 nm to about 54 nm, and in other embodiments, in the range of about 20 nm to about 35 nm.

[0082] In some embodiments, in a large space portion or a rough pattern portion between sacrificial gate structures (where the distance between adjacent sacrificial gate structures is about 50 nm or more (e.g., up to about 500 nm)), recesses may be observed, such as Fig.18D In some embodiments, the amount of recess D20 measured from the top of the adjacent sacrificial gate structure is in a range of about 1 nm to about 5 nm. In some embodiments, the difference between the maximum thickness (observed at, for example, a dense pattern) and the minimum thickness (observed at, for example, a rough pattern) of the remaining third dielectric layer 66 is in a range of about 2 nm to about 10 nm.

[0083] In the first CMP process to the third CMP process, a CMP pad with high or medium hardness (e.g., hardness>50 (Shore D)) is used for high planarization efficiency requirements. When the hardness is less than about 50, polishing may not produce good planarization efficiency, a depression phenomenon may occur in a low-density pattern area, and due to the depression effect, the third dielectric layer 66 on the first dielectric layer 62 may be removed and the dielectric layer 62 is not protected in subsequent processes. In addition, in the first CMP process to the third CMP process, because the CMP process mainly etches silicon nitride, the post-CMP cleaning process includes a pre-cleaning process (e.g., platen polishing), an ultrasonic (megasonic) wafer cleaning process, a brush conditioning process, and an IPA (isopropyl alcohol) cleaning process. In some embodiments, the brush conditioning process includes a first step and a second step. In some embodiments, the first step includes a polishing operation using an acid solution with one or more chelating agents to capture metal ions during polishing, and the second step includes using an alkaline solution (e.g., NH4OH) to remove excess organic matter.

[0084] After the CMP operation, something like Fig.12 , remove the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 to form a gate spacer 49, as shown in Fig.18E shown.

[0085] FIG. 17A to FIG. 18CThe above planarization operation may be applied to planarization operations of other underlying structures, such as fin structures, metal gate electrodes, and contacts and wiring structures.

[0086] FIG. 19A to FIG. 22C The embodiment according to the present invention is shown Figure 12 to Figure 13 It should be understood that for other embodiments of the method, FIG. 19A to FIG. 22C Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, processes, methods, dimensions, and / or configurations explained using the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0087] FIG. 19A to FIG. 19D 4 shows various views after removing the sacrificial gate structure (sacrificial gate electrode 44 and sacrificial gate dielectric layer 42) to form gate spacers 49, as shown in reference Fig.12 described. Fig.19A is along Fig.19D The X1-X1 cross-sectional view (plan view or projection view), Fig.19B is along Fig.19D The Y1-Y1 cross-sectional view, and Fig.19C is along Fig.19D In some embodiments, an insulating liner layer 60 serving as an etch stop layer is formed before forming the ILD layer 65. In some embodiments, the insulating liner layer 60 includes silicon nitride.

[0088] In some embodiments, the upper portion of the gate sidewall spacer 45 is recessed, such as Fig.19B and Fig.19C In some embodiments, during the removal of the sacrificial gate dielectric layer, the gate sidewall spacers 45 are recessed, and in other embodiments, one or more dry etching and / or wet etching operations are performed to recess the gate sidewall spacers 45. In some embodiments, after the gate sidewall spacers 45 are recessed, the uppermost surface is made of only silicon nitride-based material (e.g., silicon nitride) (layers 60 and 66).

[0089] Fig. 20A , Fig. 20B and Fig. 20C is an enlarged view of the gate spacer after forming the metal gate structure. Fig. 20A corresponding to a short channel FET (e.g., 4 nm ≤ Lg ≤ 10 nm) including a gate electrode of a static random access memory (SRAM) cell, Fig. 20B corresponds to a mid-channel FET (e.g., 12 nm ≤ Lg ≤ 20 nm) including a gate electrode of a logic circuit, and Fig. 20CCorresponding to long channel FET (50nm≤Lg≤500nm).

[0090] like FIG. 20A to FIG. 20C As shown, an interface layer 81 is formed on the channel region of the fin structure 20, and a gate dielectric layer 82 is formed over the interface layer and the inner wall of the gate sidewall spacer 45. In some embodiments, the gate dielectric layer 82 is formed over the upper surface of the etch stop layer 60 and the additional dielectric layer 66. In some embodiments, the gate dielectric layer 82 is formed by an ALD process to conformally form a layer over a high aspect ratio structure. In some embodiments, the aspect ratio (height / bottom diameter or area) of the gate spacer 49 is in the range of about 7 to about 25.

[0091] Then, a barrier layer 83 is formed over the gate dielectric layer 82. In some embodiments, the barrier layer 83 includes one or more layers of Ta, TaN, Ti, TiN, or TiSiN. In some embodiments, the thickness of the barrier layer is in the range of about 1 nm to about 3 nm. In some embodiments, the barrier layer 83 is not formed. In some embodiments, the thickness at the bottom of the barrier layer 83 is thicker than the thickness at the side. In some embodiments, the thickness at the bottom of the barrier layer 83 is about 0.5 to three times the thickness at the side.

[0092] In addition, one or more first work function adjustment material (WFM) layers are formed over the barrier layer 83. In some embodiments, the first WFM layer 84 is a p-type WFM material, such as WN, WCN, W, Ru, Co, TiN, or TiSiN. In some embodiments, the thickness of the first WFM layer is in the range of about 0.5 nm to about 10 nm, and in other embodiments in the range of about 1 nm to about 2 nm. In some embodiments, the thickness at the bottom of the first WFM layer 84 is about 0.8 to twice the thickness at the side. When the first WFM layer is made of TiN, the TiN layer is formed by a source gas including TiCl4 and NH3. In some embodiments, the TiN layer contains Cl as an impurity. In some embodiments, the Ti concentration in the TiN layer is in the range of about 10 atomic % to about 80 atomic %. When the Ti concentration is too small, the resistance of the TiN layer increases, and when the Ti concentration is too high, Ti diffusion may cause various problems (e.g., punch-through).

[0093] In addition, one or more second WFM layers 85 are formed over the first WFM layer 84. In some embodiments, the second WFM layer 85 is an n-type WFM material, such as TiAl, TiSiAl, TiAlC, TaAl, or TaAlC. In some embodiments, the thickness of the second WFM layer is in the range of about 0.5 nm to about 6 nm, and in other embodiments in the range of about 2 nm to about 5 nm. In some embodiments, the thickness at the bottom of the second WFM layer 85 is the same as the thickness at the side or three times the thickness at the side. After forming the WFM layer, a bulk metal layer 86 is formed over the WFM layer. In some embodiments, before forming the bulk metal layer, a glue layer (not shown) is formed over the WFM layer. In some embodiments, the glue layer includes one or more of Ta, WCN, TaN, Ti, TiN, or TiSiN. The bulk metal layer 86 includes W, Ta, Sn, Nb, Ru, Co, or Mo. In some embodiments, W is used. In some embodiments, the bulk metal layer 86 is formed by an ALD process using a metal halide (chloride) gas (e.g., WCl5, TaCl5, SnCl4, NbCl5, or MoCl4). In some embodiments, the bulk metal layer 86 includes a fluorine-free metal, for example, fluorine-free W formed by WCl5 as a source gas. In some embodiments, in an n-type FET, the first WFM layer (p-type material layer) is not formed.

[0094] In some embodiments, Fig. 20A As shown, the second WFM layer 85 completely fills the gate gap, and no bulk metal layer (e.g., W layer) is formed in the gate gap. In addition, in some embodiments, the conductive layer is conformally formed in the gate gap and thus does not completely fill the gate gap of the long channel FET, such as Fig. 20B In this case, one or more insulating layers 89 are formed to fill the remaining gaps between the gate electrodes, such as Fig. 20C As shown. The insulating layer 89 is formed by one or more deposition and CMP operations. In some embodiments, the insulating layer 89 includes silicon nitride.

[0095] Then, if FIG. 21A to FIG. 21C As shown, the upper portion of the conductive layer formed in the gate spacer is recessed by one or more etching operations. In some embodiments, during the etching operation, the upper portion of the sidewall spacer 45 and / or the upper portion of the gate dielectric layer 82 is also etched. In some embodiments, the top of the WFM layer is lower than the top of the gate dielectric layer 82. In other embodiments, the top of the bulk metal layer 86 is higher than the top of either or both of the WFM layers. In a long channel FET, the insulating layer 89 is not substantially etched, as shown in FIG. Fig. 21C shown.

[0096] In addition, if FIG. 22A to FIG. 22CAs shown, a gate cap insulating layer 90 is formed over the recessed conductive layer and the recessed gate dielectric layer 82. In some embodiments, the gate cap insulating layer 90 includes silicon nitride, SiON and / or SiOCN or any other suitable material. Fig. 22C In the long channel FET shown, the gate capping insulating layer 90 fills the space between the gate sidewall spacer 45 and the insulating layer 89. In some embodiments, the conductive layers 83-86 of the gate electrode and the gate dielectric layer 82 have a U-shaped cross-section.

[0097] FIG. 23A to FIG. 23C The method for forming the gate cap insulating layer 90 according to an embodiment of the present invention is shown. FIG. 21A to FIG. 21C to FIG. 22A to FIG. 22C It should be understood that for other embodiments of the method, FIG. 23A to FIG. 23C Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, processes, methods, dimensions, and / or configurations explained using the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0098] After forming the groove, as FIG. 21A to FIG. 21C As shown, one or more insulating layers 90L for gate capping insulating layers are formed in the grooves and over the ILD layers 62 and 66. Fig.23A In some embodiments, the metal gate structure includes a Fig.22A The short channel gate electrode corresponds to Fig. 22B The intermediate channel gate electrode and the corresponding Fig. 22C In addition, in some embodiments, at the edge portion ( FIG. 23A to FIG. 23C Fin end cover layers 92 and 94 are formed on the fin end cover layers (not shown).

[0099] In some embodiments, the insulating layer 90L includes silicon nitride, SiON and / or SiOCN, or any other suitable material formed by LPCVD, plasma CVD, ALD, or any other suitable film formation method.

[0100] Then, if Fig. 23B and Fig.23C As shown, one or more planarization operations such as a CMP process are performed to planarize the insulating layer 90L, thereby forming a gate cap insulating layer 90. In some embodiments, during the planarization operation, the third dielectric layer 66 remaining on the first dielectric layer 62 is also removed. In some embodiments, the remnants of the third dielectric layer 66' remain on the first dielectric layer 62. In some embodiments, the thickness of the remaining third dielectric layer 66' is about 0.2 nm to about 0.5 nm.

[0101] FIG. 24A to FIG. 24C FIG. 1 shows a method for forming source / drain contacts (and gate contacts) according to an embodiment of the present invention. Figures 14 to 16 It should be understood that for other embodiments of the method, FIG. 24A to FIG. 24C Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, processes, methods, dimensions, and / or configurations explained using the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0102] After forming the gate capping insulating layer 90, a second ILD layer 100 is formed on the first ILD layer 65 (62) and the metal gate structure having the gate capping insulating layer. Fig.24A The second ILD layer 100 includes silicon oxide, SiOC, SiOCN or any other suitable dielectric material.

[0103] Then, source / drain contact openings 110 and gate contact openings 115 are formed by using one or more photolithography and etching operations, such as Fig. 24B In some embodiments, a portion of the source / drain epitaxial layer 50 and a portion of the metal gate electrode are also etched.

[0104] Next, if Fig.24C As shown, one or more conductive layers are formed in the openings 110 and 115 , and a planarization operation is performed to form source / drain contacts 130 and a gate contact 135 .

[0105] like Fig. 24B and Fig.24C As shown, the gate capping insulating layer 90 can still electrically isolate the gate electrode and the source / drain contacts 130 even if the source / drain opening locations are not perfectly aligned with the underlying structures.

[0106] Various embodiments or examples described herein provide several advantages over the prior art. In embodiments of the present invention, since the planarization operation used in the gate replacement process includes multiple film formation processes and multiple CMP operations, the dishing problem can be effectively suppressed.

[0107] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments may provide different advantages.

[0108] According to one aspect of the invention, in a method for manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer and the first dielectric layer are planarized and recessed so that the upper portion of the sacrificial gate structure is exposed and the lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth dielectric layer and the third dielectric layer are planarized so that the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed. In one or more embodiments above and below, the first dielectric layer includes a silicon oxide-based material, and the second dielectric layer includes a silicon nitride-based material different from the first dielectric layer. In one or more embodiments above and below, the third dielectric layer includes a silicon nitride-based material, and the fourth dielectric layer includes a silicon oxide-based material different from the third dielectric layer. In one or more embodiments above and below, planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer includes: a first chemical mechanical polishing process (CMP) for etching the second dielectric layer; a second CMP process for etching the first dielectric layer, ending when the sacrificial gate electrode is exposed; and a third etching process for recessing the first dielectric layer. In one or more embodiments above and below, planarizing the fourth dielectric layer and the third dielectric layer includes: a first chemical mechanical polishing (CMP) process for etching the fourth dielectric layer; a second CMP process for etching the third dielectric layer, ending when the sacrificial gate electrode is exposed; and a third CMP process for recessing the third dielectric layer and the sacrificial gate electrode. In one or more embodiments above and below, the first CMP process includes a first endpoint detection and a first over-polishing after detecting the first endpoint, the second CMP process includes a second endpoint detection and a second over-polishing after detecting the second endpoint, and the third CMP process is time-controlled without using endpoint detection. In one or more embodiments above and below, the second over-polishing is performed for 5-15 seconds.

[0109] According to another embodiment of the present invention, in a method for manufacturing a semiconductor device, a sacrificial gate structure is formed above a substrate. Each of the sacrificial gate structures includes a sacrificial gate electrode, and the upper portion of each of the sacrificial gate structures is exposed, while the lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer. A second dielectric layer is formed above the exposed sacrificial gate structure and above the first dielectric layer. A third dielectric layer is formed above the second dielectric layer. The third dielectric layer and the second dielectric layer are planarized so that the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed from each of the sacrificial gate structures to form a gate spacer. The amount of depression at the rough pattern area is 1nm to 5nm, wherein in the rough pattern area, the distance between adjacent sacrificial gate structures is 50nm or greater. In one or more embodiments above and below, the second dielectric layer includes a silicon nitride-based material, and the third dielectric layer includes a silicon oxide-based material different from the second dielectric layer. In one or more embodiments above and below, planarizing the third dielectric layer and the second dielectric layer includes: a first chemical mechanical polishing (CMP) process for etching the third dielectric layer; a second CMP process for etching the second dielectric layer, which ends when the sacrificial gate electrode is exposed; and a third CMP process for recessing the second dielectric layer and the sacrificial gate electrode. In one or more embodiments above and below, the first CMP process includes endpoint detection and a first over-polishing after detecting the endpoint, the second CMP process includes endpoint detection and a second over-polishing after detecting the endpoint, and the third CMP process is time-controlled without using endpoint detection. In one or more embodiments above and below, the second over-polishing is performed for 5-15 seconds. In one or more embodiments above and below, the second CMP process includes setting the downward force of the CMP head to greater than zero and up to 3psi. In one or more embodiments above and below, the first CMP process includes using an abrasive containing CeO2. In one or more embodiments above and below, the second CMP process also etches the sacrificial gate electrode. In one or more embodiments above and below, in addition, a gate dielectric layer is formed in each of the gate spacers, a conductive layer is formed on the gate dielectric layer, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a gate cap insulating layer is formed on each of the recessed gate electrodes. In one or more embodiments above and below, in forming the gate cap insulating layer, a fourth dielectric layer is formed on each of the recessed gate electrodes and over the remaining third dielectric layer, and a planarization operation is performed to remove a portion of the fourth dielectric layer and the remaining third dielectric layer to expose the recessed first dielectric layer.

[0110] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a lower structure is formed above a substrate. An upper portion of each of the lower structures is exposed, and a lower portion of each of the lower structures is embedded in a first dielectric layer. A second dielectric layer is formed above the exposed lower structure and above the first dielectric layer. A third dielectric layer is formed above the second dielectric layer, and the third dielectric layer and the second dielectric layer are planarized so that the lower structure is exposed and a portion of the second dielectric layer remains on the recessed first dielectric layer. Planarizing the third dielectric layer and the second dielectric layer includes: a first chemical mechanical polishing (CMP) process for etching the third dielectric layer; a second CMP process for etching the second dielectric layer, which ends when a portion of the lower structure is exposed; and a third CMP process for recessing the second dielectric layer and the lower structure. In one or more embodiments above and below, the first CMP process includes a first endpoint detection and a first over-polishing after detecting the first endpoint, the second CMP process includes a second endpoint detection and a second over-polishing after detecting the second endpoint, and the third CMP process is time-controlled without using endpoint detection. In one or more embodiments above and below, the second overpolishing is performed for 5-15 seconds. In one or more embodiments above and below, the second dielectric layer comprises silicon nitride, and the third dielectric layer comprises silicon oxide. In one or more embodiments above and below, the first dielectric layer comprises silicon oxide.

[0111] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a sacrificial gate structure above the substrate, the sacrificial gate structure comprising a sacrificial gate electrode, the sacrificial gate electrode comprising a polysilicon or amorphous silicon layer; forming a first dielectric layer over the sacrificial gate structure; forming a second dielectric layer over the first dielectric layer; planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer so that an upper portion of the sacrificial gate structure and a polysilicon or amorphous silicon layer are exposed and a lower portion of the sacrificial gate structure is embedded in the first dielectric layer; forming a third dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer; forming a fourth dielectric layer over the third dielectric layer; planarizing the fourth dielectric layer and the third dielectric layer so that the polysilicon or amorphous silicon layer of the sacrificial gate electrode is exposed and a portion of the third dielectric layer remains on the recessed first dielectric layer; as well as removing the sacrificial gate electrode, Wherein, planarizing the fourth dielectric layer and the third dielectric layer comprises: a first chemical mechanical polishing process for etching the fourth dielectric layer; A second chemical mechanical polishing process, for etching the third dielectric layer, ends when the polysilicon or amorphous silicon layer of the sacrificial gate electrode is exposed; and a third chemical mechanical polishing process for recessing the third dielectric layer and the sacrificial gate electrode, Wherein, when the first chemical mechanical polishing process is completed, a portion of the fourth dielectric layer remains above the third dielectric layer.

2. The method according to claim 1, wherein: The first dielectric layer includes a silicon oxide-based material, and the second dielectric layer includes a silicon nitride-based material different from the first dielectric layer.

3. The method according to claim 1, wherein: The third dielectric layer includes a silicon nitride-based material, and the fourth dielectric layer includes a silicon oxide-based material different from the third dielectric layer.

4. The method according to claim 1, wherein: Planarizing the second dielectric layer and the first dielectric layer and recessing the second dielectric layer and the first dielectric layer comprises: a fourth chemical mechanical polishing (CMP) process for etching the second dielectric layer; a fifth chemical mechanical polishing process for etching the first dielectric layer, which ends when the sacrificial gate electrode is exposed; and The sixth etching process is used to recess the first dielectric layer.

5. The method according to claim 1, wherein: The first chemical mechanical polishing process includes a chemical mechanical polishing head down force in a range of greater than 0.1 up to 2 psi.

6. The method according to claim 1, wherein: The first chemical mechanical polishing process includes a first endpoint detection and a first over-polishing after detecting the first endpoint, The second chemical mechanical polishing process includes a second endpoint detection and a second over-polishing after detecting the second endpoint, and The third chemical mechanical polishing process is time controlled without using endpoint detection.

7. The method according to claim 6, wherein: The second over-polishing is performed for 5-15 seconds.

8. A method for manufacturing a semiconductor device, comprising: forming sacrificial gate structures over the substrate, wherein each of the sacrificial gate structures comprises a sacrificial gate electrode, the sacrificial gate electrode comprises a polysilicon or amorphous silicon layer, and an upper portion of each of the sacrificial gate structures and the polysilicon or amorphous silicon layer are exposed, and a lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer; forming a second dielectric layer over the exposed sacrificial gate structure and over the first dielectric layer; forming a third dielectric layer over the second dielectric layer; planarizing the third dielectric layer and the second dielectric layer so that the polysilicon or amorphous silicon layer of the sacrificial gate electrode is exposed and a portion of the second dielectric layer remains on the first dielectric layer; and removing the sacrificial gate electrode from each of the sacrificial gate structures to form a gate spacer; forming a gate electrode structure in the gate space, wherein the gate electrode structure is recessed in the gate space; forming a fourth dielectric layer on each of the recessed gate electrode structures and over the remaining portion of the second dielectric layer; and performing a planarization process operation to remove a portion of the fourth dielectric layer and a remaining portion of the second dielectric layer, The amount of depression measured at the top of the adjacent sacrificial gate structures in the rough pattern area is 1 nm to 5 nm, and the distance between the adjacent sacrificial gate structures in the rough pattern area is 50 nm or more. Wherein, planarizing the third dielectric layer and the second dielectric layer comprises: a first chemical mechanical polishing (CMP) process for etching the third dielectric layer; a second chemical mechanical polishing process for etching the second dielectric layer, ending when the sacrificial gate electrode is exposed; and a third chemical mechanical polishing process for recessing the second dielectric layer and the sacrificial gate electrode, When the first chemical mechanical polishing process is completed, a portion of the third dielectric layer remains above the second dielectric layer.

9. The method according to claim 8, wherein: The second dielectric layer includes a silicon nitride-based material, and the third dielectric layer includes a silicon oxide-based material different from the second dielectric layer.

10. The method according to claim 8, wherein: The first chemical mechanical polishing process includes a chemical mechanical polishing head down force in a range of greater than 0.1 up to 2 psi.

11. The method according to claim 8, wherein: The second CMP process includes setting a down force of the CMP process head to be greater than zero and up to 3 psi.

12. The method according to claim 8, wherein: The first chemical mechanical polishing process includes using an abrasive containing CeO 2 .

13. The method according to claim 8, wherein: The second chemical mechanical polishing process etches the sacrificial gate electrode.

14. The method according to claim 8, wherein: Forming the gate electrode structure further includes: forming a gate dielectric layer in each of the gate spacers; forming a conductive layer on the gate dielectric layer; and The gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode.

15. The method according to claim 9, wherein: The second dielectric layer includes silicon nitride.

16. A method for manufacturing a semiconductor device, comprising: forming lower structures each including a polysilicon or amorphous silicon layer over a substrate, a sidewall layer disposed on a side of the polysilicon or amorphous silicon and an etch stop layer disposed on the sidewall layer, wherein an upper portion of each of the lower structures and the polysilicon or amorphous silicon layer are exposed, and a lower portion of each of the lower structures is embedded in a first dielectric layer, and a height of the polysilicon or amorphous silicon layer from the substrate is equal to a height of the etch stop layer from the substrate; forming a second dielectric layer over the exposed underlying structure and over the first dielectric layer; forming a third dielectric layer over the second dielectric layer; and planarizing the third dielectric layer and the second dielectric layer so that the underlying structure is exposed and a portion of the second dielectric layer remains on the first dielectric layer, Wherein, planarizing the third dielectric layer and the second dielectric layer comprises: a first chemical mechanical polishing (CMP) process for etching the third dielectric layer; wherein, when the first chemical mechanical polishing process is completed, a portion of the third dielectric layer remains above the second dielectric layer; a second chemical mechanical polishing process for etching the remaining portions of the second dielectric layer and the third dielectric layer, ending when a portion of the polysilicon or amorphous silicon of the underlying structure is exposed; and A third chemical mechanical polishing process is used to recess the second dielectric layer and the underlying structure.

17. The method of claim 16, wherein: The first chemical mechanical polishing process includes a first endpoint detection and a first over-polishing after detecting the first endpoint, The second chemical mechanical polishing process includes a second endpoint detection and a second over-polishing after detecting the second endpoint, and The third chemical mechanical polishing process is time controlled without using endpoint detection.

18. The method according to claim 17, wherein: The second over-polishing is performed for 5-15 seconds.

19. The method according to claim 16, wherein: The second dielectric layer includes silicon nitride, and the third dielectric layer includes silicon oxide.

20. The method according to claim 16, wherein: The first dielectric layer includes silicon oxide.

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