Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a first conductive layer; forming a dielectric layer on the first conductive layer, the dielectric layer having an opening therein, the opening exposing the surface of the first conductive layer; forming a second conductive layer within the opening, the top surface of the second conductive layer being flush with or lower than the top surface of the dielectric layer; and forming a gap layer on the sidewall surface of the opening, the gap layer being located between the dielectric layer and the second conductive layer. The semiconductor structure formed by the method exhibits good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, which has effectively improved the operating speed of the entire integrated circuit. As the size requirements of components become smaller and smaller, the size of the corresponding conductive structures is also getting smaller and smaller.

[0003] The method for forming the conductive structure comprises: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate, the first dielectric layer having a first opening; forming a first plug within the first opening; after forming the first plug, forming a second dielectric layer on the surface of the first plug and the surface of the first dielectric layer; forming a second opening within the second dielectric layer; and after forming the second opening, forming a second plug within the second opening. The first plug and the second plug constitute the conductive structure. To reduce the resistance of the conductive structure as its size decreases, the conductive structure is formed using a material with a low resistivity.

[0004] However, the performance of semiconductor devices formed by existing technologies needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a semiconductor structure, comprising: a first conductive layer; a dielectric layer located on the first conductive layer, the dielectric layer having an opening, and the opening exposing the surface of the first conductive layer; a second conductive layer located in the opening, the top surface of the second conductive layer being flush with or lower than the top surface of the dielectric layer; a gap layer located on the sidewall surface of the opening, and the gap layer being located between the dielectric layer and the second conductive layer.

[0007] Optionally, the material of the gap layer is a conductive material.

[0008] Optionally, the material of the gap layer includes: tungsten.

[0009] Optionally, a top surface of the second conductive layer is lower than a top surface of the dielectric layer.

[0010] Optionally, the method further includes: a third conductive layer located on the surface of the second conductive layer, and the second conductive layer and the third conductive layer completely fill the opening.

[0011] Optionally, the material of the gap layer is the same as that of the third conductive layer.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a first conductive layer; forming a dielectric layer on the first conductive layer, wherein the dielectric layer has an opening, and the opening exposes the surface of the first conductive layer; forming a second conductive layer in the opening, wherein the top surface of the second conductive layer is flush with or lower than the top surface of the dielectric layer; forming a gap layer on the side wall surface of the opening, and the gap layer is located between the dielectric layer and the second conductive layer.

[0013] Optionally, the material of the gap layer is a conductive material.

[0014] Optionally, the material of the gap layer includes: tungsten.

[0015] Optionally, the method for forming the gap layer includes: forming a gap material layer on the surface of the opening side wall and the top surface of the dielectric layer, and the gap material layer is located between the second conductive layer and the dielectric layer; flattening the gap material layer until the surface of the dielectric layer is exposed, and forming a gap layer on the surface of the opening side wall.

[0016] Optionally, a top surface of the second conductive layer is lower than a top surface of the dielectric layer.

[0017] Optionally, it also includes: after forming the gap material layer and before flattening the gap material layer, forming a third conductive material layer on the surface of the gap material layer; flattening the gap material layer and the third conductive material layer until the top surface of the dielectric layer is exposed, so that the third conductive material layer forms a third conductive layer, and the gap material layer forms a gap layer, and the second conductive layer and the third conductive layer fill the opening.

[0018] Optionally, the method for forming the gap material layer includes: forming an initial gap material layer on the sidewall surface of the opening and the top surface of the dielectric layer; and performing a modification treatment on the initial gap material layer to form the gap material layer from the initial gap material layer.

[0019] Optionally, the third conductive material layer is also formed during the modification process of the initial gap material layer.

[0020] Optionally, the material of the initial gap material layer includes: semiconductor material or conductive material.

[0021] Optionally, the semiconductor material includes: silicon.

[0022] Optionally, the process for forming the initial gap material layer includes: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the gas introduced includes SiH4, the gas flow range is 0 standard ml / min to 1000 standard ml / min, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

[0023] Optionally, the modification treatment includes a displacement reaction.

[0024] Optionally, the process parameters for modifying the initial gap material layer include: the gas introduced includes WF6, the gas flow range is 0 standard ml / min to 1000 standard ml / min, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

[0025] Optionally, part of the initial gap material layer is oxidized to form an oxide layer.

[0026] Optionally, the method further includes: removing the oxide layer after forming the initial gap material layer and before forming the third conductive material layer.

[0027] Optionally, the process for removing the oxide layer includes: an ion etching process; the parameters of the ion etching process include: the gas introduced includes argon, the gas flow range is 0 standard ml / min to 1000 standard ml / min, the RF power is 0 watts to 2000 watts, and the bias power is 0 watts to 1000 watts.

[0028] Optionally, the process of planarizing the gap material layer includes: a chemical mechanical polishing process.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming a second conductive layer within an opening, a gap layer is formed on the surface of the sidewall of the opening, and the gap layer is located between the second conductive layer and the dielectric layer. The gap layer fills the space between the second conductive layer and the dielectric layer, effectively reducing the gap between the second conductive layer and the dielectric layer. Therefore, during the subsequent planarization process, the etching solution used for planarization can be reduced from passing through the gap between the second conductive layer and the sidewall of the dielectric layer, resulting in etching damage to the first conductive layer at the bottom of the opening. This protects the material of the first conductive layer, improves the contact resistance between the first conductive layer and the second conductive layer, and improves the performance of the formed semiconductor structure.

[0031] Furthermore, the initial gap material layer is modified to form a gap material layer. The modification process is a chemical reaction process that helps improve the adhesion of the formed gap material layer to the second conductive layer and the dielectric layer, thereby further reducing the gap between the second conductive layer and the dielectric layer, and between the third conductive material layer and the dielectric layer, further protecting the first conductive layer material, thereby improving the contact resistance between the first conductive layer and the second conductive layer, and improving the performance of the formed semiconductor structure.

[0032] Furthermore, by removing the partially oxidized gap material layer, the oxidized gap material layer is prevented from affecting the size of the top of the opening, so that the key sizes of the gap layer and the third conductive layer located in the opening are not affected, thereby improving the stability of the performance of the formed semiconductor structure.

[0033] In the semiconductor structure provided by the technical solution of the present invention, a gap layer is formed on the surface of the sidewall of the opening, and the gap layer is located between the dielectric layer and the second conductive layer. The gap layer fills the space between the second conductive layer and the dielectric layer, effectively reducing the gap between the second conductive layer and the dielectric layer. Thus, during the subsequent planarization process, the etching solution used for planarization can be reduced from passing through the gap between the second conductive layer and the dielectric layer sidewall, thereby reducing the etching damage to the first conductive layer at the bottom of the opening. This protects the material of the first conductive layer, improves the contact resistance between the first conductive layer and the second conductive layer, and improves the performance of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0035] Figures 6 to 11 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0036] Figures 12 to 15 1 is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the performance of semiconductor structures is poor.

[0038] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 5 The present invention is a structural schematic diagram of each step of a semiconductor junction formation method.

[0039] Please refer to Figure 1, providing a substrate 100, wherein the substrate 100 has a first conductive layer 110, the substrate 100 exposes the surface of the first conductive layer 110, the surface of the substrate 100 has a dielectric layer 120, the dielectric layer 120 has an opening 130, and the opening 130 exposes the surface of the first conductive layer 110.

[0040] Please refer to Figure 2 A second conductive layer 140 is formed in the opening 130 , and a top surface of the second conductive layer 140 is lower than a top surface of the dielectric layer 120 .

[0041] Please refer to Figure 3 , performing ion etching on the second conductive layer 140 to form a third conductive layer 150 on the exposed sidewall surface of the opening 130 .

[0042] Please refer to Figure 4 After forming the second conductive layer 140 and the third conductive layer 150 , a fourth conductive material film 160 is formed on the surface of the second conductive layer 140 and the surface of the third conductive layer 150 within the opening 130 , as well as on the surface of the dielectric layer 120 , and the fourth conductive material film 160 fills the opening 130 .

[0043] Please refer to Figure 5 , planarizing the fourth conductive material film 160 until it reaches the surface of the dielectric layer 110 , and forming a fourth conductive layer 161 in the opening 130 .

[0044] In the above method, by ion bombarding the second conductive layer 140, a portion of the material of the second conductive layer 140 is deposited on the sidewall of the exposed opening 130 to form the third conductive layer 150. The third conductive layer 150 is conducive to increasing the adhesion between the subsequent fourth conductive layer 161 and the sidewall of the dielectric layer 120, thereby reducing the etching solution used in the subsequent planarization process through the gap a (between the second conductive layer 140 and the sidewall of the dielectric layer 120, and between the fourth conductive material film 160 and the dielectric layer 120) Figure 5 ), causing loss to the first conductive layer 110 in the substrate 100.

[0045] However, the third conductive layer 150 still cannot effectively prevent the etching solution used during the planarization process from passing through the gaps between the second conductive layer 140 and the sidewalls of the dielectric layer 120, and between the fourth conductive material film 160 and the dielectric layer 120, causing damage to the first conductive layer 110 within the substrate 100. This results in a relatively high contact resistance between the second conductive layer 140 and the first conductive layer 110, and poor performance of the resulting semiconductor structure. Furthermore, the ion bombardment process not only bombards the second conductive layer 140, but also the dielectric layer 120, resulting in a reduction in the material of the dielectric layer 120 sidewalls. This, in turn, reduces the critical dimension of the fourth conductive layer 161 located in the opening 130, resulting in poor stability of the resulting semiconductor structure.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Please refer to Figure 6 , providing a first conductive layer 210.

[0048] Specifically, in this embodiment, the first conductive layer 210 is located in the substrate 200 , and the surface of the first conductive layer 210 is exposed on the substrate 200 .

[0049] In this embodiment, the substrate 200 is a single-layer substrate.

[0050] In other embodiments, the substrate may also be an SOI substrate. The SOI substrate may be a double layer of an insulating substrate and a top single crystal silicon layer, or may be a sandwich structure with an insulating thin layer as the middle layer.

[0051] The material of the substrate 200 includes silicon, germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the backing includes germanium, silicon germanium, silicon on insulator or germanium on insulator.

[0052] Please refer to Figure 7 A dielectric layer 220 is formed on the first conductive layer 210 . The dielectric layer 220 has an opening 221 therein, and the opening 221 exposes the surface of the first conductive layer 210 .

[0053] The dielectric layer 220 , on the one hand, provides support for the subsequent formation of a conductive structure, and on the other hand, serves to electrically isolate different devices.

[0054] The method for forming the dielectric layer 220 and the opening 221 includes: forming a dielectric material film (not shown in the figure) on the surface of the substrate 200; forming a mask layer (not shown in the figure) on the surface of the dielectric material film, wherein the mask layer exposes a portion of the surface of the dielectric material film; and etching the dielectric material film using the mask layer as a mask until the surface of the first conductive layer 210 is exposed, thereby forming the dielectric layer 220 and the opening 221 located in the dielectric layer 220.

[0055] The dielectric layer 220 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon oxynitride.

[0056] In this embodiment, the dielectric layer 220 is made of silicon oxide.

[0057] Please refer to Figure 8 A second conductive layer 230 is formed in the opening 221 , and a top surface of the second conductive layer 230 is lower than a top surface of the dielectric layer 220 .

[0058] The material of the second conductive layer 230 includes metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0059] In this embodiment, the material of the second conductive layer 230 is tungsten.

[0060] The second conductive layer 230 is formed by a selective chemical vapor deposition process.

[0061] Since the first conductive layer 210 and the dielectric layer 220 are made of different materials and have different surface properties, the selective chemical deposition process can form the second conductive layer 230 on the surface of the first conductive layer 210 at the bottom of the opening 221 while not depositing material on the surface of the dielectric layer 220. This helps to avoid the deposited material from closing prematurely at the top of the opening 221, thereby avoiding the formation of voids in the formed second conductive layer 230, thereby improving the performance of the formed semiconductor structure.

[0062] In other embodiments, the top surface of the second conductive layer is flush with the top surface of the dielectric layer.

[0063] Next, a gap material layer is formed on the sidewall surface of the opening 221 and the top surface of the dielectric layer 220, and the gap material layer is located between the second conductive layer 230 and the dielectric layer 220. For the specific process of forming the gap material layer, please refer to Figures 9 and 10 .

[0064] Please refer to Figure 9 An initial gap material layer 240 is formed on the sidewall surface of the opening 221 and the top surface of the dielectric layer 220 .

[0065] Specifically, in this embodiment, the initial gap material layer 240 is also located on the top surface of the second conductive layer 230 .

[0066] The material of the initial gap material layer 240 includes semiconductor material or conductive material.

[0067] In this embodiment, the material of the initial gap material layer 240 is a semiconductor material, silicon.

[0068] In this embodiment, the process of forming the initial gap material layer 240 includes: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the gas introduced includes SiH4, the gas flow range is 0 standard ml / min to 1000 standard ml / min, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

[0069] Please refer to Figure 10 , the initial gap material layer 240 is modified to form the gap material layer 241 .

[0070] It should be noted that, in this embodiment, during the process of modifying the initial gap material layer 240 , a third conductive material layer 250 is also formed.

[0071] Please continue to refer to Figure 10 , forming a third conductive material layer 250 on the surface of the gap material layer 241 .

[0072] The gap material layer 241 is made of a conductive material.

[0073] The third conductive material layer 250 is made of a conductive material.

[0074] In this embodiment, the gap material layer 241 and the third conductive material layer 250 are made of the same material, tungsten.

[0075] The third conductive material layer 250 and the gap material layer 241 are made of the same material, tungsten.

[0076] The modification treatment includes a displacement reaction.

[0077] In this embodiment, the process parameters for modifying the initial gap material layer 240 include: the gas introduced includes WF6, the gas flow range is 0 standard ml / min to 1000 standard ml / min, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

[0078] It should be noted that the modification treatment is performed by stacking layers on the surface of the gap material layer 241 , thereby selectively depositing and forming the third conductive material layer 250 .

[0079] In this embodiment, the material of the initial gap material layer 240 is Si, and the gas introduced during the modification process is WF6. The introduced gas WF6 can chemically react with Si, and Si can replace the W element from WF6 to generate W and SiF4.

[0080] The initial gap material layer 240 is modified to form a gap material layer 241. The modification process is a chemical reaction process that helps improve the adhesion of the formed gap material layer 241 to the second conductive layer 230 and the dielectric layer 220, thereby further reducing the gap between the second conductive layer 230 and the dielectric layer 220, and between the third conductive material layer 250 and the dielectric layer 220, further protecting the material of the first conductive layer 210, thereby improving the contact resistance between the first conductive layer 210 and the second conductive layer 230, and improving the performance of the formed semiconductor structure.

[0081] In this embodiment, after forming the third conductive material layer 250, before subsequently planarizing the gap material layer 241 and the third conductive material layer 250, it also includes: forming a buffer layer 260 on the surface of the third conductive material layer 250, and in the process of planarizing the gap material layer 241 and the third conductive material layer 250, also planarizing the buffer layer 260.

[0082] The buffer layer 260 is used to form a thicker film layer on the surface of the dielectric layer 220 , thereby providing a buffer for the subsequent planarization process and improving process stability.

[0083] The buffer layer 260 is a single-layer structure or a multi-layer structure.

[0084] In this embodiment, the buffer layer 260 is a single-layer structure.

[0085] The buffer layer 260 is formed by a chemical vapor deposition process.

[0086] In other embodiments, the buffer layer is a multi-layer structure, and the materials of the buffer layer are titanium nitride and tungsten.

[0087] Please refer to Figure 11 , planarize the gap material layer 241 and the third conductive material layer 250 until the top surface of the dielectric layer 220 is exposed, so that the third conductive material layer 250 forms a third conductive layer 251, and the gap material layer 241 forms a gap layer 242, and the second conductive layer 230 and the third conductive layer 251 fill the opening 221.

[0088] In this embodiment, since the surface of the third conductive material layer 250 also has a buffer layer 260, before planarizing the gap material layer 241 and the third conductive material layer 250, the planarization process also removes the buffer layer 260 to expose the surface of the third conductive material layer 250.

[0089] The process of planarizing the gap material layer 241 and the third conductive material layer 250 includes a chemical mechanical polishing process.

[0090] The chemical mechanical polishing process uses a polishing liquid.

[0091] After forming the second conductive layer 230 and the third conductive layer 251 within the opening 221, a gap layer 242 is formed on the sidewall surface of the opening 221. The gap layer 242 is located between the second conductive layer 230, the third conductive layer 251, and the dielectric layer 220. The gap layer 242 fills the space between the second conductive layer 230, the third conductive layer 251, and the dielectric layer 220, effectively reducing the gap between the second conductive layer 230, the third conductive layer 251, and the dielectric layer 220. Therefore, during the subsequent planarization process, the gap between the second conductive layer 230, the third conductive layer 251, and the dielectric layer 220 can be reduced, thereby reducing the etching damage to the first conductive layer 210 at the bottom of the opening 221 caused by the etching solution used for planarization passing through the gap between the second conductive layer 230, the third conductive layer 251, and the sidewall of the dielectric layer 220. This protects the material of the first conductive layer 210, improves the contact resistance between the first conductive layer 210, the second conductive layer 230, and the third conductive layer 251, and improves the performance of the resulting semiconductor structure.

[0092] Accordingly, the present invention also provides a semiconductor structure formed by the above method, please continue to refer to Figure 11 , including: a first conductive layer 210; a dielectric layer 220 located on the first conductive layer 210, the dielectric layer 220 having an opening 221, and the opening 221 exposing the surface of the first conductive layer 210; a second conductive layer 230 located in the opening 221, the top surface of the second conductive layer 230 being flush with or lower than the top surface of the dielectric layer 220; a gap layer 242 located on the sidewall surface of the opening 221, and the gap layer 242 being located between the dielectric layer 220 and the second conductive layer 230.

[0093] The gap layer 242 is made of a conductive material.

[0094] The material of the gap layer 242 includes tungsten.

[0095] In this embodiment, the top surface of the second conductive layer 230 is lower than the top surface of the dielectric layer 220 .

[0096] The semiconductor structure further includes a third conductive layer 251 located on the surface of the second conductive layer 230 , and the second conductive layer and the third conductive layer completely fill the opening.

[0097] The material of the second conductive layer 230 includes metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum. In this embodiment, the material of the second conductive layer 230 is tungsten.

[0098] The material of the third conductive layer 251 includes metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0099] In this embodiment, the material of the third conductive layer 251 is tungsten.

[0100] The material of the gap layer 242 is the same as that of the third conductive layer 251 .

[0101] In this embodiment, the materials of the gap layer 242 and the third conductive layer 251 are both tungsten.

[0102] Figures 12 to 15 2 is a schematic diagram illustrating the steps of a method for forming a semiconductor structure according to another embodiment of the present invention. This embodiment differs from the above embodiment in that after forming the initial gap material layer 240 and before subsequently modifying the initial gap material layer 240, the initial gap material layer 240 may be exposed to the external environment, causing a portion of the initial gap material layer 240 to oxidize, forming an oxide layer. Therefore, the oxide layer needs to be removed. This embodiment further describes the method for forming a semiconductor structure based on the above embodiment.

[0103] Please Figure 9 Continue to refer to Figure 12 After the initial gap material layer 240 is formed, a portion of the initial gap material layer 240 is oxidized to form an oxide layer 341 .

[0104] When the initial gap material layer 240 needs to be transferred between different machines, it is inevitably exposed to the external atmospheric environment, causing part of the initial gap material layer 240 to be oxidized, thereby forming an oxide layer 341. The oxide layer 341 will cause electrical isolation and affect the conductivity of the formed semiconductor structure.

[0105] Please refer to Figure 13 , remove the oxide layer 341.

[0106] The process of removing the oxide layer 341 includes: an ion etching process; the parameters of the ion etching process include: the gas introduced includes argon gas, the gas flow range is 0 standard ml / min to 1000 standard ml / min, the RF power is 0 watts to 2000 watts, and the bias power is 0 watts to 1000 watts.

[0107] It should be noted that after removing a portion of the oxide layer 341 , a portion of the surface of the initial gap material layer 240 that has not been oxidized is exposed, and will subsequently be subjected to a modification process.

[0108] The ion etching process has a large etching selectivity ratio for the oxide layer 341 and the initial gap material layer 240, so that when the oxide layer 341 is removed, no significant etching damage will be caused to the initial gap material layer 240. Therefore, the unoxidized initial gap material layer 240 can protect the dielectric layer 220, preventing the dielectric layer 220 from being etched and damaging, so that the sidewalls of the dielectric layer 220 will not be etched and damaged. That is, the size of the opening 221 in the dielectric layer 220 remains unchanged, thereby ensuring that the critical size of the conductive structure subsequently formed in the opening 221 remains unchanged, thereby improving the stability of the performance of the semiconductor structure.

[0109] The dimension refers to the distance between the opening 221 and the sidewall surface of the opening 221 in a direction perpendicular to the opening 221 .

[0110] Please refer to Figure 14 After removing the oxide layer 341 , the initial gap material layer 240 is modified so that the initial gap material layer 240 forms the gap material layer 342 .

[0111] The modification method is the same as that in the above embodiment and will not be described in detail here.

[0112] It should be noted that, in this embodiment, during the process of modifying the initial gap material layer 240 , a third conductive material layer 350 is also formed.

[0113] Please continue to refer to Figure 14 , forming a third conductive material layer 350 on the surface of the gap material layer 342 .

[0114] The material of the gap material layer 342 is the same as that of the gap material layer 241 in the above embodiment, and will not be repeated here.

[0115] The third conductive material layer 350 is made of the same material as the third conductive material layer 250 in the above embodiment, and will not be further described herein.

[0116] It should be noted that the modification treatment is performed by stacking layers on the surface of the gap material layer 342 , thereby selectively depositing and forming the third conductive material layer 350 .

[0117] After removing the oxide layer 341, the initial gap material layer 240 is exposed. The initial gap material layer 240 is modified to form a gap material layer 342. The modification process is a chemical reaction process that helps improve the adhesion of the formed gap material layer 342 to the second conductive layer 230 and the dielectric layer 220. This can further reduce the gap between the second conductive layer 230 and the dielectric layer 220, and between the formed third conductive material layer 350 and the dielectric layer 220. This further protects the material of the first conductive layer 210, thereby improving the contact resistance between the first conductive layer 210 and the second conductive layer 230, and improving the performance of the formed semiconductor structure.

[0118] In this embodiment, after forming the third conductive material layer 350, before subsequently planarizing the gap material layer 342 and the third conductive material layer 350, it also includes: forming a buffer layer 360 on the surface of the third conductive material layer 350, and in the process of planarizing the gap material layer 342 and the third conductive material layer 350, also planarizing the buffer layer 360.

[0119] The material and function of the buffer layer 360 are the same as those of the buffer layer 260 in the above embodiment, and are not described in detail here.

[0120] Please refer to Figure 15 , planarize the gap material layer 342 and the third conductive material layer 350 until the top surface of the dielectric layer 220 is exposed, so that the third conductive material layer 350 forms a third conductive layer 351, and the gap material layer 342 forms a gap layer 343, and the second conductive layer 230 and the third conductive layer 351 fill the opening 221.

[0121] In this embodiment, since the surface of the third conductive material layer 350 also has a buffer layer 360 , before planarizing the gap material layer 342 and the third conductive material layer 350 , the planarization process also removes the buffer layer 360 to expose the surface of the third conductive material layer 350 .

[0122] The process of the planarization treatment is the same as that of the planarization treatment in the above embodiment, and will not be repeated here.

[0123] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 15, including: a first conductive layer 210; a dielectric layer 220 located on the first conductive layer 210, the dielectric layer 220 having an opening 221, and the opening 221 exposing the surface of the first conductive layer 210; a second conductive layer 230 located in the opening 221, the top surface of the second conductive layer 230 being flush with or lower than the top surface of the dielectric layer 220; a gap layer 343 located on the sidewall surface of the opening 221, and the gap layer 343 being located between the dielectric layer 220 and the second conductive layer 230.

[0124] The gap layer 343 is made of a conductive material.

[0125] In this embodiment, the material of the gap layer 343 is tungsten.

[0126] In this embodiment, the top surface of the second conductive layer 230 is lower than the top surface of the dielectric layer 220 .

[0127] The semiconductor structure further includes a third conductive layer 351 located on the surface of the second conductive layer 230 , and the second conductive layer 230 and the third conductive layer 351 completely fill the opening.

[0128] The material of the second conductive layer 230 includes metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0129] In this embodiment, the material of the second conductive layer 230 is tungsten.

[0130] The material of the third conductive layer 351 includes metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0131] In this embodiment, the material of the third conductive layer 351 is tungsten.

[0132] The material of the gap layer 343 is the same as that of the third conductive layer 351 .

[0133] In this embodiment, the materials of the gap layer 343 and the third conductive layer 351 are both tungsten.

[0134] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a first conductive layer; forming a dielectric layer on the first conductive layer, wherein the dielectric layer has an opening therein, and the opening exposes a surface of the first conductive layer; forming a second conductive layer in the opening, wherein a top surface of the second conductive layer is lower than a top surface of the dielectric layer; forming a gap layer on the sidewall surface of the opening, wherein the gap layer is located between the dielectric layer and the second conductive layer; The method for forming the gap layer comprises: forming a gap material layer on the surface of the sidewall of the opening, the top surface of the dielectric layer and the top surface of the second conductive layer, wherein the gap material layer is located between the second conductive layer and the dielectric layer; The method for forming the gap material layer comprises: forming an initial gap material layer on the surface of the opening sidewall, the top surface of the dielectric layer, and the top surface of the second conductive layer; performing a modification process on the initial gap material layer to form the gap material layer; the modification process comprises a replacement reaction; During the process of modifying the initial gap material layer, a third conductive material layer is formed on the surface of the gap material layer; The gap material layer and the third conductive material layer are planarized by a chemical mechanical polishing process until the top surface of the dielectric layer is exposed, so that the third conductive material layer forms a third conductive layer and the gap material layer forms a gap layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gap layer is a conductive material.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the gap layer includes tungsten.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial gap material layer includes: semiconductor material or conductive material.

5. The method for forming a semiconductor structure according to claim 4, wherein: The semiconductor material includes silicon.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of forming the initial gap material layer includes: a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the gas introduced includes SiH4, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters for modifying the initial gap material layer include: the gas introduced includes WF6, and the temperature range is 300 degrees Celsius to 500 degrees Celsius.

8. The method for forming a semiconductor structure according to claim 1, wherein: A portion of the initial gap material layer is oxidized to form an oxide layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: After forming the initial gap material layer and before forming the third conductive material layer, the oxide layer is removed.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the oxide layer includes: an ion etching process; the parameters of the ion etching process include: the gas introduced includes argon gas, and the bias power is 0 watts to 1000 watts.

11. The method for forming a semiconductor structure according to claim 1, wherein: The second conductive layer and the third conductive layer completely fill the opening; the width of the third conductive layer is greater than that of the second conductive layer; and the gap layer is further located between the third conductive layer and the dielectric layer and between the third conductive layer and the second conductive layer.

12. A semiconductor structure, characterized in that: The semiconductor structure is obtained by using the method for forming a semiconductor structure according to any one of claims 1 to 11; the semiconductor structure comprises: a first conductive layer; a dielectric layer located on the first conductive layer, wherein the dielectric layer has an opening therein, and the opening exposes a surface of the first conductive layer; a second conductive layer located in the opening, wherein a top surface of the second conductive layer is lower than a top surface of the dielectric layer; a gap layer located on the sidewall surface of the opening, and the gap layer is located between the dielectric layer and the second conductive layer; a third conductive layer located on the surface of the second conductive layer, wherein the second conductive layer and the third conductive layer completely fill the opening; the width of the third conductive layer is greater than the width of the second conductive layer; and the gap layer is further located between the third conductive layer and the dielectric layer and between the third conductive layer and the second conductive layer; The gap layer is obtained through a replacement reaction.

13. The semiconductor structure according to claim 12, wherein: The material of the gap layer is a conductive material.

14. The semiconductor structure according to claim 13, wherein: The material of the gap layer includes tungsten.

15. The semiconductor structure according to claim 12, wherein: The material of the gap layer is the same as that of the third conductive layer.

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