Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) element and a manufacturing method thereof. The semiconductor device includes: a floating gate layer formed in a trench in a substrate; a tunneling dielectric layer located on the sidewalls and bottom of the trench; a control gate dielectric layer located on the top surface of the floating gate layer; a control gate layer located on the top surface of the control gate dielectric layer; and sidewall spacers located on the control gate dielectric layer and the sidewalls of the control gate layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a metal oxide semiconductor field effect transistor element and a manufacturing method thereof. Background Art

[0002] Integrated circuit metal oxide semiconductor field effect transistor (MOSFET) memory devices, also known as flash memory, typically include a memory region and a peripheral logic region. The memory region includes transistors having a floating gate layer and a tunnel dielectric layer located between a channel region and the top surface of a control gate layer. Transistors located in the peripheral logic region do not have a floating gate or a tunnel dielectric layer. Therefore, transistors in the memory region are typically taller than transistors in the peripheral logic region. In short, the distance from the top surface of the substrate to the top surface of the control gate layer of the transistor in the memory region is greater than the distance from the top surface of the substrate to the top surface of the control gate layer in the peripheral logic region of a MOSFET device. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor device having a metal oxide semiconductor field effect transistor element includes a floating gate layer, a tunneling dielectric layer, a control gate dielectric layer, a control gate layer, and sidewall spacers. The floating gate layer is formed within a floating gate trench in a substrate. The tunneling dielectric layer is formed on the sidewalls and bottom of the floating gate trench. The control gate dielectric layer is formed above the top surface of the floating gate layer. The control gate layer is formed above the top surface of the control gate dielectric layer. Sidewall spacers are located on the sidewalls of the control gate dielectric layer and the control gate layer.

[0004] According to another embodiment of the present disclosure, a semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) element is provided. The semiconductor device is disposed on a substrate and includes a plurality of MOSFET elements. At least one of the MOSFET elements includes a floating gate layer formed in a floating gate trench formed in the substrate.

[0005] According to one embodiment of the present disclosure, a method for fabricating a semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) element includes etching a first floating gate trench in a substrate, forming a first tunnel dielectric layer on sidewalls of the first floating gate trench, forming a first floating gate layer in the first floating gate trench on the first tunnel dielectric layer, and planarizing the first floating gate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A vertical cross-sectional view illustrating a step of etching a trench in a substrate to form a shallow trench isolation structure in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0008] Figure 2 A vertical cross-sectional view illustrating a step of depositing an insulating material in a trench in a substrate in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0009] Figure 3 A vertical cross-sectional view illustrating a step of etching a memory trench in a substrate in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0010] Figure 4 A vertical cross-sectional view illustrating a step of depositing a tunnel dielectric layer in a memory trench in a substrate in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0011] Figure 5 A vertical cross-sectional view illustrating a step of depositing a floating gate layer in a memory trench in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0012] Figure 6 A vertical cross-sectional view illustrating a step of depositing a gate dielectric layer and a control gate layer over a substrate and a floating gate layer in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0013] Figure 7 A vertical cross-sectional view illustrating a step of patterning a gate dielectric layer and a control gate layer in a method of manufacturing a semiconductor device according to some embodiments;

[0014] Figure 8 A vertical cross-sectional view illustrating a step of depositing a sidewall spacer dielectric layer over a substrate, a control gate dielectric layer, and a control gate layer in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0015] Figure 9 A vertical cross-sectional view illustrating a step of patterning a sidewall spacer dielectric layer in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0016] Figure 10 A vertical cross-sectional view illustrating a step of forming an active region in a substrate by ion implantation in a method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0017] Figure 11 illustrative vertical cross-sectional views of semiconductor devices according to various embodiments of the present disclosure;

[0018] Figure 12 is a vertical cross-sectional view illustrating another semiconductor device according to various embodiments of the present disclosure;

[0019] Figure 13 A vertical cross-sectional view illustrating a step of forming two memory trenches in another method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0020] Figure 14 A vertical cross-sectional view illustrating a step of extending the depth of one of the memory trenches in another method of manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0021] Figure 15 is a vertical cross-sectional view illustrating another semiconductor device according to various embodiments of the present disclosure;

[0022] Figure 16 A flowchart illustrating a method for manufacturing a semiconductor device according to various embodiments of the present disclosure;

[0023] Figure 17 FIG2 is a flow chart illustrating another method for manufacturing a semiconductor device according to various embodiments of the present disclosure.

[0024]

Explanation of symbols

[0025] 100: Integrated circuit components / integrated circuit metal oxide semiconductor field effect transistor (MOSFET) components

[0026] 102:Substrate

[0027] 104: Shallow Trench Isolation (STI) trench

[0028] 106:STI structure

[0029] 107a: first floating gate trench

[0030] 107b: second floating gate trench

[0031] 108a: first tunneling dielectric layer

[0032] 108b: second tunneling dielectric layer

[0033] 109: Top surface

[0034] 110a: first floating gate layer

[0035] 110b: second floating gate layer

[0036] 111a: Top surface

[0037] 112: Patterning the first gate oxide layer

[0038] 112a: Patterning the first gate oxide layer

[0039] 112b: Patterning the second gate oxide layer

[0040] 112L: continuous first gate oxide layer

[0041] 114: Patterned nitride layer

[0042] 114L: continuous nitride layer

[0043] 116: Patterning the second gate oxide layer

[0044] 116L: continuous second gate oxide layer

[0045] 118: Patterned control gate dielectric layer

[0046] 118a: first patterned control gate dielectric layer

[0047] 118b: second patterned control gate dielectric layer

[0048] 118L: Continuous control gate dielectric layer

[0049] 120: Patterned control gate layer

[0050] 120L: continuous control gate layer

[0051] 122: sidewall spacer

[0052] 122L: continuous sidewall spacer layer

[0053] 124: Ions

[0054] 126: Active area

[0055] 127: Channel area

[0056] 128: Active area

[0057] 129a: First MOSFET element

[0058] 129b: Second transistor structure

[0059] 130: Interconnect level dielectric layer

[0060] 132: Contact via / patterned control gate layer

[0061] 136: Photoresist layer

[0062] 200: Integrated circuit components / integrated circuit metal oxide semiconductor field effect transistor (MOSFET) components

[0063] 300: Integrated circuit components / integrated circuit metal oxide semiconductor field effect transistor (MOSFET) components

[0064] 400:Method

[0065] 402: Steps

[0066] 404: Steps

[0067] 406: Steps

[0068] 408: Steps

[0069] 410: Steps

[0070] 412: Steps

[0071] 414: Steps

[0072] 416: Steps

[0073] 418: Steps

[0074] 420: Steps

[0075] 422: Steps

[0076] 500:Method

[0077] 502: Steps

[0078] 504: Steps

[0079] 506: Steps

[0080] 508: Steps

[0081] 510: Steps

[0082] 512: Steps

[0083] d a :depth

[0084] d b :depth

[0085] h a :high

[0086] h b :high

[0087] t a :thickness

[0088] t b :thickness

[0089] tTDa :thickness

[0090] t TDb :thickness DETAILED DESCRIPTION

[0091] The following disclosure provides many different embodiments or examples to achieve the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely examples and are not intended to be restrictive. For example, in the subsequent description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed as direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0092] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature(s) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of an element in use or operation in addition to the orientation depicted in the figures. The device may be oriented in different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0093] In general, the structures and methods disclosed herein can be used to form metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices, such as integrated circuit MOSFET devices, wherein at least some of the MOSFETs have floating gates formed in a substrate on which the MOSFETs are formed. As described above, the transistors formed in the memory region have a floating gate layer and a tunnel dielectric layer, which are located between a channel region formed between the active region (i.e., the source region and the drain region) and the top surface of the control gate layer. Typically, the channel region is formed in the substrate, and the tunnel dielectric layer and the floating gate layer are formed above the top surface of the substrate. The control gate dielectric layer is typically formed above the floating gate layer, and the control gate layer is formed above the control gate dielectric layer. In contrast, transistors formed in the peripheral logic region do not include a floating gate layer. Adding a floating gate layer and a tunnel dielectric layer can substantially increase the height of the memory transistor relative to the logic transistor. In short, the logic region has devices with one polysilicon layer (i.e., the control gate layer), while the memory region has devices with two polysilicon layers (i.e., the floating gate layer and the control gate layer). As a result, transistors formed in the memory region are generally taller than those formed in the surrounding logic region.

[0094] The height difference between the transistors formed in the memory area and the transistors formed in the peripheral logic area may adversely affect the ability to use a single photolithography process over both areas because the focal length of the photolithography process varies between the areas. Specifically, the topographical differences between the memory area and the peripheral logic area result in these areas having different focal points, which can adversely affect the photolithography process. For example, when one of the memory area or the peripheral logic area is in focus, the other area (the memory in the peripheral logic area) may be out of focus, resulting in under-etched areas. This under-etching can cause unwanted residue to stick to the surface of the out-of-focus area (i.e., the memory in the peripheral logic area). Alternatively, when one of the memories in the peripheral logic area is in focus, the other area (the memory in the peripheral logic area) may be out of focus, resulting in over-etching of the out-of-focus area. Over-etching can cause the polysilicon layer, especially the topmost polysilicon layer, to peel off.

[0095] To reduce the height difference between transistors formed in the memory region, including a floating gate layer and a tunnel dielectric layer, various embodiments disclosed herein form the floating gate and tunnel dielectric layers of the transistors within the substrate. Consequently, the height of transistors formed in the memory region with the floating gate and tunnel dielectric layers can be substantially the same as the height of transistors in the peripheral logic region without the floating gate and tunnel dielectric layers. This allows the focal point of the lithography radiation to be substantially the same in the memory region and the peripheral logic region, thereby reducing or eliminating photolithography damage that may be caused by the different focal lengths in the memory region and the peripheral logic region.

[0096] Reference Figure 1 , illustrating an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 102, which may be a semiconductor substrate such as a commercially available silicon substrate. Shallow trench isolation (STI) trenches 104 may be etched in the substrate 102. To etch the STI trenches 104, a photoresist (not shown) may be deposited on the top surface 109 of the substrate 102 and patterned. Any suitable photoresist may be used, such as a positive or negative photoresist. In addition, the substrate 102 may be etched using any suitable wet or dry etch or a combination of wet and dry etches. The substrate 102 may be made of silicon, silicon on insulator (SOI), silicon on sapphire (SOS), or any other suitable material. The depth of the STI trenches 104 may be in the range of 50 nm to 500 nm. For example, the depth of the STI trenches 104 may be in the range of 75 nm to 400 nm, although greater or lesser depths are within the contemplated scope of the present disclosure.

[0097] Reference Figure 2STI dielectric material may be deposited in STI trenches 104 to form STI structures 106. STI structures 106 provide electrical isolation between adjacent transistors. STI structures 106 may be made of any suitable dielectric material, such as silicon oxide (SiO2). The STI dielectric material may be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or any other suitable deposition method.

[0098] Reference Figure 3 , a first floating gate trench 107a can be formed in the substrate 102 between adjacent STI structures 106. The first floating gate trench 107a can be formed by first covering the substrate 102 and the STI structure 106 with a photoresist (not shown) and patterning the photoresist. The patterned photoresist can then be used as a mask to etch the substrate 102 to form the first floating gate trench 107a. Any suitable photoresist and etchant can be used. The photoresist and / or etchant can be the same as or different from the photoresist and / or etchant used to form the STI trench 104. After forming the first floating gate trench 107a, the photoresist can be removed, such as by ashing, dissolving, or grinding. Optionally, the photoresist layer can be left on the substrate 102 and removed after forming the first tunneling dielectric layer 108a and the first floating gate layer 110a (discussed in more detail below), so that excess tunneling dielectric layer material and floating gate material can be removed during a stripping process. In different embodiments, the depth d of the first floating gate trench 107a is a It may be between 50 nm and 400 nm, such as between 75 nm and 300 nm. Trenches with smaller or larger depths may also be formed, as will be discussed in more detail below.

[0099] Reference Figure 4 The first tunnel dielectric layer 108a may be conformally deposited on the sidewalls of the first floating gate trench 107a. The first tunnel dielectric layer 108a may be made of SiO2, Si3N4, Al2O3, Y2O3, La2O3, Ta2O3, TiO2, HfO2, or ZrO2. Other suitable materials are within the contemplation of the present disclosure. The first tunnel dielectric layer 108a may be deposited by CVD, PECVD, atomic layer deposition (ALD), or any other suitable method. The thickness of the first tunnel dielectric layer 108a may be in the range of 1 nm to 15 nm, although greater or lesser thicknesses are within the contemplation of the present disclosure.

[0100] Reference Figure 5, the first floating gate layer 110a may be formed in the first floating gate trench 107a. In one embodiment, the first floating gate trench 107a may be completely filled with the first tunnel dielectric layer 108a and the first floating gate layer 110a. Thus, the height h of the first floating gate layer 110a is a and the thickness t of the first tunnel dielectric layer 108a TDa The depth d of the first floating gate trench 107a may be equal to a The first floating gate layer 110a may comprise polysilicon or any other suitable material and may be deposited by any suitable method, such as CVD, PECVD, or ALD. Optionally, a planarization step may be performed to remove any excess floating gate layer material. Thus, the top surface 111a of the first floating gate layer 110a may be coplanar with the top surface of the substrate 102. Planarization may be performed by chemical mechanical polishing or any other suitable method.

[0101] Reference Figure 6 A continuous control gate dielectric layer 118L may be deposited over the substrate 102, the first tunneling dielectric layer 108a, the first floating gate layer 110a, and the STI structure 106. In one embodiment, the continuous control gate dielectric layer 118L may include a continuous first gate oxide layer 112L, a continuous nitride layer 114L over the continuous first gate oxide layer 112L, and a continuous second gate oxide layer 116L over the continuous nitride layer 114L, thereby forming an oxide / nitride / oxide (ONO) sandwich. A continuous control gate layer 120L may then be deposited over the continuous second gate oxide layer 116L. The continuous control gate layer 120L may be made of polysilicon or any other suitable material. The continuous control gate layer 118L and the continuous control gate layer 120L may be deposited by any suitable method, such as CVD, PECVD, and ALD.

[0102] Reference Figure 7 , the continuous control gate dielectric layer 118L and the continuous control gate layer 120L can be patterned. To pattern the continuous control gate dielectric layer 118L and the continuous control gate layer 120L, a photoresist (not shown) can be deposited on the top surface of the continuous control gate layer 120L and patterned. The patterned photoresist can be used as a mask to pattern the continuous control gate dielectric layer 118L and the continuous control gate layer 120L. Ultimately, both the patterned control gate dielectric layer 118 and the patterned control gate layer 120 are formed above the first floating gate layer 110a. In one embodiment, patterning the continuous control gate dielectric layer 118L produces a patterned first gate oxide layer 112, a patterned nitride layer 114 above the patterned first gate oxide layer 112, and a patterned second gate oxide layer 116 above the patterned nitride layer 114.

[0103] Reference Figure 8 , a continuous sidewall spacer layer 122L may be deposited over the surfaces of the substrate 102, the STI structure 106, the patterned control gate dielectric layer 118, and the patterned control gate layer 120. The continuous sidewall spacer layer 122L may be made of any suitable dielectric material, including but not limited to SiO2 or Si3N4. Other suitable materials are within the contemplation of the present disclosure. The continuous sidewall spacer layer 122L may be deposited by any suitable method, such as CVD, PECVD, or ALD. A planarization step may be performed to remove any excess continuous sidewall spacer layer 122L material deposited over the patterned control gate layer 120. Planarization may be performed by chemical mechanical polishing or any other suitable method.

[0104] Reference Figure 9 , the continuous sidewall spacer layer 122L may be patterned to form sidewall spacers 122, which are located on the sidewalls of the patterned control gate dielectric layer 118 and the patterned control gate layer 120. The continuous sidewall spacer layer 122L may be patterned using a photolithography and etching process. A photoresist layer (not shown) may be deposited over the continuous sidewall spacer layer 122L and patterned. The patterned photoresist may then be used as an etch mask to pattern the continuous sidewall spacer layer 122L to produce the sidewall spacers 122. An etching process may be performed to remove the continuous sidewall spacer layer 122L covering the horizontal portions of the substrate and the STI structure 106, so that dielectric spacers are formed on the sides of the patterned control gate dielectric layer 118 and the patterned control gate layer 120.

[0105] Reference Figure 10 , portions of the substrate 102 may be implanted with ions 124 to form active regions 126, 128 (source and drain regions). Sidewall spacers 122 and the patterned control gate layer 120 may serve as masks so that the active regions 126, 128 may be self-aligned with the patterned control gate layer 120. For example, the active regions 126, 128 may be doped P-type or N-type as desired. Example N-type dopants include, but are not limited to, antimony, arsenic, and phosphorus. Example P-type dopants include, but are not limited to, boron, aluminum, and gallium. The active regions 126, 128 may have a 2x10 20 Up to 2x10 21implanted ion concentration. Greater or lesser doping concentrations may be used. In addition, the active regions 126, 128 may have different dopant concentrations from one another. The active regions 126, 128, the channel region 127, the sidewall spacers 122, and the patterned control gate layer 120 above the patterned control gate dielectric layer 118 may form a first MOSFET element 129a. A channel region 127 may be formed between the active regions 126, 128, and the channel region 127 is typically doped with a dopant type opposite to that of the active regions 126, 128. For example, if the active regions 126, 128 are P-type, the channel is N-type. If the active regions 126, 128 are N-type, the channel may be P-type. In various embodiments, the substrate may be doped prior to forming any other processing steps.

[0106] Reference Figure 11 , an interconnect-level dielectric layer 130 may be deposited over the top surface of the substrate 102, the sidewall spacers 122, and the patterned control gate layer 120. Subsequently, a photoresist layer (not shown) may be deposited and patterned to serve as a mask to form vias (not shown) in the interconnect-level dielectric layer 130. The vias may be filled with a metal, such as W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof, to form contact vias 132. Other suitable materials are within the contemplated scope of the present disclosure. In this manner, contact vias 132 coupled to the patterned control gate layer 120 and the active regions 126, 128 may be formed to complete the integrated circuit device 100. The result is that the integrated circuit device 100 includes a first MOSFET device 129a, which includes a first floating gate layer 110a formed in the substrate 102. In one embodiment, the integrated circuit device 100 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0107] Figure 12 FIG. 2 shows another integrated circuit device 200 according to other embodiments of the present disclosure. These embodiments are similar to Figure 11 However, in these embodiments, a second floating gate trench 107b may be formed in the substrate 102, the second floating gate trench 107b being deeper than the first floating gate trench 107a described above. Specifically, the depth d of the second floating gate trench 107b is b It may be in the range of 100 nm to 600 nm, such as between 150 nm and 500 nm, although greater or lesser trench depths are within the contemplation of the present disclosure.

[0108] The second tunnel dielectric layer 108b may be conformally deposited on the sidewalls of the second floating gate trench 107b. The thickness of the second tunnel dielectric layer 108b is t TDb The thickness of the first tunnel dielectric layer 108a may be TDa The second tunnel dielectric layer 108b may be the same or different. The second tunnel dielectric layer 108b may be made of SiO2, Si3N4, Al2O3, Y2O3, La2O3, Ta2O3, TiO2, HfO2, or ZrO2. Other suitable materials are within the contemplation of the present disclosure. The second tunnel dielectric layer 108b may be deposited by CVD, PECVD, atomic layer deposition (ALD), or any other suitable method. The thickness of the second tunnel dielectric layer 108b may be in the range of 1 nm to 15 nm, although greater or lesser thicknesses are within the contemplation of the present disclosure.

[0109] The second floating gate layer 110b may be formed in the second floating gate trench 107b. In one embodiment, the second floating gate trench 107b may be completely filled with the second tunnel dielectric layer 108b and the second floating gate layer 110b. Thus, the height h of the second floating gate layer 110b is b The thickness of the second tunnel dielectric layer 108b may be equal to the depth d of the second floating gate trench 107b. b Because the height h of the second floating gate layer 110b b Greater than the height h of the first floating gate layer 110a a , so for the same area occupied, the volume of the second floating gate layer 110b is larger than the volume of the first floating gate layer 110a. Because the volume of the second floating gate layer 110b is larger than the volume of the first floating gate layer 110a, the second floating gate layer 110b can store more charge than the first floating gate layer 110a. Therefore, the integrated circuit device 200 with a larger second floating gate layer 110b can be described as a higher-capacity device. The integrated circuit device 100 with a smaller first floating gate layer 110a can store less charge than the integrated circuit device 200 and can discharge more quickly. Therefore, the integrated circuit device 100 with a smaller first floating gate layer 110a can be described as a high-speed switching device.

[0110] The second floating gate layer 110b may comprise polysilicon or any other suitable material and may be deposited by any suitable method, such as CVD, PECVD, or ALD. Optionally, a planarization step may be performed to remove any excess floating gate layer material. Thus, the top surface 111b of the second floating gate layer 110b may be coplanar with the top surface of the substrate 102. Planarization may be performed by chemical mechanical polishing or any other suitable method.

[0111] In one embodiment, the patterned control gate dielectric layer 118 of the integrated circuit device 200 may be formed to be thicker than the patterned control gate dielectric layer 118 of the integrated circuit device 100. Figure 12The patterned control gate dielectric layer 118 of the integrated circuit device 200 may include the Figures 6 to 11 The ONO interlayer discussed. Figure 12 The thickness of the patterned first gate oxide layer 112 may be as Figures 6 to 11 The thickness of the patterned first gate oxide layer 112 in the integrated circuit device 100 shown in FIG is 20% to 70% thicker, but greater or lesser thicknesses are within the contemplation of the present disclosure. Figure 12 The thickness of the patterned first gate oxide layer 112 is comparable to Figures 6 to 11 The thickness of the patterned first gate oxide layer 112 in the integrated circuit device 100 shown in FIG is 30% to 60% thick, but greater or lesser thicknesses are within the contemplation of the present disclosure. Figure 12 The thickness of the patterned first gate oxide layer 112 is comparable to Figures 6 to 11 The thickness of the patterned first gate oxide layer 112 in the integrated circuit device 100 shown in FIG. 1 is 40% to 50% thicker, but greater or lesser thicknesses are within the contemplated scope of the present disclosure.

[0112] Figures 13 to 15 1 shows steps in a method of manufacturing an integrated circuit device 300 according to another embodiment. Figure 13 , in a similar Figure 3 In the step shown in FIG. 1 , a first floating gate trench 107 a and a second floating gate trench 107 b may be formed in a substrate 102 having an STI structure 106 therebetween. The STI structure 106 is located between the first floating gate trench 107 a and the second floating gate trench 107 b. In this step, the first floating gate trench 107 a and the second floating gate trench 107 b have the same depth.

[0113] Reference Figure 14 , a photoresist layer 136 may be deposited above the top surface 109 of the substrate 102. The photoresist layer 136 may fill the first floating gate trench 107a and the second floating gate trench 107b. Figure 14 As shown, the photoresist layer 136 may be patterned so that the photoresist layer 136 covers the first floating gate trench 107a and exposes the second floating gate trench 107b. The substrate 102 may then be further etched so that the depth of the second floating gate trench 107b in the substrate 102 is increased relative to the depth of the first floating gate trench 107a.

[0114] Figure 15 The integrated circuit device 300 according to the present disclosure is shown. The integrated circuit device 300 includes a first MOSFET element 129a having a first floating gate layer 110a and a second transistor 129b having a second floating gate layer 110b. The first floating gate layer 110a has a first height h, which may be referred to as a high-speed aThe second floating gate layer 110b has a second height h which can be called a high capacity. b Compared to the second height h of the second transistor structure 129b b The second floating gate layer 110b has a smaller height h, and the first floating gate layer 110a has a smaller height h a , the first MOSFET element 129a includes a smaller first floating gate layer 110a.

[0115] The first patterned control gate dielectric layer 118a and the second patterned control gate dielectric layer 118b of the first transistor 129a and the second transistor 129b can be formed by depositing continuous layers, such as a continuous first gate oxide layer 112L, a continuous nitride layer 114L, and a continuous second gate oxide layer 116L across both the first transistor 129a and the second transistor 129b, and patterning, as described above. In an alternative embodiment, the patterned second gate oxide layer 112b of the second MOSFET element 129b can be thicker than the patterned first gate oxide layer 112a of the first MOSFET element 129a. In the method of forming the alternative embodiment, a continuous first gate oxide layer 112L having a first thickness can be deposited.

[0116] In the above process, specifically, a photoresist may be deposited on the continuous first gate oxide layer 112L and patterned so as to mask the continuous first gate oxide layer 112L in the area where the first transistor 129a will be formed and expose the continuous first gate oxide layer 112L in the area where the second transistor 129b will be formed. Additional oxide material may be deposited so that the thickness of the exposed first gate oxide layer 112L increases. In this way, the thickness of the continuous first gate oxide layer 112L of the second transistor 129b may be thicker than the thickness of the continuous first gate oxide layer 112L of the first transistor 129a. The photoresist may then be removed and processing continued as described above. After patterning the continuous first gate oxide layer 112L, the continuous nitride layer 114L, the continuous second gate oxide layer 116L, and the continuous control gate layer 120L, the integrated circuit device 300 will have a first transistor 129a and a second transistor 129b. The first transistor 129a has a thickness of t a The patterned first gate oxide layer 112a of the second transistor 129b has a thickness of t b The patterned second gate oxide layer 112b has a thickness of t b Specific thickness t a In one embodiment, the thickness of the second patterned gate oxide layer 112b is t b Than the thickness t of the patterned first gate oxide layer 112a aIn one embodiment, the thickness of the second patterned gate oxide layer 112b is t b Than the thickness t of the patterned first gate oxide layer 112a a In one embodiment, the thickness of the second patterned gate oxide layer 112b is t b Than the thickness t of the patterned first gate oxide layer 112a a 40% to 50% thicker.

[0117] Figure 16The flowchart illustrates a general method 400 for fabricating an integrated circuit device 100 having a first floating gate layer 110a formed in a substrate 102. Referring to step 402, a first floating gate trench 107b may be formed in the substrate 102 by patterning a photoresist layer above the substrate 102 and performing a subsequent etching process. As described above, the etching process may include any suitable wet or dry etching, or a combination of wet and dry etching. Referring to step 404, a first tunnel dielectric layer 108a may be formed on the sidewalls of the first floating gate trench 107a. The first tunnel dielectric layer 108a may be deposited by CVD, PECVD, atomic layer deposition (ALD), or any other suitable method. Referring to step 406, a first floating gate layer 110a may be formed on the first tunnel dielectric layer 108a. The first floating gate layer 110a may be deposited by any suitable method, such as CVD, PECVD, or ALD. Referring to step 408, the first floating gate layer 110a may be patterned. A planarization step 408 may be performed to remove any excess floating gate layer material. Planarization may be performed by chemical mechanical polishing or any other suitable method. To complete the integrated circuit device 100, 200, in step 410, a continuous control gate dielectric layer 118L may be deposited over the substrate 102, the first tunneling dielectric layer 108a, and the first floating gate layer 110a. The continuous control gate dielectric layer 118L may include a continuous first gate oxide layer 112L, a continuous nitride layer 114L, and a continuous second gate oxide layer 116L. Next, in step 412, a continuous control gate layer 120L may be deposited over the continuous control gate dielectric layer 118L. In step 414, the continuous control gate dielectric layer 118L and the continuous control gate layer 120L may be patterned to form a patterned control gate dielectric layer and a patterned control gate layer 120. In step 416, a continuous sidewall spacer layer 122L may be deposited and patterned to form sidewall spacers 122 on the patterned control gate dielectric layer 118 and the patterned control gate layer 120. The sidewall spacers 122 may be used as a mask during the ion implantation step 418 to form the active regions 126, 128 (source / drain regions) and complete the first MOSFET element 129a. Next, in step 420, an interconnect-level dielectric layer 130 may be deposited, and in step 422, contact vias may be formed to the active regions 126, 128 and the patterned control gate layer 132.

[0118] Figure 17The flowchart illustrates a general method 500 for fabricating an integrated circuit device 300 having a high-speed first transistor 129a and a high-capacitance first transistor 129b, wherein a first floating gate layer 110a is embedded in a substrate 102. Referring to step 502, a first floating gate trench 107a and a second floating gate trench 107b may be etched in the substrate 102. Referring to step 504, the first floating gate trench 107a may be masked with a photoresist layer 136, and the photoresist layer 136 may be patterned to expose the second floating gate trench 107b. Referring to step 506, the second floating gate trench 107b may be etched such that the second floating gate trench 107b is deeper than the first floating gate trench 107a. Referring to step 508, the photoresist layer 136 may be removed. Referring to step 510, a first tunnel dielectric layer 108a may be formed on the sidewalls of the first floating gate trench 107a and the second floating gate trench 107b. Referring to step 512, a first floating gate layer 110a may be formed on the first tunneling dielectric layer 108a in the first floating gate layer trench 107a, and a second floating gate layer 110b may be formed on the second tunneling dielectric layer 108b in the second floating gate trench 107b. After the floating gate layers are formed on the tunneling dielectric layers in step 512, steps 408 to 422 may be performed to complete the first MOSFET device 129a and the second MOSFET device 129b.

[0119] Different embodiments of the present disclosure can provide a flash memory transistor structure having a first floating gate layer 110a buried in the substrate 102. By burying the first floating gate layer 110a in the substrate 102, the morphology of the transistor formed in the memory area can be the same as the morphology of the transistor formed in the peripheral logic area. By leveling the morphology between the transistor formed in the memory area and the transistor formed in the peripheral logic area, peeling defects caused by defocusing due to uneven height between the transistor in the memory area and the transistor in the peripheral logic area can be reduced. Uniform height allows for uniform focus in subsequent photolithography operations. Conventional stacked polysilicon flash structures utilize an i-line barrier process and a polycrystalline guard ring to repair flash damage defects. The structure formed in the different embodiments disclosed herein can omit the i-line barrier process, thereby improving process efficiency and cost. In addition, the resulting chip size can be reduced when a polycrystalline guard ring is not required.

[0120] Referring to all the drawings and according to various embodiments of the present disclosure, a MOSFET device includes: a first floating gate layer 110a formed in a first floating gate trench 107a in a substrate 102, first tunneling dielectric layers 108a and 108b formed on the sidewalls and bottom of the first floating gate trench 107a, a patterned control gate dielectric layer 118 formed on the top surface of the first floating gate layer 110a, a patterned control gate layer 120 located on the top surface of the patterned control gate dielectric layer, and sidewall spacers 122 located on the sidewalls of the patterned control gate dielectric layer 118 and the patterned control gate layer 120.

[0121] According to another embodiment of the present disclosure, an integrated circuit metal oxide semiconductor field effect transistor (MOSFET) device 100 , 200 , 300 may be disposed on a substrate 102 including a plurality of MOSFET devices 129 a or 129 b , wherein at least one of the MOSFET devices 129 a or 129 b includes a first floating gate layer 110 a formed in the substrate 102 .

[0122] Another embodiment is a method for manufacturing a MOSFET element 129a or 129b, comprising the following steps: etching a first floating gate trench 107a in a substrate 102, forming a first tunneling dielectric layer 108a, 108b on the sidewalls of the first floating gate trenches 107a, 107b, forming a first floating gate layer 110a in the first floating gate trenches 107a, 107b on the first tunneling dielectric layer 108a, 108b, and planarizing the first floating gate layers 110a, 110b.

[0123] According to one embodiment of the present disclosure, a semiconductor device having a metal oxide semiconductor field effect transistor element includes a floating gate layer, a tunneling dielectric layer, a control gate dielectric layer, a control gate layer, and sidewall spacers. The floating gate layer is formed in a floating gate trench in a substrate. The tunneling dielectric layer is formed on the sidewalls and bottom of the floating gate trench. The control gate dielectric layer is formed above the top surface of the floating gate layer. The control gate layer is formed above the top surface of the control gate dielectric layer. Sidewall spacers are located on the sidewalls of the control gate dielectric layer and the control gate layer. In one or more of the foregoing and following embodiments, the control gate dielectric layer includes an oxide / nitride / oxide sandwich. In one or more of the foregoing and following embodiments, the top surface of the floating gate layer is coplanar with the top surface of the substrate. In one or more of the foregoing and following embodiments, the substrate includes source and drain regions, wherein the floating gate layer and the control gate layer are formed between the source and drain regions. In one or more of the foregoing and following embodiments, the semiconductor device also includes an interconnect-level dielectric layer and a plurality of contact vias. The interconnection-level dielectric layer covers the substrate. The contact vias are located in the interconnection-level dielectric layer and electrically couple the source region, the drain region and the control gate layer.

[0124] According to another embodiment of the present disclosure, a semiconductor device having a metal oxide semiconductor field effect transistor element is provided. The semiconductor device is located on a substrate, and the semiconductor device includes a plurality of metal oxide semiconductor field effect transistor elements. At least one of these metal oxide semiconductor field effect transistor elements includes a floating gate layer formed in a floating gate trench, and the floating gate trench is formed in the substrate. In one or more of the aforementioned and following embodiments, these metal oxide semiconductor field effect transistor elements include a first transistor structure and a second transistor structure. The first transistor structure includes a first floating gate layer formed in a first floating gate trench in the substrate, and the first floating gate layer has a first height. The second transistor structure includes a second floating gate layer formed in a second floating gate trench in the substrate, and the second floating gate layer has a second height, wherein the second height is different from the first height. In one or more of the aforementioned and following embodiments, the semiconductor device further includes a first patterned gate oxide layer on the top surface of the first floating gate layer, and a second patterned gate oxide layer on the top surface of the second floating gate layer, wherein the second gate oxide layer is thicker than the first gate oxide layer. In one or more of the foregoing and following embodiments, the second gate oxide layer is 30% to 60% thicker than the first gate oxide layer. In one or more of the foregoing and following embodiments, the semiconductor device further includes static random access memory or dynamic random access memory. In one or more of the foregoing and following embodiments, the first transistor structure has a higher switching speed than the second transistor structure. In one or more of the foregoing and following embodiments, the second transistor structure has a higher charge storage capacity than the first transistor structure.

[0125] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device having a metal oxide semiconductor field effect transistor element includes etching a first floating gate trench in a substrate. Forming a first tunnel dielectric layer on the sidewalls of the first floating gate trench. Forming a first floating gate layer in the first floating gate trench on the first tunnel dielectric layer. Planarizing the first floating gate layer. In one or more of the aforementioned and following embodiments, the method further includes forming a continuous control gate dielectric layer above the first floating gate layer. Forming a continuous first control gate layer above the continuous control gate dielectric layer. And etching the continuous control gate dielectric layer and the continuous control gate layer to form a patterned control gate dielectric layer and a patterned control gate layer. In one or more of the aforementioned and following embodiments, the step of forming the control gate dielectric layer includes forming a continuous first oxide layer, forming a continuous nitride layer above the continuous first oxide layer, and forming a continuous second oxide layer above the continuous nitride layer. In one or more of the aforementioned and following embodiments, the method further includes etching a second trench in the substrate. Forming a second tunnel dielectric layer on the sidewalls of the second trench. and forming a second floating gate layer on the second tunneling dielectric layer. In one or more of the foregoing and following embodiments, the method further includes forming a patterned control gate dielectric layer and a patterned control gate layer above the second tunneling dielectric layer and the second floating gate layer. In one or more of the foregoing and following embodiments, the patterned control gate layer above the second floating gate layer includes a patterned first oxide layer, the patterned first oxide layer having a thickness that is 30% to 60% thicker than the thickness of the patterned control gate layer above the first floating gate layer. In one or more of the foregoing and following embodiments, the second tunneling dielectric layer is formed in the same step as the first tunneling dielectric layer, and the second floating gate layer is formed in the same step as the first tunneling dielectric layer. In one or more of the foregoing and following embodiments, the method further includes forming sidewall spacers on the control gate dielectric layer and the control gate layer. And forming source and drain regions in the substrate using the sidewall spacers as masks.

[0126] The above summarizes the features or examples of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments or examples described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device having a metal oxide semiconductor field effect transistor element, characterized in that: The semiconductor device comprises: A first transistor structure comprising: a first floating gate layer formed in a first floating gate trench in a substrate, wherein the first floating gate trench is formed in the substrate and the first floating gate layer has a first height; and a first tunnel dielectric layer formed on sidewalls and a bottom of the first floating gate trench; a second transistor structure comprising: a second floating gate layer formed in a second floating gate trench in the substrate, wherein the second floating gate trench is formed in the substrate and the floating gate layer has a second height, wherein the second height is different from the first height; and a second tunneling dielectric layer formed on sidewalls and a bottom of the second floating gate trench; a control gate dielectric layer formed on a top surface of the first floating gate layer and the second floating gate layer; a control gate layer formed on a top surface of the control gate dielectric layer; and A sidewall spacer is located on the sidewalls of the control gate dielectric layer and the control gate layer.

2. The semiconductor device according to claim 1, wherein The control gate dielectric layer includes an oxide / nitride / oxide sandwich.

3. The semiconductor device according to claim 1, wherein The top surface of the first floating gate layer is coplanar with a top surface of the substrate.

4. The semiconductor device according to claim 1, wherein A source and drain region is further included in the substrate, wherein the first floating gate layer and the control gate layer are formed between the source and drain regions.

5. The semiconductor device according to claim 4, wherein Further including: an interconnect-level dielectric layer covering the substrate; as well as A plurality of contact vias are located in the interconnection-level dielectric layer and electrically couple the source region, the drain region and the control gate layer.

6. A semiconductor device having a metal oxide semiconductor field effect transistor element, the semiconductor device being located on a substrate, characterized in that: include: A plurality of metal oxide semiconductor field effect transistor devices, comprising: a first transistor structure comprising a first floating gate layer formed in a first floating gate trench in the substrate, the first floating gate layer having a first height; as well as a second transistor structure comprising a second floating gate layer formed in a second floating gate trench in the substrate, the second floating gate layer having a second height, wherein the second height is different from the first height; At least one of the plurality of MOSFET devices includes a floating gate layer formed in a floating gate trench formed in the substrate.

7. The semiconductor device according to claim 6, wherein: The method further includes a first patterned gate oxide layer on a top surface of the first floating gate layer and a second patterned gate oxide layer on a top surface of the second floating gate layer, wherein the second patterned gate oxide layer is thicker than the first patterned gate oxide layer.

8. The semiconductor device according to claim 7, wherein The second patterned gate oxide layer is 30% to 60% thicker than the first patterned gate oxide layer.

9. The semiconductor device according to claim 6, wherein The system further includes a static random access memory (SRAM) or a dynamic random access memory (DRAM).

10. The semiconductor device according to claim 6, wherein The first transistor structure comprises a higher switching speed than the second transistor structure.

11. The semiconductor device according to claim 6, wherein The second transistor structure includes a higher charge storage capacity than the first transistor structure.

12. A method for manufacturing a semiconductor device having a metal oxide semiconductor field effect transistor element, characterized in that: The following steps are involved: Etching a first floating gate trench and a second floating gate trench in a substrate; forming a first tunnel dielectric layer on the sidewall of the first floating gate trench, and forming a second tunnel dielectric layer on the sidewall of the second floating gate trench; forming a first floating gate layer in the first floating gate trench on the first tunnel dielectric layer, wherein the first floating gate layer has a first height, and forming a second floating gate layer in the second floating gate trench on the second tunnel dielectric layer, wherein the second floating gate layer has a second height that is different from the first height; planarizing the first floating gate layer and the second floating gate layer; forming a continuous control gate dielectric layer over the first floating gate layer and the second floating gate layer, and including forming a continuous first oxide layer, forming a continuous nitride layer over the continuous first oxide layer, and forming a continuous second oxide layer over the continuous nitride layer; forming a continuous control gate layer above the continuous control gate dielectric layer; etching the continuous control gate dielectric layer and the continuous control gate layer to form a patterned control gate dielectric layer and a patterned control gate layer; forming a sidewall spacer on the patterned control gate dielectric layer and the patterned control gate layer; and A source and drain region is formed in the substrate using the sidewall spacer as a mask.

13. The method according to claim 12, characterized in that The step of forming the patterned control gate dielectric layer and the patterned control gate layer includes depositing a photoresist on the top surface of the continuous control gate layer; and The photoresist is patterned, wherein the patterned photoresist is used as a mask to pattern the continuous control gate dielectric layer and the continuous control gate layer.

14. The method according to claim 12, characterized in that The method further includes forming a patterned control gate dielectric layer and a patterned control gate layer above the second tunneling dielectric layer and the second floating gate layer.

15. The method according to claim 14, characterized in that The patterned control gate layer above the second floating gate layer includes a patterned first oxide layer having a thickness that is 30% to 60% thicker than a thickness of the patterned control gate dielectric layer above the first floating gate layer.

16. The method according to claim 12, characterized in that The second tunnel dielectric layer is formed in the same step as the first tunnel dielectric layer, and the second floating gate layer is formed in the same step as the first floating gate layer.

17. The method according to claim 13, wherein Forming the sidewall spacer comprises the following steps: depositing a continuous sidewall spacer layer over the substrate; and An etching process is performed to remove a horizontal portion of the continuous sidewall spacer layer, so that the sidewall spacers are formed on the side surfaces of the patterned control gate dielectric layer and the patterned control gate layer.

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