Semiconductor device structure and method for forming the same

Abstract

The present invention provides a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a substrate having a base and a fin located above the base; a gate stack located above a top of the fin; a first nanostructure located above the fin and passing through the gate stack; a second nanostructure located above the first nanostructure and passing through the gate stack, the gate stack having a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure; a stressor structure located above the fin and connected to the first nanostructure and the second nanostructure; a first inner spacer located between the first portion and the stressor structure; and a second inner spacer located between the second portion and the stressor structure, the first inner spacer being wider than the second inner spacer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, and more particularly, to a gate all around (GAA) transistor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] In the evolution of integrated circuits, as geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases, functional density (i.e., the number of interconnected devices per chip area) increases. Such scaling down generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes become more difficult. Therefore, forming increasingly smaller and reliable semiconductor devices is a challenge. Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor device structure and a method for forming the same to solve at least one of the above problems.

[0006] An embodiment of the present invention includes a semiconductor device structure, comprising: a substrate having a base and a fin located above the base; a gate stack located above a top of the fin; a first nanostructure located above the fin and passing through the gate stack; a second nanostructure located above the first nanostructure and passing through the gate stack, the gate stack having a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure; a stressor structure located above the fin and connected to the first nanostructure and the second nanostructure; a first inner spacer located between the first portion and the stressor structure; and a second inner spacer located between the second portion and the stressor structure, the first inner spacer being wider than the second inner spacer.

[0007] Embodiments of the present invention also include a semiconductor device structure, comprising: a substrate having a base and a fin located above the base; a first nanostructure located above the fin; a second nanostructure located above the first nanostructure, the fin, the first nanostructure, and the second nanostructure being separated from each other; a gate stack surrounding the first nanostructure, the second nanostructure, and the top of the fin, wherein the gate stack has a first portion and a second portion, the first portion being between the first nanostructure and the fin, and the second portion being between the first nanostructure and the second nanostructure; a stressor structure located above the fin and connected to the first nanostructure and the second nanostructure; a first inner spacer located between the first portion and the stressor structure, wherein the first inner spacer has a first gap; and a second inner spacer located between the second portion and the stressor structure, the second inner spacer having a second gap, and the first gap is wider than the second gap.

[0008] An embodiment of the present invention further includes a method for forming a semiconductor device structure, comprising: providing a substrate having a base and a fin located on the base; forming a nanostructure stack on the fin, wherein the nanostructure stack includes a first nanostructure, a second nanostructure, a third nanostructure and a fourth nanostructure formed in sequence on the fin; forming a gate stack on the nanostructure stack and the fin; partially removing the nanostructure stack and the fin not covered by the gate stack to form a groove in the nanostructure stack and the fin; and removing the ends of the first nanostructure and the third nanostructure through the groove to form a first groove and a second groove in the nanostructure stack, the first groove being located between the fin and the second nanostructure, the second groove being located between the second nanostructure and the fourth nanostructure, and the first groove being wider than the second groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the components may be enlarged or reduced to clearly illustrate the technical features of the embodiments of the present invention.

[0010] Figure 1A-1F The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0011] Figure 1A-1 To illustrate according to some embodiments Figure 1A A perspective view of a semiconductor device structure.

[0012] Figure 1F-1 To illustrate according to some embodiments Figure 1F A perspective view of a semiconductor device structure.

[0013] Figure 1F-2 To illustrate according to some embodiments Figure 1F-1 A cross-sectional view of the semiconductor device structure along the section line 1F-2-1F-2'.

[0014] Figure 2A-2E The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0015] Figure 2E-1 To illustrate according to some embodiments Figure 2E A perspective view of a semiconductor device structure.

[0016] Figure 2E-2 To illustrate according to some embodiments Figure 2E-1 A cross-sectional view of the semiconductor device structure along the section line 2E-2-2E-2'.

[0017] Figures 3A-3D The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0018] Figure 3D-1 To illustrate according to some embodiments Figure 3D A perspective view of a semiconductor device structure.

[0019] Figure 3D-2 To illustrate according to some embodiments Figure 3D-1 A cross-sectional view of the semiconductor device structure along the section line 3D-2-3D-2'.

[0020] Figures 4A-4C The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0021] Figure 4C-1 To illustrate according to some embodiments Figure 4C A perspective view of a semiconductor device structure.

[0022] Figure 4C-2 To illustrate according to some embodiments Figure 4C-1 A cross-sectional view of the semiconductor device structure along the section line 4C-2-4C-2'.

[0023] Figures 5A-5D The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0024] Figure 5D-1 To illustrate according to some embodiments Figure 5D A perspective view of a semiconductor device structure.

[0025] Figure 5D-2 To illustrate according to some embodiments Figure 5D-1 A cross-sectional view of the semiconductor device structure along the section line 5D-2-5D-2'.

[0026] Figures 6A-6C The figures are cross-sectional views illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0027] Figure 6C-1 To illustrate according to some embodiments Figure 6C A perspective view of a semiconductor device structure.

[0028] Figure 6C-2 To illustrate according to some embodiments Figure 6C-1 A cross-sectional view of the semiconductor device structure along the section line 6C-2-6C-2'.

[0029] The reference numerals are as follows:

[0030] 100, 200, 300, 400, 500, 600: semiconductor device structure

[0031] 110:Substrate

[0032] 112: base

[0033] 114: Fins

[0034] 114a: vertical axis

[0035] 120: Nanostructure Stacking

[0036] 120a: Groove

[0037] 120b: Inner wall

[0038] 121,122,123,124,125,126,127,128: Nanostructures

[0039] 121a,122a,123a,124a,125a,126a,127a,128a: Side walls

[0040] 130: Isolation layer

[0041] 140: Gate stack

[0042] 142: Gate dielectric layer

[0043] 142a: Side wall

[0044] 144: Gate electrode

[0045] 144a: Side wall

[0046] 150: mask layer

[0047] 152: Sidewall

[0048] 160: spacer structure

[0049] 162: spacer layer

[0050] 164: spacer layer

[0051] 166: Groove

[0052] 170: inner spacer material layer

[0053] 171: Film layer

[0054] 171a: Side wall

[0055] 172,174,176,178:Internal spacer

[0056] 172a, 174a, 176a, 178a: Sidewall

[0057] 180: Stress source structure

[0058] 190: Dielectric layer

[0059] 210: Gate stack

[0060] 212: Gate dielectric layer

[0061] 214: Work function metal layer

[0062] 216: Gate electrode layer

[0063] T: Groove

[0064] W120a: Width

[0065] W122, W124, W126, W128: Width

[0066] W172, W174, W176, W178: Width

[0067] W180: Width

[0068] R1, R2, R3, R4: groove

[0069] 1F-2-1F-2',2E-2-2E-2',3D-2-3D-2',4C-2-4C-2',5D-2-5D-2',6C-2-6C-2': Section Line

[0070] V1, V2, V3, V4: gap

[0071] W1, W2, W3, W4: width

[0072] W5,W6,W7,W8: Width

[0073] 1A-1A', 1F-1F', 2E-2E', 3D-3D', 4C-4C', 5D-5D': Section lines DETAILED DESCRIPTION

[0074] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the embodiments of the present invention may reuse numbers and / or text in each example. Such repetition is for the sake of brevity and clarity, and does not represent the relationship between the various embodiments and / or forms discussed.

[0075] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein. These spatially relative terms are used to facilitate describing the relationship between one (or some) element or feature and another (or some) element or feature in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is rotated to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used herein will also be interpreted based on the orientation after the rotation. It should be understood that additional operations may be provided before, during, and / or after the stages described in these embodiments, and other embodiments of the method may replace or eliminate some operations.

[0076] The term "substantially" in the description, such as "substantially flat" or "substantially coplanar", etc., can be understood by those of ordinary skill in the art. In some embodiments, the adjective "substantially" can be removed. Where applicable, the term "substantially" can also include embodiments of "entirely", "completely", "all", etc. Where applicable, the term "substantially" can also refer to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. In addition, the term "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from a specific arrangement, and can include, for example, deviations of up to 10°. The word "substantially" does not exclude "completely", for example, a composition that "substantially does not contain" Y may not contain Y at all.

[0077] The term "about" in conjunction with a specific distance or size may be interpreted as not excluding minor deviations from the specific distance or size and may include deviations of up to 10%, for example. The term "about" relative to a numerical value x may mean x±5 or 10%.

[0078] Several embodiments of the present invention have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated in different embodiments. Even if some embodiments perform operations in a specific order, these operations may also be performed in another logical order.

[0079] The gate all around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing for the creation of patterns having, for example, a smaller pitch than would be achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the gate all around structure.

[0080] According to some embodiments, Figure 1A-1F A cross-sectional view illustrating various stages of a process for forming a semiconductor device structure is shown. According to some embodiments, Figure 1A-1 Show Figure 1A A perspective view of a semiconductor device structure.

[0081] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, a substrate 110 is provided. According to some embodiments, the substrate 110 has a base 112 and a fin 114 on the base 112. The substrate 110 includes, for example, a semiconductor substrate. The substrate 110 includes, for example, a semiconductor wafer (eg, a silicon wafer) or a portion of a silicon wafer.

[0082] In some embodiments, substrate 110 is made of an elemental semiconductor material, including single crystal, polycrystalline, or amorphous silicon or germanium. In other embodiments, substrate 110 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination thereof. Substrate 110 may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0083] In some embodiments, substrate 110 is a device wafer that includes various device components. In some embodiments, the various device components are formed within and / or on substrate 110. For the sake of clarity and simplicity, the various device components are not shown in the figures. Examples of the various device components include active devices, passive devices, other suitable components, or combinations thereof. Active components may include transistors or diodes (not shown) formed on the surface of substrate 110. Passive components may include resistors, capacitors, or other suitable passive components.

[0084] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.

[0085] Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various device components. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0086] In some embodiments, isolation features (not shown) are formed in substrate 110. The isolation features are used to define active regions and electrically isolate device components in the active regions within and / or on substrate 110. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0087] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, nanostructure stack 120 is formed on fin 114. According to some embodiments, nanostructure stack 120 includes nanostructures 121, 122, 123, 124, 125, 126, 127, and 128.

[0088] According to some embodiments, nanostructures 121, 122, 123, 124, 125, 126, 127, and 128 are sequentially stacked on fin 114. According to some embodiments, nanostructures 121, 122, 123, 124, 125, 126, 127, and 128 include nanowires or nanosheets.

[0089] According to some embodiments, nanostructures 121, 123, 125, and 127 are made of the same first material. According to some embodiments, the first material is different from the material of substrate 110. According to some embodiments, the first material includes an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0090] According to some embodiments, the first material includes a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe, or GaAsP, or a combination thereof.

[0091] According to some embodiments, nanostructures 122, 124, 126, and 128 are made of the same second material. According to some embodiments, the second material is different from the first material. According to some embodiments, the second material is the same as the material of substrate 110. According to some embodiments, the second material comprises an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0092] According to some embodiments, the second material includes a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe, or GaAsP, or a combination thereof.

[0093] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, an isolation layer 130 is formed on the base 112. According to some embodiments, the fin 114 is partially buried in the isolation layer 130. According to some embodiments, the fin 114 is surrounded by the isolation layer 130.

[0094] According to some embodiments, the isolation layer 130 is made of a dielectric material such as an oxygen-containing material (e.g., silicon oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a low-k (low dielectric constant) material, a porous dielectric material, glass, or a combination thereof. According to some embodiments, the glass includes borosilicate glass (BSG), phosphoricsilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof.

[0095] According to some embodiments, the isolation layer 130 is formed using a deposition process or a spin coating process, a chemical mechanical polishing process, and an etch-back process. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a flowable chemical vapor deposition (FCVD) process, a sputtering process, or a combination thereof.

[0096] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, a gate stack 140 is formed on the nanostructure stack 120, the fin 114 and the isolation layer 130. According to some embodiments, for the sake of simplicity, Figure 1A-1 Only one of the gate stacks 140 is shown. Figure 1A As shown in FIG, trenches T are located between adjacent gate stacks 140 to separate adjacent gate stacks 140 from each other.

[0097] According to some embodiments, each gate stack 140 includes a gate dielectric layer 142 and a gate electrode 144. According to some embodiments, the gate electrode 144 is located on the gate dielectric layer 142. According to some embodiments, the gate dielectric layer 142 is located between the gate electrode 144 and the nanostructure stack 120.

[0098] According to some embodiments, the gate dielectric layer 142 is also located between the gate electrode 144 and the fin 114. According to some embodiments, the gate dielectric layer 142 is located between the gate electrode 144 and the isolation layer 130.

[0099] According to some embodiments, the gate dielectric layer 142 is made of an oxygen-containing material, such as silicon oxide. According to some embodiments, the gate dielectric layer 142 is formed using a chemical vapor deposition process and an etching process. According to some embodiments, the gate electrode 144 is made of a semiconductor material, such as polysilicon. According to some embodiments, the gate electrode 144 is formed using a chemical vapor deposition process and an etching process.

[0100] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, a mask layer 150 is formed on the gate stack 140. According to some embodiments, the mask layer 150 is made of a material different from the material of the gate stack 140. According to some embodiments, the mask layer 150 is made of a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride).

[0101] According to some embodiments, Figure 1A and Figure 1A-1 As shown in FIG, a spacer structure 160 is formed on the gate dielectric layer 142, the gate electrode 144, and the sidewalls 142a, 144a, and 152 of the mask layer 150. According to some embodiments, the spacer structure 160 surrounds the gate stack 140 and the mask layer 150. According to some embodiments, the spacer structure 160 is located above the nanostructure stack 120, the fin structure 114, and the isolation layer 130.

[0102] According to some embodiments, the spacer structure 160 includes spacer layers 162 and 164. According to some embodiments, the spacer layer 162 is located between the spacer layer 164 and the gate stack 140. According to some embodiments, the spacer layer 162 is also located between the spacer layer 164 and the mask layer 150. According to some embodiments, the spacer layers 162 and 164 are made of different materials. In some other embodiments, the spacer layers 162 and 164 are made of the same material.

[0103] According to some embodiments, the spacer layers 162 and 164 include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. According to some embodiments, the spacer layers 162 and 164 are made of a different material than the gate stack 140 and the mask layer 150. According to some embodiments, forming the spacer layers 162 and 164 includes a deposition process and an anisotropic etching process.

[0104] According to some embodiments, Figure 1B As shown in FIG, portions of the nanostructure stack 120 not covered by the gate stack 140 and the spacer structure 160 are removed. According to some embodiments, the removal process forms trenches 120a in the nanostructure stack 120 and the fin 114.

[0105] According to some embodiments, each trench 120a has a width W120a that decreases toward the fin 114. According to some embodiments, the width W120a is measured along the longitudinal axis 114a of the fin 114. According to some embodiments, Figure 1A-1F 、 Figure 2A-2E 、 Figures 3A-3D 、 Figures 4A-4C 、 Figures 5A-5D and Figures 6A-6C The width shown in is measured along the longitudinal axis 114 a of the fin 114. According to some embodiments, the removal process includes an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0106] According to some embodiments, Figure 1CAs shown in FIG, the ends of nanostructures 121, 123, 125, and 127 are removed by trenches 120a and T. According to some embodiments, the removal process forms recesses R1, R2, R3, and R4 in nanostructure stack 120. According to some embodiments, recess R1 is located between fin 114 and nanostructure 122.

[0107] According to some embodiments, recess R2 is located between nanostructures 122 and 124. According to some embodiments, recess R3 is located between nanostructures 124 and 126. According to some embodiments, recess R4 is located between nanostructures 126 and 128. According to some embodiments, the removal process includes an etching process, such as a dry etching process or a wet etching process.

[0108] According to some embodiments, Figure 1C As shown in FIG, an inner spacer material layer 170 is formed over the mask layer 150, the spacer structure 160, the nanostructure stack 120, and the fin 114. According to some embodiments, the recesses R1, R2, R3, and R4 are filled with the inner spacer material layer 170. According to some embodiments, the inner spacer material layer 170 directly contacts the sidewalls 121a, 123a, 125a, and 127a of the nanostructures 121, 123, 125, and 127.

[0109] According to some embodiments, the inner spacer material layer 170 is made of an insulating material such as an oxygen-containing material (e.g., silicon oxide), a nitrogen-containing material (e.g., silicon nitride), a nitrogen-oxygen-containing material (e.g., silicon oxynitride), a carbon-containing material (e.g., silicon carbide), a high dielectric constant material (e.g., HfO2, ZrO2, HfZrO2, or Al2O3), or a low dielectric constant material.

[0110] According to some embodiments, the term "high-k dielectric constant material" refers to a material having a dielectric constant greater than that of silicon dioxide. According to some embodiments, the term "low-k dielectric constant material" refers to a material having a dielectric constant less than that of silicon dioxide. According to some embodiments, the inner spacer material layer 170 is formed using a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a similar process.

[0111] According to some embodiments, Figure 1D As shown in FIG, portions of the inner spacer material layer 170 outside the grooves R1, R2, R3, and R4 are removed to form inner spacers 172, 174, 176, and 178 in the grooves R1, R2, R3, and R4, respectively. According to some embodiments, the inner spacer 172 (or the groove R1) has a width W172.

[0112] According to some embodiments, inner spacer 174 (or groove R2) has a width W174. According to some embodiments, inner spacer 176 (or groove R3) has a width W176. According to some embodiments, inner spacer 178 (or groove R4) has a width W178.

[0113] According to some embodiments, width W172 is greater than width W174. That is, according to some embodiments, inner spacer 172 (or recess R1) is wider than inner spacer 174 (or recess R2). According to some embodiments, width W174 is wider than width W176 or W178. That is, according to some embodiments, inner spacer 174 (or recess R2) is wider than inner spacer 176 or 178 (or recess R3 or R4).

[0114] According to some embodiments, width W176 and width W178 are approximately equal. According to some embodiments, width W172 ranges from approximately 4 nm to approximately 14 nm. According to some embodiments, width W174 ranges from approximately 3 nm to approximately 12 nm. According to some embodiments, width W176 ranges from approximately 2 nm to approximately 10 nm. According to some embodiments, width W178 ranges from approximately 2 nm to approximately 10 nm.

[0115] In some embodiments, the sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a of the nanostructure 128, inner spacer 178, nanostructure 126, inner spacer 176, nanostructure 124, inner spacer 174, nanostructure 122, and inner spacer 172, together with the surface 116 of the substrate 110, form a continuous inner wall of the trench 120a.

[0116] According to some embodiments, each sidewall 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 is aligned with adjacent sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and adjacent surface 116. According to some embodiments, sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 collectively form a continuously curved inner wall of trench 120a. According to some embodiments, sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a collectively form a continuously curved inner wall.

[0117] According to some embodiments, Figure 1EAs shown in FIG, stressor structures 180 are formed in trenches 120a. According to some embodiments, stressor structures 180 are connected to nanostructures 122, 124, 126, and 128. According to some embodiments, stressor structures 180 directly contact nanostructures 122, 124, 126, and 128, inner spacers 172, 174, 176, and 178, and substrate 110. According to some embodiments, each stressor structure 180 has a width W180 that decreases toward substrate 110.

[0118] According to some embodiments, the stressor structure 180 is made of a semiconductor material (eg, silicon germanium) having a P-type dopant, such as a Group IIIA element, such as boron or other suitable materials.

[0119] According to some embodiments, the stressor structure 180 is formed of a semiconductor material (e.g., silicon) having an N-type dopant, such as a Group VA element. Group VA elements include phosphorus (P), antimony (Sb), or other suitable Group VA materials. According to some embodiments, the stressor structure 180 is formed using an epitaxial process.

[0120] According to some embodiments, Figure 1E As shown in FIG, a dielectric layer 190 is formed on the stressor structure 180. The dielectric layer 190 includes a dielectric material such as an oxygen-containing material (such as silicon oxide), a nitrogen-containing oxygen material (such as silicon oxynitride), a low-k dielectric constant material, a porous dielectric material, glass, or a combination thereof.

[0121] According to some embodiments, the glass includes borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof. According to some embodiments, the dielectric layer 190 is formed by a deposition process (e.g., a chemical deposition process) and a planarization process (e.g., a chemical mechanical polishing process).

[0122] According to some embodiments, Figure 1E and Figure 1F As shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms a trench 166 in the spacer structure 160. According to some embodiments, as Figure 1E and Figure 1FAs shown in FIG, nanostructures 121, 123, 125, and 127 are removed through trench 166. According to some embodiments, the removal process of gate stack 140, mask layer 150, and nanostructures 121, 123, 125, and 127 includes an etching process such as a wet etching process or a dry etching process.

[0123] According to some embodiments, Figure 1F-1 for Figure 1F According to some embodiments, Figure 1F-2 for Figure 1F-1 A cross-sectional view of the semiconductor device structure along the section line 1F-2-1F-2'.

[0124] According to some embodiments, Figure 1F 、 Figure 1F-1 and Figure 1F-2 As shown in FIG, a gate stack 210 is formed in the trench 166. In this step, the semiconductor device structure 100 is substantially formed. According to some embodiments, the gate stack 210 surrounds the nanostructures 122, 124, 126, and 128.

[0125] According to some embodiments, gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of nanostructures 122, 124, 126, and 128 and trench 166. Gate dielectric layer 212 is made of a high-k material such as HfO2, ZrO2, HfZrO2, or Al2O3. Gate dielectric layer 212 is formed using an atomic layer deposition process or other suitable process.

[0126] According to some embodiments, a work function metal layer 214 is conformally formed on the gate dielectric layer 212. The work function metal layer 214 is made of TiN, TaN, TiSiN, or other suitable conductive materials. The work function metal layer 214 is formed using an atomic layer deposition process or other suitable process.

[0127] According to some embodiments, a gate electrode layer 216 is formed on the work function metal layer 214. The gate electrode layer 216 is made of W, Co, Al, or other suitable conductive materials and is formed using an atomic layer deposition process or other suitable process.

[0128] According to some embodiments, Figure 1F As shown in FIG, nanostructures 122, 124, 126, and 128 pass through gate stack 210. According to some embodiments, nanostructure 122 is wider than nanostructure 124. That is, according to some embodiments, a width W122 of nanostructure 122 is wider than a width W124 of nanostructure 124.

[0129] According to some embodiments, nanostructure 124 is wider than nanostructure 126. That is, according to some embodiments, width W124 of nanostructure 124 is wider than width W126 of nanostructure 126. According to some embodiments, width W126 is substantially equal to width W128 of nanostructure 128.

[0130] According to some embodiments, stressor structures 180 adjacent to nanostructure 122 are narrower than stressor structures 180 adjacent to nanostructure 124. According to some embodiments, stressor structures 180 adjacent to inner spacers 172 are narrower than stressor structures 180 adjacent to inner spacers 174. According to some embodiments, fin 114 and nanostructures 122, 124, 126, and 128 are spaced apart from one another.

[0131] According to some embodiments, Figure 2A-2E The cross-sectional view of each stage of the process for forming a semiconductor device structure is shown in FIG. Figure 1B After the steps, Figure 2A As shown in FIG, a portion of the nanostructure stack 120 is removed from the inner wall 120b of the trench 120a to enlarge the trench 120a.

[0132] According to some embodiments, nanostructure 128 is wider than nanostructure 122. According to some embodiments, nanostructure 122 is wider than nanostructure 126. According to some embodiments, nanostructure 126 is wider than nanostructure 124. According to some embodiments, the removal process includes an isotropic etching process or a wet etching process.

[0133] According to some embodiments, Figure 2B As shown in FIG, the ends of nanostructures 121, 123, 125, and 127 are removed by trenches 120a and T. According to some embodiments, the removal process forms recesses R1, R2, R3, and R4 in nanostructure stack 120. According to some embodiments, recess R1 is located between fin 114 and nanostructure 122.

[0134] According to some embodiments, recess R2 is located between nanostructures 122 and 124. According to some embodiments, recess R3 is located between nanostructures 124 and 126. According to some embodiments, recess R4 is located between nanostructures 126 and 128. According to some embodiments, the removal process includes an etching process such as a dry etching process or a wet etching process.

[0135] According to some embodiments, Figure 2BAs shown in FIG, an inner spacer material layer 170 is formed over the mask layer 150, the spacer structure 160, the nanostructure stack 120, and the fin 114. According to some embodiments, the recesses R1, R2, R3, and R4 are filled with the inner spacer material layer 170. According to some embodiments, the inner spacer material layer 170 directly contacts the sidewalls 121a, 123a, 125a, and 127a of the nanostructures 121, 123, 125, and 127.

[0136] According to some embodiments, Figure 2C As shown in FIG, portions of the inner spacer material layer 170 outside of the recesses R1, R2, R3, and R4 are removed to form inner spacers 172, 174, 176, and 178 in the recesses R1, R2, R3, and R4, respectively. According to some embodiments, the inner spacer 172 (or recess R1) has a width W172. According to some embodiments, the inner spacer 174 (or recess R2) has a width W174. According to some embodiments, the inner spacer 176 (or recess R3) has a width W176. According to some embodiments, the inner spacer 178 (or recess R4) has a width W178.

[0137] According to some embodiments, width W172 is greater than width W178. That is, according to some embodiments, inner spacer 172 (or recess R1) is wider than inner spacer 178 (or recess R4). According to some embodiments, width W172 is greater than width W178. According to some embodiments, width W178 is greater than width W176 or W174. That is, according to some embodiments, inner spacer 178 (or recess R4) is wider than inner spacer 176 or 174 (or recess R3 or R2).

[0138] According to some embodiments, width W176 is substantially equal to width W174. According to some embodiments, width W172 is in a range of about 4 nm to about 14 nm. According to some embodiments, width W174 is in a range of about 2 nm to about 9 nm. According to some embodiments, width W176 is in a range of about 2 nm to about 9 nm. According to some embodiments, width W178 is in a range of about 3 nm to about 10 nm.

[0139] In some embodiments, sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a of the nanostructure 128, inner spacer 178, nanostructure 126, inner spacer 176, nanostructure 124, inner spacer 174, nanostructure 122, and inner spacer 172, and the surface 116 of the substrate 110 collectively form a continuous inner wall of the trench 120a.

[0140] According to some embodiments, each sidewall 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 is aligned with adjacent sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and adjacent surface 116. According to some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0141] According to some embodiments, Figure 2D As shown in FIG, a stressor structure 180 is formed in the trench 120a. According to some embodiments, the stressor structure 180 is connected to the nanostructures 122, 124, 126, and 128. According to some embodiments, the stressor structure 180 is in direct contact with the nanostructures 122, 124, 126, and 128, the inner spacers 172, 174, 176, and 178, and the substrate 110.

[0142] According to some embodiments, Figure 2D As shown in FIG, a dielectric layer 190 is formed over the stressor structure 180. According to some embodiments, the stressor structure 180 has a width W180 that continuously decreases toward the fin 114. According to some embodiments, the width W180 also continuously decreases toward the dielectric layer 190.

[0143] According to some embodiments, Figure 2D and Figure 2E As shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms the trench 166 in the spacer structure 160. According to some embodiments, as Figure 2D and Figure 2E As shown in FIG, nanostructures 121, 123, 125, and 127 are removed through trench 166. According to some embodiments, the removal process of gate stack 140, mask layer 150, and nanostructures 121, 123, 125, and 127 includes an etching process such as a wet etching process or a dry etching process.

[0144] According to some embodiments, Figure 2E-1 for Figure 2E According to some embodiments, Figure 2E-2 For semiconductor device structures along Figure 2E-1 The cross-sectional view is shown along the section line 2E-2-2E-2'.

[0145] According to some embodiments, Figure 2E 、 Figure 2E-1 and Figure 2E-2As shown in FIG, a gate stack 210 is formed in the trench 166. In this step, the semiconductor device structure 200 is substantially formed. According to some embodiments, the gate stack 210 surrounds the nanostructures 122, 124, 126, and 128.

[0146] According to some embodiments, the gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, the gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of the nanostructures 122, 124, 126, and 128 and the trench 166. According to some embodiments, the work function metal layer 214 conformally covers the gate dielectric layer 212. According to some embodiments, the gate electrode layer 216 is formed on the work function metal layer 214.

[0147] According to some embodiments, Figure 2E , nanostructures 122, 124, 126, and 128 pass through gate stack 210. According to some embodiments, width W128 of nanostructure 128 is wider than width W122 of nanostructure 122. According to some embodiments, width W122 is wider than width W126 of nanostructure 126. According to some embodiments, width W126 is wider than width W124 of nanostructure 124.

[0148] According to some embodiments, when the semiconductor device structure 200 operates, current is applied from the top of the stressor structure 180 into the stressor structure 180. Therefore, current flows more easily into the upper nanostructures (e.g., nanostructure 128) than into the lower nanostructures (e.g., nanostructure 124 or 122), which reduces the uniformity of current flowing through the nanostructures 122, 124, 126, and 128. Since nanostructure 128 is wider and has a higher resistance, it reduces the current flowing through nanostructure 128 and, therefore, improves the uniformity of current flowing through the nanostructures 122, 124, 126, and 128.

[0149] According to some embodiments, stressor structures 180 adjacent to nanostructure 122 are narrower than stressor structures 180 adjacent to nanostructure 124. According to some embodiments, stressor structures 180 adjacent to nanostructure 126 are narrower than stressor structures 180 adjacent to nanostructure 124.

[0150] According to some embodiments, stressor structures 180 adjacent to nanostructure 128 are narrower than stressor structures 180 adjacent to nanostructure 126. According to some embodiments, stressor structures 180 adjacent to inner spacer 172 are narrower than stressor structures 180 adjacent to inner spacer 174. According to some embodiments, fin 114 and nanostructures 122, 124, 126, and 128 are spaced apart from one another.

[0151] According to some embodiments, Figures 3A-3D The cross-sectional view of each stage of the process for forming a semiconductor device structure. According to some embodiments, Figure 1B After the steps, Figure 3A As shown in FIG, the ends of nanostructures 121, 123, 125, and 127 are removed by trenches 120a and T. According to some embodiments, the removal process forms recesses R1, R2, R3, and R4 in nanostructure stack 120. According to some embodiments, recess R1 is located between fin 114 and nanostructure 122.

[0152] According to some embodiments, recess R2 is located between nanostructures 122 and 124. According to some embodiments, recess R3 is located between nanostructures 124 and 126. According to some embodiments, recess R4 is located between nanostructures 126 and 128. According to some embodiments, the removal process includes an etching process such as a dry etching process or a wet etching process.

[0153] According to some embodiments, Figure 3A As shown in FIG, an inner spacer material layer 170 is formed over the mask layer 150, the spacer structure 160, the nanostructure stack 120, and the fin 114. According to some embodiments, the inner spacer material layer 170 covers the recesses R1, R2, R3, and R4. According to some embodiments, the inner spacer material layer 170 directly contacts the sidewalls 121a, 123a, 125a, and 127a of the nanostructures 121, 123, 125, and 127.

[0154] According to some embodiments, the inner spacer material layer 170 has voids V1, V2, V3, and V4. According to some embodiments, the voids V1, V2, V3, and V4 are respectively located within the recesses R1, R2, R3, and R4. According to some embodiments, the voids V1, V2, V3, and V4 are also referred to as air voids. According to some embodiments, the inner spacer material layer 170 is formed using a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a similar process.

[0155] According to some embodiments, Figure 3A and Figure 3B As shown in FIG, portions of the inner spacer material layer 170 outside the recesses R1, R2, R3, and R4 are removed to form inner spacers 172, 174, 176, and 178 within the recesses R1, R2, R3, and R4, respectively. In some embodiments, the voids V1, V2, V3, and V4 are closed voids. In some other embodiments, the voids V1, V2, V3, and V4 are open voids.

[0156] According to some embodiments, void V1 has a width W1. According to some embodiments, void V2 has a width W2. According to some embodiments, void V3 has a width W3. According to some embodiments, void V4 has a width W4.

[0157] According to some embodiments, width W1 is greater than width W2. That is, gap V1 is wider than gap V2. According to some embodiments, width W2 is greater than width W3 or W4. That is, gap V2 is wider than gap V3 or V4.

[0158] According to some embodiments, width W3 is substantially equal to width W4. According to some embodiments, width W1 is in a range of about 5 nm to about 10 nm. According to some embodiments, width W2 is in a range of about 4 nm to about 8 nm. According to some embodiments, width W3 is in a range of about 3 nm to about 6 nm. According to some embodiments, width W4 is in a range of about 3 nm to about 6 nm.

[0159] In some embodiments, sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a of nanostructure 128, inner spacer 178, nanostructure 126, inner spacer 176, nanostructure 124, inner spacer 174, nanostructure 122, and inner spacer 172, and surface 116 of substrate 110 collectively form a continuous inner wall of trench 120a. According to some embodiments, each sidewall 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 is aligned with adjacent sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and adjacent surface 116.

[0160] According to some embodiments, Figure 3C As shown in FIG, a stressor structure 180 is formed in the trench 120a. According to some embodiments, the stressor structure 180 is connected to the nanostructures 122, 124, 126, and 128. According to some embodiments, the stressor structure 180 is in direct contact with the nanostructures 122, 124, 126, and 128, the inner spacers 172, 174, 176, and 178, and the substrate 110. According to some embodiments, as Figure 3C As shown in FIG, a dielectric layer 190 is formed on the stressor structure 180 .

[0161] According to some embodiments, Figure 3C and Figure 3D As shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms the trench 166 in the spacer structure 160. According to some embodiments, as Figure 3C and Figure 3DAs shown in FIG, nanostructures 121 , 123 , 125 , and 127 are removed by trench 166 .

[0162] According to some embodiments, Figure 3D-1 for Figure 3D According to some embodiments, Figure 3D-2 For semiconductor device structures along Figure 3D-1 The cross-sectional view is shown along the section line 3D-2-3D-2'.

[0163] According to some embodiments, Figure 3D 、 Figure 3D-1 and Figure 3D-2 As shown in FIG, a gate stack 210 is formed in the trench 166. In this step, the semiconductor device structure 300 is generally formed. According to some embodiments, the gate stack 210 surrounds the nanostructures 122, 124, 126, and 128.

[0164] According to some embodiments, the gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, the gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of the nanostructures 122, 124, 126, and 128 and the trench 166. According to some embodiments, the work function metal layer 214 conformally covers the gate dielectric layer 212. According to some embodiments, the gate electrode layer 216 is formed on the work function metal layer 214.

[0165] According to some embodiments, Figure 3D As shown, voids V1, V2, V3, and V4 are filled with air. That is, according to some embodiments, voids V1, V2, V3, and V4 are air voids. According to some embodiments, because air has a low dielectric constant (approximately 1), forming voids V1, V2, V3, and V4 can reduce parasitic capacitance between gate stack 210 and stressor structure 180. Therefore, according to some embodiments, the performance of semiconductor device structure 300 is improved.

[0166] According to some embodiments, voids V1, V2, V3, and V4 have a teardrop shape (or a water drop shape). According to some embodiments, nanostructure 122 is wider than nanostructure 124. According to some embodiments, nanostructure 124 is wider than nanostructure 126 or 128.

[0167] According to some embodiments, the stressor structure 180 adjacent to the nanostructure 122 is narrower than the stressor structure 180 adjacent to the nanostructure 124. According to some embodiments, the stressor structure 180 adjacent to the inner spacer 172 is narrower than the stressor structure 180 adjacent to the inner spacer 174. According to some embodiments, the stressor structure 180 adjacent to the inner spacer 174 is narrower than the stressor structure 180 adjacent to the inner spacer 176.

[0168] According to some embodiments, Figures 4A-4C The cross-sectional view of each stage of the process for forming a semiconductor device structure is shown in FIG. Figure 1B After the steps, Figure 4A As shown in FIG, the ends of nanostructures 121, 123, 125, and 127 are removed by trench 120a. According to some embodiments, the removal process forms recesses R1, R2, R3, and R4 in nanostructure stack 120. According to some embodiments, recess R1 is located between fin 114 and nanostructure 122.

[0169] According to some embodiments, recess R2 is located between nanostructures 122 and 124. According to some embodiments, recess R3 is located between nanostructures 124 and 126. According to some embodiments, recess R4 is located between nanostructures 126 and 128. According to some embodiments, the removal process includes an etching process such as a dry etching process or a wet etching process.

[0170] According to some embodiments, Figure 4A As shown in FIG, an inner spacer material layer 170 is formed over the mask layer 150, the spacer structure 160, the nanostructure stack 120, and the fin 114. According to some embodiments, the inner spacer material layer 170 covers the recesses R1, R2, R3, and R4. According to some embodiments, the inner spacer material layer 170 directly contacts the nanostructures 121, 122, 123, 124, 125, 126, 127, and 128.

[0171] According to some embodiments, the inner spacer material layer 170 has voids V1, V2, V3, and V4. According to some embodiments, the voids V1, V2, V3, and V4 are respectively within the recesses R1, R2, R3, and R4. According to some embodiments, the inner spacer material layer 170 is formed using a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a similar process.

[0172] According to some embodiments, Figure 4A As shown in FIG, a film layer 171 is conformally formed on the inner spacer material layer 170. According to some embodiments, the film layer 171 conformably covers the inner walls of the voids V1, V2, V3, and V4. According to some embodiments, the film layer 171 and the inner spacer material layer 170 are made of different materials. According to some embodiments, the dielectric constant of the material of the inner spacer material layer 170 is greater than the dielectric constant of the material of the film layer 171.

[0173] According to some embodiments, the film layer 171 is made of an insulating material such as an oxygen-containing material (eg, silicon oxide), a nitrogen-containing material (eg, silicon nitride), a nitrogen-oxygen-containing material (eg, silicon oxynitride), a carbon-containing material (eg, silicon carbide), or a low-k dielectric constant material.

[0174] The film layer 171 is formed using a deposition process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. In some embodiments, the inner spacer material layer 170 is formed using a physical vapor deposition process, and the film layer 171 is formed using an atomic layer deposition process.

[0175] According to some embodiments, Figure 4A and Figure 4B As shown in FIG, portions of the inner spacer material layer 170 and the film layer 171 outside the grooves R1, R2, R3 and R4 are removed to form inner spacers 172, 174, 176 and 178 in the grooves R1, R2, R3 and R4, respectively.

[0176] According to some embodiments, inner spacer 172 includes inner spacer material layer 170 and film layer 171 remaining in recess R1. According to some embodiments, inner spacer 174 includes inner spacer material layer 170 and film layer 171 remaining in recess R2. According to some embodiments, inner spacer 176 includes inner spacer material layer 170 and film layer 171 remaining in recess R3. According to some embodiments, inner spacer 178 includes inner spacer material layer 170 and film layer 171 remaining in recess R4.

[0177] According to some embodiments, void V1 in inner spacer 172 has width W1. According to some embodiments, void V2 in inner spacer 174 has width W2. According to some embodiments, void V3 in inner spacer 176 has width W3. According to some embodiments, void V4 in inner spacer 178 has width W4.

[0178] According to some embodiments, width W1 is greater than width W2. That is, gap V1 is wider than gap V2. According to some embodiments, width W2 is greater than width W3 or W4. That is, gap V2 is wider than gap V3 or V4.

[0179] According to some embodiments, width W3 is substantially equal to width W4. According to some embodiments, width W1 is in a range of about 5 nm to about 10 nm. According to some embodiments, width W2 is in a range of about 4 nm to about 8 nm. According to some embodiments, width W3 is in a range of about 3 nm to about 6 nm. According to some embodiments, width W4 is in a range of about 3 nm to about 6 nm.

[0180] In some embodiments, sidewalls 128a, 171a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a of nanostructure 128, film layer 171, inner spacer 178, nanostructure 126, inner spacer 176, nanostructure 124, inner spacer 174, nanostructure 122, and inner spacer 172, and surface 116 of substrate 110 collectively form a continuous inner wall of trench 120a. According to some embodiments, each sidewall 128a, 171a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 is aligned with adjacent sidewalls 128a, 171a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and adjacent surface 116.

[0181] According to some embodiments, Figure 4C As shown in FIG, a stressor structure 180 is formed in the trench 120a. According to some embodiments, the stressor structure 180 is connected to the nanostructures 122, 124, 126, and 128. According to some embodiments, the stressor structure 180 is in direct contact with the nanostructures 122, 124, 126, and 128, the inner spacers 172, 174, 176, and 178, the film layer 171, and the substrate 110. According to some embodiments, as Figure 4C As shown in FIG, a dielectric layer 190 is formed on the stressor structure 180 .

[0182] According to some embodiments, Figure 4B and Figure 4C As shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms the trench 166 in the spacer structure 160. According to some embodiments, as Figure 4B and Figure 4C As shown in FIG, nanostructures 121 , 123 , 125 , and 127 are removed by trench 166 .

[0183] According to some embodiments, Figure 4C-1 for Figure 4C According to some embodiments, Figure 4C-2 For semiconductor device structures along Figure 4C-1 The cross-sectional view is shown along the section line 4C-2-4C-2'.

[0184] According to some embodiments, Figure 4C 、 Figure 4C-1 and Figure 4C-2 As shown in FIG, gate stack 210 is formed in trench 166. In this step, semiconductor device structure 400 is generally formed. According to some embodiments, gate stack 210 surrounds nanostructures 122, 124, 126, and 128.

[0185] According to some embodiments, gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of nanostructures 122, 124, 126, and 128 and trenches 166.

[0186] According to some embodiments, a work function metal layer 214 is conformally formed on the gate dielectric layer 212. According to some embodiments, a gate electrode layer 216 is formed on the work function metal layer 214.

[0187] According to some embodiments, Figure 4C As shown, voids V1, V2, V3, and V4 are filled with air. That is, according to some embodiments, voids V1, V2, V3, and V4 are air voids. According to some embodiments, the voids have a teardrop shape. According to some embodiments, nanostructure 122 is wider than nanostructure 124. According to some embodiments, nanostructure 124 is wider than nanostructures 126 or 128.

[0188] According to some embodiments, the stressor structure 180 adjacent to the inner spacer 172 is narrower than the stressor structure 180 adjacent to the inner spacer 174. According to some embodiments, the stressor structure 180 adjacent to the inner spacer 174 is narrower than the stressor structure 180 adjacent to the inner spacer 176. According to some embodiments, the stressor structure 180 adjacent to the inner spacer 174 is narrower than the stressor structure 180 adjacent to the inner spacer 176. According to some embodiments, the stressor structure 180 adjacent to the inner spacer 176 and the stressor structure 180 adjacent to the inner spacer 178 have substantially the same width.

[0189] According to some embodiments, the dielectric constant of the material of the inner spacers 172, 174, 176, and 178 is greater than the dielectric constant of the material of the film layer 171. Therefore, according to some embodiments, the inner spacers 172, 174, 176, and 178 having a higher dielectric constant can prevent the gate stack 210 from being broken down. Thus, according to some embodiments, the inner spacers 172, 174, 176, and 178 can prevent the gate stack 210 and the stressor structure 180 from being short-circuited.

[0190] According to some embodiments, the film layer 171 having a lower dielectric constant can reduce the parasitic capacitance between the gate stack 210 and the stressor structure 180. Therefore, according to some embodiments, the performance of the semiconductor device structure 400 is improved.

[0191] According to some embodiments, Figures 5A-5D The cross-sectional view of each stage of the process for forming a semiconductor device structure. According to some embodiments, Figure 2A After the steps, Figure 5AAs shown in FIG, the ends of nanostructures 121, 123, 125, and 127 are removed by trenches 120a and T. According to some embodiments, the removal process forms recesses R1, R2, R3, and R4 in nanostructure stack 120. According to some embodiments, recess R1 is located between substrate 110 and nanostructure 122.

[0192] According to some embodiments, recess R2 is located between nanostructures 122 and 124. According to some embodiments, recess R3 is located between nanostructures 124 and 126. According to some embodiments, recess R4 is located between nanostructures 126 and 128. According to some embodiments, the removal process includes an etching process such as a dry etching process or a wet etching process.

[0193] According to some embodiments, Figure 5A As shown in FIG, an inner spacer material layer 170 is formed over the mask layer 150, the spacer structure 160, the nanostructure stack 120, and the fin 114. According to some embodiments, the inner spacer material layer 170 covers the recesses R1, R2, R3, and R4. According to some embodiments, the inner spacer material layer 170 directly contacts the sidewalls 121a, 123a, 125a, and 127a of the nanostructures 121, 123, 125, and 127.

[0194] According to some embodiments, the inner spacer material layer 170 has voids V1, V2, V3, and V4. According to some embodiments, the voids V1, V2, V3, and V4 are respectively within the recesses R1, R2, R3, and R4. According to some embodiments, the inner spacer material layer 170 is formed using a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a similar process.

[0195] According to some embodiments, Figure 5A and Figure 5B As shown in FIG, portions of the inner spacer material layer 170 outside the recesses R1, R2, R3, and R4 are removed to form inner spacers 172, 174, 176, and 178 in the recesses R1, R2, R3, and R4, respectively. In some other embodiments, the voids V1, V2, V3, and V4 are open voids. In some embodiments, the voids V1, V2, V3, and V4 are closed voids.

[0196] According to some embodiments, void V1 has a width of W5. According to some embodiments, void V2 has a width of W6. According to some embodiments, void V3 has a width of W7. According to some embodiments, void V4 has a width of W8. According to some embodiments, width W5 is greater than width W8. That is, void V1 is wider than void V4. According to some embodiments, width W8 is greater than widths W6 or W7. That is, void V4 is wider than voids V2 or V3.

[0197] According to some embodiments, width W6 is substantially equal to width W7. According to some embodiments, width W5 is in a range of about 4 nm to about 10 nm. According to some embodiments, width W6 is in a range of about 1 nm to about 5 nm. According to some embodiments, width W7 is in a range of about 1 nm to about 5 nm. According to some embodiments, width W8 is in a range of about 3 nm to about 6 nm.

[0198] In some embodiments, the sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a and 172a of the nanostructure 128, inner spacer 178, nanostructure 126, inner spacer 176, nanostructure 124, inner spacer 174, nanostructure 122 and inner spacer 172 and the surface 116 of the substrate 110 are aligned with the adjacent sidewalls 128a, 178a, 126a, 176a, 124a, 174a, 122a and 172a and the adjacent surface 116.

[0199] According to some embodiments, Figure 5C As shown in FIG, a stressor structure 180 is formed in the trench 120a. According to some embodiments, the stressor structure 180 is connected to the nanostructures 122, 124, 126, and 128. According to some embodiments, the stressor structure 180 is in direct contact with the nanostructures 122, 124, 126, and 128, the inner spacers 172, 174, 176, and 178, and the substrate 110. According to some embodiments, as Figure 5C As shown in FIG, a dielectric layer 190 is formed on the stressor structure 180 .

[0200] According to some embodiments, Figure 5C and Figure 5D As shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms the trench 166 in the spacer structure 160. According to some embodiments, as Figure 5C and Figure 5D As shown in FIG, nanostructures 121 , 123 , 125 , and 127 are removed by trench 166 .

[0201] According to some embodiments, Figure 5D-1 for Figure 5D According to some embodiments, Figure 5D-2 For semiconductor device structures along Figure 5D-1 The cross-sectional view is shown along the section line 5D-2-5D-2'.

[0202] According to some embodiments, Figure 5D 、 Figure 5D-1 and Figure 5D-2As shown in FIG, gate stack 210 is formed in trench 166. In this step, semiconductor device structure 500 is generally formed. According to some embodiments, gate stack 210 surrounds nanostructures 122, 124, 126, and 128.

[0203] According to some embodiments, gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of nanostructures 122, 124, 126, and 128 and trenches 166.

[0204] According to some embodiments, the work function metal layer 214 conformally covers the gate dielectric layer 212. According to some embodiments, a gate electrode layer 216 is formed on the work function metal layer 214.

[0205] According to some embodiments, Figure 5D As shown, voids V1, V2, V3, and V4 are filled with air. That is, according to some embodiments, voids V1, V2, V3, and V4 are air voids. According to some embodiments, the voids have a teardrop shape. According to some embodiments, nanostructure 122 is wider than nanostructure 126. According to some embodiments, nanostructure 126 is wider than nanostructure 124.

[0206] According to some embodiments, stressor structures 180 adjacent to inner spacer 172 are narrower than stressor structures 180 adjacent to inner spacer 174. According to some embodiments, stressor structures 180 adjacent to inner spacer 178 are narrower than stressor structures 180 adjacent to inner spacers 174 or 176.

[0207] According to some embodiments, Figures 6A-6C The cross-sectional view of each stage of the process for forming a semiconductor device structure. According to some embodiments, Figure 5A After the steps, Figure 6A As shown in FIG, a film layer 171 is conformally formed on the inner spacer material layer 170. According to some embodiments, the film layer 171 conformally covers the inner walls of the voids V1, V2, V3, and V4.

[0208] According to some embodiments, the membrane layer 171 and the inner spacer material layer 170 are made of different materials. According to some embodiments, the dielectric constant of the material of the inner spacer material layer 170 is greater than the dielectric constant of the material of the membrane layer 171. In some embodiments, the inner spacer material layer 170 is formed using a physical vapor deposition process, and the membrane layer 171 is formed using an atomic layer deposition process.

[0209] According to some embodiments, Figure 6A and Figure 6BAs shown in FIG, portions of the inner spacer material layer 170 and the film layer 171 outside the grooves R1, R2, R3 and R4 are removed to form inner spacers 172, 174, 176 and 178 in the grooves R1, R2, R3 and R4, respectively.

[0210] According to some embodiments, inner spacer 172 includes inner spacer material layer 170 and film layer 171 remaining in recess R1. According to some embodiments, inner spacer 174 includes inner spacer material layer 170 and film layer 171 remaining in recess R2. According to some embodiments, inner spacer 176 includes inner spacer material layer 170 and film layer 171 remaining in recess R3. According to some embodiments, inner spacer 178 includes inner spacer material layer 170 and film layer 171 remaining in recess R4.

[0211] According to some embodiments, void V1 in inner spacer 172 is wider than void V4 in inner spacer 178. According to some embodiments, void V4 is wider than void V2 in inner spacer 174 or void V3 in inner spacer 176.

[0212] In some embodiments, the sidewalls 128a, 178a, 171a, 126a, 176a, 124a, 174a, 122a and 172a of the nanostructure 128, the inner spacer 178, the film layer 171, the nanostructure 126, the inner spacer 176, the nanostructure 124, the inner spacer 174, the nanostructure 122 and the inner spacer 172 and the surface 116 of the substrate 110 together form a continuous inner wall of the trench 120a.

[0213] According to some embodiments, each sidewall 128a, 171a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and surface 116 is aligned with adjacent sidewalls 128a, 171a, 178a, 126a, 176a, 124a, 174a, 122a, and 172a and adjacent surface 116.

[0214] According to some embodiments, Figure 6B and Figure 6C As shown in FIG, a stressor structure 180 is formed in the trench 120a. According to some embodiments, the stressor structure 180 is connected to the nanostructures 122, 124, 126 and 128. According to some embodiments, as Figure 6C As shown in FIG, a dielectric layer 190 is formed on the stressor structure 180 .

[0215] According to some embodiments, Figure 6B and Figure 6CAs shown in , the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms the trench 166 in the spacer structure 160. According to some embodiments, as Figure 6B and Figure 6C As shown in FIG, nanostructures 121 , 123 , 125 , and 127 are removed by trench 166 .

[0216] According to some embodiments, Figure 6C-1 for Figure 6C According to some embodiments, Figure 6C-2 For semiconductor device structures along Figure 6C-1 The cross-sectional view is shown along the section line 6C-2-6C-2'.

[0217] According to some embodiments, Figure 6C 、 Figure 6C-1 and Figure 6C-2 As shown in FIG, gate stack 210 is formed in trench 166. According to some embodiments, in this step, semiconductor device structure 600 is generally formed. According to some embodiments, gate stack 210 surrounds nanostructures 122, 124, 126, and 128.

[0218] According to some embodiments, gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216. According to some embodiments, gate dielectric layer 212 conformally covers the inner walls and bottom surfaces of nanostructures 122, 124, 126, and 128 and trenches 166.

[0219] According to some embodiments, a work function metal layer 214 is conformally formed on the gate dielectric layer 212. According to some embodiments, a gate electrode layer 216 is formed on the work function metal layer 214.

[0220] According to some embodiments, Figure 6C As shown, voids V1, V2, V3, and V4 are filled with air. That is, according to some embodiments, voids V1, V2, V3, and V4 are air voids. According to some embodiments, voids V1, V2, V3, and V4 have a teardrop shape. According to some embodiments, nanostructure 128 is wider than nanostructure 122. According to some embodiments, nanostructure 122 is wider than nanostructure 126. According to some embodiments, nanostructure 126 is wider than nanostructure 124.

[0221] The processes and structures for forming the semiconductor device structures 200 , 300 , 400 , 500 , and 600 may be similar to or the same as the processes and structures for forming the semiconductor device structure 100 described above.

[0222] According to some embodiments, a semiconductor device structure and a method for forming the same are provided. The method (used to form the semiconductor device structure) forms an inner spacer between a gate stack and a stressor structure to prevent short circuits between the gate stack and the stressor structure. The inner spacer has different dimensions (e.g., width) depending on design requirements. The inner spacer has air gaps to reduce the dielectric constant of the inner spacer and, thereby, reduce parasitic capacitance between the gate stack and the stressor structure. Thus, the performance of the semiconductor device structure is improved.

[0223] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin located above the base. The semiconductor device structure includes a gate stack surrounding a top portion of the fin. The semiconductor device structure includes a gate stack located above a top portion of the fin. The semiconductor device structure includes a first nanostructure located above the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure located above the first nanostructure and passing through the gate stack. The gate stack includes a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure. The semiconductor device structure includes a stressor structure located above the fin and connected to the first nanostructure and the second nanostructure. The semiconductor device structure includes a first inner spacer located between the first portion and the stressor structure. The semiconductor device structure includes a second inner spacer located between the second portion and the stressor structure. The first inner spacer is wider than the second inner spacer. In one embodiment, the first nanostructure is wider than the second nanostructure as measured along a longitudinal axis of the fin. In one embodiment, the stressor structure adjacent to the first nanostructure is narrower than the stressor structure adjacent to the second nanostructure. In one embodiment, the stressor structure adjacent to the first inner spacer is narrower than the stressor structure adjacent to the second inner spacer. In one embodiment, the width of the stressor structure decreases toward the fin. In one embodiment, the first sidewall of the first nanostructure, the second sidewall of the first inner spacer, and the third sidewall of the second spacer together form a continuously curved sidewall. In one embodiment, the semiconductor device structure further includes a third nanostructure located above the second nanostructure and having a third portion located between the second nanostructure and the third nanostructure through a gate stack; and a third inner spacer located between the third portion and the stressor structure, the third inner spacer being wider than the second inner spacer. In one embodiment, the third inner spacer is narrower than the first inner spacer. In one embodiment, the third nanostructure is wider than the first nanostructure, and the first nanostructure is wider than the second nanostructure.

[0224] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin located above the base. The semiconductor device structure includes a first nanostructure located above the fin. The semiconductor device structure includes a second nanostructure located above the first nanostructure. The fin, the first nanostructure, and the second nanostructure are spaced apart from one another. The semiconductor device structure includes a gate stack surrounding the first nanostructure, the second nanostructure, and a top portion of the fin. The gate stack includes a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure. The semiconductor device structure includes a stressor structure located above the fin and connected to the first nanostructure and the second nanostructure. The semiconductor device structure includes a first inner spacer located between the first portion and the stressor structure. The first inner spacer has a first gap. The semiconductor device structure includes a second inner spacer located between the second portion and the stressor structure. The second inner spacer has a second gap, and the first gap is wider than the second gap. In one embodiment, the first gap is an air gap. In one embodiment, the first gap has a teardrop shape. In one embodiment, the semiconductor device structure further includes a third nanostructure located above the second nanostructure and passing through a gate stack, the gate stack further including a third portion located between the second and third nanostructures; and a third inner spacer located between the third portion and the stressor structure, the third inner spacer including a third gap, the third gap being wider than the second gap and narrower than the first gap. In one embodiment, the semiconductor device structure further includes a film layer conformably covering an inner wall of the first gap.

[0225] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base and a fin located on the base. The method includes forming a nanostructure stack on the fin. The nanostructure stack includes a first nanostructure, a second nanostructure, a third nanostructure, and a fourth nanostructure formed in sequence on the fin. The method includes forming a gate stack on the nanostructure stack and the fin. The method includes partially removing the nanostructure stack and the fin not covered by the gate stack to form a groove in the nanostructure stack and the fin. The method includes removing the ends of the first nanostructure and the third nanostructure through the groove to form a first groove and a second groove in the nanostructure stack. The first groove is located between the fin and the second nanostructure, the second groove is located between the second nanostructure and the fourth nanostructure, and the first groove is wider than the second groove. In one embodiment, the method for forming a semiconductor device structure also includes forming a first inner spacer and a second inner spacer in the first groove and the second groove, respectively, and the first inner spacer is wider than the second inner spacer. In one embodiment, the method for semiconductor device structure further includes forming a stressor structure in the trench and connected to the second nanostructure and the fourth nanostructure, the stressor structure having a width that decreases toward the fin. In one embodiment, the first inner spacer has a first gap, the second inner spacer has a second gap, and the first gap is wider than the second gap. In one embodiment, the method for semiconductor device structure further includes forming a film layer to conformally cover a first inner wall of the first gap and a second inner wall of the second gap. In one embodiment, the method for semiconductor device structure further includes removing a portion of the nanostructure stack from the inner wall of the trench to expand the trench before removing the ends of the first nanostructure and the third nanostructure.

[0226] The foregoing text summarizes the characteristic components of many embodiments so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the embodiments of the present invention. Various changes, replacements or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention of the embodiments of the present invention, and therefore the scope of protection of the present invention shall be as defined by the appended claims. In addition, although the present invention has been disclosed as above with several preferred embodiments, they are not intended to limit the present invention, and not all advantages have been described in detail herein.

Claims

1. A semiconductor device structure comprising: a substrate having a base and a fin located on the base; a gate stack located on a top portion of the fin; a first nanostructure located above the fin and passing through the gate stack; a second nanostructure located above the first nanostructure and passing through the gate stack, wherein the gate stack has a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure; a stressor structure located on the fin and connected to the first nanostructure and the second nanostructure; a first inner spacer located between the first portion and the stressor structure; a second inner spacer located between the second portion and the stressor structure, wherein the first inner spacer is wider than the second inner spacer; a film layer located in the first inner spacer, wherein the dielectric constant of the film layer is smaller than the dielectric constant of the first inner spacer; and A first low dielectric constant structure is located in the film layer, wherein the film layer surrounds the first low dielectric constant structure, so that the first low dielectric constant structure is separated from the first inner spacer through the film layer. 2 . The semiconductor device structure of claim 1 , wherein the first nanostructure is wider than the second nanostructure measured along a longitudinal axis of the fin. 3 . The semiconductor device structure of claim 2 , wherein the stressor structure adjacent to the first nanostructure is narrower than the stressor structure adjacent to the second nanostructure. 4 . The semiconductor device structure of claim 1 , wherein the stressor structure adjacent to the first inner spacer is narrower than the stressor structure adjacent to the second inner spacer. The semiconductor device structure of claim 1 , wherein a width of the stressor structure decreases toward the fin. 6 . The semiconductor device structure according to claim 1 , wherein a first sidewall of the first nanostructure, a second sidewall of the first inner spacer, and a third sidewall of the second inner spacer together form a continuously curved sidewall.

7. The semiconductor device structure of claim 1 , further comprising: a third nanostructure located above the second nanostructure and passing through the gate stack, wherein the gate stack further has a third portion located between the second nanostructure and the third nanostructure; as well as A third inner spacer is located between the third portion and the stressor structure, wherein the third inner spacer is wider than the second inner spacer. 8 . The semiconductor device structure according to claim 7 , wherein the third inner spacer is narrower than the first inner spacer. 9 . The semiconductor device structure of claim 7 , wherein the third nanostructure is wider than the first nanostructure, and the first nanostructure is wider than the second nanostructure.

10. A semiconductor device structure comprising: a substrate having a base and a fin located on the base; a first nanostructure located on the fin; a second nanostructure located on the first nanostructure, wherein the fin, the first nanostructure, and the second nanostructure are spaced apart from each other; a gate stack surrounding the first nanostructure, the second nanostructure, and a top portion of the fin, wherein the gate stack has a first portion and a second portion, the first portion being located between the first nanostructure and the fin, and the second portion being located between the first nanostructure and the second nanostructure; a stressor structure located on the fin and connected to the first nanostructure and the second nanostructure; a first inner spacer located between the first portion and the stressor structure, wherein the first inner spacer has a first gap; a film layer disposed in the first inner spacer, wherein the dielectric constant of the film layer is less than the dielectric constant of the first inner spacer, wherein the first void is disposed in the film layer, wherein the film layer surrounds the first void such that the first void is separated from the first inner spacer by the film layer; as well as A second inner spacer is located between the second portion and the stressor structure, wherein the second inner spacer has a second gap, and the first gap is wider than the second gap. The semiconductor device structure according to claim 10 , wherein the first gap is an air gap. 12 . The semiconductor device structure of claim 10 , wherein the first gap has a teardrop shape.

13. The semiconductor device structure of claim 10, further comprising: a third nanostructure located above the second nanostructure and passing through the gate stack, wherein the gate stack further has a third portion located between the second nanostructure and the third nanostructure; as well as A third inner spacer is located between the third portion and the stressor structure, wherein the third inner spacer has a third gap, and the third gap is wider than the second gap and narrower than the first gap.

14. The semiconductor device structure according to claim 10, wherein: The film layer conformably covers an inner wall of the first gap.

15. A method for forming a semiconductor device structure, comprising: Providing a substrate having a base and a fin located on the base; forming a nanostructure stack on the fin, wherein the nanostructure stack comprises a first nanostructure, a second nanostructure, a third nanostructure, and a fourth nanostructure sequentially formed on the fin; forming a gate stack over the nanostructure stack and the fin; Partially removing portions of the nanostructure stack and the fin not covered by the gate stack to form a trench in the nanostructure stack and the fin; removing ends of the first nanostructure and the third nanostructure through the trench to form a first groove and a second groove in the nanostructure stack, wherein the first groove is located between the fin and the second nanostructure, the second groove is located between the second nanostructure and the fourth nanostructure, and the first groove is wider than the second groove; forming a first inner spacer and a second inner spacer in the first groove and the second groove respectively, wherein the first inner spacer has a first gap; and A film layer is formed in the first inner spacer, wherein the dielectric constant of the film layer is less than the dielectric constant of the first inner spacer, wherein the first void is located in the film layer, wherein the film layer surrounds the first void so that the first void is separated from the first inner spacer by the film layer. 16 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the first inner spacer is wider than the second inner spacer.

17. The method for forming a semiconductor device structure according to claim 16, further comprising: A stressor structure is formed in the trench and connected to the second nanostructure and the fourth nanostructure, wherein the stressor structure has a width that decreases toward the fin. 18 . The method for forming a semiconductor device structure according to claim 16 , wherein the second inner spacer has a second gap, and the first gap is wider than the second gap.

19. The method for forming a semiconductor device structure according to claim 18, wherein The film layer is formed to conformably cover a first inner wall of the first gap and a second inner wall of the second gap.

20. The method of forming a semiconductor device structure according to claim 15, further comprising: Before removing the end portions of the first nanostructure and the third nanostructure, a portion of the nanostructure stack is removed from an inner wall of the trench to enlarge the trench.

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