Avalanche photodiode

Abstract

The present disclosure relates to semiconductor structures, and more particularly to avalanche photodiodes and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom formed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material disposed on the first semiconductor material; and a third semiconductor material disposed on the photosensitive semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to avalanche photodiodes and manufacturing methods thereof. Background Art

[0002] An avalanche photodiode (APD) is a highly sensitive semiconductor photodiode that converts light into electricity using the photoelectric effect. From a functional perspective, an avalanche photodiode can be regarded as a semiconductor analog of a photomultiplier tube. Typical applications of avalanche photodiodes are long-distance fiber optic communication and quantum sensing for control algorithms. Newer applications include positron emission tomography and particle physics.

[0003] The applicability and practicality of avalanche photodiodes depend on many parameters. For example, two factors are quantum efficiency and total leakage. The quantum efficiency indicates how incident photons are absorbed and then used to generate primary charge carriers; while the total leakage current is the sum of dark current, photocurrent, and noise.

[0004] The sensitivity of a photodiode depends on the length of the optical path through the photosensitive material and the ability of the generated carrier pairs to reach the electrodes / contact / cathode. In a conventional structure, the carriers travel along a two-dimensional path (e.g., vertically or laterally), which results in a longer path. Due to the longer path of a conventional avalanche photodiode, the photon recombination frequency in the photosensitive material is very high, leading to signal loss or weakening of the signal itself. In addition, the photosensitive material itself needs to be very thick, which has a high growth cost and takes a long time, and may make the integration with other circuit elements more challenging. Summary of the Invention

[0005] In one aspect of the present disclosure, a structure includes: a substrate material having a trench with sidewalls and a bottom including the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material disposed on the first semiconductor material; and a third semiconductor material disposed on the photosensitive semiconductor material.

[0006] In one aspect of the present disclosure, a structure includes: a semiconductor material; a trench formed in the semiconductor material, the trench having sidewalls and a bottom; a semiconductor material having a first dopant type lining the sidewalls and the bottom of the trench; an intrinsic photosensitive semiconductor material in contact with the semiconductor material; a second semiconductor material having the first dopant type, located in the trench, and in contact with the intrinsic photosensitive semiconductor material; and an isolation structure including a reflective material surrounding the trench and positioned away from the intrinsic photosensitive semiconductor material.

[0007] In one aspect of the present disclosure, a method includes: forming a trench in a substrate; providing a lining of semiconductor material on sidewalls and a bottom of the trench; forming an undoped photosensitive material on the semiconductor material within the trench; forming another semiconductor material on the undoped photosensitive material within the outer side of the trench; and forming a trench structure having a reflective material in the substrate adjacent to the lining of the semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, the present disclosure is described with reference to the several figures mentioned, by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0009] Figure 1 A substrate having trenches, among other features, according to an aspect of the present disclosure, and a corresponding manufacturing process are shown.

[0010] Figure 2 A semiconductor material lining both a bottom surface and sidewalls of a trench, among other features, according to an aspect of the present disclosure, and a corresponding manufacturing process are shown.

[0011] Figure 3 Additional semiconductor material within a trench for forming a photodiode, among other features, according to an aspect of the present disclosure, and a corresponding manufacturing process are shown.

[0012] Figure 4 A shallow trench isolation structure surrounding a photodiode, among other features, according to an aspect of the present disclosure, and a corresponding manufacturing process are shown.

[0013] Figure 5 A carrier path within a photodiode, according to an aspect of the present disclosure, is shown.

[0014] Figure 6A and Figure 6B Different shapes of a photodiode, according to an aspect of the present disclosure, are shown.

[0015] Figure 7 The formation of contacts to a photodiode, among other features, according to an aspect of the present disclosure, and a corresponding manufacturing process are shown.

[0016] Figure 8 A photodiode according to another aspect of the present disclosure is shown.

[0017] Figure 9 A photodiode according to a further another aspect of the present disclosure is shown.

[0018] Figure 10A and Figure 10B Different arrays of a photodiode, according to an aspect of the present disclosure, are shown.

[0019] Figure 11 It is a comparative diagram showing the responsivity of the photodiodes of the present disclosure and those of a conventional system, in which the photon path is only two-dimensional, for example, from top to bottom (vertical) or from one side to the other (lateral). Detailed implementation

[0020] The present disclosure relates to semiconductor structures, and more particularly to avalanche photodiodes and manufacturing methods. More specifically, the present disclosure relates to structures and methods for forming avalanche photodiodes in concentric shapes (or other shapes). Advantageously, in addition to the close packing of unit cells and improved reflection, due to a special shape factor (such as circular), the avalanche photodiodes described herein exhibit increased sensitivity. In addition, the avalanche photodiodes can be integrated with other devices using established / existing processes.

[0021] In a more specific embodiment, the avalanche photodiode is formed in a trench having sidewalls and a bottom composed of exposed semiconductor material. Compared with an oxide having a growth-inhibiting Ge material on the sidewalls, a semiconductor material such as silicon is provided along the sidewalls and the bottom of the trench to enhance the growth of a photosensitive material (such as a germanium (Ge) layer). That is, in the structure provided herein, the Ge layer grows from both the bottom and the sidewalls of the trench, rather than only from the bottom of the trench.

[0022] In an embodiment, by implementing the structure herein, a layered epitaxial growth (relative to a solid Ge mass) can be used to create a shorter three-dimensional (3D) path (relative to a strictly linear path) for the generated carriers, thereby reducing the risk of carrier recombination that may occur before detection. In a further embodiment, within the trench, a polyfilm stack is grown in a layered manner from the bottom and the outside, and a P+ plug is located in the center of the structure to provide bias for the operation of the avalanche diode.

[0023] The avalanche photodiodes of the present disclosure can be manufactured in a variety of different ways using a variety of different tools. Generally, however, methods and tools are used to form structures having micron- and nanoscale dimensions. Methods (i.e., techniques) for manufacturing the avalanche photodiodes of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned by a photolithography process on top of the wafer. Specifically, the manufacturing of the avalanche photodiode uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film through photolithographic imaging; and (iii) selectively etching the film with respect to the mask.

[0024] Figure 1Shows a substrate with trenches and a corresponding manufacturing process, among other features, according to aspects of the present disclosure. More specifically, structure 10 includes substrate 12. Substrate 12 can represent, for example, a CMOS chip. In an embodiment, substrate 12 is preferably a Si material; however, other semiconductor materials can be contemplated herein. For example, substrate 12 can be composed of any suitable material including SiC, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors. In a preferred embodiment, substrate 12 is an N-type substrate composed of a single semiconductor material (such as bulk silicon); however, as described with respect to Figure 9 For example, substrate 12 can be a P-type substrate.

[0025] Hard mask 14 is deposited on substrate 12. In an embodiment, hard mask 14 can be a nitride or other hard mask material known in the art, such that the present disclosure can be fully understood without further explanation. Hard mask 14 can be deposited by known deposition methods, such as chemical vapor deposition (CVD) processes. Hard mask 14 will prevent epitaxial growth of semiconductor material on the surface of substrate 12 in subsequent processes.

[0026] Still referring to Figure 1 , trenches 16 are formed in substrate 12 using conventional lithography and etching processes known to those skilled in the art. In a non-limiting example, trenches 16 can have a depth of approximately 2.5 μm (however, other dimensions can be contemplated herein). When forming trenches 16, the resist formed above hard mask 14 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (such as reactive ion etching (RIE)) will be used to form one or more trenches 16 in substrate 12 through the openings in hard mask 14 and the resist. As described with respect to Figure 6A And Figure 6B Trenches 16 can have many different configurations, such as circular, square, etc. After the etching process, an HF clean can be performed to remove contaminants from the surface of trenches 16, thereby ensuring that the exposed semiconductor material on the bottom surface and sidewalls of trenches 16 has a clean surface. The resist can be removed by conventional oxygen ashing processes or other known strippers.

[0027] Due to the selectivity of the chemicals during the etching process, substrate 12 can be etched laterally under hard mask 14 relative to the openings in hard mask 14. By having a lateral recess, an overhang 16a of hard mask 14 will be formed above trenches 16. Overhang 16a will pin dislocations, maintain separation between materials, and avoid pinch-off and improve epitaxial growth in subsequent processes.

[0028] In Figure 2In this case, the semiconductor material 18 grows on both the bottom surface and the sidewalls of the trench 16 below the overhang 16a. In an embodiment, the semiconductor material 18 is a liner formed by a selective epitaxial growth process that starts from the exposed semiconductor material on both the sidewalls and the bottom surface of the trench 16. The semiconductor material 18 can grow, for example, along an annular ring. Those of ordinary skill in the art should understand that the hard mask 14 will prevent the semiconductor material from growing on the surface of the substrate 12 outside the trench 16. The semiconductor material 18 will be a P-type semiconductor material, preferably composed of the same material as the substrate 12 (such as Si). In an alternative embodiment, the semiconductor material 18 can be a different material, such as SiGe.

[0029] As Figure 3 shown, additional semiconductor material 20 is selectively grown on the semiconductor material 18. In an embodiment, the additional semiconductor material 20 is an intrinsic photosensitive semiconductor material (undoped) formed by an epitaxial growth process. The semiconductor material 20 is preferably a Ge material to provide excellent responsiveness and is thicker than the liner composed of the semiconductor material 18. In an alternative embodiment, the semiconductor material 20 can be Si, SiGe, etc. Then, semiconductor material 22 is grown in the remaining portion of the trench 17 above the semiconductor material 20. The semiconductor material 22 will also grow on the exposed upper surface of the semiconductor material 20. The semiconductor material 22 is preferably the same material as the semiconductor material 18. For example, the semiconductor material 22 is a P+-type semiconductor material or polysilicon.

[0030] In an embodiment, the semiconductor material 22 is a P+ plug located at the center of the structure to provide a bias for the operation of the avalanche photodiode. In this way, an N-P-I-P photodiode 25 can be formed. More specifically, the P+ material (such as the semiconductor material 22) located at the center of the photodiode 25 and the P+ material (such as the semiconductor material 18) located on the sides and bottom of the SiGe material (such as the semiconductor material 20) form an avalanche photodiode (APD) that is biased in three dimensions, thereby increasing the likelihood of picking up a signal before carrier recombination.

[0031] In Figure 4Herein, the hard mask is now removed by a selective etching process. In an embodiment, removing the hard mask will leave a space "x" between the semiconductor material 22 and the edge of the trench 16 (e.g., the photodiode 25). A shallow trench isolation structure or a deep oxide-filled / liner trench 24 is formed around the now-filled trench 16 (e.g., the photodiode 25). In an embodiment, the shallow trench isolation structure or the deep oxide-filled / liner trench 24 should be spaced apart from the intrinsic material (e.g., the Ge material 20) to avoid damaging such material and thus reduce any possibility of photon capture. Also, depending on the performance parameters, the shallow trench isolation structure or the deep oxide-filled / liner trench 24 can have various depths, including depths below the depth of the trench 16 (e.g., the photodiode 25).

[0032] The shallow trench isolation structure or the deep oxide-filled / liner trench 24 can be fabricated by conventional lithography, etching, and deposition methods. For example, a resist formed over the substrate 12 and the photodiode 25 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., RIE) will be used to form one or more trenches in the substrate 12 on the side of the photodiode 25. After removing the resist, an insulator material (e.g., oxide) can be deposited by any conventional deposition process (e.g., a CVD process). Any residual material on the surface of the substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0033] As representatively shown in Figure 5 photons enter the photodiode 25 and generate carriers in the intrinsic material, and these carriers travel through the intrinsic semiconductor material 20 (e.g., the Ge material) to the semiconductor material 18 on all sides (as shown by the arrows). In this way, the photodiode 25 has a three-dimensional current. By allowing the three-dimensional current to flow, the carrier path to the substrate 12, or more precisely, the carrier path through the semiconductor material (p material) 18 to the substrate (N-type material) 12 is much shorter (compared to known photodiodes having a path from top to bottom) because the intrinsic semiconductor material 20 is surrounded by the semiconductor material 18 on its sides and bottom. Also, by having a shorter path, the possibility of carrier recombination is smaller, resulting in less loss of signal strength.

[0034] Additionally, the shallow trench isolation structure or the deep oxide-filled / lined trench 24 will act as a reflector or mirror to inhibit light from entering the substrate 12 from the sides of the trench; instead, any light (photons) is effectively pushed towards the lining 18 and into the substrate 12. In other words, the shallow trench isolation structure or the deep oxide-filled / lined trench 24 formed around the outside of the photodiode 25 provides a reflective interface to maximize the interaction of incident photons with the intrinsic semiconductor material 20 for generating carriers. For example, a reflective surface is provided to increase the residence time of photons in the Ge material.

[0035] Figure 6A and Figure 6B illustrate different cross-sectional shapes of the photodiode 25. For example, in Figure 6A , the cross-sectional profile of the photodiode 25 is circular (columnar); while in Figure 6B , the cross-sectional profile of the photodiode 25 is quadrilateral (e.g., square). However, it should be understood that other profiles are also contemplated herein, such as but not limited to bar-shaped, rectangular, oval, octagonal, etc.

[0036] Figure 7 illustrate, among other features, the formation of contacts to the photodiode and the corresponding manufacturing processes. In Figure 7 , a semiconductor material 26 (e.g., polysilicon) is formed on the top side of the photodiode 25. The semiconductor material 26 will serve as a contact to the top of the semiconductor material 26 (e.g., the P+ plug of the photodiode 25). More specifically, the semiconductor material 26 will drive current into the photodiode 25 to bias the plug 22 and drive carriers from the center of the photodiode 25 (e.g., the semiconductor material 20) to the outside of the photodiode 25 (e.g., the lining 18 of the semiconductor material). In this way, the drive current will effectively amplify the signal.

[0037] The film 28 (e.g., nitride or other hard mask material) will cover or isolate the semiconductor material 26 to prevent the formation of silicide on the top of the photodiode 25. The unsilicided top surface will provide optimal performance under front illumination of the photodiode 25.

[0038] A silicide contact 30 is formed on the exposed surface of the substrate 12 on one side of the photodiode 25. Those skilled in the art should understand that the silicidation process begins with the deposition of a thin transition metal layer (e.g., nickel, cobalt, or titanium) above the semiconductor material of the substrate 12. After depositing the material, the structure is heated to react the transition metal with the exposed silicon (or other semiconductor materials described herein), thereby forming a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving behind the silicide contact 30.

[0039] Still referring toFigure 7 , an interlayer dielectric material (e.g., oxide) 32 is deposited over the structure. A trench is formed in the interlayer dielectric material (e.g., oxide) 32 that is aligned with and exposes the upper surface of the silicide contact 30. The trench is formed by conventional lithography and etching processes as described herein. The trench is filled with a metal material (e.g., tungsten) to form a contact 34. Those skilled in the art will understand that the contact 34 is used to detect the current generated by photons impinging on the photodiode 25 (e.g., the semiconductor material 20 of the photodiode 25).

[0040] Figure 8 A photodiode is shown in accordance with another aspect of the present disclosure. More specifically, in Figure 8 the structure 10a, a silicide contact 30 is formed directly on the top surface of the photodiode 25 (e.g., the semiconductor material 22). This arrangement is suitable for backside illumination. Thereafter, as referenced Figure 7 above, a contact 34 is formed to the silicide contact 30.

[0041] Figure 9 A photodiode is shown in accordance with another aspect of the present disclosure. In Figure 9 the structure 10b, the photodiode 25 includes a film stack arrangement (e.g., P-I-P-N) different from the film stack arrangement described with reference to Figures 1 to 8 . Specifically, the substrate 12a, the semiconductor material 18a, and the semiconductor material 22a are P-type semiconductor materials; while the semiconductor material 20 remains an intrinsic semiconductor material (undoped) formed by an epitaxial growth process on the semiconductor material 18a.

[0042] However, in this embodiment, the semiconductor material 22a does not completely fill the remaining portion of the trench. Instead, an N-type semiconductor material 36 will be epitaxially grown on the semiconductor material 22a. Alternatively, the semiconductor material 22a can be grown to completely fill the remaining portion of the trench, and then a lithography and etching process can be performed to form a trench in its central portion. Then, the trench can be filled with the N-type semiconductor material 36 by epitaxial growth on the semiconductor material 22a. A silicide contact 30 is formed directly on the top surface of the photodiode 25 (e.g., the semiconductor material 36), and as referenced Figure 7 above, a contact 34 is formed to the silicide contact 30. This arrangement is also suitable for backside illumination. It should also be understood that this configuration (e.g., by using a polysilicon contact and no silicidation occurring above the detector) can also be used to practice frontside illumination.

[0043] Figure 10A and Figure 10B show different arrays of photodiodes in accordance with aspects of the present disclosure. More specifically, Figure 10AShows an array of quadrilateral (e.g., square or rectangular) photodiodes 25, Figure 10B Shows an array of circular photodiodes 25. Although the array of quadrilateral (e.g., square or rectangular) photodiodes 25 is arranged in an aligned manner with each other, they can take other forms. Additionally, it should be noted that the array of circular photodiodes 25 is more closely packed together than the quadrilateral (e.g., square or rectangular) photodiodes 25 (e.g., 18 photodiodes vs. 16 photodiodes).

[0044] Figure 11 Is a comparison graph showing the responsivity of the photodiodes of the present disclosure and those of a conventional system, where in the conventional system, the photon path is only two-dimensional, e.g., from top to bottom (vertical) or from one side to the other (lateral). In this graph, the x-axis is the wavelength (μm) and the y-axis is the responsivity (mA / W). Line “A” represents a photodiode with Ge material, and line “B” represents a photodiode with Si material, both of which have a three-dimensional (3D) path according to aspects of the present disclosure; while line “C” represents a photodiode with Ge material whose path is only in the lateral direction, and line “D” represents a photodiode with Ge material that only includes a path only in the vertical direction. It can be clearly seen from the graph that at a wavelength of approximately 0.7 μm, the photodiodes of lines “A” and “B” have the maximum responsivity. Additionally, in the wavelength range of approximately 1.5 μm, the Ge implementation shown by line “A” is far superior to any other implementation.

[0045] Avalanche photodiodes can be utilized in system-on-chip (SoC) technology. Those skilled in the art should understand that an SoC is an integrated circuit (also referred to as a “chip”) that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0046] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers with leads fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with surface and / or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device and a central processing unit.

[0047] The description of the various embodiments of the present disclosure has been given for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the marketplace, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: a substrate material having trenches, the trenches having sidewalls and a bottom including the substrate material, the substrate material being composed of a semiconductor material; a first semiconductor material lining the sidewalls and the bottom of the trenches; a photosensitive semiconductor material disposed on the first semiconductor material; and a third semiconductor material including a plug located at the center of the photosensitive semiconductor material and extending on the top surface of the photosensitive semiconductor material.

2. The semiconductor structure according to claim 1, further comprising an isolation structure extending into the substrate material and surrounding the trenches, away from the photosensitive semiconductor material.

3. The semiconductor structure according to claim 2, wherein, the isolation structure includes a reflective material that reflects photons into the first semiconductor material lining the sidewalls and the bottom of the trenches.

4. The semiconductor structure according to claim 1, wherein, the photosensitive semiconductor material includes an intrinsic material.

5. The semiconductor structure according to claim 4, wherein, the intrinsic material includes an undoped Ge material.

6. The semiconductor structure according to claim 4, wherein, the substrate material includes an N-type semiconductor material, and the first semiconductor material and the third semiconductor material include a P-type semiconductor material.

7. The semiconductor structure according to claim 6, wherein, the third semiconductor material includes a P+ plug to bias the operation of an avalanche photodiode.

8. The semiconductor structure according to claim 7, further comprising a semiconductor material located on the P+ plug and a masking material located above the semiconductor material to prevent the formation of silicide on the P+ plug.

9. The semiconductor structure according to claim 8, wherein, the P+ plug includes an unsilicided material, and a contact is formed on one side of the trench, the contact being in electrical contact with the substrate to detect a signal.

10. The semiconductor structure according to claim 7, further comprising a silicide and a contact located on the P+ plug.

11. The semiconductor structure according to claim 3, further comprising a fourth semiconductor material located on the third semiconductor material, the third semiconductor material and the fourth semiconductor material being entirely located within the trenches, wherein, the substrate material, the first semiconductor material, and the third semiconductor material include P-type materials, and the fourth semiconductor material includes an N-type material.

12. The semiconductor structure according to claim 11, further comprising a silicide contact and a contact electrically connected to the N-type material.

13. A semiconductor structure, comprising: a semiconductor material; a trench formed in the semiconductor material, the trench having sidewalls and a bottom; a semiconductor material having a first dopant type lining the sidewalls and the bottom of the trench; an intrinsic photosensitive semiconductor material in contact with the semiconductor material; A second semiconductor material, having the first dopant type, is located in the trench and in contact with the intrinsic photosensitive semiconductor material; and an isolation structure, including a reflective material surrounding the trench, is positioned away from the intrinsic photosensitive semiconductor material, wherein the second semiconductor material includes a plug located at the center of the intrinsic photosensitive semiconductor material and extending on the top surface of the intrinsic photosensitive semiconductor material.

14. The semiconductor structure according to claim 13, wherein the semiconductor material includes an N-type material, the first dopant type includes a P-type material, and the structure further includes a masking material located above the second semiconductor material to prevent the formation of silicide on the second semiconductor material.

15. The semiconductor structure according to claim 13, wherein the semiconductor material includes an N-type material, the first dopant type includes a P-type material, and further includes a silicide contact directly on the second semiconductor material.

16. The semiconductor structure according to claim 13, further including an N-type semiconductor material directly on the second semiconductor material within the trench, wherein the semiconductor material and the second semiconductor material are P-type materials, and the intrinsic photosensitive semiconductor material includes undoped Ge material.

17. The semiconductor structure according to claim 13, wherein the intrinsic photosensitive semiconductor material includes undoped Ge material.

18. The semiconductor structure according to claim 13, further including a silicide contact and a contact electrically connected to the semiconductor material.

19. The semiconductor structure according to claim 13, wherein the cross-section of the trench is circular or quadrilateral.

20. A method of forming a semiconductor structure, including: forming a trench in a substrate composed of a semiconductor material; providing a lining of semiconductor material on the sidewalls and bottom of the trench; forming an undoped photosensitive material on the semiconductor material within the trench; forming another semiconductor material on the undoped photosensitive material within the outer side of the trench; and forming a trench structure having a reflective material in the substrate adjacent to the lining of the semiconductor material, wherein the another semiconductor material includes a plug located at the center of the undoped photosensitive material and extending on the top surface of the undoped photosensitive material.

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