Power transistor gate charge harvester for internal power generation

Abstract

A gate charge harvester (106) includes a harvesting capacitor (Charv) having a first plate and a second plate. The second plate is coupled to a lower rail (e.g., a ground layer), and the first plate is coupled to send a voltage (Vpre) to a regulator (108). The gate charge harvester also includes a low-side harvesting transistor (MharvLS) having a first terminal coupled to a gate of a low-side power transistor (Ml) and a second terminal coupled to the first plate.

Description

TECHNICAL FIELD

[0001] The present application relates generally to the field of power control circuits. More specifically, and without limitation, the description is directed to a power transistor gate charge harvester for internal power generation. SUMMARY

[0002] Some embodiments provide a circuit to recover a portion of the power transistor gate charge during gate discharge to generate a recycled logic supply voltage. The recycled logic supply voltage replaces a portion of the input logic supply voltage, which is generated from an input voltage Vin; the recycled logic supply voltage can improve the overall efficiency of the power circuit.

[0003] In one aspect, embodiments of a gate charge harvester are described. The gate charge harvester includes a harvesting capacitor having a first plate and a second plate, the second plate coupled to a lower rail; and a low-side harvesting transistor having a first terminal coupled to a gate of a low-side power transistor and a second terminal coupled to the first plate, wherein the first plate is further coupled to send a voltage to a regulator.

[0004] In another aspect, embodiments of an integrated power circuit are described. The integrated power circuit includes a low-side power transistor and a high-side power transistor coupled in series between a first pin and a second pin; a gate driver coupled to provide a low-side gate control signal to a gate of the low-side power transistor and a high-side gate control signal to a gate of the high-side power transistor; and a gate charge harvester including a harvesting capacitor having a first plate and a second plate, the second plate coupled to a lower rail; a first N-type metal oxide silicon (NMOS) harvesting transistor having a first terminal coupled to a gate of the high-side power transistor and a second terminal coupled to the first plate; and a second NMOS harvesting transistor having a first terminal coupled to a gate of the low-side power transistor and a second terminal coupled to the first plate, wherein the first plate is further coupled to provide a harvested voltage.

[0005] In yet another aspect, embodiments of an integrated power circuit are described. The integrated power circuit includes a power transistor coupled between a first pin and a second pin; a gate driver coupled to provide a gate control signal to a gate of the power transistor; and a gate charge harvester including a harvesting capacitor having a first plate and a second plate, the second plate coupled to a lower rail; and a N-type metal oxide silicon (NMOS) harvesting transistor having a first terminal coupled to a gate of the power transistor and a second terminal coupled to the first plate; wherein the first plate is further coupled to provide a harvested voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] In the drawings, which are incorporated in and constitute a part of the specification, embodiments of the application are illustrated by way of example and not by way of limitation in the accompanying drawings, in which like reference numerals indicate like elements. Different instances of an "an" or "a" embodiment of the application are not necessarily referred to as the same instance of an embodiment, and such instances of an embodiment of the application can include different elements. In the description of embodiments of the application, relative terms such as "first," "second," "third," and the like can be used solely to distinguish one instance from another instance without necessarily implying a serial or chronological order, unless otherwise indicated by the context. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of those skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicit

[0007] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments of the application and together with the description, explain these embodiments. Various advantages and features of

[0008] Figure 1A An example of a DC / DC boost converter with gate charge harvester according to an embodiment is depicted;

[0009] Figure 1B An example of a DC / DC boost converter with gate charge harvester according to an embodiment is depicted;

[0010] Figure 1C An example of a DC / DC boost converter with gate charge harvester according to an embodiment is depicted;

[0011] Figure 1D An example of a DC / DC boost converter with gate charge harvester according to an embodiment is depicted;

[0012] Figure 2 An example of a DC / DC boost converter with gate charge harvester according to an embodiment is depicted; Figure 1A Various voltage levels during operation of the circuit of

[0013] Figure 3 A block diagram of various circuits within a DC / DC boost converter according to an embodiment is depicted;

[0014] Figure 4A For analog, it compares the efficiency of AVDD supply current generation on increased logic level current load in a circuit with gate charge harvester versus prior art circuit without gate charge harvester;

[0015] Figure 4B An example of a prior art circuit and Figure 5 Figure 1A ​efficiency of the circuit over a range of output currents Iout;

[0016] Figure 4C efficiency improvement provided by the gate charge harvester is depicted;

[0017] Figure 5 a block diagram of various circuits within a DC / DC boost converter according to the prior art is depicted;

[0018] Figure 6 an example of a DC / DC boost converter according to the prior art is depicted; and

[0019] Figure 7 various voltage levels during operation of the circuit of Figure 6 are depicted. DETAILED DESCRIPTION

[0020] Embodiments of the present application will now be described in detail with reference to the drawings. To provide a thorough understanding of the present application, numerous specific details are set forth in the description below. However, the present application can be practiced without these specific details. In other instances, well-known features are not described in detail to avoid unnecessarily complicating the description.

[0021] Figure 5A high level block diagram of a DC / DC boost converter 500 according to the prior art is depicted. The DC / DC boost converter 500 depicts an input voltage Vin, which is coupled through an inductor L to a switch node SW. A low side power transistor Ml is coupled in series with a high side power transistor M2 between a lower rail (which can be a ground plane) and an output voltage Vout (which is shown coupled to an output capacitor Cout and a load represented by an output resistor Rout). In the embodiment shown, the low side power transistor Ml is an N-type metal oxide silicon (NMOS) power transistor, while the high side power transistor M2 is a P-type metal oxide silicon (PMOS) power transistor, although these are not limiting. The gate of the low side power transistor Ml is coupled to receive a low side gate control signal LS_GATE, while the high side power transistor M2 is coupled to receive a high side gate control signal HS_GATE, both of which are provided by a boost gate driver 502. The boost gate driver 502 receives a control signal from a boost control circuit 505. The power to operate the boost control circuit 505 and the boost gate driver 502 is provided by an internal low dropout (LDO) regulator 508, which is responsible for generating both a gate driver supply voltage Vmax (not specifically shown in this figure) and a logic supply voltage AVDD from the input voltage. The internal LDO regulator 508 can also provide the logic supply voltage AVDD to other control circuits and any additional circuitry, such as a monitoring circuit (not specifically shown). The gate driver supply voltage Vmax is the larger of the input voltage Vin and the output voltage Vout. In order to operate the DC / DC boost converter 500, the internal LDO regulator 508 can sometimes draw a large current, so it is desirable to improve the efficiency of the system. This description aims to reduce this problem by harvesting a portion of the gate charge on the low side power transistor Ml and the high side power transistor M2 to provide a portion of the logic supply voltage AVDD. The gate charge is otherwise routed to the ground plane and is lost each time the gate discharges. In order to better understand how this gate charge is harvested, we first take a closer look at the boost gate driver 502.

[0022] Figure 6 A slightly more detailed example of a DC / DC boost converter 600 according to the prior art is depicted. The DC / DC boost converter 600 again includes a low side power transistor Ml and a high side power transistor M2 coupled in series between a lower rail and an output node providing an output voltage Vout. The switch node SW between the low side power transistor Ml and the high side power transistor M2 is coupled to an input voltage Vin through an inductor L. An output transistor Cout is coupled between the output voltage Vout and the lower rail; an output resistor Rout represents a load on the output.

[0023] The gate driver 602 is an example embodiment of the boost gate driver 502. The gate driver 602 is coupled to the gate of the low-side power transistor Ml and the gate of the high-side power transistor M2, and includes four gate control transistors. A first P-type gate control transistor M3 is coupled in series with a first N-type gate control transistor M4 between a gate driver supply voltage Vmax and a lower rail, with a node between the first P-type gate control transistor M3 and the first N-type gate control transistor M4 providing a low-side gate control signal LS_GATE. Similarly, a second P-type gate control transistor M5 is coupled in series with a second N-type gate control transistor M6 between the gate driver supply voltage Vmax and the lower rail, with a node between the second P-type gate control transistor M5 and the second N-type gate control transistor M6 providing a high-side gate control signal HS_GATE. A logic circuit 604 receives one or more boost control signals provided by the aforementioned voltage control and / or current control. The logic circuit 604 provides four intermediate control signals to the gates of the gate control transistors M3, M4, M5, M6, respectively: a low-side-P control signal LS_P, a low-side-N control signal LS_N, a high-side-P control signal HS_P, and a high-side-N control signal HS_N.

[0024] Figure 7 Timing related to driving one of the low-side power transistor Ml and the high-side power transistor M2 is depicted. Figure 7 Two graphs 700A, 700B are included. The graph 700A depicts voltages on the gates of the power transistors. Although the low-side power transistor Ml (which is an NMOS) turns on with the gate going high, and the high-side power transistor M2 (which is a PMOS) turns off with the gate going high, the gates of both power transistors are driven in the same manner. Due to the similar gate drive method, only one example waveform is given, with the names LS_GATE and HS_GATE replaced by a power gate control signal xx_GATE to indicate that the voltage shown can refer to either the high-side gate control signal HS_GATE or the low-side gate control signal LS_GATE. The graph 700B depicts voltages on the various gate control transistors of the gate driver 602 driving the power gate control signal xx_GATE shown in the graph 700A. Similar to the graph above, the names LS_P and HS_P are replaced by an intermediate-P control signal xx_P to indicate that the voltage can refer to the voltage on either the low-side-P control signal LS_P or the high-side-P control signal HS_P, and the names LS_N and HS_N are replaced by an intermediate-N control signal xx_N to indicate that the voltage can refer to the voltage on either the low-side-N control signal LS_N or the high-side-N control signal HS_N.

[0025] The non-overlapping of the gate drivers between the intermediate-P control signal xx_P and the intermediate-N control signal xx_N is necessary to avoid cross-conduction. This non-overlapping is shown and labeled as the P-dead time Tdead,p and the N-dead time Tdead,n, both of which are well controlled. During both the P-dead time Tdead,p and the N-dead time Tdead,n, the power gate control signals xx_GATE are both high impedance. The transition of the intermediate-P control signal xx_P and the intermediate-N control signal xx_N in the region around the P-dead time Tdead,p is divided into six time segments, indicated by the circled numbers 1-6. To facilitate the distinction of the time segments, the P-dead time Tdead,p and the N-dead time Tdead,n are drawn by long dashed lines, while the other time segments are drawn by shorter dashed lines.

[0026] During time segment (1), both the intermediate-N control signal xx_N and the intermediate-P control signal xx_P are coupled to ground. The intermediate-P control signal xx_P causes the corresponding P-type gate control transistor (either the first P-type gate control transistor M3 or the second P-type gate control transistor M5) to conduct current, and the intermediate-N control signal xx_N causes the corresponding N-type gate control transistor (either the first N-type gate control transistor M4 or the second N-type gate control transistor M6) to turn off. This results in the corresponding power gate control signal xx_GATE being at a high potential, which is a high impedance in the case of the first power gate control signal xx_GATE1, and a low impedance in the case of the second power gate control signal xx_GATE2. Figure 6The intermediate-P control signal xx_P rises during time period (2). During the P-dead time Tdead,p (which is also time period (3)), both of the gate control transistors associated with the intermediate-N control signal xx_N and the intermediate-P control signal xx_P are in an off state, and the power gate control signal xx_GATE is high impedance. This P-dead time Tdead,p that occurs after the intermediate-P control signal xx_P rises and before the intermediate-N control signal xx_N rises serves to avoid potential cross current between the gate driver supply voltage Vmax and the ground plane, and also serves to improve efficiency. During time period (4), the P-dead time Tdead,p has ended, and the voltage on the intermediate-N control signal xx_N rises to the gate driver supply voltage Vmax. The increasing voltage on the intermediate-N control signal xx_N begins to pull the voltage on the power gate control signal xx_GATE to ground. During time period (5), the dynamic transition of the power gate control signal xx_GATE ends as the power gate control signal xx_GATE is at a low potential. During time period (6), which continues until the intermediate-P control signal xx_P is grounded, the reverse operation turns off the intermediate-N control signal xx_N and the intermediate-P control signal xx_P, which will cause the power gate control signal xx_GATE to charge to a high potential again.

[0027] Figure 1A An example of a DC / DC boost converter 100A containing a gate charge harvester 106A in an integrated circuit chip 101A is depicted in accordance with an embodiment. The DC / DC boost converter 100A contains a low-side power transistor Ml and a high-side power transistor M2 coupled in series between a first pin Pl and a second pin P2, with a switch node SW coupled to a third pin. During operation of the DC / DC boost converter 100A, the first pin Pl is coupled to a ground plane, the second pin P2 is coupled to an output capacitor Cout and a load represented by a resistor Rout, and the third pin P3 is coupled to an inductor L and through the inductor L to an input voltage Vin. For simplicity and without loss of generality, it is assumed that the gates of the low-side power transistor Ml and the high-side power transistor M2 are subjected to either the gate driver supply voltage Vmax in the case of the low-side power transistor Ml or the ground plane in the case of the high-side power transistor M2, thus not violating the maximum allowed gate / source or gate / body potentials. In other embodiments (not specifically shown), the high potential of the low-side gate control signal LS_GATE and the low potential of the high-side gate control signal HS_GATE are clamped to a safe potential, such that the gates of the low-side power transistor Ml and the high-side power transistor M2 are safe.

[0028] Low-side power transistor Ml and high-side power transistor M2 are phase-inverted enabled such that DC / DC boost converter 100A operates in continuous operation to charge and discharge inductor L for energy transfer to output capacitor Cout. Turn-on and turn-off of the gates of low-side power transistor Ml and high-side power transistor M2 exhibit characteristic non-overlapping behavior to avoid cross-conduction. This non-overlap is guaranteed by the appropriate gate drive topology provided by logic circuit 104 to control low-side gate control signal LS_GATE and high-side gate control signal HS_GATE through gate driver 102. Similar gate drive non-overlap between low-side-P control signal LS_P and low-side-N control signal LS_N and between high-side-P control signal HS_P and high-side-N control signal HS_N can be used to avoid gate driver cross-conduction. This approach can be particularly important in high-power and / or high-efficiency systems or in systems where peak efficiency and / or light load efficiency is critical, where low-side power transistor Ml and high-side power transistor M2 are large and also require non-negligible gate drive circuitry.

[0029] Gate driver 102 contains first P-type gate control transistor M3 and first N-type gate control transistor M4 coupled in series between gate driver supply voltage Vmax and lower rail to provide low-side gate control signal LS_GATE, and second P-type gate control transistor M5 and second N-type gate control transistor M6 coupled in series between gate driver supply voltage Vmax and lower rail to provide high-side gate control signal HS_GATE. Gate driver 102 receives low-side-P control signal LS_P, low-side-N control signal LS_N, high-side-P control signal HS_P, and high-side-N control signal HS_N from logic circuit 104, which itself receives boost control signal as input.

[0030] The gate charge harvester 106A contains two transistors that control the harvesting of gate charge and a capacitor that can temporarily store the harvested gate charge. A low-side harvesting transistor MharvLS is coupled between a low-side gate control signal LS_GATE and a first plate of a harvesting capacitor Charv, and a high-side harvesting transistor MharvHS is coupled between a high-side gate control signal HS_GATE and the first plate of the harvesting capacitor Charv. In each of the examples presented in this application, the low-side harvesting transistor MharvLS and the high-side harvesting transistor MharvHS are shown as NMOS transistors for simplicity, although any type of transistor can be used. A harvesting gate control signal Gharv controls the timing of the low-side harvesting transistor MharvLS and the high-side harvesting transistor MharvHS. A second plate of the harvesting capacitor Charv is coupled to the lower rail. As shown below, the harvested voltage Vpre is an unregulated voltage that is less than the gate driver supply voltage Vmax and greater than the logic supply voltage AVDD. The harvested voltage Vpre also varies greatly over time and is not suitable for use as a supply voltage. Therefore, the harvested voltage Vpre is provided to a harvesting regulator 108, which can regulate the harvested voltage Vpre to generate a recirculated logic supply voltage AVDDrecyl on an AVDD capacitor Cavdd to power a resistor load Ravdd. The harvesting regulator 108 can be a simple LDO regulator or any other circuit that generates a recirculated logic supply voltage AVDDrecyl with a controlled voltage from the uncontrolled harvested voltage Vpre. Reference is made to Figure 2 The operation of the gate charge harvester 106A is described how it accommodates the operation of the gate driver 102.

[0031] Figure 2 Similar to Figure 7 but describing the differences brought by the gate charge harvester 106A. The plot 200A again depicts the charge on the power gate control signal xx_GATE, with the power gate control signal 202 depicting the charge loss when there is no charge harvesting, and the power gate control signal 204 depicting the charge loss when the charge is harvested. The harvested voltage Vpre 206 and the recirculated logic supply voltage AVDDrecyl are also shown. The plot 200B again depicts the mid-N control signal xx_N and the mid-P control signal xx_P, and also depicts the harvesting gate control signal Gharv.

[0032] The transitions of the intermediate-P control signal xx_P and the intermediate-N control signal xx_N during the time period Tdead,p are again divided into six sections, which are again denoted by the encircled numbers 1-6. During the time period (1), both the intermediate-N control signal xx_N and the intermediate-P control signal xx_P are connected to the ground plane. The low value on the intermediate-P control signal xx_P causes the respective one of the first P-type gate control transistor M3 and the second P-type gate control transistor M5 to conduct current. The low value on the intermediate-N control signal xx_N causes the respective one of the first N-type gate control transistor M4 and the second N-type gate control transistor M6 to turn off. The power gate control signal xx_GATE is at a high potential, in this example, the value of the high potential is equal to the gate driver supply voltage Vmax. During time period (2), the intermediate-N control signal xx_N remains at a low potential, and the intermediate-P control signal xx_P rises to a high potential. At the beginning of the P-dead time Tdead,p, which is also time period (3), the intermediate-N control signal xx_N keeps the respective one of the N-type gate control transistors M4, M6 in the off state, and the intermediate-P control signal xx_P keeps the respective one of the P-type gate control transistors M3, M5 in the off state.

[0033] Once both the intermediate control transistors xx_N and xx_P have kept the respective gate control transistors off for the time period (3), the harvesting gate control signal Gharv is pulled to a high potential, such that the respective gate / source voltage Vgs,harv is now greater than the harvested voltage Vpre plus the threshold voltage Vth of the harvesting transistor, and the low-side harvesting transistor MharvLS and the high-side harvesting transistor MharvHS are enabled. Instead of the power gate control signal xx_GATE having a floating potential as indicated by the old waveform in the power gate control signal 202, the power gate control signal 204 now reduces the harvesting current as indicated by the waveform. Then, the harvested voltage Vpre 206 increases to approach the value of the power gate control signal xx_GATE 204, and the follow gate potential until the end of the P-dead time Tdead,p.

[0034] During time period (4), the intermediate-N control signal xx_N rises to a high potential and begins to pull the power gate control signal xx_GATE low. At the same time, the harvest gate control signal Gharv is pulled low to stop harvesting. The power gate control signal 204 is now further discharged to a low potential, and due to the sampling of the power gate control signal 204, the harvested voltage Vpre on the harvest capacitor Charv is at a high value. During time periods (5) and (6), the gate switching does not change from the older switching pattern. From the voltage Vpre 206, such as a post-regulator of the harvest regulator 108, further down-converts the charge stored on the harvest capacitor Charv to a logic supply voltage AVDDrecyl that can be stored on a logic level capacitor Cavdd and provided to a resistor load Ravdd.

[0035] It is contemplated that a dead time between the low-side power transistor Ml and the high-side power transistor M2 also needs to be provided, although for simplicity, Figure 1A A single harvest gate control signal Gharv is depicted, but a low-side harvest gate control signal GharvLS and a high-side harvest gate control signal GharvHS can be used to control the timing of the gate harvesting from the power transistors, respectively, as will be shown in other examples.

[0036] Figure 3A high level block diagram of the DC / DC boost converter 300 according to an embodiment is depicted. Distinctions are made in this diagram between the input logic supply voltage AVDDin, the recycled logic supply voltage AVDDrecyl, and the multiplexed logic supply voltage AVDDmux which includes both AVDDin and AVDDrecl. The internal LDO regulator 308 seen previously provides the supply rail to the boost control circuit 305 and boost gate driver 302, which is now supported by the gate charge harvester 306 and decision circuit 310. The gate charge harvester 306 is coupled to harvest a portion of the gate charge on the low side power transistor Ml and high side power transistor M2 at any time when switching activity is present on the low side power transistor Ml and high side power transistor M2. After regulating the harvested voltage Vpre, the result is provided to the decision circuit 310 as the recycled logic supply voltage AVDDrecyl. The decision circuit 310 multiplexes the input logic supply voltage AVDDin from the internal LDO regulator 308 and the recycled logic supply voltage AVDDrecyl from the gate charge harvester 306 to provide the multiplexed logic supply voltage AVDDmux. Because there can be periods of time during operation of the DC / DC boost converter 300 when the low side power transistor Ml and high side power transistor M2 are not switching, the decision circuit 310 must ensure that the use of the recycled logic supply voltage AVDDrecyl does not interfere with critical switching operations. In one embodiment, the decision circuit 310 utilizes the recycled logic supply voltage AVDDrecyl to power only the non-switching critical portions of the boost converter. In one embodiment, the decision circuit 310 ensures proper multiplexing of the input logic supply voltage AVDDin and the recycled logic supply voltage AVDDrecyl as soon as switching of the low side power transistor Ml and high side power transistor M2 begins or stops, and the recycled logic supply voltage AVDDrecyl is established or collapses.

[0037] Figure 4A For the analog, the efficiency of AVDD supply current generation on the increased logic level current load is compared for the circuit with the gate charge harvester versus the prior art circuit without the gate charge harvester. Current consumption at the current load I AVDD increase level is simulated first, Table 1 shows the results for the prior art circuit, and Table 2 provides the results for the circuit with the gate charge harvester.

[0038] Table 1 No Gate Charge Harvester

[0039] I_AVDD I_SUM I_VMAX I_VIN I_HARV 0 1.334 mA 1.33 mA 4.5 uA 0 20 uA 1.354 mA 1.33 mA 24.5 uA 0 40 uA 1.374 mA 1.33 mA 44.4 uA 0 60 uA 1.393 mA 1.33 mA 64.3 uA 0 80 uA 1.413 mA 1.33 mA 84.2 uA 0 100 uA 1.433 mA 1.33 mA 104 uA 0

[0040] In these tables, I_AVDD is the current load, I_VMAX is the current generated to provide the gate driver supply voltage, I_VIN is the current generated to provide the logic supply voltage, I_SUM is the sum of the generated currents (I_VMAX + I_VIN), and I_HARV is the current harvested by the gate charge harvester. In Table 1, no gate charge is harvested, and the harvested current I_HARV is zero for all values of the current load I_AVDD. As the value of the current load I_AVDD increases, the gate current drawn as I_MAX remains constant, but the current generated to provide the logic supply voltage I_VIN increases, so I_SUM also increases as the current load I_AVDD increases.

[0041] Table 2 with gate charge harvester

[0042] I_AVDD I_SUM I_VMAX I_VIN I_HARV 0 1.33 mA 1.33 mA 0 0 20 uA 1.33 mA 1.33 mA 0 24.5 uA 40 uA 1.33 mA 1.33 mA 0 44.4 uA 60 uA 1.33 mA 1.33 mA 0 64.3 uA 80 uA 1.33 mA 1.33 mA 0 84.2 uA 100 uA 1.33 mA 1.33 mA 0 104 uA

[0043] In Table 2, the gate charge harvester provides the logic supply voltage, so there is no need to generate the current I_VIN for this purpose. Since the current generated to provide the gate driver supply voltage I_VMAX is constant, the value of I_SUM is also constant. Based on the values of the sum of the generated currents I_SUM shown in the two tables above, efficiency calculations were performed with the input voltage Vin equal to 3.8 V, the output voltage Vout equal to 4.6 V, and the output current Iout equal to 10 mA. The results are shown in Table 3 below, which describes the efficiency of the prior art circuit decreasing linearly as the current load I_AVDD increases, while the efficiency of the circuit remains constant between the values of the current load I_AVDD. Figure 4A

[0044] Table 3 efficiency improvement

[0045]

[0046] Figure 4B Efficiency calculations for the prior art circuit of Figure 5 and the circuit of Figure 1A are depicted in the range of output currents Iout. In Figure 4B , the efficiency of both circuits increases as the output current Iout increases. At the lowest output current Iout value of 1.00E-03, there is a small but noticeable improvement using the gate charge harvester, while at the highest output current Iout value of 1.00E-01, the efficiencies are practically the same. In Figure 4C ​The efficiency improvement over the prior art is quantified more clearly in the graph. In this graph, it can be seen that the efficiency improvement of the gate charge harvester is about 1.44% at the lowest output current Ioutof 1.00E-3, and about 0.08% at the highest output current Ioutof 1.00E-1.

[0047] Simulations were also performed to determine the ramp time of the harvested voltage Vpreand the recycled logic supply voltage AVDDrecyl. The rate at which the harvested voltage Vpreramps up depends on the size of the harvesting transistors MharvLSand MharvHS, while the rate at which the recycled logic supply voltage AVDDrecylramps up depends on the bandwidth of the regulator 108. The simulations were performed with an input voltage Vinof 3.8 V and an output voltage Voutof 4.6 V. In one embodiment, the harvested voltage Vpreramps up to an average voltage of about 4.5 V in about 10 μβ, while the recycled logic supply voltage AVDDrecylramps up to a value of about 1.8 V in about 60 μβ.

[0048] Although the gate charge harvester 106A has been described as part of the DC / DC boost converter 100A having a PMOS power transistor for the high-side power transistor M2, the gate charge harvester can be used in other circuits. Figure 1BA DC / DC boost converter 100B is depicted that is implemented on an IC chip 101B and contains a gate charge harvester 106B according to an embodiment. The DC / DC boost converter 100B is similar in most respects to the DC / DC boost converter 100A, but differs in several important respects. To avoid repetition, the similarities are not repeated and only the differences are focused on. In the DC / DC boost converter 100B, instead of being equipped with a PMOS power transistor for the high-side power transistor M2, an NMOS power transistor is utilized. As is known, a bootstrap gate driver (not specifically shown) provides a bootstrap voltage Vboot to the high-side driver circuit. Also, while a single harvest gate control signal Gharv is shown in the gate charge harvester 106A, the gate charge harvester 106B contains two separate gate control signals. A high-side harvest gate control signal GharvHS is provided to the high-side harvest transistor MharvHS and a low-side harvest gate control signal GharvLS is provided to the low-side harvest transistor MharvLS. In at least one embodiment, the low-side harvest gate control signal GharvLS is coupled high during a first dead time of both the first P-type gate control transistor M3 and the first N-type gate control transistor M4, which occurs when the first P-type gate control transistor M3 has turned off and the N-type gate control transistor M4 has not yet turned on. Similarly, the high-side harvest gate control signal GharvHS is coupled high during a second dead time of both the second P-type gate control transistor M5 and the second N-type gate control transistor M6, which occurs when the second P-type gate control transistor M5 has turned off and the second N-type gate control transistor M6 has not yet turned on.

[0049] Figure 1C A DC / DC boost converter 100C is depicted that is implemented on an IC chip 101C and contains a low-side power transistor Ml coupled in series with a diode Dl between a first pin P1 and a second pin P2. A switch node SW is located between the low-side power transistor Ml and the diode Dl. During operation of the DC / DC boost converter 100C, the first pin P1 is coupled to a ground plane and the pin P2 is coupled to an output capacitor Cout to provide an output voltage Vout to a load represented by a resistor Rout. Because only a single power transistor is used in this application, the gate driver 102C contains only a first P-type gate control transistor coupled in series with a first N-type gate control transistor between a gate driver supply voltage Vmax and a lower rail, and receives a low-side-P control signal LS P and a high-side-N control signal LS N from the logic circuit 104. The gate charge harvester 106C includes a low-side harvest transistor MharvLS coupled between the gate of the low-side power transistor Ml and a first plate of a harvest capacitor Charv.

[0050] Figure 1D A high level block diagram of a DC / DC buck converter 100D implemented on an IC chip 101D and containing a gate charge harvester 106D is depicted in accordance with an embodiment. For the DC / DC buck converter 100D, a low side power transistor Ml is coupled in series with a high side power transistor M2 between a first pin PI and a second pin P2. A node between the low side power transistor Ml and the high side power transistor M2 is coupled to a third pin P3. During operation of the DC / DC buck converter 100D, the pin PI is coupled to a ground plane, the pin P2 is coupled to an input voltage Vin, and the pin P3 is coupled to provide an output voltage Vout. A gate driver 102 is again coupled to provide a low side gate control signal LS_GATE to the gate of the low side power transistor Ml and a high side gate control signal HS_GATE to the gate of the high side power transistor M2. The gate charge harvester 106D operates in a similar manner to the previously described gate charge harvesters 106A, 106B. In the illustrated embodiment, the high side power transistor M2 is a PMOS power transistor and the low side power transistor Ml is an NMOS power transistor. However, both the high side power transistor M2 and the low side power transistor Ml can be NMOS power transistors. In one embodiment, the high side power transistor M2 can be replaced by a diode, as Figure 1C shown.

[0051] The gate charge harvester harvests a portion of the gate charge that is currently wasted when the gate of a power transistor is discharged. The gate charge harvester requires only one respective harvesting transistor for each power transistor, with a harvesting control signal providing the proper timing of the charge harvesting and a harvesting capacitor on which to store the harvested charge. The harvesting process provides uncontrolled harvested charge that can then be sent to a regulator that down-converts the harvested charge to a logic supply voltage with a constant voltage. The gate charge used to turn on and turn off the power transistors is initially drawn from the input voltage Vin or the output voltage Vout, which in some embodiments can itself be obtained from the input voltage Vin by up-conversion. The gate charge harvesting can allow some of these charges to be recirculated and down-converted to provide a logic level voltage that is lower than the power gate voltage. By taking over the generation of some of the internal logic supplies, the overall efficiency of the IC chip is improved.

[0052] The claims are not limited to any particular embodiment or example, and nothing in this specification should be interpreted as suggesting that any particular feature, element, step, action, or function is essential. The use of the terms "may" and "may be" in referring to elements or steps of the example embodiments is not used to limit or clarify the example embodiments, but is intended to convey that the steps are optional. Single forms of elements are intended to encompass one or more of the elements, unless otherwise expressly stated. The description includes all structural and functional equivalents to the elements disclosed above, and such equivalents are in the scope of the claims. Thus, the exemplary embodiments described herein can be practiced with various modifications and variations, and accordingly, the examples are not limited to the specific embodiments and examples described.

Claims

1. A DC / DC boost converter circuit comprising: a ground plane adapted to be coupled to a switching node of a voltage source through an inductor, and an output terminal coupled to the switching node and adapted to be coupled to a first load; a power transistor having a drain and a source coupled in series between the ground plane and the switching node and having a gate; a gate driver circuit having an output coupled to the gate of the power transistor; a sampling capacitor having a first plate coupled to a sampled voltage output and having a second plate coupled to the ground plane; and a sampling transistor having a first terminal coupled to the gate of the power transistor and a second terminal coupled to the first plate; a sampling regulator having an input coupled to the sampled voltage output and having a second load output coupled to a second load separate from the first load.

2. The DC / DC boost converter circuit of claim 1, comprising: an internal regulator having an input adapted to be coupled to the voltage source and having an internal regulator output; a decision circuit having an input coupled to the internal regulator output, an input coupled to the second load output, and a decision output; a boost control circuit having an input coupled to the decision output and a boost control output; and wherein the gate driver circuit has an input coupled to the boost control output.

3. The DC / DC boost converter circuit of claim 2, wherein the internal regulator output provides an input logic supply voltage AVDDin.

4. The DC / DC boost converter circuit of claim 2, wherein the second load output provides a recycled supply voltage AVDDrecyl.

5. The DC / DC boost converter circuit of claim 2, wherein the decision output provides a multiplexed logic supply voltage AVDDmux.

6. The DC / DC boost converter circuit of claim 2, wherein the decision output provides a multiplexed logic supply voltage AVDDmux including an input logic supply voltage AVDDin from the internal regulator output and a recycled supply voltage AVDDrecyl from the second load output.

7. The DC / DC boost converter circuit of claim 1, wherein the power transistor is an NMOS transistor having the source connected to the ground plane and the drain connected to the switching node.

8. The DC / DC boost converter circuit of claim 1, comprising a diode having an anode connected to the switching node and a cathode connected to the output terminal.

9. The DC / DC boost converter circuit of claim 1, wherein the sampling transistor is an NMOS transistor having a drain connected to the gate of the power transistor and a source connected to the first plate. ​ 10. The DC / DC boost converter circuit of claim 1, wherein the power transistor and the cascode transistor are NMOS transistors.

11. The DC / DC boost converter circuit of claim 1, wherein the gate driver circuit has an input coupled to the second load output.

12. The DC / DC boost converter circuit of claim 1, wherein the power transistor is a first power transistor and comprising a second power transistor having one terminal connected to the switching node, having another terminal connected to the output, and having a gate.

13. The DC / DC boost converter circuit of claim 12, wherein: the gate driver circuit has a second output; the cascode transistor is a first cascode transistor; and comprising: a second cascode transistor having a first terminal coupled to the gate of the second power transistor and having a second terminal coupled to the first plate of the cascode capacitor.

14. The DC / DC boost converter circuit of claim 13, wherein the second power transistor is a PMOS transistor having a drain connected to the switching node and a source connected to the output.

15. The DC / DC boost converter circuit of claim 13, wherein the second cascode transistor is an NMOS transistor having a drain coupled to the gate of the second power transistor and a source coupled to the first plate of the cascode capacitor.

Images