Gate electrode deposition and structures formed therefrom

Abstract

The present disclosure relates to gate electrode deposition and structures formed therefrom. A method includes depositing a first work function tuning layer over a gate dielectric layer using an atomic layer deposition process. The atomic layer deposition process includes: depositing one or more first nitride monolayers; and depositing one or more carbide monolayers over the one or more first nitride monolayers. The method also includes: depositing an adhesion layer for the first work function tuning layer; and depositing a conductive material over the adhesion layer.

Description

Technical Field

[0001] The present disclosure relates generally to gate electrode deposition and structures formed therefrom. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a gate electrode is provided, the method comprising: depositing a first work function tuning layer on a gate dielectric layer using an atomic layer deposition process, wherein the atomic layer deposition process comprises: depositing one or more first nitride monolayers; and depositing one or more carbide monolayers on the one or more first nitride monolayers; depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material on the adhesion layer.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first groove between first gate spacers; depositing a p-type work function tuning layer in the first groove, wherein depositing the p-type work function tuning layer comprises: depositing a first monolayer of nitride; depositing a second monolayer of carbide on top of the first monolayer; and depositing a third monolayer of the nitride on top of the second monolayer; depositing an n-type work function tuning layer in the first groove and on top of the p-type work function tuning layer; depositing an adhesion layer in the first groove and on top of the n-type work function tuning layer; and depositing a conductive filling material in the first groove and on top of the adhesion layer.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first source / drain region; a second source / drain region; and a first gate located between the first source / drain region and the second source / drain region, the first gate including: a gate dielectric; and a gate electrode located on the gate dielectric, the gate electrode including: a first p-type work function tuning metal located on the gate dielectric, the first p-type work function tuning metal containing carbon and nitrogen; an adhesion layer located on the first p-type work function tuning metal; and a filling metal located on the adhesion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When combined with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.17A , Fig. 17B , Fig.18A and Fig.18B is a cross-sectional view of an intermediate stage in fabricating a FinFET according to some embodiments.

[0010] Fig.16A and Fig. 16B A deposition process according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] Various embodiments provide a method for depositing a work function metal (WFM) layer of a gate electrode for improved work function tuning. In some embodiments, the WFM layer is a p-type layer formed by an atomic layer deposition (ALD) process. The ALD process can deposit a combination of a nitride monolayer (e.g., titanium nitride, tantalum nitride, etc.) and a carbide monolayer (e.g., titanium carbide, tantalum carbide, etc.). By adjusting the ratio of the number of deposited carbide monolayers to the number of nitride monolayers, the work function of the gate electrode can be more accurately tuned. For example, a higher carbon-to-nitrogen ratio in the WFM layer may result in a lower work function (e.g., more n-type), and a lower carbon-to-nitrogen ratio in the WFM layer may result in a higher work function (e.g., more p-type).

[0014] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 is above and protrudes from between adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used only to refer to a semiconductor substrate or a semiconductor substrate containing an isolation region. In addition, although the fin 52 is illustrated as a single, continuous material as the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to a portion extending between adjacent isolation regions 56.

[0015] The gate dielectric layer 92 is along the sidewalls of the fin 52 and over its top surface, and the gate electrode 94 is located over the gate dielectric layer 92. The source / drain regions 82 are disposed in opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross sections used in the following figures are further shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction perpendicular to the direction of current flow between, for example, the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction of current flow between, for example, the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs), and the like.

[0017] Figures 2 to 18B is a cross-sectional view of an intermediate stage in the FinFET fabrication process according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA is shown, except for multiple fins / FinFETs. Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.17A and Fig.18A Along Figure 1The reference section AA shown is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig. 17B and Fig.18B Along Figure 1 A similar cross section BB is shown, except with multiple fins / FinFETs. Fig. 10C and Fig. 10D Along Figure 1 Reference cross section CC shown in FIG. 1 shows, in addition to multiple fins / FinFETs.

[0018] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0019] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type FinFET. The p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by a separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0020] exist Figure 3In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic.

[0021] The fins may be patterned by any suitable method. For example, the fins 52 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller spacing than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fins 52.

[0022] exist Figure 4 In the embodiment, the insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material (e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) can first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material, such as those discussed above, can be formed over the liner.

[0023] exist Figure 5In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that the top surfaces of the mask or the fin 52, respectively, are flush with the insulating material 54 after the planarization process is completed.

[0024] exist Figure 6 In the embodiment of the present invention, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed so that the upper portion of the fin 52 in the n-type region 50N and the p-type region 50P protrudes from between the adjacent STI regions 56. In addition, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., a dishing), or a combination thereof as shown. The top surface of the STI region 56 can be formed into a flat, convex surface, and / or a concave surface by appropriate etching. The STI region 56 can be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fin 52)). For example, oxide removal, such as using dilute hydrofluoric (dHF) acid, can be used.

[0025] about Figures 2 to 6 The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 can be recessed, and a material different from the fin 52 can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed over the recessed material. In further embodiments, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially grown homoepitaxial structures or heteroepitaxial structures, the epitaxially grown material can be doped in situ during growth, which can avoid previous and subsequent implants, although in situ doping and implant doping can be used together.

[0026] Furthermore, it may be advantageous to epitaxially grow a different material in the n-type region 50N (eg, NMOS region) than in the p-type region 50P (eg, PMOS region). In various embodiments, the upper portion of the fin 52 may be formed of: silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0027] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N, and an N-well may be formed in the P-type region 50P. In some embodiments, a P-well or an N-well is formed in both the n-type region 50N and the P-type region 50P.

[0028] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be implemented using photoresists and / or other masks (not shown). For example, a photoresist may be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed using a spin coating technique, and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the implantation of n-type impurities into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0029] After the p-type region 50P is implanted, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed by using a spin coating technique, and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0030] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the material of the grown epitaxial fins may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0031] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material and may be selected from a group including: amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 may be made of other materials that have high etch selectivity from etching of the isolation region (e.g., STI region 56 and / or dummy dielectric layer 60). The mask layer 64 may include one or more layers of, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed on the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 60 is shown to cover only the fin 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, extends above the STI region and between the dummy gate layer 62 and the STI region 56.

[0032] FIG. 8A to FIG. 16B Various additional steps in fabricating example devices are shown. FIG. 8A to FIG. 16B Features in either the n-type region 50N or the p-type region 50P are shown. For example, FIG. 8A to FIG. 16B The structure shown may be applicable to both the n-type region 50N and the p-type region 50P. In the text accompanying each figure, the differences, if any, in the structures of the n-type region 50N and the p-type region 50P are described.

[0033] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 (see Figure 7 ) can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The longitudinal direction of the dummy gate 72 can also be substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0034] In addition, Fig. 8A and Figure 8B In the embodiment, the gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0035] After forming the gate sealing spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 As discussed in the implantation, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 52 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a doping depth of from about 10 15 cm -3 To about 10 19 cm -3 Annealing can be used to repair implant damage and activate implanted impurities.

[0036] exist Fig.9A and Fig. 9B In the embodiment, the gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, etc.

[0037] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., before forming gate spacers 86, gate seal spacers 80 may not be etched, thereby producing an "L-shaped" gate seal spacer), spacers may be formed and removed, and the like. In addition, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region of an n-type device may be formed before forming the gate seal spacer 80, while the LDD region of a p-type device may be formed after forming the gate seal spacer 80.

[0038] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short out the subsequently formed gates of the resulting FinFETs. The material of the epitaxial source / drain regions 82 may be selected to exert stress in the corresponding channel regions 58, thereby improving performance.

[0039] The epitaxial source / drain region 82 in the n-type region 50N may be formed by masking the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a recess in the fin 52. The epitaxial source / drain region 82 in the n-type region 50N is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region 50N may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0040] The epitaxial source / drain region 82 in the p-type region 50P may be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P may include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 82 in the p-type region 50P may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0041] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions and then annealing. The source / drain regions may have a surface area of ​​about 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0042] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in n-type region 50N and p-type region 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward from the sidewalls of fin 52. Fig. 10C As shown, these facets allow adjacent source / drain regions 82 of the same FinFET to merge. Fig. 10D As shown, adjacent source / drain regions 82 remain separated after the epitaxial process is completed. Fig. 10C and Fig. 10D In the illustrated embodiment, gate spacer 86 is formed to cover a portion of the sidewalls of fin 52 extending over STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacer 86 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI region 56.

[0043] exist Fig.11A and Fig. 11B In the embodiment, a first interlayer dielectric (ILD) 88 is deposited on Fig. 10A and Fig. 10B88 is formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having a lower etch rate than the material of the overlying first ILD 88.

[0044] exist Fig. 12A and Fig. 12B In the process, a planarization process (e.g., CMP) may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0045] exist Fig.13A and Fig. 13BIn the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in the etching step(s) to form the recess 90. The portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region of the die (e.g., the core logic region) and remains in the recess 90 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 72 without etching or little etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. Then, the dummy dielectric layer 60 may be selectively removed after the dummy gate 72 is removed.

[0046] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a gate dielectric layer 92 and a gate electrode 94 are formed for replacing the gate. Fig. 14C Shows Fig. 14B Detailed view of region 89 of . The gate dielectric layer 92 may be one or more layers deposited in the recess 90, such as on the top surface and sidewalls of the fin 52, and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interfacial layer 92A of silicon oxide, such as formed by thermal oxidation or chemical oxidation, and an overlying high-k dielectric material 92B, such as a metal oxide or silicate of the following metals: hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where portions of the dummy gate dielectric 60 remain in the recess 90 , the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (eg, SiO 2 ).

[0047] Gate electrode 94 is deposited over gate dielectric layer 92 and fills the remaining portion of recess 90. Gate electrode 94 may include a metal-containing material such as titanium nitride, titanium oxide, titanium carbonitride, tantalum nitride, tantalum carbide, tantalum carbonitride, titanium aluminum, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Fig. 14B A single-layer gate electrode 94 is shown in FIG. 1 , but the gate electrode 94 may include any number of p-type work function tuning layers 94A, any number of n-type work function tuning layers 94B, one or more glue layers 94C, and a filling material 94D, such as Fig. 14C As shown. In the n-type region 50N, the p-type work function tuning layer 94A can be removed before depositing (one or more) n-type work function tuning layers 94B. After filling the recess 90, a planarization process such as CMP can be performed to remove excess portions of the material of the gate dielectric layer 92 and the gate electrode 94, which are located above the top surface of the ILD 88. Therefore, the remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack". The gate and the gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0048] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the liner layer 94A can be removed from the n-type region 50N before depositing the work function tuning layer(s) 94B. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, such that the gate dielectric layer 92 can be a different material, and / or the gate electrode 94 in each region can be formed by different processes, such that the gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0049] FIG. 15A to FIG. 15D 9 shows a cross-sectional view of forming a gate electrode 94 according to some embodiments. For ease of illustration, only a detailed view of the gate electrode of the p-type region 50P and the n-type region 50N is shown (eg, similar to Fig. 14B and Fig. 14C area 89).

[0050] exist Fig.15A In the embodiment of the present invention, a p-type work function tuning layer 94A is deposited in the recess 90 in the p-type region 50P and the n-type region 50N. In some embodiments, the p-type work function tuning layer 94A includes titanium carbide nitride (Ti—CN) formed using an ALD process. Fig.16A 2 shows a process flow of an embodiment ALD process 200 when the p-type work function tuning layer 94A includes Ti—CN. The ALD process 200 may include deposition cycles 202, 204, and 206, all of which are performed in a single process (e.g., in-situ in the same process chamber without breaking vacuum). Each of the deposition cycles 202, 204, and 206 may be performed in a single process. / Loop to In some embodiments, the ALD process 200 may be performed at a temperature in a range of 200° C. to 600° C. and a pressure in a range of 0.5 Torr to 50 Torr.

[0051] The ALD process 200 begins with one or more deposition cycles 202 to deposit one or more titanium nitride monolayers. Each deposition cycle 202 includes: pulsing a first titanium-containing precursor (e.g., TiCl4, etc.) into the ALD chamber to purge the ALD chamber; pulsing a second nitrogen-containing precursor (e.g., NH3) into the ALD chamber to purge the ALD chamber. The titanium-containing precursor reacts with the nitrogen-containing precursor to deposit a titanium nitride monolayer on the exposed surface of the recess 90. Each deposition cycle 202 deposits a single titanium nitride monolayer, and any number of deposition cycles 202 may be performed to deposit a desired number of titanium nitride monolayers.

[0052] The ALD process 200 continues with one or more deposition cycles 204 to deposit one or more titanium carbide monolayers. Each deposition cycle 204 includes: delivering a first titanium-containing precursor (e.g., TiCl4, etc.) into the ALD chamber in the form of a pulse to purge the ALD chamber; delivering a third carbon-containing precursor (e.g., trimethylaluminum (TMA), triethylaluminum (TEA), etc.) into the ALD chamber in the form of a pulse to purge the ALD chamber. The titanium-containing precursor reacts with the carbon-containing precursor to deposit a titanium carbide monolayer on the exposed surface of the groove 90. Each deposition cycle 204 deposits a single titanium carbide monolayer, and any number of deposition cycles 204 can be performed to deposit a desired number of titanium carbide monolayers.

[0053] Subsequently, the ALD process 200 continues with one or more deposition cycles 206 to deposit one or more additional titanium nitride monolayers. Each deposition cycle 206 includes: delivering a first titanium-containing precursor (e.g., TiCl4, etc.) into the ALD chamber in a pulsed form to purge the ALD chamber; delivering a second nitrogen-containing precursor (e.g., NH3) into the ALD chamber in a pulsed form to purge the ALD chamber. Similar to the deposition cycle 202, the titanium-containing precursor reacts with the nitrogen-containing precursor to deposit a titanium nitride monolayer on the exposed surface of the recess 90. Each deposition cycle 206 deposits a single titanium nitride monolayer, and any number of deposition cycles 206 may be performed to deposit a desired number of titanium nitride monolayers on top of the titanium carbide monolayer.

[0054] Alternatively, in some embodiments, the p-type work function tuning layer 94A includes tantalum carbide nitride (Ta—CN) formed using an ALD process. Fig. 16B 2 shows a process flow of an embodiment ALD process 210 when the p-type work function tuning layer 94A includes Ta-CN. The ALD process 210 may include deposition cycles 212, 214, and 216, all of which are performed in a single process (e.g., in-situ in the same process chamber without breaking vacuum). Each of the deposition cycles 212, 214, and 216 may be performed in a single process. / Loop to In some embodiments, the ALD process 210 may be performed at a temperature in a range of 200° C. to 600° C. and a pressure in a range of 0.5 Torr to 50 Torr.

[0055] The ALD process 210 begins with one or more deposition cycles 212 to deposit one or more tantalum nitride monolayers. Each deposition cycle 212 includes: delivering a fourth tantalum-containing precursor (e.g., TaCl5, etc.) into the ALD chamber in a pulsed form to purge the ALD chamber; delivering a second nitrogen-containing precursor (e.g., NH3) into the ALD chamber in a pulsed form to purge the ALD chamber. The tantalum-containing precursor reacts with the nitrogen-containing precursor to deposit a tantalum nitride monolayer on the exposed surface of the recess 90. Each deposition cycle 212 deposits a single tantalum nitride monolayer, and any number of deposition cycles 212 may be performed to deposit a desired number of tantalum nitride monolayers.

[0056] The ALD process 210 continues with one or more deposition cycles 214 to deposit one or more tantalum carbide monolayers. Each deposition cycle 214 includes: delivering a fourth tantalum-containing precursor (e.g., TaCl5, etc.) into the ALD chamber in a pulsed form to purge the ALD chamber; delivering a third carbon-containing precursor (e.g., TMA, TEA, etc.) into the ALD chamber in a pulsed form to purge the ALD chamber. The tantalum-containing precursor reacts with the carbon-containing precursor to deposit a titanium carbide monolayer on the exposed surface of the recess 90. Each deposition cycle 214 deposits a single tantalum carbide monolayer, and any number of deposition cycles 214 may be performed to deposit a desired number of tantalum carbide monolayers.

[0057] Subsequently, the ALD process 210 continues with one or more deposition cycles 216 to deposit one or more additional tantalum nitride monolayers. Each deposition cycle 216 includes: delivering a fourth tantalum-containing precursor (e.g., TaCl5, etc.) into the ALD chamber in a pulsed form to purge the ALD chamber; delivering a second nitrogen-containing precursor (e.g., NH3) into the ALD chamber in a pulsed form to purge the ALD chamber. Similar to the deposition cycle 212, the tantalum-containing precursor reacts with the nitrogen-containing precursor to deposit a tantalum nitride monolayer on the exposed surface of the recess 90. Each deposition cycle 216 deposits a single tantalum nitride monolayer, and any number of deposition cycles 216 may be performed to deposit a desired number of tantalum nitride monolayers on top of the tantalum carbide monolayer.

[0058] By adjusting the number of carbide deposition cycles in the ALD process (e.g., cycles 204 or 214 described above) and / or adjusting the number of nitrogen deposition cycles in the ALD process (e.g., cycles 202, 206, 212, and / or 216 described above), the carbon to nitrogen ratio in the p-type work function tuning layer 94A can be adjusted to achieve a desired work function. For example, by increasing the number of carbide deposition cycles in the ALD process, the carbon to nitrogen ratio in the p-type work function tuning layer 94A can be increased. By depositing the p-type work function tuning layer 94A to have a relatively high carbon to nitrogen ratio, a lower work function (e.g., more n-type) can be achieved. Additionally, by depositing the p-type work function tuning layer 94A to have a relatively low carbon to nitrogen ratio, a higher work function (e.g., more p-type) can be achieved. In some embodiments, the carbon to nitrogen ratio in the p-type work function tuning layer 94A is in a range of 0.05 to 0.95. In some embodiments, the carbon to nitrogen ratio in the p-type work function tuning layer 94A is in the range of 0.05 to 0.55, which allows for precise tuning of the work functions (and associated threshold voltages) of the various transistors of the device. Thus, various embodiments provide a method for tuning the work function of a p-type work function tuning layer with improved accuracy.

[0059] In addition, although only one p-type work function tuning layer is shown, it should be understood that some embodiments may include a semiconductor device having a first gate electrode and a second gate electrode with different p-type work function tuning layers. For example, the first gate electrode may include a first p-type work function tuning layer having a first carbon-nitrogen ratio, and the second gate may include a second p-type work function tuning layer having a second carbon-nitrogen ratio. The first carbon-nitrogen ratio may be different from the second carbon-nitrogen ratio. The first p-type work function tuning layer and the second p-type work function tuning layer may be selectively formed, for example, by appropriately masking a groove for each of the first gate electrode and the second gate electrode during deposition and / or etching of the first and / or second p-type work function tuning layers. In this way, based on the circuit design, different types of gate electrodes may be formed with different p-type work function tuning layers, different work functions, and different threshold voltages. For example, in some embodiments, the first carbon-nitrogen ratio may be higher than the second carbon-nitrogen ratio, and thus the first gate electrode may have a lower work function (e.g., a lower threshold voltage) than the second gate electrode.

[0060] refer to Fig. 15B , processing can continue by removing the p-type work function tuning layer 94A from the recess 90 in the n-type region 50N while leaving the p-type work function tuning layer 94A in the recess 90 in the p-type region 50P. In some embodiments, selectively removing the p-type work function tuning layer 94A from the n-type region 50N can be achieved by masking the p-type work function tuning layer 94A in the p-type region 50P. For example, a mask (e.g., a backside anti-reflective (BARC) layer) can be deposited in the recess 90 in the p-type region 50P to cover the p-type work function tuning layer 94A while performing an etching process to remove the p-type work function tuning layer 94A from the n-type region 50N. After the etching process, the mask can then be removed.

[0061] exist Fig. 15C , an n-type work function tuning layer 94B is then conformally formed in the grooves 90 in the n-type region 50N and the p-type region 50P. In addition, the n-type work function tuning layer 94B can be deposited on the p-type work function tuning layer 94C in the p-type region 50P. The n-type work function tuning layer 94B can be any acceptable material that tunes the work function of the device to a desired amount in consideration of the application of the device to be formed, and can be deposited using any acceptable deposition process. In some embodiments, the n-type work function tuning layer 94B can include aluminum (Al), aluminum nitride (AlN), titanium aluminum (TiAl), tantalum aluminum (TaAl), etc. deposited by ALD, CVD, PVD, etc.

[0062] exist Fig.15DIn the embodiment, an adhesion layer or glue layer 94C is conformally formed on the n-type work function tuning layer 94B in the n-type region 50N and the p-type region 50P. The glue layer 116 may include titanium nitride (TiN) or the like deposited by ALD or the like. Fig.15D In the embodiment, a conductive material 94D is deposited on the glue layer 94C. The conductive material D9 may include a metal, such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), and combinations thereof. The conductive material 94D may be deposited using CVD, PVD, or a combination thereof. The conductive material 94D fills the remaining portion of the groove 90.

[0063] After depositing the conductive material 94D, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 92, the p-type work function tuning layer 94A, the n-type work function tuning layer 94B, the glue layer 94C, and the conductive material 94D, which are located above the top surface of the ILD 90, to form the gate dielectric 92 and the gate electrode 94.

[0064] exist Fig.15A and Fig. 15B In the embodiment of the present invention, a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask may be disposed between the opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack to form a groove directly over the gate stack and between the opposing portions of the gate spacers 86. The gate mask 96 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 88.

[0065] Also like Fig.17A and Fig. 17B As shown, the second ILD 108 is deposited on the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 ( Fig.18A and Fig.18B ) passes through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0066] exist Fig.18A and Fig.18BIn some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown) (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contacts 112 and the gate contact 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 may be formed in different cross sections, which may avoid shorting of the contacts.

[0067] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate wraparound structures, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. A dummy gate stack and source / drain regions are formed in a manner similar to the above-described embodiments. After removing the dummy gate stack, the sacrificial layer in the channel region can be partially or completely removed. A replacement gate structure is formed in a manner similar to the above-described embodiments, the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts of the replacement gate structure and the source / drain region can be formed in a manner similar to the above-described embodiments. A nanostructured device as disclosed in U.S. Patent Application Publication No. 2016 / 0365414 can be formed, the entire contents of which are incorporated herein by reference.

[0068] Various embodiments provide a method for depositing a WFM layer of a gate electrode for improved work function tuning. In some embodiments, the WFM layer is a p-type layer formed by an ALD process. The ALD process can deposit a combination of a nitride monolayer (e.g., titanium nitride, tantalum nitride, etc.) and a carbide monolayer (e.g., titanium carbide, tantalum carbide, etc.). By adjusting the ratio of the number of deposited carbide monolayers to the number of nitride monolayers, the work function of the gate electrode can be more accurately tuned. For example, a higher carbon-nitrogen ratio in the WFM layer may result in the WFM layer having a lower work function (e.g., more n-type), and a lower carbon-nitrogen ratio in the WFM layer may result in the WFM layer having a higher work function (e.g., more p-type).

[0069] In some embodiments, a method for forming a gate electrode comprises: depositing a first work function tuning layer on a gate dielectric layer using an atomic layer deposition process, wherein the atomic layer deposition process comprises: depositing one or more first nitride monolayers; and depositing one or more carbide monolayers on the one or more first nitride monolayers; depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material on the adhesion layer. Optionally, in some embodiments, depositing the one or more first nitride monolayers comprises: delivering a metal-containing precursor in a deposition chamber performing the atomic layer deposition process in a pulsed form; and delivering a nitrogen-containing precursor in a pulsed form in the deposition chamber. Optionally, in some embodiments, the metal-containing precursor is TiCl4 and the nitrogen-containing precursor is NH3. Optionally, in some embodiments, the metal-containing precursor is TaCl5 and the nitrogen-containing precursor is NH3. Optionally, in some embodiments, depositing the one or more carbide monolayers comprises: delivering a metal-containing precursor in a deposition chamber performing the atomic layer deposition process in the form of pulses; and delivering a carbon-containing precursor in the deposition chamber in the form of pulses. Optionally, in some embodiments, the metal-containing precursor is TiCl4, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA). Optionally, in some embodiments, the metal-containing precursor is TaCl5, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA). Optionally, in some embodiments, the atomic layer deposition process further comprises depositing one or more second nitride monolayers on top of the one or more carbide monolayers. Optionally, in some embodiments, the method further comprises depositing a second work function tuning layer on the first work function tuning layer before depositing the adhesion layer. Optionally, in some embodiments, the first work function tuning layer is a p-type layer, and wherein the second work function tuning layer is an n-type layer.

[0070] In some embodiments, a method includes: forming a first recess between first gate spacers; depositing a p-type work function tuning layer in the first recess, wherein depositing the p-type work function tuning layer includes: depositing a first monolayer of nitride; depositing a second monolayer of carbide on top of the first monolayer; and depositing a third monolayer of nitride on top of the second monolayer; depositing an n-type work function tuning layer in the first recess and on top of the p-type work function tuning layer; depositing an adhesion layer in the first recess and on top of the n-type work function tuning layer; and depositing a conductive fill material in the first recess and on top of the adhesion layer. Optionally, in some embodiments, depositing the first monolayer and depositing the third monolayer include depositing a tantalum-containing monolayer. Optionally, in some embodiments, depositing the first monolayer and depositing the third monolayer include depositing a titanium-containing monolayer. Optionally, in some embodiments, the method further comprises: forming a second recess between the second gate spacers; depositing the p-type work function tuning layer in the second recess; removing a first portion of the p-type work function tuning layer from the second recess while masking a second portion of the p-type work function tuning layer in the first recess; depositing the n-type work function tuning layer in the second recess after removing the first portion of the p-type work function tuning layer; depositing the adhesion layer in the second recess over the n-type work function tuning layer; and depositing the conductive fill material in the second recess over the adhesion layer. Optionally, in some embodiments, depositing the second monolayer comprises flowing a carbon-containing precursor, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

[0071] In some embodiments, a device includes: a first source / drain region; a second source / drain region; and a first gate located between the first source / drain region and the second source / drain region, the first gate including: a gate dielectric; and a gate electrode located on the gate dielectric, the gate including: a first p-type work function tuning metal located on the gate dielectric, the first p-type work function tuning metal comprising carbon and nitrogen; an adhesion layer located on the first p-type work function tuning metal; and a filler metal located on the adhesion layer. Optionally, in some embodiments, the first p-type work function tuning metal further comprises titanium. Optionally, in some embodiments, the first p-type work function tuning metal further comprises tantalum. Optionally, in some embodiments, the device further comprises an n-type work function tuning metal located between the first p-type work function tuning metal and the adhesion layer. Optionally, in some embodiments, the carbon-nitrogen ratio in the first p-type work function tuning metal is in a range between 0.05 and 0.55.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0073] Example 1 is a method for forming a gate electrode, the method comprising: depositing a first work function tuning layer on a gate dielectric layer using an atomic layer deposition process, wherein the atomic layer deposition process comprises: depositing one or more first nitride monolayers; and depositing one or more carbide monolayers on the one or more first nitride monolayers; depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material on the adhesion layer.

[0074] Example 2 is the method described in Example 1, wherein depositing the one or more first nitride monolayers includes: delivering a metal-containing precursor in a pulsed form in a deposition chamber performing the atomic layer deposition process; and delivering a nitrogen-containing precursor in a pulsed form in the deposition chamber.

[0075] Example 3 is the method of Example 2, wherein the metal-containing precursor is TiCl4 and the nitrogen-containing precursor is NH3.

[0076] Example 4 is the method described in Example 2, wherein the metal-containing precursor is TaCl5 and the nitrogen-containing precursor is NH3.

[0077] Example 5 is the method described in Example 1, wherein depositing the one or more carbide monolayers includes: delivering a metal-containing precursor in a pulsed form in a deposition chamber performing the atomic layer deposition process; and delivering a carbon-containing precursor in a pulsed form in the deposition chamber.

[0078] Example 6 is the method of Example 5, wherein the metal-containing precursor is TiCl4, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

[0079] Example 7 is the method of Example 5, wherein the metal-containing precursor is TaCl5, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

[0080] Example 8 is the method of Example 1, wherein the atomic layer deposition process further includes depositing one or more second nitride monolayers over the one or more carbide monolayers.

[0081] Example 9 is the method of Example 1, wherein the method further comprises depositing a second work function tuning layer on the first work function tuning layer before depositing the adhesion layer.

[0082] Example 10 is the method of Example 9, wherein the first work function tuning layer is a p-type layer, and wherein the second work function tuning layer is an n-type layer.

[0083] Example 11 is a method for forming a semiconductor device, comprising: forming a first groove between a first gate spacer; depositing a p-type work function tuning layer in the first groove, wherein depositing the p-type work function tuning layer comprises: depositing a first monolayer of nitride; depositing a second monolayer of carbide on top of the first monolayer; and depositing a third monolayer of the nitride on top of the second monolayer; depositing an n-type work function tuning layer in the first groove and on top of the p-type work function tuning layer; depositing an adhesion layer in the first groove and on top of the n-type work function tuning layer; and depositing a conductive filling material in the first groove and on top of the adhesion layer.

[0084] Example 12 is the method of 11, wherein depositing the first monolayer and depositing the third monolayer include depositing a tantalum-containing monolayer.

[0085] Example 13 is the method of Example 11, wherein depositing the first monolayer and depositing the third monolayer include depositing a titanium-containing monolayer.

[0086] Example 14 is the method described in Example 11, further including: forming a second groove between the second gate spacers; depositing the p-type work function tuning layer in the second groove; removing a first portion of the p-type work function tuning layer from the second groove while masking a second portion of the p-type work function tuning layer in the first groove; depositing the n-type work function tuning layer in the second groove after removing the first portion of the p-type work function tuning layer; depositing the adhesion layer in the second groove and on top of the n-type work function tuning layer; and depositing the conductive filling material in the second groove and on top of the adhesion layer.

[0087] Example 15 is the method of Example 11, wherein depositing the second monolayer includes flowing a carbon-containing precursor, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

[0088] Example 16 is a semiconductor device comprising: a first source / drain region; a second source / drain region; and a first gate located between the first source / drain region and the second source / drain region, the first gate comprising: a gate dielectric; and a gate electrode located on the gate dielectric, the gate electrode comprising: a first p-type work function tuning metal located on the gate dielectric, the first p-type work function tuning metal comprising carbon and nitrogen; an adhesion layer located on the first p-type work function tuning metal; and a filling metal located on the adhesion layer.

[0089] Example 17 is the device of Example 16, wherein the first p-type work function tuning metal further comprises titanium.

[0090] Example 18 is the device of Example 16, wherein the first p-type work function tuning metal further comprises tantalum.

[0091] Example 19 is the device of Example 16, further comprising an n-type work function tuning metal located between the first p-type work function tuning metal and the adhesion layer.

[0092] Example 20 is the device of Example 16, wherein a carbon-nitrogen ratio in the first p-type work function tuning metal is in a range of 0.05 to 0.55.

Claims

1. A method for forming a gate electrode, the method comprising: Depositing a first work function tuning layer on the gate dielectric layer using an atomic layer deposition process, wherein the atomic layer deposition process comprises: depositing one or more first nitride monolayers; depositing one or more carbide monolayers over the one or more first nitride monolayers; and depositing one or more second nitride monolayers over the one or more carbide monolayers; depositing an adhesion layer of the first work function tuning layer; and A conductive material is deposited over the adhesion layer.

2. The method according to claim 1, wherein: Depositing the one or more first nitride monolayers comprises: delivering a metal-containing precursor in pulses in a deposition chamber performing the atomic layer deposition process; and A nitrogen-containing precursor is delivered in pulses within the deposition chamber.

3. The method according to claim 2, wherein: The metal-containing precursor is TiCl4, and the nitrogen-containing precursor is NH3.

4. The method according to claim 2, wherein: The metal-containing precursor is TaCl5, and the nitrogen-containing precursor is NH3.

5. The method according to claim 1, wherein: Depositing the one or more carbide monolayers comprises: delivering a metal-containing precursor in pulses in a deposition chamber performing the atomic layer deposition process; and A carbon-containing precursor is delivered in pulses within the deposition chamber.

6. The method according to claim 5, wherein: The metal-containing precursor is TiCl4, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

7. The method according to claim 5, wherein: The metal-containing precursor is TaCl5, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

8. The method according to claim 1, wherein: The method also includes depositing a second work function tuning layer on the first work function tuning layer before depositing the adhesion layer.

9. The method according to claim 8, wherein: The first work function tuning layer is a p-type layer, and wherein the second work function tuning layer is an n-type layer.

10. A method for forming a semiconductor device, comprising: forming a first recess between the first gate spacers; Depositing a p-type work function tuning layer in the first groove, wherein depositing the p-type work function tuning layer comprises: depositing a first monolayer of nitride; depositing a second monolayer of carbide over the first monolayer; and depositing a third monolayer of the nitride over the second monolayer; depositing an n-type work function tuning layer in the first groove and on the p-type work function tuning layer; depositing an adhesion layer in the first groove and over the n-type work function tuning layer; and A conductive fill material is deposited in the first recess over the adhesion layer.

11. The method according to claim 10, wherein: Depositing the first monolayer and depositing the third monolayer include depositing a tantalum-containing monolayer.

12. The method according to claim 10, wherein: Depositing the first monolayer and depositing the third monolayer include depositing a titanium-containing monolayer.

13. The method according to claim 10, further comprising: forming a second recess between the second gate spacers; depositing the p-type work function tuning layer in the second groove; removing a first portion of the p-type work function tuning layer from the second groove while masking a second portion of the p-type work function tuning layer in the first groove; depositing the n-type work function tuning layer in the second groove after removing the first portion of the p-type work function tuning layer; depositing the adhesion layer in the second groove and over the n-type work function tuning layer; as well as The conductive fill material is deposited in the second recess over the adhesion layer.

14. The method according to claim 10, wherein: Depositing the second monolayer includes flowing a carbon-containing precursor, and wherein the carbon-containing precursor is trimethylaluminum (TMA) or triethylaluminum (TEA).

15. A semiconductor device comprising: a first source / drain region; a second source / drain region; as well as A first gate is located between the first source / drain region and the second source / drain region, and the first gate includes: a gate dielectric; and A gate electrode is located on the gate dielectric, and the gate electrode comprises: A first p-type work function tuning metal is located on the gate dielectric, the first p-type work function tuning metal contains carbon and nitrogen, wherein the first p-type work function tuning metal includes: a first monolayer of nitride; a second monolayer of carbide over the first monolayer; and a third monolayer of said nitride over said second monolayer; an adhesion layer located on the first p-type work function tuning metal; and A filler metal is located on the bonding layer.

16. The semiconductor device according to claim 15, wherein: The first p-type work function tuning metal further comprises titanium.

17. The semiconductor device according to claim 15, wherein: The first p-type work function tuning metal further comprises tantalum. 18 . The semiconductor device of claim 15 , further comprising an n-type work function tuning metal between the first p-type work function tuning metal and the adhesion layer.

19. The semiconductor device according to claim 15, wherein: The carbon-to-nitrogen ratio in the first p-type work function tuning metal is in the range of 0.05 to 0.55.

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