Semiconductor equipment

Abstract

A semiconductor device may include: a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and an external terminal. A bottom surface of the substrate may include a first region and a second region spaced apart from each other. The first semiconductor chip may have a first active surface facing a top surface of a core portion of the substrate. The first antenna pattern may be disposed on the top surface of the substrate and electrically connected to the first semiconductor chip. The external terminal may be disposed on the first region of the bottom surface of the substrate, and the second antenna pattern may be disposed on the second region of the bottom surface of the substrate.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10 - 2020 - 0049074, filed with the Korean Intellectual Property Office on April 23, 2020, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including an antenna. Background art

[0004] To meet the increasing demand for high - performance electronic devices recently, it is necessary to increase the frequency and bandwidth of electromagnetic waves of each component to be used in mobile devices such as smart phones. Specifically, for millimeter - wave and 5G antenna modules, it is not only necessary to reduce the size of the module, but also to minimize the interference between components in the antenna module. In addition, to ensure the degree of freedom of the installation position in the device, there are many restrictions on the geometric characteristics (e.g., size, thickness, etc.) of the module. Summary of the invention

[0005] Embodiments of the inventive concept provide a semiconductor device including an antenna pattern configured to reduce a shadow region and improve signal radiation efficiency.

[0006] Embodiments of the inventive concept provide a semiconductor device having a reduced size.

[0007] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics.

[0008] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate, a bottom surface of the substrate including a first region and a second region spaced apart from each other; a first semiconductor chip buried in the substrate, the first semiconductor chip having a first active surface facing a top surface of a core portion of the substrate; a first antenna pattern disposed on the top surface of the substrate and electrically connected to the first semiconductor chip; a second antenna pattern disposed on the first region of the bottom surface of the substrate; and external terminals disposed on the second region of the bottom surface of the substrate.

[0009] According to an embodiment of the inventive concept, a semiconductor device may include: a core portion having a first surface and a second surface opposite to each other; a first build portion and a second build portion disposed on the first surface and the second surface, respectively, each of the first build portion and the second build portion including a plurality of insulating layers and a plurality of interconnect layers stacked in sequence; a first semiconductor chip disposed in a first mounting region formed by partially removing the core portion and electrically connected to the first build portion; a first antenna pattern disposed on a surface of the first build portion; a second antenna pattern disposed on a surface of the second build portion; and an external terminal disposed on a surface of the second build portion. The second antenna pattern may be disposed on a first region of the second build portion. The external terminal may be disposed on a second region of the second build portion, the second region being different from the first region.

[0010] According to an embodiment of the inventive concept, a semiconductor device may include: a first redistribution substrate; a first semiconductor chip having a first active surface in contact with a top surface of the first redistribution substrate; a second redistribution substrate disposed above the first redistribution substrate to cover the first semiconductor chip; a vertical connection terminal disposed at a side of the first semiconductor chip to vertically connect the first redistribution substrate and the second redistribution substrate to each other; a first antenna pattern disposed on a top surface of the second redistribution substrate and electrically connected to the first semiconductor chip through the second redistribution substrate; a second antenna pattern disposed on a first region of a bottom surface of the first redistribution substrate; and an external terminal disposed on a second region of the bottom surface of the first redistribution substrate, the first region and the second region being spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be understood more clearly from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments described herein.

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0014] Figure 3 and Figure 4 is a plan view showing a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 5 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0016] Figure 6 is a plan view of a semiconductor device showing an embodiment according to the inventive concept.

[0017] Figures 7 to 10 are cross-sectional views of a semiconductor device showing embodiments according to the inventive concept. Detailed Description

[0018] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings showing example embodiments.

[0019] Figure 1 is a cross-sectional view of a semiconductor device showing an embodiment according to the inventive concept. Figure 2 is a cross-sectional view of a semiconductor device showing an embodiment according to the inventive concept. Figure 3 and Figure 4 is a plan view of a semiconductor device showing an embodiment according to the inventive concept. For example, Figure 3 is showing Figure 1 a top view of the semiconductor device, and Figure 4 is showing Figure 1 a bottom view of the semiconductor device.

[0020] Referring to Figure 1 , the semiconductor device may include: an interconnection substrate CS, a first semiconductor chip 200, a first antenna pattern 300, and a second antenna pattern 400.

[0021] The interconnection substrate CS may include: a core portion C; an upper build portion UB disposed on a top surface of the core portion C; and a lower build portion LB disposed on a bottom surface of the core portion C.

[0022] The core portion C can extend in a specific direction (e.g., horizontally). When viewed in a plan view, the core portion C can take the form of a core pattern formed by removing a portion of a continuous core layer. The area removed from the core layer can correspond to the mounting area 110, in which the first semiconductor chip 200 is placed. A core portion C having a single opening (or recess) is shown exemplarily, but the present invention is not limited to this example. In another embodiment, the core portion C may include two or more openings or recesses. In other words, the interconnect substrate CS may include multiple openings or recesses that are spaced apart from each other when viewed in a plan view. In addition, multiple discrete core portions C may be formed in the semiconductor device. The core portion C may have an insulating material. For example, the core portion C may be formed of or include at least one of glass fiber, ceramic sheet, epoxy material, or resin. Alternatively, the core portion C may be formed of or include at least one of stainless steel, aluminum (Al), nickel (Ni), magnesium (Mg), zinc (Zn), tantalum (Ta), or a combination thereof.

[0023] The vertical connection terminal 102 may be provided to vertically penetrate the core part C. The vertical connection terminal 102 may electrically connect the upper build-up part UB to the lower build-up part LB.

[0024] The first semiconductor chip 200 may be disposed in the mounting region 110 of the core portion C. The mounting region 110 may be a region formed by partially removing a continuous portion of a core layer to form the core portion C. The mounting region 110 may extend between the top surface 100a and the bottom surface 100b of the core portion C. In other words, the mounting region 110 may be defined by a via in the core portion C that extends from the top surface 100a of the core portion C to the bottom surface 100b of the core portion C. Alternatively, the mounting region 110 may take the form of a recess of the core portion C that extends from the top surface 100a of the core portion C partially through the core portion C toward the bottom surface 100b of the core portion C, as in Figure 2 As shown. Figure 1 The following description is given with reference to the structure of FIG. 1 , but the following description is also applicable to the mounting area 110 which adopts a recessed form.

[0025] The first semiconductor chip 200 may be spaced apart from the sidewall of the via hole (e.g., the inner surface of the mounting area 110 of the core part C) by a predetermined distance and may be surrounded by the inner surface of the mounting area 110 of the core part C. In other words, when observed in a plan view, the core part C may be arranged to surround the first semiconductor chip 200. The first semiconductor chip 200 may be arranged in a face-up manner. For example, the first semiconductor chip 200 may be arranged to have an active surface 200a facing the top surface 100a. The first semiconductor chip 200 may include a first chip pad 202 that faces the top surface 100a of the core part C. The active surface 200a of the first semiconductor chip 200 may be exposed at the top surface 100a of the core part C, and the passive surface 200b of the first semiconductor chip 200 may be exposed at the bottom surface 100b of the core part C. Alternatively, in Figure 2 In the case of the structure of, the first semiconductor chip 200 may be mounted on the bottom surface of the mounting area 110 such that the active surface 200a faces the top surface 100a. Accordingly, the active surface 200a of the first semiconductor chip 200 may be exposed to the outside near the top surface 100a of the core part C, and the passive surface 200b of the first semiconductor chip 200 may be in contact with the core part C. The term "contact" used in this sense means direct connection (i.e., touching). In this case, the first semiconductor chip 200 may be attached to the bottom surface of the mounting area 110 using an adhesive, a bonding film, or the like. The following description will be given again based on Figure 1 the structure of. The thickness of the first semiconductor chip 200 may be less than the total thickness of the interconnect substrate CS. For example, the thickness of the first semiconductor chip 200 may be equal to or less than the thickness of the core part C. In Figure 1 In the case of the structure shown, the thickness of the first semiconductor chip 200 may be substantially equal to the thickness of the core part C. In Figure 2 In the case of the structure shown, the thickness of the first semiconductor chip 200 may be less than the thickness of the core part C. The term described as "substantially equal" may be exactly equal or may be equal within an acceptable variation that may occur, for example, due to the manufacturing process.

[0026] The first semiconductor chip 200 may include an integrated circuit having a radio frequency integrated circuit (RFIC) to generate radio frequency signals to be transmitted through the first antenna pattern 300 and the second antenna pattern 400 and / or receive radio frequency signals to be received from the first antenna pattern 300 and the second antenna pattern 400. The first semiconductor chip 200 may be electrically connected to the first antenna pattern 300 and the second antenna pattern 400, and this may enable the transmission and reception of corresponding electromagnetic radio frequency signals (which may be referred to as antenna signals herein) in multiple directions. In some examples, the first antenna pattern 300 and the second antenna pattern 400 may be configured to operate using the same radio frequency carrier signal. For example, the first antenna pattern 300 and the second antenna pattern 400 may be the same pattern or share the same pattern, for example, having radiating elements of the same size forming the first antenna pattern 300 and the second antenna pattern 400 and having the same spacing (or the same pitch) between the radiating elements forming the first antenna pattern 300 and the second antenna pattern 400. In the embodiments described herein, the radiating elements of the first antenna pattern 300 and the second antenna pattern 400 correspond to the patch pattern 302 and the patch pattern 402 (but other antenna types may be implemented), and the radiating elements of the first antenna pattern 300 and the second antenna pattern 400 may not have a direct electrical connection to an external device (e.g., in contrast to a direct electrical connection to the substrate pad 146). In an embodiment, the integrated circuit of the first semiconductor chip 200 may include multiple electronic devices. For example, the integrated circuit may be configured to include various electronic devices, such as a power management integrated circuit (PMIC), a modem, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA), which are used to operate the foregoing radio frequency integrated circuit in addition to operating the radio frequency integrated circuit. The integrated circuit of the first semiconductor chip 200 including the radio frequency integrated circuit and the electronic devices may convert a digital signal (e.g., a baseband signal, etc.) to be transmitted from the outside into an analog signal (e.g., a high-frequency radio frequency signal, etc.), and may provide the analog signal to the first antenna pattern 300 and the second antenna pattern 400.

[0027] In the mounting area 110, the space between the core portion C and the first semiconductor chip 200 may be filled with an insulating material 104. The insulating material 104 may be formed of or include an insulating polymer.

[0028] According to an embodiment of the inventive concept, since the first semiconductor chip 200 is buried in the interconnect substrate CS, it is necessary to mount the first semiconductor chip 200 on the surface of the interconnect substrate CS, so that the semiconductor device may be provided with a reduced size.

[0029] The lower build portion LB and the upper build portion UB can respectively cover the bottom surface 100b and the top surface 100a of the core portion C. The upper build portion UB can be in contact with the top surface 100a of the core portion C and the active surface 200a of the first semiconductor chip 200. The lower build portion LB can cover the bottom surface 100b of the core portion C and the passive surface 200b of the first semiconductor chip 200.

[0030] The upper build portion UB can include a plurality of upper insulating layers 122 and a plurality of upper interconnect layers 124, which are sequentially stacked on the top surface 100a of the core portion C. The upper build portion UB can cover the top surface 100a of the core portion C and the active surface 200a of the first semiconductor chip 200. The lower build portion LB can include a plurality of lower insulating layers 142 and a plurality of lower interconnect layers 144, which are sequentially stacked on the bottom surface 100b of the core portion C. The lower build portion LB can cover the bottom surface 100b of the core portion C and the passive surface 200b of the first semiconductor chip 200. Each of the upper insulating layer 122 and the lower insulating layer 142 can be formed of or include at least one of a prepreg, an Ajinomoto build (ABF) film, FR-4, or a bismaleimide triazine (BT). Each of the upper interconnect layer 124 and the lower interconnect layer 144 can include at least one circuit pattern. The upper interconnect layer 124 can be used as a connection pattern that electrically connects the first semiconductor chip 200 to the first antenna pattern 300. The lower interconnect layer 144 can be electrically connected to the upper interconnect layer 124 through the vertical connection terminal 102 and can be used as a connection pattern that electrically connects the first semiconductor chip 200 to the second antenna pattern 400. Each of the upper interconnect layer 124 and the lower interconnect layer 144 can be formed of or include at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or a combination thereof.

[0031] The first antenna pattern 300 may be disposed on the upper build portion UB. The first antenna pattern 300 may be a planar antenna array including a plurality of first patch patterns 302 (e.g., patch antennas) disposed on the top surface UBa of the upper build portion UB. The first patch patterns 302 may be disposed throughout the top surface UBa of the upper build portion UB, so that the first antenna pattern 300 may overlap the first semiconductor chip 200 in the third direction D3. Each of the first patch patterns 302 of the first antenna pattern 300 may be a patch antenna. For example, the first patch patterns 302 may be arranged on the top surface UBa of the upper build portion UB and may be used to form broadside radiation. The first patch patterns 302 may be periodically arranged in the first direction D1 and the second direction D2, as Figure 3 shown. Each of the first patch patterns 302 may be a flat plate-like structure whose width is much larger than its thickness. The first antenna pattern 300 may be configured to receive an electrical signal from the first semiconductor chip 200 and transmit an antenna signal in an upward direction or a lateral direction of the upper build portion UB. Depending on the structure and position of the first antenna pattern 300, the antenna signal of the semiconductor device may have an omnidirectional radiation property. For example, the first antenna pattern 300 may be disposed throughout the top surface UBa of the upper build portion UB, and in this case, the antenna signal may have a wide radiation area and a large radiation angle. The first antenna pattern 300 may be formed of at least one of conductive materials (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof) or include at least one of conductive materials (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof), but the inventive concept is not limited to these examples.

[0032] According to an embodiment of the inventive concept, since the first semiconductor chip 200 is buried in the core portion C of the interconnect substrate CS and is connected to the first antenna pattern 300 only through the upper build portion UB of the interconnect substrate CS, the length of the electrical connection path between the first semiconductor chip 200 and the first antenna pattern 300 may be reduced. Accordingly, the electrical characteristics of the semiconductor device may be improved.

[0033] The external terminal 500 may be disposed below the lower build portion LB. The external terminal 500 may be disposed on a first region R1 of the bottom surface LBa of the lower build portion LB. For example, the external terminal 500 may be disposed on the substrate pad 146, and the substrate pad 146 is disposed on the first region R1 of the bottom surface LBa of the lower build portion LB. Here, the substrate pad 146 may be a part of the lower interconnect layer 144 that is exposed from the lower insulating layer 142 of the lower build portion LB, or the substrate pad 146 may be an additional pad that is disposed on the lower insulating layer 142 of the lower build portion LB and is connected to the lower interconnect layer 144. The external terminal 500 may be electrically connected to the first semiconductor chip 200 through the lower interconnect layer 144, the vertical connection terminal 102, and the upper interconnect layer 124. The external terminal 500 may include solder balls, solder bumps, etc.

[0034] The second antenna pattern 400 may be disposed below the lower build portion LB. The second antenna pattern 400 may be disposed on a second region R2 of the bottom surface LBa of the lower build portion LB. The first region R1 and the second region R2 may be arranged along a first direction D1. Thus, the second antenna pattern 400 may be spaced apart from the external terminal 500 in the first direction D1. The area of the second region R2 may be 0.5 to 2.0 times the area of the first region R1. The second antenna pattern 400 may be a planar antenna array that includes a plurality of second patch patterns 402 disposed on the bottom surface LBa of the lower build portion LB. Each of the second patch patterns 402 of the second antenna pattern 400 may be a patch antenna. For example, the second patch patterns 402 may be disposed on the bottom surface LBa of the lower build portion LB and may be used to form broadside radiation. The second patch patterns 402 may be periodically arranged in the first direction D1 and a second direction D2, as Figure 4As shown. Each of the second patch patterns 402 may be a flat plate-like structure, and the width of the flat plate-like structure is much larger than its thickness. The second antenna pattern 400 may be configured to receive an electrical signal from the first semiconductor chip 200 and transmit an antenna signal in the downward direction or the lateral direction of the lower build portion LB. The second antenna pattern 400 may be electrically connected to the first semiconductor chip 200 through the lower interconnect layer 144, the vertical connection terminals 102, and the upper interconnect layer 124. The first semiconductor chip 200 may be configured to apply electrical signals to the first antenna pattern 300 and the second antenna pattern 400 simultaneously or separately. According to the structure and position of the second antenna pattern 400, the antenna signal of the semiconductor device may have an omnidirectional radiation property. The second antenna pattern 400 may be formed of at least one of conductive materials (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof) or include at least one of conductive materials (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof), but the inventive concept is not limited to these examples.

[0035] According to an embodiment of the inventive concept, the first semiconductor chip 200 may be buried in the core portion C of the interconnect substrate CS, the second antenna pattern 400 may be disposed on the entire area below the interconnect substrate CS except for the first region R1 where the external terminals 500 are provided, and the antenna signal may have a wide radiation area and a large radiation angle in the downward direction of the semiconductor device. Therefore, in the downward direction of the semiconductor device, the shadow area of the antenna signal may be reduced and the signal radiation efficiency may be improved.

[0036] The semiconductor device may further include a third antenna pattern 600. The third antenna pattern 600 may be disposed on the side surface 100c of the core portion C. The third antenna pattern 600 may include a Yagi antenna. The third antenna pattern 600 may be electrically connected to the first semiconductor chip 200 through the upper build portion UB or the lower build portion LB. The third antenna pattern 600 may be configured to receive an electrical signal from the first semiconductor chip 200 and transmit an antenna signal in the lateral direction of the core portion C. The third antenna pattern 600 may transmit the antenna signal to the shadow area formed between the radiation area of the first antenna pattern 300 and the radiation area of the second antenna pattern 400, and thus the shadow area of the antenna signal may be reduced. In an embodiment, the third antenna pattern 600 may not be provided.

[0037] The semiconductor device can be mounted on an external substrate 1000, where the external terminals 500 are interposed between the semiconductor device and the external substrate 1000. The first semiconductor chip 200 of the semiconductor device can be electrically connected to the external substrate 1000 through the external terminals 500. In an embodiment, the external substrate 1000 can be a motherboard or main board of an external electronic product, or can be a body directly containing the semiconductor device. However, the inventive concept is not limited to this example, and the external substrate 1000 can represent one of various electronic products in which the semiconductor device can be included, mounted on, or coupled to the electronic product.

[0038] The semiconductor device can be mounted on the external substrate 1000 in a flip-chip manner. For example, between the external substrate 1000 and the lower build portion LB, the external terminals 500 can connect the external substrate pads 1002 of the external substrate 1000 to the substrate pads 146. Since the first semiconductor chip 200 is not mounted below the lower build portion LB and is buried in the core portion C, the gap between the external substrate 1000 and the lower build portion LB can be reduced. Accordingly, the size of the semiconductor device can be reduced. The distance between the external substrate 1000 and the lower build portion LB can be 1 / 4 to 1 / 2 times the wavelength of the electromagnetic wave emitted from the second antenna pattern 400.

[0039] Figure 5 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept. Figure 6 is a plan view showing a semiconductor device according to an embodiment of the inventive concept. The following description will focus on the region where the external terminals and the second antenna pattern are provided. For the sake of brevity of description, the previously described elements may be identified by the same reference numerals and will not be described again.

[0040] Figures 1 to 4 An example in which the first region R1 and the second region R2 are arranged in the first direction D1 is shown, but the inventive concept is not limited to this example.

[0041] Reference Figure 5 and Figure 6 and, the first region R1 can be located in the middle of the bottom surface LBa of the lower build portion LB. The external terminals 500 can be provided below the lower build portion LB. The external terminals 500 can be provided on the first region R1 of the bottom surface LBa of the lower build portion LB. For example, the external terminals 500 can be provided on the substrate pads 146 provided on the first region R1 of the bottom surface LBa of the lower build portion LB.

[0042] The semiconductor device can be mounted on the external substrate 1000, where the external terminal 500 is interposed between the semiconductor device and the external substrate 1000. The first semiconductor chip 200 of the semiconductor device can be electrically connected to the external substrate 1000 through the external terminal 500. Since the external terminal 500 is disposed on the first region R1 located in the middle of the lower construction part LB, the external terminal 500 can more stably support the center of gravity of the semiconductor device, and thus the structural stability of the semiconductor device can be improved.

[0043] The second region R2 can be located in the peripheral region of the bottom surface LBa of the lower construction part LB. For example, when observed in a plan view, the second region R2 can surround the first region R1. The second antenna pattern 400 can be disposed below the lower construction part LB. The second antenna pattern 400 can be disposed on the second region R2 of the bottom surface LBa of the lower construction part LB. The second antenna pattern 400 can be a planar antenna array including a plurality of second patch patterns 402 disposed on the bottom surface LBa of the lower construction part LB. Each of the second patch patterns 402 of the second antenna pattern 400 can be a patch antenna. The second antenna pattern 400 can be configured to receive an electrical signal from the first semiconductor chip 200 and transmit an antenna signal in the downward direction or the lateral direction of the lower construction part LB. Since the second antenna pattern 400 is disposed on the first region R1 located in the peripheral region of the lower construction part LB, the radiation efficiency of the antenna signal transmitted in the lateral direction of the lower construction part LB can be improved, and the shadow region of the antenna signal of the semiconductor device in the downward direction can be reduced.

[0044] Figure 7 and Figure 8 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept.

[0045] Figures 1 to 4 An example in which one first semiconductor chip is provided is shown, but the inventive concept is not limited to this example.

[0046] Reference Figure 7, not only can the first semiconductor chip 200 be disposed in the mounting area 110 of the core part C, but also the second semiconductor chip 700 can be disposed in the mounting area 110 of the core part C. The first semiconductor chip 200 and the second semiconductor chip 700 can be spaced apart from the inner surface of the mounting area 110 by a predetermined distance and can be surrounded by the inner surface of the mounting area 110. In other words, when observed in a plan view, the core part C can be arranged to surround both the first semiconductor chip 200 and the second semiconductor chip 700. In the mounting area 110, the first semiconductor chip 200 and the second semiconductor chip 700 can be spaced apart from each other. In an embodiment, the first semiconductor chip 200 can be disposed in an upward-facing manner, and the second semiconductor chip 700 can be disposed in a downward-facing manner. For example, the first semiconductor chip 200 can be arranged to have an active surface 200a facing the top surface 100a, and the second semiconductor chip 700 can be arranged to have an active surface 700a facing the bottom surface 100b. The first semiconductor chip 200 can include a first chip pad 202, and the first chip pad 202 is disposed at a level near the top surface 100a of the core part C, and the second semiconductor chip 700 can include a second chip pad 702, and the second chip pad 702 is disposed at a level near the bottom surface 100b of the core part C. The active surface 200a of the first semiconductor chip 200 can be exposed to the outside near the top surface 100a of the core part C, and the active surface 700a of the second semiconductor chip 700 can be exposed to the outside near the bottom surface 100b of the core part C.

[0047] Each of the first semiconductor chip 200 and the second semiconductor chip 700 can include an integrated circuit having a radio frequency integrated circuit (RFIC). Since the first semiconductor chip 200 is electrically connected to the first antenna pattern 300 and the second semiconductor chip 700 is electrically connected to the second antenna pattern 400, antenna signals can be transmitted in various directions. In an embodiment, the integrated circuit of each of the first semiconductor chip 200 and the second semiconductor chip 700 can include a plurality of electronic devices. For example, the integrated circuit can be configured to include various electronic devices, such as a power management integrated circuit (PMIC), a modem, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA), which are used to operate the aforementioned radio frequency integrated circuit in addition to operating the radio frequency integrated circuit.

[0048] In the mounting area 110, the space between the core part C and the first semiconductor chip 200, the space between the core part C and the second semiconductor chip 700, and the space between the first semiconductor chip 200 and the second semiconductor chip 700 can be filled with an insulating material 104.

[0049] The lower construction part LB and the upper construction part UB can respectively cover the bottom surface 100b and the top surface 100a of the core part C. The upper construction part UB can be in contact with the top surface 100a of the core part C, the active surface 200a of the first semiconductor chip 200, and the passive surface 700b of the second semiconductor chip 700. The lower construction part LB can cover the bottom surface 100b of the core part C, the passive surface 200b of the first semiconductor chip 200, and the active surface 700a of the second semiconductor chip 700.

[0050] The upper construction part UB can include an upper insulating layer 122 and an upper interconnect layer 124, which are sequentially stacked on the top surface 100a of the core part C. The upper interconnect layer 124 can be used as a connection pattern that electrically connects the first semiconductor chip 200 to the first antenna pattern 300. Since the first semiconductor chip 200 is buried in the core part C of the interconnect substrate CS and is only connected to the first antenna pattern 300 through the upper construction part UB of the interconnect substrate CS, the length of the electrical connection path between the first semiconductor chip 200 and the first antenna pattern 300 can be reduced. This can enable the electrical characteristics of the semiconductor device to be improved.

[0051] The lower construction part LB can include a lower insulating layer 142 and a lower interconnect layer 144, which are sequentially stacked on the bottom surface 100b of the core part C. The lower interconnect layer 144 can be used as a connection pattern that electrically connects the second semiconductor chip 700 to the second antenna pattern 400. Since the second semiconductor chip 700 is buried in the core part C of the interconnect substrate CS and is only connected to the second antenna pattern 400 through the lower construction part LB of the interconnect substrate CS, the length of the electrical connection path between the second semiconductor chip 700 and the second antenna pattern 400 can be reduced. This can enable the electrical characteristics of the semiconductor device to be improved.

[0052] In addition, the first semiconductor chip 200 can send an electrical signal to the first antenna pattern 300, and the second semiconductor chip 700 can send an electrical signal to the second antenna pattern 400. That is to say, the first antenna pattern 300 and the second antenna pattern 400 can be independently operated, and the antenna signals of the first antenna pattern 300 and the second antenna pattern 400 can be independently adjusted when needed.

[0053] In a specific embodiment, the first semiconductor chip 200 and the second semiconductor chip 700 can be respectively disposed on different mounting areas.

[0054] Reference Figure 8, the core part C may include a plurality of mounting areas 110. For example, the mounting area 110 may include a first mounting area 110a and a second mounting area 110b, and the first mounting area 110a and the second mounting area 110b are spaced apart from each other. In an embodiment, the first mounting area 110a and the second mounting area 110b may be spaced apart from each other in the first direction D1. Each of the first mounting area 110a and the second mounting area 110b may be an area formed by partially removing the core pattern of the core part C. Each of the first mounting area 110a and the second mounting area 110b may be exposed to the outside near the top surface 100a and the bottom surface 100b of the core part C. In other words, each of the first mounting area 110a and the second mounting area 110b may be a via-like area that extends from the top surface 100a of the core part C to the bottom surface 100b of the core part C. Alternatively, the first mounting area 110a may be a recessed area that extends from the top surface 100a of the core part C toward the bottom surface 100b of the core part C, and the second mounting area 110b may be a recessed area that extends from the bottom surface 100b of the core part C toward the top surface 100a of the core part C.

[0055] The first semiconductor chip 200 may be disposed in the first mounting area 110a, and the second semiconductor chip 700 may be disposed in the second mounting area 110b. The first semiconductor chip 200 may be spaced apart from the inner surface of the first mounting area 110a by a predetermined distance and may be surrounded by the inner surface of the first mounting area 110a. The second semiconductor chip 700 may be spaced apart from the inner surface of the second mounting area 110b by a predetermined distance and may be surrounded by the inner surface of the second mounting area 110b. The active surface 200a of the first semiconductor chip 200 may be exposed to the outside near the top surface 100a of the core part C, and the active surface 700a of the second semiconductor chip 700 may be exposed to the outside near the bottom surface 100b of the core part C.

[0056] The lower construction part LB and the upper construction part UB may cover the bottom surface 100b and the top surface 100a of the core part C, respectively. The upper construction part UB may be in contact with the top surface 100a of the core part C, the active surface 200a of the first semiconductor chip 200, and the passive surface 700b of the second semiconductor chip 700. The lower construction part LB may cover the bottom surface 100b of the core part C, the passive surface 200b of the first semiconductor chip 200, and the active surface 700a of the second semiconductor chip 700.

[0057] The upper build-up portion UB may include a plurality of upper insulating layers 122 and a plurality of upper interconnect layers 124, and the plurality of upper insulating layers 122 and the plurality of upper interconnect layers 124 are sequentially stacked on the top surface 100a of the core portion C. The upper interconnect layer 124 may serve as a connection pattern that electrically connects the first semiconductor chip 200 to the first antenna pattern 300. Since the first semiconductor chip 200 is buried in the core portion C of the interconnect substrate CS and is connected to the first antenna pattern 300 only through the upper build-up portion UB of the interconnect substrate CS, the length of the electrical connection path between the first semiconductor chip 200 and the first antenna pattern 300 can be reduced.

[0058] The lower build-up portion LB may include a plurality of lower insulating layers 142 and a plurality of lower interconnect layers 144, and the plurality of lower insulating layers 142 and the plurality of lower interconnect layers 144 are sequentially stacked on the bottom surface 100b of the core portion C. The lower interconnect layer 144 may serve as a connection pattern that electrically connects the second semiconductor chip 700 to the second antenna pattern 400. Since the second semiconductor chip 700 is disposed in the second mounting region 110b (the second mounting region 110b is disposed independently of the first mounting region 110a for the first semiconductor chip 200), the second semiconductor chip 700 can be freely disposed. Accordingly, the second semiconductor chip 700 or the second mounting region 110b can be formed near the second antenna pattern 400 connected to the second semiconductor chip 700, and this can enable the length of the electrical connection path between the second semiconductor chip 700 and the second antenna pattern 400 to be reduced. As a result, the electrical characteristics of the semiconductor device can be improved.

[0059] Figure 9 is a cross-sectional view of a semiconductor device showing an embodiment according to the inventive concept.

[0060] Reference Figure 9 , the semiconductor device may include an upper redistribution substrate 120, a semiconductor chip 200, a molding layer 104 as an insulating material, a lower redistribution substrate 140, a first antenna pattern 300, and a second antenna pattern 400.

[0061] The upper redistribution substrate 120 may include an upper dielectric layer 122 and upper redistribution patterns 124 respectively disposed in the upper dielectric layer 122. The upper redistribution substrate 120 may be configured to allow electrical connection redistribution or rewiring of the semiconductor chip 200 via the first chip pad 202 to another component (e.g., the first antenna pattern 300).

[0062] Although not shown, an upper protective layer may be disposed on the top surface of the upper redistribution substrate 120. The upper protective layer may cover the upper redistribution substrate 120.

[0063] The first antenna pattern 300 may be disposed on the upper redistribution substrate 120 or the upper protective layer. The first antenna pattern 300 may be configured to have substantially the same features as those described with reference to Figure 1 and Figure 3 For example, the first antenna pattern 300 may be arranged on the upper redistribution substrate 120 along the first direction D1 and the second direction D2, and may be electrically connected to the semiconductor chip 200 through the upper redistribution substrate 120.

[0064] The semiconductor chip 200 may be mounted on the upper redistribution substrate 120. The semiconductor chip 200 may be arranged such that the active surface 200a faces the upper redistribution substrate 120. The semiconductor chip 200 may be coupled to the upper redistribution pattern 124 of the upper redistribution substrate 120 through the chip pad 202.

[0065] The molding layer 104 may be disposed on the surface of the upper redistribution substrate 120. For example, the molding layer 104 may be arranged to cover the bottom surface of the upper redistribution substrate 120 and surround the semiconductor chip 200. The molding layer 104 may cover the side surface and the passive surface 200b of the semiconductor chip 200. The molding layer 104 may be formed of an insulating material (e.g., epoxy molding compound (EMC)) or include an insulating material (e.g., epoxy molding compound (EMC)).

[0066] The via hole 106 may be disposed in the molding layer 104. The via hole 106 may be disposed near the semiconductor chip 200 to vertically penetrate the molding layer 104. The via hole 106 may have a width that decreases in the direction toward the upper redistribution substrate 120. The via hole 106 may penetrate the molding layer 104 and may protrude above the top surface of the molding layer 104. For example, the via hole 106 may extend into the upper dielectric layer 122 of the upper redistribution substrate 120 and may be coupled to the upper redistribution pattern 124.

[0067] Although not shown, a via hole seed layer may be interposed between the molding layer 104 and the via hole 106. For example, the via hole seed layer may be arranged to surround the side surface of the via hole 106.

[0068] The lower redistribution substrate 140 may be disposed under the molding layer 104. The lower redistribution substrate 140 may include a lower dielectric layer 142 disposed on the molding layer 104 and lower redistribution patterns 144 disposed in each of the lower dielectric layers 142.

[0069] Although not shown, a lower protective layer may be disposed on the top surface of the lower redistribution substrate 140. The lower protective layer may cover the lower redistribution substrate 140.

[0070] The external terminal 500 may be disposed on the lower redistribution substrate 140 or the lower protective layer. The external terminal 500 may be disposed on the first region R1 of the lower redistribution substrate 140. For example, the external terminal 500 may be disposed on the substrate pad 146, and the substrate pad 146 is disposed on the first region R1 of the bottom surface of the lower redistribution substrate 140. The external terminal 500 may include solder balls, solder bumps, etc.

[0071] The second antenna pattern 400 may be disposed on the lower redistribution substrate 140 or the lower protective layer. The second antenna pattern 400 may be disposed on the second region R2 of the bottom surface of the lower redistribution substrate 140. The first region R1 and the second region R2 may be arranged along the first direction D1. Accordingly, the second antenna pattern 400 may be spaced apart from the external terminal 500 in the first direction D1. The second antenna pattern 400 may be configured to have substantially the same features as those Figure 1 and Figure 4 described. For example, the second antenna pattern 400 may be arranged on the lower redistribution substrate 140 along the first direction D1 and the second direction D2, and may be electrically connected to the semiconductor chip 200 through the lower redistribution substrate 140, the via hole 106, and the upper redistribution substrate 120.

[0072] The semiconductor device may further include a third antenna pattern 600. The third antenna pattern 600 may be disposed on the side surface of the molding layer 104. The third antenna pattern 600 may include a Yagi antenna. The third antenna pattern 600 may be electrically connected to the semiconductor chip 200 through the upper redistribution substrate 120 or the lower redistribution substrate 140.

[0073] Figure 10 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0074] Reference Figure 10 , the semiconductor device may include: a lower substrate 140, a connection substrate 100, a redistribution substrate 120, a semiconductor chip 200, a first antenna pattern 300, and a second antenna pattern 400.

[0075] In an embodiment, the lower substrate 140 may be a printed circuit board (PCB) having a top surface on which signal patterns are provided. In another embodiment, the lower substrate 140 may have a structure in which insulating layers and interconnect layers are alternately stacked.

[0076] The external terminal 500 may be disposed below the lower substrate 140. The external terminal 500 may be disposed on the first region R1 of the lower substrate 140. For example, the external terminal 500 may be disposed on the substrate pad 146, and the substrate pad 146 is disposed on the first region R1 of the bottom surface of the lower substrate 140. The external terminal 5,000 may include solder balls, solder bumps, etc.

[0077] The second antenna pattern 400 may be disposed below the lower substrate 140. The second antenna pattern 400 may be disposed on a second region R2 of the bottom surface of the lower substrate 140. The first region R1 and the second region R2 may be arranged along a first direction D1. The second antenna pattern 400 may be configured to have features substantially the same as those Figure 1 and Figure 4 described. For example, the second antenna pattern 400 may be arranged on the lower substrate 140 along the first direction D1 and a second direction D2.

[0078] The connection substrate 100 may be disposed on the lower substrate 140. The connection substrate 100 may be mounted on the top surface of the lower substrate 140. For example, the connection substrate 100 may be coupled to the lower substrate 140 through terminals 109 (e.g., solder bumps and solder balls). The connection substrate 100 may be electrically connected to the external terminal 500 and the second antenna pattern 400 through the lower substrate 140.

[0079] An opening may be provided to penetrate the connection substrate 100 and thereby connect the bottom surface and the top surface of the connection substrate 100. The connection substrate 100 may include a base layer 107 and a conductive portion 108 in the base layer 107. As an example, the base layer 107 may be formed of or include silicon oxide. The conductive portion 108 may be disposed outside the connection substrate 100, and the opening may be between the conductive portion 108 and the connection substrate 100. The conductive portion 108 may include: a connection substrate pad disposed on the bottom surface of the connection substrate 100; a connection substrate via vertically penetrating the base layer 107; and a conductive pattern disposed between the base layers 107 and for redistribution of the electrical connection path.

[0080] The semiconductor chip 200 may be disposed on the lower substrate 140. The semiconductor chip 200 may be disposed in the opening of the connection substrate 100. When observed in a plan view, the semiconductor chip 200 may have an area smaller than the opening. In an embodiment, the semiconductor chip 200 may have a passive surface 200b facing the lower substrate 140 and an active surface 200a opposite to the passive surface 200b. For example, the semiconductor chip 200 may include: chip pads 202, and the chip pads 202 face the lower substrate 140.

[0081] The molding layer 104 may be disposed on the surface of the lower substrate 140. The molding layer 104 may be configured to fill the space between the connection substrate 100 and the first semiconductor chip 200. The molding layer 104 may cover the passive surface 200b of the semiconductor chip 200 and the bottom surface of the connection substrate 100. The molding layer 104 may expose the connection substrate pads of the conductive portion 108 near the bottom surface of the connection substrate 100. The molding layer 104 may be formed of or include at least one of an insulating polymer (e.g., Ajinomoto Build Film (ABF) or epoxy-based polymer) or a polymeric material (e.g., thermosetting resin).

[0082] The upper redistribution substrate 120 may be disposed on the connection substrate 100. The upper redistribution substrate 120 may include an upper dielectric layer 122 and upper redistribution patterns 124 respectively disposed in the upper dielectric layer 122. The upper redistribution substrate 120 may allow for the redistribution or rerouting of the electrical connection of the semiconductor chip 200 via the first chip pads 202 to another component (e.g., the first antenna pattern 300). For example, the upper redistribution pattern 124 may be coupled to the chip pads 202 of the semiconductor chip 200 and the conductive portion 108 of the connection substrate 100. In an embodiment, the semiconductor chip 200 may be mounted on the upper redistribution substrate 120. Figure 10 An example is shown in which the chip pads 202 of the semiconductor chip 200 are in contact with the upper redistribution patterns 124 of the upper redistribution substrate 120, but in an embodiment, terminals (e.g., solder balls or solder bumps) may be used for the connection of the chip pads 202. Thus, the second antenna pattern 400 may be electrically connected to the semiconductor chip 200 through the lower substrate 140, the connection substrate 100, and the upper redistribution substrate 120.

[0083] Although not shown, an upper protective layer may be disposed on the top surface of the upper redistribution substrate 120. The upper protective layer may cover the upper redistribution substrate 120.

[0084] The first antenna pattern 300 may be disposed on the upper redistribution substrate 120 or the upper protective layer. The first antenna pattern 300 may be configured to have substantially the same features as those Figure 1 and Figure 3 described. For example, the first antenna pattern 300 may be arranged on the upper redistribution substrate 120 along the first direction D1 and the second direction D2, and may be electrically connected to the semiconductor chip 200 through the upper redistribution substrate 120.

[0085] Although in Figure 9 and Figure 10Although not shown, in addition to the semiconductor chip 200, a second semiconductor chip may be included between the upper redistribution substrate 120 and the lower redistribution substrate 140, thereby providing a first semiconductor chip and a second semiconductor chip included between the upper redistribution substrate 120 and the lower redistribution substrate 140. The first semiconductor chip and the second semiconductor chip may be spaced apart from each other. The first semiconductor chip may be disposed in an upward-facing manner, and the second semiconductor chip may be disposed in a downward-facing manner. For example, the first semiconductor chip may be disposed to have an active surface in contact with the upper redistribution substrate 120, and the second semiconductor chip may be disposed to have an active surface in contact with the lower redistribution substrate 140. The first semiconductor chip may be coupled to the upper redistribution pattern 124 of the upper redistribution substrate 120 through chip pads included in the first semiconductor chip. The second semiconductor chip may be coupled to the lower redistribution pattern 144 of the lower redistribution substrate 140 through chip pads included in the second semiconductor chip. In a manner similar to Figure 7 the disclosure of, the first semiconductor chip may be electrically connected to the first antenna pattern 300, and the second semiconductor chip may be electrically connected to the second antenna pattern 400.

[0086] According to an embodiment of the inventive concept, a semiconductor device may include a semiconductor chip buried in an interconnection substrate, and thus, it is necessary to mount the semiconductor chip on the surface of the interconnection substrate. Accordingly, the size of the semiconductor device may be reduced.

[0087] In an embodiment, the semiconductor chip may be buried in a core portion of the interconnection substrate and may be connected to the first antenna pattern only through an upper build portion of the interconnection substrate. Accordingly, the length of an electrical connection path between the semiconductor chip and the first antenna pattern may be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0088] In addition, the second antenna pattern may be disposed over the entire region under the interconnection substrate except for a region where connection terminals are disposed, and this may allow the antenna signal to have a wide radiation region and a large radiation angle in the downward direction of the semiconductor device. Accordingly, in the downward direction of the semiconductor device, a shadow region of the antenna signal may be reduced and signal radiation efficiency may be improved.

[0089] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, the substrate including an upper construction portion provided on the top of the substrate and a lower construction portion provided on the bottom of the substrate, the bottom surface of the lower construction portion including a first region and a second region spaced apart from each other; A first semiconductor chip, buried in the substrate, the first semiconductor chip having a first active surface, the first active surface facing the top surface of the core portion of the substrate, and contacting and electrically connecting to the upper construction portion; A first antenna pattern, provided on the top surface of the upper construction portion, and electrically connected to the first semiconductor chip via the upper construction portion; A second antenna pattern, provided on the first region of the bottom surface of the lower construction portion, and electrically connected to the first semiconductor chip; And External terminals, provided on the second region of the bottom surface of the lower construction portion.

2. The semiconductor device according to claim 1, wherein, When observed in a plan view, the first region surrounds the second region.

3. The semiconductor device according to claim 1, wherein, The first antenna pattern vertically overlaps with the first semiconductor chip.

4. The semiconductor device according to claim 1, wherein, The first antenna pattern is connected to a first chip pad through the upper construction portion, the first chip pad being provided on the first active surface of the first semiconductor chip, and The second antenna pattern is connected to the first chip pad of the first semiconductor chip through a vertical connection terminal, the vertical connection terminal extending from the bottom surface of the upper construction portion to the top surface of the lower construction portion.

5. The semiconductor device according to claim 4, wherein, In a first direction perpendicular to the top surface of the substrate, the upper construction portion is provided at a higher level than the first semiconductor chip.

6. The semiconductor device according to claim 1 further comprises: A second semiconductor chip buried in the substrate, Wherein, the second semiconductor chip has a second active surface, the second active surface facing the bottom surface of the core portion of the substrate, and The second antenna pattern is connected to a second chip pad through the lower construction portion, the second chip pad being provided on the second active surface of the second semiconductor chip.

7. The semiconductor device according to claim 6, wherein, In a first direction perpendicular to the top surface of the substrate, the lower construction portion is provided at a lower level than the first semiconductor chip.

8. The semiconductor device according to claim 6, wherein, The second semiconductor chip is spaced apart from the first semiconductor chip in a second direction parallel to the top surface of the substrate, and The second region is spaced apart from the first region in the second direction.

9. The semiconductor device according to claim 1, wherein, The area of the first region is 0.5 to 2.0 times the area of the second region.

10. A semiconductor device, comprising: A core portion, having a first surface and a second surface opposite to each other; A first construction portion and a second construction portion, respectively provided on the first surface and the second surface, each of the first construction portion and the second construction portion including a plurality of insulating layers and a plurality of interconnect layers stacked in sequence; A first semiconductor chip, provided in a first mounting region formed by partially removing a part of the core portion, and the active surface of the first semiconductor chip contacting and electrically connecting to the first construction portion; A first antenna pattern, provided on the top surface of the first construction portion, and electrically connected to the first semiconductor chip via the first construction portion; A second antenna pattern, disposed on a bottom surface of the second building portion and electrically connected to the first semiconductor chip; and External terminals, disposed on the bottom surface of the second building portion, wherein the second antenna pattern is disposed on a first region of the second building portion, and the external terminals are disposed on a second region of the second building portion, the second region being spaced apart from the first region.

11. The semiconductor device according to claim 10, wherein, When observed in a plan view, the first region surrounds the second region.

12. The semiconductor device according to claim 10, wherein, The external terminals are coupled to an external substrate, and a distance between the external substrate and the second building portion is 1 / 4 to 1 / 2 times a wavelength of electromagnetic waves emitted from the second antenna pattern.

13. The semiconductor device according to claim 10, wherein, The first antenna pattern is electrically connected to the first semiconductor chip through the first building portion, and the second antenna pattern is electrically connected to the first semiconductor chip through at least one of a vertical connection terminal and a via hole, the second building portion, and the first building portion.

14. The semiconductor device according to claim 10 further comprises: A second semiconductor chip, the second semiconductor chip being disposed in the first mounting region of the core portion so as to be spaced apart from the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the second building portion.

15. The semiconductor device according to claim 14, wherein, The first antenna pattern is electrically connected to the first semiconductor chip through the first building portion, and the second antenna pattern is electrically connected to the second semiconductor chip through the second building portion.

16. The semiconductor device according to claim 14, wherein, The second semiconductor chip is spaced apart from the first semiconductor chip in a first direction parallel to a first surface of the core portion, and the second region is spaced apart from the first region in the first direction.

17. The semiconductor device according to claim 10 further comprises: A third semiconductor chip, the third semiconductor chip being disposed in a second mounting region formed by removing another part of the core portion, wherein the third semiconductor chip is electrically connected to the second building portion.

18. A semiconductor device, comprising: A first redistribution substrate; A first semiconductor chip having a first active surface in contact with and electrically connected to a bottom surface of the first redistribution substrate; A molding layer, disposed on the bottom surface of the first redistribution substrate, the first semiconductor chip being buried in the molding layer; A second redistribution substrate, disposed on the molding layer and below the first semiconductor chip in a direction perpendicular to the bottom surface of the first redistribution substrate; A conductive portion, disposed at a side surface of the first semiconductor chip to electrically connect the first redistribution substrate and the second redistribution substrate to each other; A first antenna pattern, disposed on a top surface of the first redistribution substrate and electrically connected to the first semiconductor chip through the first redistribution substrate; A second antenna pattern, disposed on a first region of a bottom surface of the second redistribution substrate and electrically connected to the first semiconductor chip; and External terminals, disposed on a second region of the bottom surface of the second redistribution substrate, the first region and the second region being spaced apart from each other.

19. The semiconductor device according to claim 18 further comprises: An insulating layer, the insulating layer being disposed between the first redistribution substrate and the second redistribution substrate to bury the first semiconductor chip, Wherein the conductive portion includes a through hole that extends from the top surface of the first redistribution substrate to the bottom surface of the second redistribution substrate to vertically penetrate the insulating layer.

20. The semiconductor device according to claim 18 further comprises: A connection substrate is disposed between the first redistribution substrate and the second redistribution substrate and is spaced apart from the first semiconductor chip. Wherein the first semiconductor chip is disposed in a mounting area formed by partially removing the connection substrate, and the conductive portion includes a conductive portion buried in the base layer of the connection substrate.

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