Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate and a preparation method thereof, and a display device. The display substrate includes an effective area and a frame area, the effective area includes a display area and at least one test area, the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, the test area includes at least one test unit, the test unit includes a test transistor, a plurality of test leads, and a plurality of test terminals, the test transistor has the same structure as at least one transistor in the pixel driving circuit, and the plurality of test terminals are connected to the test transistor through a plurality of test leads; the frame area is provided with a plurality of test pins and a plurality of connecting wires, and the plurality of test pins are correspondingly connected to the plurality of test terminals through a plurality of connecting wires. The present disclosure forms a test circuit in the effective area, and the characteristics of the test transistor in the test circuit are substantially consistent with the characteristics of the corresponding transistor in the display area, and the test transistor can accurately reflect the actual characteristics of the transistor in the display area.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as the light-emitting device and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] The inventors of the present application have found through research that the test components on the existing OLED display substrate cannot accurately reflect the actual characteristics of the transistors in the display area. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a preparation method thereof, and a display device, so as to solve the problem that the existing test components cannot accurately reflect the actual characteristics of the transistors in the display area.

[0006] The present disclosure provides a display substrate, comprising an effective area and a frame area located outside the effective area, wherein the effective area comprises a display area and at least one test area, wherein the display area comprises a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel driving circuit, wherein the test area comprises at least one test unit, wherein the test unit comprises a test transistor, a plurality of test leads and a plurality of test terminals, wherein the test transistor has the same structure as at least one transistor in the pixel driving circuit, and the plurality of test terminals are connected to the test transistor through the plurality of test leads; wherein the frame area is provided with a plurality of test pins and a plurality of connecting wires, wherein the plurality of test pins are correspondingly connected to the plurality of test terminals through the plurality of connecting wires.

[0007] In an exemplary embodiment, at least one test terminal and a test lead connected to the test terminal are disposed in the same layer and are an integrated structure connected to each other.

[0008] In an exemplary embodiment, the test unit further includes a plurality of auxiliary pins, the plurality of auxiliary pins are correspondingly connected to the plurality of test pins through the plurality of connection lines, and the plurality of test terminals are correspondingly connected to the plurality of auxiliary pins through vias.

[0009] In an exemplary embodiment, at least one test pin, at least one auxiliary pin, and a connection line connecting the test pin and the auxiliary pin are arranged in the same layer and are an integrated structure connected to each other.

[0010] In an exemplary embodiment, the multiple test terminals include at least a gate test terminal, a source test terminal and a drain test terminal, and the multiple test leads include at least a gate test lead, a source test lead and a drain test lead; the control electrode of the test transistor is connected to the gate test terminal through the gate test lead, the first electrode of the test transistor is connected to the source test terminal through the source test lead, and the second electrode of the test transistor is connected to the drain test terminal through the drain test lead.

[0011] In an exemplary embodiment, the test area further includes at least one dummy pixel, the at least one dummy pixel includes a dummy pixel driving circuit, the dummy pixel driving circuit has the same structure as the pixel driving circuit, and the dummy pixel driving circuit is arranged between adjacent test leads.

[0012] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence on a base; the first semiconductor layer includes an active layer of multiple polysilicon transistors, the first conductive layer includes gate electrodes of multiple polysilicon transistors and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of a storage capacitor, the second semiconductor layer includes an active layer of multiple oxide transistors, the third conductive layer includes gate electrodes of multiple oxide transistors, the fourth conductive layer includes first and second electrodes of multiple polysilicon transistors and first and second electrodes of multiple oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

[0013] In an exemplary embodiment, the plurality of test terminals are located on the fourth conductive layer.

[0014] In an exemplary embodiment, the plurality of test leads are located on the fourth conductive layer or the fifth conductive layer.

[0015] In an exemplary embodiment, the test pins, the connection wires and the auxiliary pins are located on the second conductive layer.

[0016] In an exemplary embodiment, the pixel driving circuit includes at least one metal oxide transistor and at least one low-temperature polysilicon transistor, and the test area includes at least one first test transistor or a second test transistor having the same structure as the metal oxide transistor, and at least one third test transistor or a fourth test transistor having the same structure as the low-temperature polysilicon transistor.

[0017] In an exemplary embodiment, a first region of a first test active layer in the first test transistor is connected to a first source test lead, a second region of the first test active layer is connected to a first drain test lead through a via, and a first test gate electrode in the first test transistor is connected to a first gate test lead through a via.

[0018] In an exemplary embodiment, the first test transistor further includes a first test connection electrode connected to the first region of the first test active layer through a via hole, and the first source test lead is connected to the first test connection electrode through the via hole.

[0019] In an exemplary embodiment, the first test transistor further includes a first test shielding line connected to the first gate test lead through a via.

[0020] In an exemplary embodiment, the first region of the third test active layer in the third test transistor is connected to the third source test lead through a via, the second electrode of the third test active layer is connected to the third drain test lead through a via, and the third test gate electrode in the third test transistor is connected to the third gate test lead.

[0021] In an exemplary embodiment, the third test transistor further includes a third test connection electrode, the third test connection electrode is connected to the third test gate electrode through a via hole, and the first gate test lead is connected to the third test connection electrode through the via hole.

[0022] In an exemplary embodiment, the third test transistor also includes a test shielding block and a shielding connection line connected to the test shielding block, the shielding connection line is connected to one end of the third auxiliary test lead through a via, and the other end of the third auxiliary test lead is connected to the third auxiliary test terminal.

[0023] In an exemplary embodiment, the first region of the fourth test active layer in the fourth test transistor is connected to the fourth source test lead, the second electrode of the fourth test active layer is connected to the fourth drain test lead through a via, and the fourth test gate electrode in the first test transistor is connected to the fourth gate test lead through a via.

[0024] In an exemplary embodiment, the fourth test transistor further includes a fourth test connection electrode connected to the first region of the fourth test active layer through a via hole, and the fourth source test lead is connected to the fourth test connection electrode through the via hole.

[0025] The present disclosure also provides a display device, comprising the aforementioned display substrate.

[0026] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate comprises an active area and a frame area located outside the active area, wherein the active area comprises a display area and at least one test area, and the display area comprises a plurality of sub-pixels; the preparation method comprises:

[0027] At least one pixel driving circuit is formed in at least one sub-pixel in the display area, at least one test unit is formed in the test area, and a plurality of test pins and a plurality of connection lines are formed in the frame area;

[0028] The test unit includes a test transistor, multiple test leads and multiple test terminals. The test transistor has the same structure as at least one transistor in the pixel driving circuit. The multiple test terminals are connected to the test transistor through the multiple test leads; the multiple test pins are correspondingly connected to the multiple test terminals through multiple connecting lines.

[0029] The exemplary embodiments of the present disclosure disclose a display substrate and a method for preparing the same, and a display device. A test circuit is formed in an effective area, and the characteristics of a test transistor in the test circuit are substantially consistent with the characteristics of a corresponding transistor in a display area. The test transistor can accurately reflect the actual characteristics of the transistor in the display area, which can not only ensure that the transistor characteristics are within a specified reference range, but also collect transistor characteristic data in the display area as a reference for analyzing defects.

[0030] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0032] Figure 1 is a structural schematic diagram of a display device;

[0033] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0034] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0035] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0036] Figure 5 is a working timing diagram of a pixel driving circuit;

[0037] Figure 6 A schematic plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0038] Figure 7 A schematic plan view of a test area according to an exemplary embodiment of the present disclosure;

[0039] Figure 8 A schematic diagram of the arrangement of test transistors in a circuit area according to an exemplary embodiment of the present disclosure;

[0040] Fig. 9 It is a structural schematic diagram of a first test transistor TC1 according to an exemplary embodiment of the present disclosure;

[0041] Fig.10 It is a structural schematic diagram of a third test transistor TC3 of an exemplary embodiment of the present disclosure;

[0042] Fig.11 It is a structural schematic diagram of a fourth test transistor TC4 according to an exemplary embodiment of the present disclosure;

[0043] Fig.12 It is a structural schematic diagram of a fifth test transistor TC5 according to an exemplary embodiment of the present disclosure;

[0044] Figure 13 to Figure 14 It is a schematic diagram after forming a shielding layer pattern according to an embodiment of the present disclosure;

[0045] Figures 15a to 16c It is a schematic diagram after forming a first semiconductor layer pattern according to an embodiment of the present disclosure;

[0046] Figures 17a to 18d It is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0047] Figures 19a to 20d It is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0048] Figures 21a to 22d It is a schematic diagram after forming a second semiconductor layer pattern according to an embodiment of the present disclosure;

[0049] Figures 23a to 24d It is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0050] Figures 25a to 26d It is a schematic diagram after forming a sixth insulating layer pattern according to an embodiment of the present disclosure;

[0051] Figures 27a to 28d It is a schematic diagram after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0052] Figures 29a to 30d It is a schematic diagram after forming a first planar layer pattern according to an embodiment of the present disclosure;

[0053] Figures 31a to 32d It is a schematic diagram after forming the fifth conductive layer pattern according to the embodiment of the present disclosure.

[0054] Description of reference numerals:

[0055] 11—first shielding line; 12—second shielding line; 13—third shielding line;

[0056] 14—shielding block; 21—first active layer; 22—second active layer;

[0057] 23—third active layer; 24—fourth active layer; 25—fifth active layer;

[0058] 26—sixth active layer; 27—seventh active layer; 31—first scanning signal line;

[0059] 32—light-emitting control line; 33—first electrode plate; 34—opening;

[0060] 41—first shielding line; 42—second shielding line; 43—first initial signal line;

[0061] 44—second electrode plate; 51—second scanning signal line; 52—third scanning signal line;

[0062] 61—first connecting electrode; 62—second connecting electrode; 63—third connecting electrode;

[0063] 64—fourth connecting electrode; 65—fifth connecting electrode; 66—sixth connecting electrode;

[0064] 67—second initial signal line; 71—data signal line; 72—first power line;

[0065] 73—anode connection electrode; 100—effective area; 101—first test shielding line;

[0066] 102—first test active layer; 103—first test gate electrode; 105—first source test lead;

[0067] 106—first drain test lead; 107—first gate test lead; 108—first test connection electrode;

[0068] 109—first test power supply electrode; 110—display area; 200—frame area;

[0069] 300—test area; 301—test shielding block; 302—third test active layer;

[0070] 303—third test gate electrode; 305—third source test lead; 306—third drain test lead;

[0071] 307—third grid test lead; 308—third test connection electrode; 309—third auxiliary test lead;

[0072] 310—test terminal; 320—test lead; 330—test transistor;

[0073] 400—test unit; 402—fourth test active layer; 403—fourth test gate electrode;

[0074] 405—a fourth source test lead; 406—a fourth drain test lead; 407—a fourth gate test lead;

[0075] 408—fourth test connection electrode; 500—test pin; 502—fifth test active layer;

[0076] 503—fifth test gate electrode; 505—fifth source test lead; 506—fifth drain test lead;

[0077] 507—fifth grid test lead; 508—fifth test connection electrode; 510—connection line;

[0078] 520—auxiliary pin; 600—virtual pixel; 601—substrate;

[0079] 602—driving circuit layer; 603—light-emitting structure layer; 604—packaging layer. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0081] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0082] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0083] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0084] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0085] In this specification, a transistor refers to an element including at least three test terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode test terminal, drain region, or drain electrode) and a source electrode (source electrode test terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0086] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0087] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0088] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0089] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0090] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0091] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m may be a natural number. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0092] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light, and the four sub-pixels may each include a circuit unit and a light-emitting device, the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0093] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a white subpixel (W) emitting white light, the third subpixel P3 may be a blue subpixel (B) emitting blue light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light.

[0094] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. In an exemplary embodiment, four sub-pixels may be arranged in parallel horizontally to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a square, a diamond, or in parallel vertically, which is not limited in the present disclosure.

[0095] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as a pixel row, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0096] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels of the display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 602 arranged on a substrate 601, a light-emitting structure layer 603 arranged on a side of the driving circuit layer 602 away from the substrate, and an encapsulation layer 604 arranged on a side of the light-emitting structure layer 603 away from the substrate.

[0097] In an exemplary embodiment, the substrate 601 may be a flexible substrate or a rigid substrate. The driving circuit layer 602 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. Figure 3 Only one driving transistor and one storage capacitor are used as examples for illustration. The light-emitting structure layer 603 of each sub-pixel may include multiple film layers constituting a light-emitting device, and the multiple film layers may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation layer 604 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer 603.

[0098] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (Hole Injection Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together, the hole blocking layer of all sub-pixels may be a common layer connected together, and the emitting layer and the electron blocking layer of adjacent sub-pixels may have a small overlap, or may be isolated.

[0099] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, first initial signal line INIT1, second initial signal line INIT1, first power line VDD and second power line VSS).

[0100] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0101] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0102] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0103] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0104] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0105] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0106] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0107] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initial voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0108] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0109] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0110] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0111] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the first initial signal line INIT1 may extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D may extend in a vertical direction.

[0112] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0113] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the pixel driving circuit of the example is described in detail. Figure 4 The pixel driving circuit in the embodiment includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 8 signal lines, and all 7 transistors are P-type transistors. In an exemplary embodiment, taking OLED as an example, the operation process of the pixel driving circuit may include:

[0114] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the first initial signal line INIT1 is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0115] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0116] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0117] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0118] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0119] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0120] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide). The low-temperature polysilicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantages of low leakage current. The low-temperature polysilicon transistor and the metal oxide transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.

[0121] Since the use of metal oxide transistors will bring about some characteristic-related defects, in order to better monitor the working characteristics of metal oxide transistors and the working characteristics of related transistors, the related technology usually sets a test component (Test Element Group, TEG for short) on the display substrate to monitor the working characteristics of the transistors in the display area. In a display substrate, the test component is set in the border area outside the display area. The inventor of the present application has found that since the position of the test component is outside the display area, there is a difference between the characteristics of the transistors in the test component and the corresponding transistor characteristics in the display area, and the test component cannot accurately reflect the actual characteristics of the transistors in the display area.

[0122] Figure 6 FIG. 1 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure. Figure 6As shown, in an exemplary embodiment, the display panel may include an active area (AA) 100 and a frame area 200 located at the periphery of the active area 100. The active area 100 may include a first edge (left edge) and a second edge (right edge) arranged oppositely in a first direction X, and a third edge (upper edge) and a fourth edge (lower edge) arranged oppositely in a second direction Y, and adjacent edges are connected by arc-shaped chamfers to form a rounded quadrilateral shape, and the first direction X and the second direction Y intersect. The frame area 200 may include a first frame (left frame) and a second frame (right frame) arranged oppositely in the first direction X, a third frame (upper frame) and a fourth frame (lower frame) arranged oppositely in the second direction Y, and a first corner connecting the first frame and the third frame, a second corner connecting the second frame and the third frame, a third corner connecting the first frame and the fourth frame, and a fourth corner connecting the second frame and the fourth frame.

[0123] In an exemplary embodiment, the first edge and the second edge may be parallel to the second direction Y, and the third edge and the fourth edge may be parallel to the first direction X. In an exemplary embodiment, the first direction X may be an extending direction (row direction) of the scan signal lines in the active area 100, the second direction Y may be an extending direction (column direction) of the data signal lines in the active area 100, and the first direction X and the second direction Y may be perpendicular to each other.

[0124] In an exemplary embodiment, the active area 100 may include a display area 110 and at least one test area 300, the test area 300 is configured to set a test circuit, and the test circuit is configured to monitor the working characteristics of the transistors in the display area 110, which can not only ensure that the transistor characteristics are within a specified reference range, but also collect transistor characteristic data in the display area as a reference for analyzing failures. In an exemplary embodiment, the area outside the test area 300 in the active area 100 can be the display area 110, and the display area 110 can include a plurality of pixel units arranged in a matrix, at least one pixel unit can include a plurality of sub-pixels, at least one sub-pixel can include a circuit unit and a light-emitting device, the circuit unit can include at least a scan signal line, a data signal line, a light-emitting signal line and a pixel driving circuit, the pixel driving circuit can be connected to the scan signal line, the data signal line and the light-emitting signal line, respectively, and the light-emitting device is connected to the pixel driving circuit.

[0125] In an exemplary embodiment, the border region 200 may be provided with a gate drive circuit (GOA) and other circuits. The gate drive circuit may include a plurality of cascaded shift register units, the shift register unit being connected to at least one scan signal line of the display area and configured to provide a gate drive signal to at least one scan signal line of the display area. In some possible implementations, the specific form of the shift register unit is various, and the present disclosure is not limited thereto.

[0126] In an exemplary embodiment, the shape of the test area 300 may be a strip shape extending along the first direction X. The position of the test area 300 in the effective area 100 may be laid out according to corresponding requirements. For example, the test area 300 may be located in the effective area 100 near the upper frame. For another example, the test area 300 may be located in the effective area 100 near the left frame. For another example, the test area 300 may be located in the effective area 100 near the right frame, which is not limited in the present disclosure. In the following exemplary embodiments, the test area 300 is set at the third edge (near the upper frame) of the effective area 100 as an example for explanation.

[0127] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the test area 300 may be any one or more of the following: a triangle, a rectangle, a trapezoid, a polygon, a circle, and an ellipse.

[0128] Figure 7 FIG. 1 is a schematic plan view of a test area of ​​an exemplary embodiment of the present disclosure. Figure 7 As shown, in an exemplary embodiment, the test area 300 may be arranged at the upper edge of the effective area 100 (close to the upper frame of the frame area 200), and the test area 300 may include a terminal sub-area 300A, a lead sub-area 300B, and a circuit sub-area 300C arranged in sequence along the second direction Y. In an exemplary embodiment, the terminal sub-area 300A may include a plurality of test terminals 310, the plurality of test terminals 310 are arranged in sequence along the first direction X, and there is a first spacing between adjacent test terminals 310. The lead sub-area 300B may include a plurality of test leads 320, each test lead 320 extends along the second direction Y, the plurality of test leads 320 are arranged in sequence along the first direction X, and there is a second spacing between adjacent test leads 320. The circuit sub-area 300C may include a plurality of test transistors 330, the plurality of test transistors 330 are arranged in sequence along the first direction X, and there is a third spacing between adjacent test transistors 330.

[0129] In an exemplary embodiment, a plurality of test terminals 310 may be divided into a plurality of test terminal groups, at least one test terminal group may include three test terminals 310 or four test terminals 310, a plurality of test leads 320 may be divided into a plurality of test lead groups, at least one test lead group may include three test leads 320 or four test leads 320, three test terminals 310 or four test terminals 310 in a test terminal group are respectively connected to a test transistor 330 through three test leads 320 or four test leads 320 in a test lead group, a test lead group, a test terminal group connected to the test lead group, and a test transistor 330 connected to the test lead group constitute a test unit 400, and a plurality of test units 400 arranged in sequence along a first direction X constitute a test circuit of the exemplary embodiment disclosed herein.

[0130] In an exemplary embodiment, three of the test terminal groups may be source test terminals, drain test terminals and gate test terminals, respectively, and the four test terminals 310 in the test terminal group may be source test terminals, drain test terminals, gate test terminals and auxiliary test terminals, respectively. The three test leads 320 in the test lead group may be source test leads, drain test leads and gate test leads, respectively, and the four test leads 320 in the test lead group may be source test leads, drain test leads, gate test leads and auxiliary test leads, respectively. The test transistor 330 may include a first electrode (source electrode), a second electrode (drain electrode) and a control electrode (gate electrode). In an exemplary embodiment, the source test terminal may be connected to the first electrode of the test transistor through the source test lead, the drain test terminal may be connected to the second electrode of the test transistor through the drain test lead, the gate test terminal may be connected to the control electrode of the test transistor through the gate test lead, and the auxiliary test terminal may be connected to the auxiliary electrode of the test transistor through the auxiliary test lead.

[0131] In an exemplary embodiment, taking the pixel driving circuit of the 7T1C structure in the display area as an example, the multiple test transistors 330 in the test area 300 may include any one or more of the following: a first test transistor TC1 having the same or similar structure as the first transistor T1 in the pixel driving circuit, a second test transistor TC2 having the same or similar structure as the second transistor T2 in the pixel driving circuit, a third test transistor TC3 having the same or similar structure as the third transistor T3 in the pixel driving circuit, a fourth test transistor TC4 having the same or similar structure as the fourth transistor T4 in the pixel driving circuit, a fifth test transistor TC5 having the same or similar structure as the fifth transistor T5 in the pixel driving circuit, a sixth test transistor TC6 having the same or similar structure as the sixth transistor T6 in the pixel driving circuit, and a seventh test transistor TC7 having the same or similar structure as the seventh transistor T7 in the pixel driving circuit.

[0132] In an exemplary embodiment, the frame area 200 of the display panel may be provided with a plurality of test pins (PAD) 500, and the plurality of test pins 500 may be correspondingly connected to the plurality of test terminals 310 of the terminal sub-area 300A through a plurality of connection lines 510. The plurality of test pins are configured to be connected to an external test device, so that the external test device can perform a test through the plurality of test pins 500 of the frame area.

[0133] In an exemplary embodiment, the lead sub-area 300B may be provided with a plurality of dummy pixels (Dummy Pixel) 600, in which a dummy pixel driving circuit is provided to more realistically reflect the characteristics of the transistor in the display area. In an exemplary embodiment, the dummy pixel 600 may be provided between adjacent test leads 320. The plurality of dummy pixels may be provided sequentially along the first direction X, or the plurality of dummy pixels may be provided sequentially along the second direction Y, or the plurality of dummy pixels may be provided sequentially along the first direction X and the second direction Y, respectively, and the present disclosure is not limited thereto.

[0134] Figure 8 FIG. 1 is a schematic diagram of the arrangement of test transistors in a circuit area according to an exemplary embodiment of the present disclosure. Figure 8 As shown, in an exemplary embodiment, the test area 300 may include a first test unit 410, a third test unit 430, a fourth test unit 440 and a fifth test unit 450 arranged in sequence along the first direction X, and a border area 200 adjacent to the test area 300 may be provided with a plurality of test pins 500 and a plurality of connecting lines 510.

[0135] In an exemplary embodiment, the first test unit 410 may include a first test transistor TC1, three test leads 320, and three test terminals 310. The three test leads 320 may include: a first source test lead, a first drain test lead, and a first gate test lead respectively connected to the first test transistor TC1, and the three test terminals 310 may include: a first source test terminal connected to the first source test lead, a first drain test terminal connected to the first drain test lead, and a first gate test terminal connected to the first gate test lead. In an exemplary embodiment, the first test transistor TC1 may be a metal oxide transistor, which has the same or similar structure as the first transistor T1 in the pixel driving circuit.

[0136] In an exemplary embodiment, the third test unit 430 may include a third test transistor TC3, four test leads 320, and four test terminals 310. The four test leads 320 may include: a third source test lead, a third drain test lead, a third gate test lead, and a third auxiliary test lead respectively connected to the third test transistor TC3, and the four test terminals 310 may include: a third source test terminal connected to the third source test lead, a third drain test terminal connected to the third drain test lead, a third gate test terminal connected to the third gate test lead, and a third auxiliary test terminal connected to the third auxiliary test lead. In an exemplary embodiment, the third test transistor TC3 may be a low temperature polysilicon transistor, which has the same or similar structure as the third transistor T3 in the pixel driving circuit.

[0137] In an exemplary embodiment, the fourth test unit 440 may include a fourth test transistor TC4, three test leads 320, and three test terminals 310. The three test leads 320 may include: a fourth source test lead, a fourth drain test lead, and a fourth gate test lead respectively connected to the fourth test transistor TC4, and the three test terminals 310 may include: a fourth source test terminal connected to the fourth source test lead, a fourth drain test terminal connected to the fourth drain test lead, and a fourth gate test terminal connected to the fourth gate test lead. In an exemplary embodiment, the fourth test transistor TC4 may be a low temperature polysilicon transistor, which has the same or similar structure as the fourth transistor T4 in the pixel driving circuit.

[0138] In an exemplary embodiment, the fifth test unit 450 may include a fifth test transistor TC5, three test leads 320, and three test terminals 310. The three test leads 320 may include: a fifth source test lead, a fifth drain test lead, and a fifth gate test lead respectively connected to the fifth test transistor TC5, and the three test terminals 310 may include: a fifth source test terminal connected to the fifth source test lead, a fifth drain test terminal connected to the fifth drain test lead, and a fifth gate test terminal connected to the fifth gate test lead. In an exemplary embodiment, the fifth test transistor TC5 may be a low temperature polysilicon transistor, which has the same or similar structure as the fifth transistor T5 in the pixel driving circuit.

[0139] In an exemplary embodiment, at least one test terminal 310 and a test lead 320 connected to the test terminal 310 may be an integrated structure connected to each other, and both are arranged in the same layer and formed simultaneously by the same patterning process. At least one test terminal 310 and a test lead 320 connected to the test terminal 310 may be arranged in different layers, and both are connected by vias.

[0140] In an exemplary embodiment, the test area 300 may be provided with a plurality of dummy pixels (Dummy Pixel) 600, each of which may include at least one pixel driving circuit to more realistically reflect the transistor characteristics of the display area. In an exemplary embodiment, in a first direction X, the dummy pixel 600 may be provided between adjacent test leads 320, and in a second direction Y, the dummy pixel 600 may be provided between the test terminal 310 and the test transistor 330. In an exemplary embodiment, a plurality of dummy pixels may be provided sequentially along the first direction X, or a plurality of dummy pixels may be provided sequentially along the second direction Y, or a plurality of dummy pixels may be provided sequentially along the first direction X and sequentially, respectively, and the present disclosure is not limited thereto.

[0141] In an exemplary embodiment, the test area 300 may be provided with a plurality of auxiliary pins 520, and the plurality of auxiliary pins 520 are correspondingly connected to the plurality of test pins 500 of the frame area 200 through the plurality of connection lines 510 of the frame area 200. In an exemplary embodiment, the plurality of auxiliary pins 520 correspond to the positions of the plurality of test terminals 310, and the orthographic projections of the test terminals 310 on the display substrate plane at least partially overlap with the orthographic projections of the corresponding auxiliary pins 520 on the display substrate plane.

[0142] In an exemplary embodiment, at least one connection line 510 and the test pin 500 and the auxiliary pin 520 respectively connected to the connection line 510 are an integrated structure connected to each other, and the three are arranged in the same layer and formed simultaneously through the same patterning process.

[0143] In an exemplary embodiment, the test terminal 310 and the auxiliary pin 520 are disposed on different conductive layers, and the test terminal 310 is connected to the auxiliary pin 520 at a corresponding position through a via hole.

[0144] Fig. 9 FIG. 1 is a schematic diagram of a structure of a first test transistor TC1 according to an exemplary embodiment of the present disclosure. Fig. 9 As shown, in an exemplary embodiment, the first test transistor TC1 may include a first test shielding line 101 , a first test active layer 102 , a first test gate electrode 103 , a first test connection electrode 108 , and a first test power supply electrode 109 .

[0145] In an exemplary embodiment, the first source test lead 105 is connected to the first test connection electrode 108 through a via hole. The first test connection electrode 108 may serve as a first test source electrode of the first test transistor TC1 and is connected to the first region of the first test active layer 102 through a via hole.

[0146] In an exemplary embodiment, the first drain test lead 106 may serve as a first test drain electrode of the first test transistor TC1 , and be connected to the second region of the first test active layer 102 through a via hole.

[0147] In an exemplary embodiment, the first gate test lead 107 is connected to the first test gate electrode 103 through a via.

[0148] In an exemplary embodiment, the first test shielding line 101 may serve as an auxiliary gate electrode of the first test transistor TC1 , and the first gate test lead 107 is further connected to the first test shielding line 101 through a via.

[0149] In an exemplary embodiment, the orthographic projection of the first test power electrode 109 on the display substrate plane at least partially overlaps with the orthographic projections of the first test shielding line 101 , the first test active layer 102 , and the first test gate electrode 103 on the display substrate plane.

[0150] Fig.10 FIG. 1 is a schematic diagram of the structure of a third test transistor TC3 according to an exemplary embodiment of the present disclosure. Fig.10 As shown, in an exemplary embodiment, the third test transistor TC3 may include a test shielding block 301 , a shielding connection line 301 - 1 , a third test active layer 302 , a third test gate electrode 303 , and a third test connection electrode 308 .

[0151] In an exemplary embodiment, the third source test lead 305 may serve as a third test source electrode of the third test transistor TC3 , and be connected to the first region of the third test active layer 302 through a via hole.

[0152] In an exemplary embodiment, the third drain test lead 306 may serve as a third test drain electrode of the third test transistor TC3 , and be connected to the third region of the third test active layer 302 through a via hole.

[0153] In an exemplary embodiment, the third test connection electrode 308 is connected to the third test gate electrode 303 through a via hole, and the third gate test lead 307 is connected to the third test connection electrode 308 through a via hole.

[0154] In an exemplary embodiment, the test shielding block 301 can be used as an auxiliary gate electrode of the third test transistor TC3. One end of the shielding connection line 301-1 is connected to the test shielding block 301, and the other end of the shielding connection line 301-1 is connected to the third auxiliary test lead 309 through a via, and the other end of the third auxiliary test lead 309 is connected to the third auxiliary test terminal.

[0155] Fig.11 FIG. 1 is a schematic diagram of the structure of a fourth test transistor TC4 according to an exemplary embodiment of the present disclosure. Fig.11 As shown, in an exemplary embodiment, the fourth test transistor TC4 may include a fourth test active layer 402 , a fourth test gate electrode 403 , and a fourth test connection electrode 408 .

[0156] In an exemplary embodiment, the fourth source test lead 405 is connected to the fourth test connection electrode 408 through a via, the fourth test connection electrode 408 can serve as the fourth test source electrode of the fourth test transistor TC4, and the fourth test connection electrode 408 is connected to the first region of the fourth test active layer 402 through a via.

[0157] In an exemplary embodiment, the fourth drain test lead 406 may serve as a fourth test drain electrode of the fourth test transistor TC4 , and be connected to the second region of the fourth test active layer 402 through a via hole.

[0158] In an exemplary embodiment, the fourth gate test lead 407 is connected to the fourth test gate electrode 403 through a via hole.

[0159] Fig.12 FIG. 1 is a schematic diagram of the structure of a fifth test transistor TC5 according to an exemplary embodiment of the present disclosure. Fig.12 As shown, in an exemplary embodiment, the fifth test transistor TC5 may include a fifth test active layer 502 , a fifth test gate electrode 503 , and a fifth test connection electrode 508 .

[0160] In an exemplary embodiment, the fifth source test lead 505 is connected to the first region of the fifth test active layer 502 through a via.

[0161] In an exemplary embodiment, the fifth drain test lead 506 is connected to the fifth test connection electrode 508 through a via, the fifth test connection electrode 508 can serve as the fifth test drain electrode of the fifth test transistor TC5, and the fifth test connection electrode 508 is connected to the second region of the fifth test active layer 502 through a via.

[0162] In an exemplary embodiment, the fifth gate test lead 507 is connected to the fifth test gate electrode 503 through a via.

[0163] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0164] In an exemplary embodiment, taking eight circuit units (2 unit rows and 4 unit columns) as an example, the preparation process of the driving circuit layer may include the following operations.

[0165] (1) Prepare a substrate on a glass carrier 1. In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier. The material of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the material of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on the glass carrier 1, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0166] (2) Forming a shielding layer pattern. In an exemplary embodiment, forming a shielding layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a shielding layer pattern on the substrate, such as Fig.13 and Fig.14 As shown, Fig.13 It is a planar structural diagram of the shielding layer pattern in the eight circuit units of the display area. Fig.14 FIG. 4 is a planar structural diagram of the area where the third test transistor TC3 is located in the test area.

[0167] In an exemplary embodiment, in the display area, the shielding layer pattern of each circuit unit may include a first shielding line 11, a second shielding line 12, a third shielding line 13 and a shielding block 14. The shape of the shielding block 14 may be rectangular, and the corners of the rectangle may be chamfered. The first shielding line 11 may be in the shape of a strip extending along the first direction X, and the first shielding line 11 is arranged on one side of the first direction X of the shielding block 14 and is connected to the shielding block 14. The second shielding line 12 may be in the shape of a strip extending along the second direction Y, and the second shielding line 12 is arranged on one side of the second direction Y of the shielding block 14 and is connected to the shielding block 14. The third shielding line 13 may be in the shape of a broken line extending along the second direction Y, and the third shielding line 13 is arranged on one side of the shielding block 14 in the opposite direction of the second direction Y, and is connected to the shielding block 14.

[0168] In an exemplary embodiment, the first shielding line 11 of each circuit unit is connected to the shielding block 14 of the adjacent circuit unit in the first direction X, so that the shielding layers in one circuit unit row are connected as one, forming an interconnected integrated structure.

[0169] In an exemplary embodiment, the second shielding line 12 of each circuit unit is connected to the third shielding line 13 of the circuit unit adjacent in the second direction Y, so that the shielding layers in one circuit unit column are connected as one to form an interconnected integrated structure.

[0170] In an exemplary embodiment, the shielding layers in the circuit unit rows and the circuit unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0171] In an exemplary embodiment, the blocking layer in the Nth column and the blocking layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the blocking layer in the N+1th column and the blocking layer in the N+2th column may be mirror-symmetrical with respect to the second center line, the blocking layer in the N+2th column and the blocking layer in the N+3th column may be mirror-symmetrical with respect to the third center line, and the first center line, the second center line, and the third center line may be straight lines extending along the second direction Y between adjacent circuit unit columns, respectively.

[0172] In an exemplary embodiment, the shapes of the shielding layers in a plurality of circuit unit rows may be the same.

[0173] In an exemplary embodiment, in the test area, the shielding layer pattern in the area where each third test transistor TC3 is located may include a test shielding block 301 and a shielding connection line 301-1, the shape of the test shielding block 301 is substantially the same as the shape of the shielding block 14 of each circuit unit in the display area, the shielding connection line 301-1 may include a first connecting sub-segment and a second connecting sub-segment, the first end of the first connecting sub-segment is connected to the test shielding block 301, the second end of the first connecting sub-segment is extended along the second direction Y, and then connected to the first end of the second connecting sub-segment, the second end of the second connecting sub-segment extends along the first direction X, and the second end of the second connecting sub-segment is configured to be connected to a third auxiliary test line formed subsequently.

[0174] (3) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film in sequence on the substrate having the aforementioned pattern, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer pattern, and a first semiconductor layer pattern disposed on the first insulating layer, such as Figure 15a to Figure 15b , Figures 16a to 16c As shown, Fig.15a It is the planar structure diagram of eight circuit units in the display area. Fig.15b for Fig.15a A schematic plan view of the first semiconductor layer in FIG. Fig.16a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Fig.16b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.16c FIG. 4 is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area.

[0175] In an exemplary embodiment, in the display area, the first semiconductor layer pattern of each circuit unit may include the third active layer 23 of the third transistor T3 to the seventh active layer 27 of the seventh transistor T7 , and the third active layer 23 to the seventh active layer 27 are connected to each other as an integral structure.

[0176] In an exemplary embodiment, the fourth active layer 24 and the seventh active layer 27 in the Mth row circuit unit are located on a side of the third active layer 23 of the circuit unit away from the M+1th row circuit unit, and the fifth active layer 25 and the sixth active layer 26 in the Mth row circuit unit are located on a side of the third active layer 23 close to the M+1th row circuit unit.

[0177] In an exemplary embodiment, the third active layer 23 may be shaped like a letter "J", the fourth active layer 24 and the seventh active layer 27 may be shaped like an letter "I", and the fifth active layer 25 and the sixth active layer 26 may be shaped like an letter "L".

[0178] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 23-1 of the third active layer 23 simultaneously serves as the second region 24-2 of the fourth active layer 24 and the second region 25-2 of the fifth active layer 25, the second region 23-2 of the third active layer 23 simultaneously serves as the first region 26-1 of the sixth active layer 26, the second region 26-2 of the sixth active layer 26 simultaneously serves as the second region 27-2 of the seventh active layer 27, and the first region 24-1 of the fourth active layer 24, the first region 25-1 of the fifth active layer 25, and the first region 27-1 of the seventh active layer 27 are separately provided.

[0179] In an exemplary embodiment, in each circuit unit row, the first region 25-1 of the fifth active layer 25 in the Nth column and the first region 25-1 of the fifth active layer 25 in the N+1th column are connected to each other, and the first region 25-1 of the fifth active layer 25 in the N+2th column and the first region 25-1 of the fifth active layer 25 in the N+3th column are connected to each other. In an exemplary embodiment, since the first region of the fifth active layer in each circuit unit is connected to the first power line formed subsequently, by forming the first regions of the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it is possible to ensure that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0180] In an exemplary embodiment, the first semiconductor layer in the Nth column and the first semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the first semiconductor layer in the N+1th column and the first semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the first semiconductor layer in the N+2th column and the first semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0181] In an exemplary embodiment, the shapes of the shielding layers in a plurality of circuit unit rows may be the same.

[0182] In an exemplary embodiment, in the test area, the first semiconductor layer pattern of the region where each third test transistor TC3 is located may include a third test active layer 302, the first semiconductor layer pattern of the region where each fourth test transistor TC4 is located may include a fourth test active layer 402, and the first semiconductor layer pattern of the region where each fifth test transistor TC5 is located may include a fifth test active layer 502.

[0183] In an exemplary embodiment, the shape of the third test active layer 302 is substantially the same as the shape of the third active layer 23 of each circuit unit in the display area, the shape of the fourth test active layer 402 is substantially the same as the shape of the fourth active layer 24 of each circuit unit in the display area, and the shape of the fifth test active layer 502 is substantially the same as the shape of the fifth active layer 25 of each circuit unit in the display area.

[0184] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are LTPS thin film transistors. In an exemplary embodiment, patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.

[0185] (4) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on a substrate having the aforementioned pattern, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Figure 17a to Figure 17b , Figures 18a to 18d As shown, Fig.17a It is the planar structure diagram of eight circuit units in the display area. Fig.17b for Fig.17a A plan view of the first conductive layer in FIG. Fig.18a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Fig.18b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.18c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.18d FIG. 1 is a plan view of a frame region adjacent to the test region. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0186] In an exemplary embodiment, in the display area, the first conductive layer pattern includes at least: a first scan signal line 31, a light emitting control line 32 and a first electrode plate 33 of a storage capacitor, and the main parts of the first scan signal line 31 and the light emitting control line 32 may extend along the first direction X. The first scan signal line 31 in the Mth row circuit unit is located at a side of the first electrode plate 33 of the circuit unit away from the M+1th row circuit unit, and the light emitting control line 32 may be located at a side of the first electrode plate 33 of the circuit unit close to the M+1th row circuit unit.

[0187] In an exemplary embodiment, the first electrode plate 33 may be located between the first scanning signal line 31 and the light emitting control line 32, the first electrode plate 33 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 33 on the substrate and the orthographic projection of the third active layer of the third transistor T3 on the substrate have an overlapping area. In an exemplary embodiment, the first electrode plate 33 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0188] In an exemplary embodiment, the area where the first scan signal line 31 overlaps with the fourth active layer serves as the gate electrode of the fourth transistor T4, the area where the first scan signal line 31 overlaps with the seventh active layer serves as the gate electrode of the seventh transistor T7, the area where the light emitting control line 32 overlaps with the fifth active layer serves as the gate electrode of the fifth transistor T5, and the area where the light emitting control line 32 overlaps with the sixth active layer serves as the gate electrode of the sixth transistor T6.

[0189] In an exemplary embodiment, the first scanning signal line 31 and the light emitting control line 32 may be designed with equal widths, or may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0190] In an exemplary embodiment, in the test area, the first conductive layer pattern of the region where each third test transistor TC3 is located may include a third test gate electrode 303, the first conductive layer pattern of the region where each fourth test transistor TC4 is located may include a fourth test gate electrode 403, and the first conductive layer pattern of the region where each fifth test transistor TC5 is located may include a fifth test gate electrode 503.

[0191] In an exemplary embodiment, the shape of the third test gate electrode 303 is substantially the same as the shape of the first electrode plate 33 of each circuit unit in the display area, the orthographic projection of the third test gate electrode 303 on the substrate and the orthographic projection of the third test active layer 302 on the substrate have an overlapping area, and the shape of the overlapping area of ​​the third test gate electrode 303 and the third test active layer 302 is substantially the same as the shape of the overlapping area of ​​the first electrode plate 33 and the third active layer 23 in the display area. The shape of the overlapping area of ​​the fourth test gate electrode 403 and the fourth test active layer 402 is substantially the same as the shape of the overlapping area of ​​the first scan signal line 31 and the fourth active layer 24 in the display area, and the shape of the overlapping area of ​​the fifth test gate electrode 503 and the fifth test active layer 502 is substantially the same as the shape of the overlapping area of ​​the light emitting control line 32 and the fifth active layer 25 in the display area.

[0192] In an exemplary embodiment, a main portion of the fourth test gate electrode 403 may extend along the first direction X, and an end portion in the first direction X may be provided with a rectangular fourth connection block configured to be connected to a fourth gate test lead formed subsequently.

[0193] In an exemplary embodiment, a main portion of the fifth test gate electrode 503 may extend along the first direction X, and an end portion in the first direction X may be provided with a rectangular fifth connection block configured to be connected to a fifth gate test lead formed subsequently.

[0194] In an exemplary embodiment, the first conductive layer pattern may include a plurality of test pins 500 and a plurality of connection lines 510 in the frame region 200 near the test region 300 , and may include a plurality of auxiliary pins 520 in the test region 300 near the frame region 200 .

[0195] In an exemplary embodiment, the connection line 510 , the test pin 500 connected to the connection line 510 , and the auxiliary pin 520 are an integrated structure connected to each other, that is, the three are arranged in the same layer and are formed simultaneously through the same patterning process.

[0196] In an exemplary embodiment, the test pin 500 is configured so that an external test device can perform a test through the test pin 500 , and the auxiliary pin 520 is configured to be connected to a test terminal formed subsequently.

[0197] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the third active layer to the seventh active layer are both conductorized.

[0198] (5) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Figure 19a to Figure 19b , Figures 20a to 20d As shown, Fig.19a It is the planar structure diagram of eight circuit units in the display area. Fig.19b for Fig.19a A plan view of the second conductive layer in FIG. Fig.20a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Fig.20b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.20c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.20d FIG. 1 is a planar structural diagram of a region where the first test transistor TC1 is located in the test region. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0199] In an exemplary embodiment, in the display area, the second conductive layer pattern includes at least: a first shielding line 41, a second shielding line 42, a first initial signal line 43, and a second electrode plate 44, and the main parts of the first shielding line 41, the second shielding line 42, and the first initial signal line 43 can extend along the first direction X. The second electrode plate 44, as another electrode plate of the storage capacitor, can be located between the second shielding line 42 and the light emitting control line 32 of the present circuit unit.

[0200] In an exemplary embodiment, the first shielding line 41 is configured as a shielding layer for the first transistor T1 to shield the channel of the first transistor T1, and the second shielding line 42 is configured as a shielding layer for the second transistor T2 to shield the channel of the second transistor T2 to ensure the electrical performance of the oxide first transistor T1 and the oxide second transistor T2.

[0201] In an exemplary embodiment, the outline of the second electrode plate 44 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 44 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate, and the first electrode plate 33 and the second electrode plate 44 constitute a storage capacitor of the pixel driving circuit. An opening 45 is provided on the second electrode plate 44, and the opening 45 can be located in the middle of the second electrode plate 44. The opening 45 can be rectangular, so that the second electrode plate 44 forms a ring structure. The opening 45 exposes the third insulating layer covering the first electrode plate 33, and the orthographic projection of the first electrode plate 33 on the substrate includes the orthographic projection of the opening 45 on the substrate. In an exemplary embodiment, the opening 45 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening 45 and exposes the first electrode plate 33, so that the second pole of the first transistor T1 formed subsequently is connected to the first electrode plate 33.

[0202] In the exemplary embodiment, in each circuit unit row, the second electrode plate 44 of the Nth column and the second electrode plate 44 of the N+1th column are connected to each other, and the second electrode plate 44 of the N+2th column and the second electrode plate 44 of the N+3th column are connected to each other. In the exemplary embodiment, since the second electrode plate 44 in each circuit unit is connected to the first power line formed subsequently, by forming the second electrode plates 44 of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the second electrode plates 44 of adjacent circuit units have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0203] In an exemplary embodiment, in the test area, the second conductive layer pattern in the region where each first test transistor TC1 is located may include a first test shielding line 101 having substantially the same shape as the first shielding line 41 of each circuit unit in the display area.

[0204] In an exemplary embodiment, the structure of the region where each of the third test transistor TC3 , the fourth test transistor TC4 , and the fifth test transistor TC5 is located may be the same as the structure after the previous process.

[0205] (6) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, such as Figure 21a to Figure 21b , Figures 22a to 22d As shown, Fig.21a It is the planar structure diagram of eight circuit units in the display area. Figure 21b for Fig.21a A schematic plan view of the second semiconductor layer in FIG. Fig.22a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Figure 22b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.22c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.22d FIG. 4 is a planar structural diagram of the area where the first test transistor TC1 is located in the test area.

[0206] In an exemplary embodiment, in the display area, the second semiconductor layer pattern in each circuit unit includes at least a first active layer 21 of the first transistor T1 and a second active layer 22 of the second transistor T2, and the first active layer 21 and the second active layer 22 are an integral structure connected to each other.

[0207] In an exemplary embodiment, the first active layer 21 and the second active layer 22 may be shaped like an "I", the second region 21-2 of the first active layer 21 also serves as the first region 22-1 of the second active layer 22, and the first region 21-1 of the first active layer 21 and the second region 22-2 of the second active layer 22 are separately provided.

[0208] In an exemplary embodiment, the second semiconductor layer in the Nth column and the second semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the second semiconductor layer in the N+1th column and the second semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the second semiconductor layer in the N+2th column and the second semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0209] In exemplary embodiments, shapes of the second semiconductor layers in a plurality of circuit unit rows may be the same.

[0210] In an exemplary embodiment, in the test area, the second semiconductor layer pattern in the area where each first test transistor TC1 is located may include a first test active layer 102, the shape of the first test active layer 102 is substantially the same as the shape of the first active layer 21 of each circuit unit in the display area, and the shape of the overlapping area between the first test active layer 102 and the first test shielding line 101 is substantially the same as the shape of the overlapping area between the first active layer 21 and the first shielding line 41 in the display area.

[0211] In an exemplary embodiment, the structure of the region where each of the third test transistor TC3 , the fourth test transistor TC4 , and the fifth test transistor TC5 is located may be the same as the structure after the previous process.

[0212] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide thin film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor film may be made of indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0213] (7) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, such as Figure 23a to Figure 23b , Figures 24a to 24d As shown, Fig.23a It is the planar structure diagram of eight circuit units in the display area. Figure 23b for Fig.23a A plan view of the third conductive layer in FIG. Fig.24a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Figure 24b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.24c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.24d FIG. 1 is a planar structural diagram of a region where the first test transistor TC1 is located in the test region. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0214] In an exemplary embodiment, in the display area, the third conductive layer pattern includes at least: a second scan signal line 51 and a third scan signal line 52, the main parts of the second scan signal line 51 and the third scan signal line 52 can extend along the first direction X, and the second scan signal line 51 in the Mth row circuit unit is located on the side of the third scan signal line 52 away from the M+1th row circuit unit.

[0215] In an exemplary embodiment, the region where the second scan signal line 51 overlaps the first active layer serves as the gate electrode of the first transistor T1 , and the region where the third scan signal line 52 overlaps the second active layer serves as the gate electrode of the second transistor T2 .

[0216] In an exemplary embodiment, the third scan signal line 52 carries the same signal as the first scan signal line 31 , that is, both are connected to the same signal source.

[0217] In an exemplary embodiment, the signals of the first shielding line 41 and the second scanning signal line 51 can be the same, that is, both are connected to the same signal source, so that the first shielding line 41 can be used as the bottom gate electrode of the first transistor T1 to form a double-gate structure first transistor T1.

[0218] In an exemplary embodiment, the signals of the second shielding line 42 and the third scanning signal line 52 can be the same, that is, both are connected to the same signal source, so that the second shielding line 42 can serve as the bottom gate electrode of the second transistor T2 to form a second transistor T2 with a dual-gate structure.

[0219] In an exemplary embodiment, in the test area, the third conductive layer pattern in the area where each first test transistor TC1 is located may include a first test gate electrode 103, the shape of the first test gate electrode 103 is substantially the same as the shape of the second scan signal line 51 of each circuit unit in the display area, and the shape of the overlapping area between the first test gate electrode 103 and the first test active layer 102 is substantially the same as the shape of the overlapping area between the second scan signal line 51 and the first active layer 21 in the display area.

[0220] In an exemplary embodiment, the structure of the region where each of the third test transistor TC3 , the fourth test transistor TC4 , and the fifth test transistor TC5 is located may be the same as the structure after the previous process.

[0221] (8) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of via holes are disposed on the sixth insulating layer, such as Figure 25a to Figure 25b , Figures 26a to 26d As shown, Fig.25a It is the planar structure diagram of eight circuit units in the display area. Fig.25b for Fig.25a A plan view of multiple vias in the Fig.26a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Figure 26b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.26c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.26d FIG. 4 is a planar structural diagram of the area where the first test transistor TC1 is located in the test area.

[0222] In an exemplary embodiment, in the display area, the multiple vias in each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10 and an eleventh via V11.

[0223] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 45 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 33. The first via hole V1 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 33 through the via hole.

[0224] In an exemplary embodiment, the second via hole V2 is located within the range of the orthographic projection of the second electrode plate 44 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second electrode plate 44. The second via hole V2 is configured to connect the first power line formed subsequently to the second electrode plate 44 through the via hole. In an exemplary embodiment, the second via hole V2 as a power via hole may include a plurality of second via holes V2, and the plurality of second via holes V2 may be arranged in sequence along the second direction Y to increase the connection reliability between the first power line and the second electrode plate 44.

[0225] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer. The third via hole V3 is configured to connect a seventh connection electrode formed subsequently to the fifth active layer through the via hole.

[0226] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer). The fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the fourth active layer. The fifth via hole V5 is configured to connect a subsequently formed data signal line to the fourth active layer through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the sixth insulating layer and the fifth insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the second active layer (also the second region of the first active layer). The sixth via hole V6 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first active layer through the via hole, and to connect the first electrode of the second transistor T2 formed subsequently to the second active layer through the via hole.

[0229] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the seventh active layer. The seventh via hole V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole.

[0230] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the first active layer on the substrate, and the sixth insulating layer and the fifth insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the first active layer. The eighth via hole V8 is configured to connect the first electrode of the first transistor T1 formed subsequently to the first active layer through the via hole.

[0231] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the sixth insulating layer and the fifth insulating layer in the ninth via hole V9 are etched away to expose the surface of the second region of the second active layer. The ninth via hole V9 is configured to connect the second electrode of the second transistor T2 formed subsequently to the second active layer through the via hole.

[0232] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the third active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the second region of the third active layer (also the first region of the sixth active layer). The tenth via hole V10 is configured to connect the second electrode of the third transistor T3 formed subsequently to the third active layer through the via hole, and to connect the first electrode of the sixth transistor T6 formed subsequently to the sixth active layer through the via hole.

[0233] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first initial signal line 43 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first initial signal line 43. The eleventh via hole V11 is configured to connect the first electrode of the first transistor T1 formed subsequently to the first initial signal line 43 through the via hole.

[0234] In an exemplary embodiment, in the test area, the plurality of vias include at least: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, a twenty-eighth via V28, a twenty-ninth via V29, a thirtieth via V30, a thirty-first via V31, a thirty-second via V32, a thirty-third via V33 and a thirty-fourth via V34.

[0235] In an exemplary embodiment, the twenty-first via hole V21 is located in the area where the third test transistor TC3 is located, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third test gate electrode 303 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the third test gate electrode 303.

[0236] In an exemplary embodiment, the twenty-second via hole V22 is located in the area where the third test transistor TC3 is located, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third test active layer 302 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the first area of ​​the third test active layer 302.

[0237] In an exemplary embodiment, the twenty-third via hole V23 is located in the area where the third test transistor TC3 is located, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third test active layer 302 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the second area of ​​the third test active layer 302.

[0238] In an exemplary embodiment, the twenty-fourth via hole V24 is located in the area where the third test transistor TC3 is located, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the shielding connection line 301-1 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the shielding connection line 301-1. In an exemplary embodiment, there may be a plurality of the twenty-fourth via holes V24 to improve connection reliability.

[0239] In an exemplary embodiment, the twenty-fifth via hole V25 is located in the area where the fourth test transistor TC4 is located, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the fourth test active layer 402 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the first area of ​​the fourth test active layer 402.

[0240] In an exemplary embodiment, the twenty-sixth via hole V26 is located in the area where the fourth test transistor TC4 is located, the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the fourth test active layer 402 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-sixth via hole V26 are etched away to expose the surface of the second area of ​​the fourth test active layer 402.

[0241] In an exemplary embodiment, the twenty-seventh via hole V27 is located in the region where the fourth test transistor TC4 is located, the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the fourth test gate electrode 403 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the twenty-seventh via hole V27 are etched away to expose the surface of the fourth test gate electrode 403. In an exemplary embodiment, there may be a plurality of the twenty-seventh via holes V27 to improve connection reliability.

[0242] In an exemplary embodiment, the twenty-eighth via hole V28 is located in the area where the fifth test transistor TC5 is located, the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the fifth test active layer 502 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-eighth via hole V28 are etched away to expose the surface of the first area of ​​the fifth test active layer 502.

[0243] In an exemplary embodiment, the twenty-ninth via V29 is located in the area where the fifth test transistor TC5 is located, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the fifth test active layer 502 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the second area of ​​the fifth test active layer 502.

[0244] In an exemplary embodiment, the 30th via hole V30 is located in the area where the fifth test transistor TC5 is located, the orthographic projection of the 30th via hole V30 on the substrate is located within the range of the orthographic projection of the fifth test gate electrode 503 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the 30th via hole V30 are etched away to expose the surface of the fifth test gate electrode 503. In an exemplary embodiment, there may be a plurality of the 30th via holes V30 to improve connection reliability.

[0245] In an exemplary embodiment, the thirty-first via hole V31 is located in the area where the first test transistor TC1 is located, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first test active layer 102 on the substrate, and the sixth insulating layer and the fifth insulating layer in the thirty-first via hole V31 are etched away to expose the surface of the first area of ​​the first test active layer 102.

[0246] In an exemplary embodiment, the thirty-second via hole V32 is located in the area where the first test transistor TC1 is located, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the first test active layer 102 on the substrate, and the sixth insulating layer and the fifth insulating layer in the thirty-second via hole V32 are etched away to expose the surface of the second area of ​​the first test active layer 102.

[0247] In an exemplary embodiment, the thirty-third via hole V33 is located in the area where the first test transistor TC1 is located, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the first test shielding line 101 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the thirty-third via hole V33 are etched away to expose the surface of the first test shielding line 101. In an exemplary embodiment, there may be a plurality of the thirty-third via holes V33 to improve connection reliability.

[0248] In an exemplary embodiment, the thirty-fourth via hole V34 is located in the region where the first test transistor TC1 is located, the orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the first test gate electrode 103 on the substrate, and the sixth insulating layer in the thirty-fourth via hole V34 is etched away to expose the surface of the first test gate electrode 103. In an exemplary embodiment, there may be a plurality of the thirty-fourth via holes V34 to improve connection reliability.

[0249] In an exemplary embodiment, in the test area 300 near the frame area 200, a plurality of connection vias are further provided in the area where some auxiliary pins 520 are located, and the orthographic projections of the connection vias on the substrate are located within the range of the orthographic projections of the auxiliary pins 520 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the connection vias are etched away to expose the surface of the auxiliary pins 520. In an exemplary embodiment, the connection vias are configured to be connected to the test terminals formed subsequently through the vias.

[0250] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Figure 27a to Figure 27b , Figures 28a to 28d As shown, Fig.27aIt is the planar structure diagram of eight circuit units in the display area. Figure 27b for Fig.27a A plan view of the fourth conductive layer in FIG. Fig.28a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Fig.28b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.28c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.28d FIG. 1 is a planar structural diagram of a region where the first test transistor TC1 is located in the test region. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0251] In an exemplary embodiment, in the display area, the fourth conductive layer includes at least first, second, third, fourth, fifth, sixth, and sixth connection electrodes 61 , 62 , 63 , 64 , 65 , 66 , and a second initial signal line 67 .

[0252] In an exemplary embodiment, the first connection electrode 61 is in a zigzag shape with a main part extending along the second direction Y, and its first end is connected to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the sixth via hole V6, and its second end is connected to the first electrode plate 33 through the first via hole V1, so that the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 61 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0253] In an exemplary embodiment, a first end of the second connection electrode 62 is connected to the first initial signal line 43 through the eleventh via hole V11, and a second end thereof is connected to the first region of the first active layer through the eighth via hole V8, so that the initial voltage transmitted by the first initial signal line 43 is written into the first transistor T1. In an exemplary embodiment, the second connection electrode 62 can serve as the first pole of the first transistor T1.

[0254] In an exemplary embodiment, the third connection electrode 63 is connected to the first region of the fourth active layer through the fifth via hole V5. In an exemplary embodiment, the third connection electrode 63 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0255] In an exemplary embodiment, the fourth connection electrode 64 is connected to the second electrode plate 44 through the second via hole V2 on the one hand, and is connected to the first region of the fifth active layer through the third via hole V3 on the other hand. In an exemplary embodiment, the fourth connection electrode 64 can serve as a first electrode of the fifth transistor T5, and is configured to be connected to a first power line formed subsequently.

[0256] In the exemplary embodiment, in each circuit unit row, the fourth connection electrode 64 in the Nth column and the fourth connection electrode 64 in the N+1th column are connected to each other, and the fourth connection electrode 64 in the N+2th column and the fourth connection electrode 64 in the N+3th column are connected to each other. In the exemplary embodiment, since the fourth connection electrode 64 in each circuit unit is connected to the first power line formed subsequently, by forming the fourth connection electrodes 64 of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the fourth connection electrodes 64 of adjacent circuit units have the same potential, which is beneficial to improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.

[0257] In an exemplary embodiment, one end of the fifth connection electrode 65 is connected to the second region of the second active layer through a ninth via hole V9, and the other end of the fifth connection electrode 65 is connected to the second region of the third active layer (also the first region of the sixth active layer) through a tenth via hole V10. In an exemplary embodiment, the fifth connection electrode 65 can simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, so that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential.

[0258] In an exemplary embodiment, the sixth connection electrode 66 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4. In an exemplary embodiment, the sixth connection electrode 66 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 66 is configured to be connected to the anode connection electrode formed subsequently.

[0259] In an exemplary embodiment, the second initial signal line 67 may be in a zigzag shape with a main portion extending along the first direction X. The second initial signal line 67 is connected to the first regions of the plurality of seventh active layers through the plurality of seventh via holes V7 in a circuit unit row, and writes the initial voltage into the plurality of seventh transistors T7 in a circuit unit row. In an exemplary embodiment, since the second initial signal line 67 is connected to the first regions of all the seventh active layers in a circuit unit row, it is ensured that the first electrodes of all the seventh transistors T7 in a circuit unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0260] In an exemplary embodiment, in the test region, the fourth conductive layer pattern may include a source test lead, a drain test lead, a gate test lead, an auxiliary test lead, and a test connection electrode of a test transistor.

[0261] In an exemplary embodiment, in the area where the third test transistor TC3 of the test region is located, the fourth conductive layer pattern may include a third source test lead 305 , a third drain test lead 306 , a third test connection electrode 308 and a third auxiliary test lead 309 .

[0262] In an exemplary embodiment, the third source test lead 305 can be used as a third source test electrode of the third test transistor TC3, a first end of which is connected to the first region of the third test active layer 302 through the twenty-second via hole V22, and a second end of which is connected to a third source test terminal (not shown). In an exemplary embodiment, the third source test lead 305 and the third source test terminal can be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the third source test terminal is connected to an auxiliary pin through a connecting via.

[0263] In an exemplary embodiment, the third leakage test lead 306 can be used as a third leakage test electrode of the third test transistor TC3, a first end of which is connected to the second region of the third test active layer 302 through a twenty-third via hole V23, and a second end of which is connected to a third leakage test terminal (not shown). In an exemplary embodiment, the third leakage test lead 306 and the third leakage test terminal can be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the third leakage test terminal is connected to an auxiliary pin through a connecting via.

[0264] In an exemplary embodiment, the third test connection electrode 308 can be a zigzag shape extending along the second direction Y, and the end of the third test connection electrode 308 in the second direction Y is connected to the third test gate electrode 303 through the twenty-first via V21. The third test connection electrode 308 is configured to be connected to the third gate test lead formed subsequently.

[0265] In an exemplary embodiment, the first end of the third auxiliary test lead 309 is connected to the shielding connection line 301-1 through a plurality of twenty-fourth vias V24, and the second end of the third auxiliary test lead 309 is connected to the third auxiliary test terminal (not shown). In an exemplary embodiment, the third auxiliary test lead 309 and the third auxiliary test terminal can be an integrated structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the third auxiliary test terminal is connected to an auxiliary pin through a connecting via.

[0266] In an exemplary embodiment, in the area where the fourth test transistor TC4 of the test region is located, the fourth conductive layer pattern may include a fourth drain test lead 406 , a fourth gate test lead 407 , and a fourth test connection electrode 408 .

[0267] In an exemplary embodiment, the fourth leakage test lead 406 can be used as a fourth leakage test electrode of the fourth test transistor TC4, a first end of which is connected to the second region of the fourth test active layer 402 through the twenty-sixth via hole V26, and a second end of which is connected to a fourth leakage test terminal (not shown). In an exemplary embodiment, the fourth leakage test lead 406 and the fourth leakage test terminal can be an integrated structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the fourth leakage test terminal is connected to an auxiliary pin through a connecting via.

[0268] In an exemplary embodiment, a first end of the fourth gate test lead 407 is connected to the fourth test gate electrode 403 through a plurality of twenty-seventh vias V27, and a second end of the fourth gate test lead 407 is connected to a fourth gate test terminal (not shown). In an exemplary embodiment, the fourth gate test lead 407 and the fourth gate test terminal may be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the fourth gate test terminal is connected to an auxiliary pin through a connecting via.

[0269] In an exemplary embodiment, the fourth test connection electrode 408 can serve as the fourth source test electrode of the fourth test transistor TC4. The fourth test connection electrode 408 is rectangular and is connected to the first area of ​​the fourth test active layer 402 through the twenty-fifth via V25. The fourth test active layer 402 is configured to be connected to the fourth source test lead formed subsequently.

[0270] In an exemplary embodiment, in the area where the fifth test transistor TC5 of the test region is located, the fourth conductive layer pattern may include a fifth source test lead 505 , a fifth gate test lead 507 , and a fifth test connection electrode 508 .

[0271] In an exemplary embodiment, the fifth source test lead 505 can be used as the fifth source test electrode of the fifth test transistor TC5, and its first end is connected to the first area of ​​the fifth test active layer 502 through the twenty-eighth via hole V28, and its second end is connected to the fifth source test terminal (not shown). In an exemplary embodiment, the fifth source test lead 505 and the fifth source test terminal can be an integrated structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the fifth source test terminal is connected to an auxiliary pin through a connecting via.

[0272] In an exemplary embodiment, a first end of the fifth gate test lead 507 is connected to the fifth test gate electrode 503 through a plurality of thirtieth vias V30, and a second end of the fifth gate test lead 507 is connected to a fifth gate test terminal (not shown). In an exemplary embodiment, the fifth gate test lead 507 and the fifth gate test terminal can be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the fifth gate test terminal is connected to an auxiliary pin through a connecting via.

[0273] In an exemplary embodiment, the fifth test connection electrode 508 can serve as the fifth drain test electrode of the fifth test transistor TC5. The fifth test connection electrode 508 can be rectangular and connected to the second area of ​​the fifth test active layer 502 through the twenty-ninth via V29. The fifth test connection electrode 508 is configured to be connected to the fifth drain test lead formed subsequently.

[0274] In an exemplary embodiment, in the area where the first test transistor TC1 of the test region is located, the fourth conductive layer pattern may include a first drain test lead 106 , a first gate test lead 107 , and a first test connection electrode 108 .

[0275] In an exemplary embodiment, the first leakage test lead 106 can be used as a first leakage test electrode of the first test transistor TC1, a first end of which is connected to the second region of the first test active layer 102 through the thirty-second via hole V32, and a second end of which is connected to a first leakage test terminal (not shown). In an exemplary embodiment, the first leakage test lead 106 and the first leakage test terminal can be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the first leakage test terminal is connected to an auxiliary pin through a connecting via.

[0276] In an exemplary embodiment, the first end of the first gate test lead 107 is connected to the first test shielding line 101 through a plurality of thirty-third vias V33 on the one hand, and is connected to the first test gate electrode 103 through a plurality of thirty-fourth vias V34 on the other hand, and the second end of the first gate test lead 107 is connected to the first gate test terminal (not shown). Since the first test shielding line 101 located below the first test active layer 102 and the first test gate electrode 103 located above the first test active layer 102 are simultaneously connected to the first gate test lead 107, a first transistor T1 of a dual-gate structure is realized. In an exemplary embodiment, the first gate test lead 107 and the first gate test terminal can be an integrated structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the first gate test terminal is connected to an auxiliary pin through a connecting via.

[0277] In an exemplary embodiment, the first test connection electrode 108 can be in a "T" shape, and the end on one side of the second direction Y is connected to the first area of ​​the first test active layer 102 through the thirty-first via V31. The first test connection electrode 108 is configured to be connected to the first source test lead formed subsequently.

[0278] (10) Forming a seventh insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the first planar layer pattern may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the seventh insulating layer, and a plurality of via holes are disposed on the seventh insulating layer and the first planar layer, such as Figure 29a to Figure 29b , Figures 30a to 30d As shown, Fig.29a It is the planar structure diagram of eight circuit units in the display area. Fig.29b for Fig.29a A plan view of multiple vias in the Fig.30a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Fig.30b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Fig.30c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.30d FIG. 4 is a planar structural diagram of the area where the first test transistor TC1 is located in the test area.

[0279] In an exemplary embodiment, in the display area, the plurality of via holes in each circuit unit includes at least a forty-first via hole V41 , a forty-second via hole V42 , and a forty-third via hole V43 .

[0280] In an exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the third connection electrode 63 on the substrate, and the first flat layer and the seventh insulating layer in the forty-first via hole V41 are etched away to expose the surface of the third connection electrode 63. The forty-first via hole V41 is configured to connect a subsequently formed data signal line to the third connection electrode 63 through the via hole.

[0281] In an exemplary embodiment, the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 64 on the substrate, and the first flat layer and the seventh insulating layer in the forty-second via hole V42 are etched away to expose the surface of the fourth connection electrode 64. The forty-second via hole V42 is configured to connect the first power line formed subsequently to the fourth connection electrode 64 through the via hole.

[0282] In an exemplary embodiment, the orthographic projection of the forty-third via hole V43 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 66 on the substrate, and the first flat layer and the seventh insulating layer in the forty-third via hole V43 are etched away to expose the surface of the sixth connection electrode 66. The forty-third via hole V432 is configured to connect the anode connection electrode formed subsequently to the sixth connection electrode 66 through the via hole.

[0283] In an exemplary embodiment, in the test area, the plurality of vias include at least a fifty-first via V51 , a fifty-second via V52 , a fifty-third via V53 , and a fifty-fourth via V54 .

[0284] In an exemplary embodiment, the fifty-first via hole V51 is located in the area where the third test transistor TC3 is located, the orthographic projection of the fifty-first via hole V51 on the substrate is located within the range of the orthographic projection of the third test connection electrode 308 on the substrate, the first flat layer and the seventh insulating layer in the fifty-first via hole V51 are etched away to expose the surface of the third test connection electrode 308, and the fifty-first via hole V51 is configured to connect the subsequently formed third gate test lead to the third test connection electrode 308 through the via hole.

[0285] In an exemplary embodiment, the fifty-second via V52 is located in the area where the fourth test transistor TC4 is located, the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the fourth test connection electrode 408 on the substrate, the first flat layer and the seventh insulating layer in the fifty-second via V52 are etched away to expose the surface of the fourth test connection electrode 408, and the fifty-second via V52 is configured to connect a subsequently formed fourth source test lead to the fourth test connection electrode 408 through the via.

[0286] In an exemplary embodiment, the fifty-third via V53 is located in the area where the fifth test transistor TC5 is located, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the fifth test connection electrode 508 on the substrate, the first flat layer and the seventh insulating layer in the fifty-third via V53 are etched away to expose the surface of the fifth test connection electrode 508, and the fifty-third via V53 is configured to connect the subsequently formed fifth leakage test lead to the fifth test connection electrode 508 through the via.

[0287] In an exemplary embodiment, the fifty-fourth via hole V54 is located in the region where the third test transistor TC3 is located, the orthographic projection of the fifty-fourth via hole V54 on the substrate is located within the range of the orthographic projection of the first test connection electrode 108 on the substrate, the first flat layer and the seventh insulating layer in the fifty-fourth via hole V54 are etched away to expose the surface of the first test connection electrode 108, and the fifty-fourth via hole V54 is configured to connect the first source test lead formed subsequently to the first test connection electrode 108 through the via hole. In an exemplary embodiment, there may be a plurality of the fifty-fourth via holes V54 to improve connection reliability.

[0288] In an exemplary embodiment, in the test area 300 near the frame area 200, a plurality of connection vias are further provided in the area where some auxiliary pins 520 are located, and the orthographic projections of the connection vias on the substrate are located within the range of the orthographic projections of the auxiliary pins 520 on the substrate, and the first flat layer, the seventh insulating layer, the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the connection vias are etched away to expose the surface of the auxiliary pins 520. In an exemplary embodiment, the connection vias are configured to be connected to the test terminals formed subsequently through the vias.

[0289] (11) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Figure 31a to Figure 31b , Figures 32a to 32d As shown, Fig.31a It is the planar structure diagram of eight circuit units in the display area. Fig.31b for Fig.31a A plan view of the fifth conductive layer in FIG. Fig.32a is a planar structural diagram of the area where the third test transistor TC3 is located in the test area, Figure 32b is a planar structural diagram of the area where the fourth test transistor TC4 is located in the test area, Figure 32c is a planar structural diagram of the area where the fifth test transistor TC5 is located in the test area, Fig.32d FIG. 1 is a planar structural diagram of a region where the first test transistor TC1 is located in the test region. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0290] In an exemplary embodiment, in the display area, the fifth conductive layer includes at least a data signal line 71 , a first power line 72 , and an anode connection electrode 73 .

[0291] In an exemplary embodiment, the data signal line 71 is a straight line whose main part extends along the second direction Y, and the data signal line 71 is connected to the third connection electrode 63 through the forty-first via hole V41. Since the third connection electrode 63 is connected to the first region of the fourth active layer through the via hole, the data signal line 71 is connected to the first electrode of the fourth transistor T4, and the data signal is written into the fourth transistor T4.

[0292] In an exemplary embodiment, the first power line 72 is in a zigzag shape with a main portion extending along the second direction Y, and the first power line 72 is connected to the fourth connection electrode 64 through the 42nd via hole V42. Since the fourth connection electrode 64 is connected to the second electrode plate 44 and the first region of the fifth active layer through the via holes, the first power line 72 is connected to the second electrode plate 44 and the first electrode of the fifth transistor T5, and the power signal is written into the fifth transistor T5.

[0293] In the exemplary embodiment, the anode connection electrode 73 is connected to the sixth connection electrode 66 through the forty-third via hole V43. Since the sixth connection electrode 66 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the anode connection electrode 73 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0294] In an exemplary embodiment, in the test region, the fifth conductive layer pattern may include a first source test lead 105 , a first test power electrode 109 , a third gate test lead 307 , a fourth source test lead 405 , and a fifth drain test lead 506 .

[0295] In an exemplary embodiment, the third gate test lead 307 is located in the region where the third test transistor TC3 is located, the first end of the third gate test lead 307 is connected to the third test connection electrode 308 through the fifty-first via hole V51, and the second end of the third gate test lead 307 is connected to the third gate test terminal (not shown). In an exemplary embodiment, the third gate test lead 307 and the third gate test terminal can be an integral structure connected to each other, both are arranged in the same layer and are formed simultaneously through the same patterning process, and the third gate test terminal is connected to an auxiliary pin through a connecting via.

[0296] In an exemplary embodiment, the fourth source test lead 405 is located in the region where the fourth test transistor TC4 is located, the first end of the fourth source test lead 405 is connected to the fourth test connection electrode 408 through the fifty-second via V52, and the second end of the fourth source test lead 405 is connected to the fourth source test terminal (not shown). In an exemplary embodiment, the fourth source test lead 405 and the fourth source test terminal can be an integral structure connected to each other, both are arranged in the same layer and are formed simultaneously through the same patterning process, and the fourth source test terminal is connected to an auxiliary pin through a connecting via.

[0297] In an exemplary embodiment, the fifth leakage test lead 506 is located in the area where the fifth test transistor TC5 is located, the first end of the fifth leakage test lead 506 is connected to the fifth test connection electrode 508 through the fifty-third via V53, and the second end of the fifth leakage test lead 506 is connected to the fifth leakage test terminal (not shown). In an exemplary embodiment, the fifth leakage test lead 506 and the fifth leakage test terminal can be an integrated structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the fifth leakage test terminal is connected to an auxiliary pin through a connecting via.

[0298] In an exemplary embodiment, the first source test lead 105 is located in the area where the first test transistor TC1 is located, and the first end of the first source test lead 105 is connected to the first test connection electrode 108 through a plurality of fifty-fourth vias V54, and the second end of the first source test lead 105 is connected to the first source test terminal (not shown). In an exemplary embodiment, the first source test lead 105 and the first source test terminal can be an integral structure connected to each other, both of which are arranged in the same layer and formed simultaneously through the same patterning process, and the first source test terminal is connected to an auxiliary pin through a connecting via.

[0299] In an exemplary embodiment, the shape of the first test power electrode 109 is substantially the same as the shape of the first power line 72 of each circuit unit in the display area.

[0300] At this point, the drive circuit layer is prepared on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the drive circuit layer may include a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on the substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors, the first conductive layer includes gate electrodes of multiple polysilicon transistors and a first plate of a storage capacitor, the second conductive layer includes a second plate of a storage capacitor, the second semiconductor layer includes an active layer of multiple oxide transistors, the third conductive layer includes gate electrodes of multiple oxide transistors, the fourth conductive layer includes first and second electrodes of multiple polysilicon transistors and first and second electrodes of multiple oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

[0301] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer and a first flat layer, the first insulating layer is arranged between the blocking layer and the first semiconductor layer, the second insulating layer is arranged between the first semiconductor layer and the first conductive layer, the third insulating layer is arranged between the first conductive layer and the second conductive layer, the fourth insulating layer is arranged between the second conductive layer and the second semiconductor layer, the fifth insulating layer is arranged between the second semiconductor layer and the third conductive layer, the sixth insulating layer is arranged between the third conductive layer and the fourth conductive layer, and the seventh insulating layer and the first flat layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0302] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer may include the following operations. A second flat layer pattern is formed, and at least an anode via is provided on the second flat layer. An anode pattern is formed, and the anode is connected to the anode connection electrode through the anode via. An anode pixel definition layer is formed, and a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode. An organic light-emitting layer is formed by evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0303] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer may be called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called a gate insulating (GI) layer, the sixth insulating layer may be called an interlayer insulating (ILD) layer, and the seventh insulating layer may be called a passivation (PVX) layer.

[0304] The structure and preparation process shown above in the present disclosure are merely exemplary illustrations. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure does not limit this.

[0305] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the present disclosure forms a test circuit in the effective area, and the characteristics of the test transistor in the test circuit are basically consistent with the corresponding transistor characteristics in the display area. The test transistor can accurately reflect the actual characteristics of the transistor in the display area, which can not only ensure that the transistor characteristics are within the specified reference range, but also can be used as a reference for analyzing poor transistors by collecting transistor characteristic data in the display area. The exemplary embodiment of the present disclosure proposes that the layout of the test circuit is reasonable, which can save space in the effective area. The preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high production efficiency, low production cost, and high yield rate.

[0306] The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided by the aforementioned exemplary embodiment. In an exemplary embodiment, the display substrate includes an active area and a frame area located outside the active area, the active area includes a display area and at least one test area, the display area includes a plurality of sub-pixels; the manufacturing method may include:

[0307] At least one pixel driving circuit is formed in at least one sub-pixel in the display area, at least one test unit is formed in the test area, and a plurality of test pins and a plurality of connection lines are formed in the frame area;

[0308] The test unit includes a test transistor, multiple test leads and multiple test terminals. The test transistor has the same structure as at least one transistor in the pixel driving circuit. The multiple test terminals are connected to the test transistor through the multiple test leads; the multiple test pins are correspondingly connected to the multiple test terminals through multiple connecting lines.

[0309] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0310] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: The invention comprises an effective area and a frame area located outside the effective area, wherein the effective area comprises a display area and at least one test area, wherein the display area comprises a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel driving circuit, wherein the test area comprises at least one test unit, wherein the test unit comprises a test transistor, a plurality of test leads and a plurality of test terminals, wherein the test transistor has the same structure as at least one transistor in the pixel driving circuit, and the plurality of test terminals are connected to the test transistor through the plurality of test leads; and wherein the frame area is provided with a plurality of test pins and a plurality of connecting wires, wherein the plurality of test pins are correspondingly connected to the plurality of test terminals through the plurality of connecting wires.

2. The display substrate according to claim 1, characterized in that: At least one test terminal and a test lead connected to the test terminal are arranged in the same layer and are an integrated structure connected to each other.

3. The display substrate according to claim 1, characterized in that: The test unit further includes a plurality of auxiliary pins, the plurality of auxiliary pins are correspondingly connected to the plurality of test pins through the plurality of connection lines, and the plurality of test terminals are correspondingly connected to the plurality of auxiliary pins through vias.

4. The display substrate according to claim 3, characterized in that: At least one test pin, at least one auxiliary pin and a connection line connecting the test pin and the auxiliary pin are arranged in the same layer and are an integrated structure connected to each other.

5. The display substrate according to claim 1, characterized in that: The multiple test terminals include at least a gate test terminal, a source test terminal and a drain test terminal, and the multiple test leads include at least a gate test lead, a source test lead and a drain test lead; the control electrode of the test transistor is connected to the gate test terminal through the gate test lead, the first electrode of the test transistor is connected to the source test terminal through the source test lead, and the second electrode of the test transistor is connected to the drain test terminal through the drain test lead.

6. The display substrate according to claim 1, characterized in that: The test area further includes at least one virtual pixel, and the at least one virtual pixel includes a virtual pixel driving circuit. The virtual pixel driving circuit has the same structure as the pixel driving circuit, and the virtual pixel driving circuit is arranged between adjacent test leads.

7. The display substrate according to any one of claims 1 to 6, characterized in that: In a plane perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially arranged on a base; the first semiconductor layer includes an active layer of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of a storage capacitor, the second semiconductor layer includes an active layer of a plurality of oxide transistors, the third conductive layer includes gate electrodes of a plurality of oxide transistors, the fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

8. The display substrate according to claim 7, characterized in that: The plurality of test terminals are located on the fourth conductive layer.

9. The display substrate according to claim 7, characterized in that: The plurality of test leads are located on the fourth conductive layer or the fifth conductive layer.

10. The display substrate according to claim 7, characterized in that: The test pins, connecting wires and auxiliary pins are located on the second conductive layer.

11. The display substrate according to any one of claims 1 to 6, characterized in that: The pixel driving circuit includes at least one metal oxide transistor and at least one low-temperature polysilicon transistor, and the test area includes at least one first test transistor or a second test transistor having the same structure as the metal oxide transistor, and at least one third test transistor or a fourth test transistor having the same structure as the low-temperature polysilicon transistor.

12. The display substrate according to claim 11, characterized in that: The first area of ​​the first test active layer in the first test transistor is connected to the first source test lead, the second area of ​​the first test active layer is connected to the first drain test lead through a via, and the first test gate electrode in the first test transistor is connected to the first gate test lead through a via.

13. The display substrate according to claim 12, characterized in that: The first test transistor further includes a first test connection electrode, the first test connection electrode is connected to the first region of the first test active layer through a via hole, and the first source test lead is connected to the first test connection electrode through the via hole.

14. The display substrate according to claim 12, characterized in that: The first test transistor further includes a first test shielding line, and the first test shielding line is connected to the first gate test lead through a via.

15. The display substrate according to claim 11, characterized in that: The first area of ​​the third test active layer in the third test transistor is connected to the third source test lead through a via, the second electrode of the third test active layer is connected to the third drain test lead through a via, and the third test gate electrode in the third test transistor is connected to the third gate test lead.

16. The display substrate according to claim 15, characterized in that: The third test transistor further includes a third test connection electrode, the third test connection electrode is connected to the third test gate electrode through a via hole, and the first gate test lead is connected to the third test connection electrode through the via hole.

17. The display substrate according to claim 15, characterized in that: The third test transistor also includes a test shielding block and a shielding connection line connected to the test shielding block, the shielding connection line is connected to one end of the third auxiliary test lead through a via, and the other end of the third auxiliary test lead is connected to the third auxiliary test terminal.

18. The display substrate according to claim 11, characterized in that: The first area of ​​the fourth test active layer in the fourth test transistor is connected to the fourth source test lead, the second electrode of the fourth test active layer is connected to the fourth drain test lead through a via, and the fourth test gate electrode in the first test transistor is connected to the fourth gate test lead through a via.

19. The display substrate according to claim 18, characterized in that: The fourth test transistor further includes a fourth test connection electrode, the fourth test connection electrode is connected to the first region of the fourth test active layer through a via hole, and the fourth source test lead is connected to the fourth test connection electrode through a via hole.

20. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 19.

21. A method for preparing a display substrate, characterized in that: The display substrate includes an active area and a frame area located outside the active area, the active area includes a display area and at least one test area, the display area includes a plurality of sub-pixels; the preparation method includes: At least one pixel driving circuit is formed in at least one sub-pixel in the display area, at least one test unit is formed in the test area, and a plurality of test pins and a plurality of connection lines are formed in the frame area; The test unit includes a test transistor, multiple test leads and multiple test terminals. The test transistor has the same structure as at least one transistor in the pixel driving circuit. The multiple test terminals are connected to the test transistor through the multiple test leads; the multiple test pins are correspondingly connected to the multiple test terminals through multiple connecting lines.

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