Clock phase control circuit and clock phase control method

Abstract

The present application provides a clock phase control circuit and a clock phase control method. The clock phase control circuit comprises a frequency divider, a multiplexer and a controller. The frequency divider receives a first clock signal and outputs a plurality of second clock signals. The multiplexer receives the plurality of second clock signals and outputs one of the plurality of second clock signals. The controller is coupled to the frequency divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the plurality of second clock signals according to the selection signal. The clock phase control circuit and the clock phase control method of the present application can switch the clock signal appropriately to output a clock signal with appropriate clock frequency.

Description

Technical Field

[0001] This invention relates to a control circuit and a control method, and more particularly to a clock stage control circuit and a clock stage control method. Background Technology

[0002] As the computing power requirements of chips (such as high-performance computing (HPC) chips or AI accelerator chips) increase, the power consumption of these high-performance chips also increases. However, in use cases requiring peak performance, the operating power of the chip may exceed the peak limit of the system design or chip design, causing the system to shut down, the core processing to malfunction, or even the chip to be damaged. However, traditional overcurrent protection (OCP) mechanisms only shut down or reset the system to an idle state, resulting in performance loss, overshoot issues, and increased complexity in system processing. Summary of the Invention

[0003] This invention relates to a clock phase control circuit and a clock phase control method, which can appropriately switch the clock signal when an overcurrent event occurs, so as to output a core clock signal with an appropriate clock frequency.

[0004] According to an embodiment of the present invention, the clock phase control circuit includes a frequency divider, a multiplexer, and a controller. The frequency divider receives a first clock signal and outputs a plurality of second clock signals. The multiplexer receives the plurality of second clock signals and outputs one of the plurality of second clock signals. The controller is coupled to the frequency divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another of the plurality of second clock signals according to the selection signal.

[0005] According to an embodiment of the present invention, the clock phase control method of the present invention includes the following steps: receiving a first clock signal through a frequency divider and outputting a plurality of second clock signals; receiving a plurality of second clock signals through a multiplexer and outputting one of the plurality of second clock signals; when the controller receives an interrupt signal, outputting a selection signal to the multiplexer according to the interrupt signal; and outputting another of the plurality of second clock signals according to the selection signal through the multiplexer.

[0006] Based on the above, the clock phase control circuit and clock phase control method of the present invention can automatically reduce the clock frequency of the clock signal when an overcurrent event occurs, so as to output a core clock signal with an appropriate clock frequency, thereby enabling the processing core to maintain its computing power even in the event of an overcurrent event.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a clock phase control circuit according to an embodiment of the present invention;

[0009] Figure 2 This is a flowchart of a clock phase control method according to an embodiment of the present invention;

[0010] Figure 3 This is a circuit diagram of a clock phase control circuit according to another embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of clock signal switching according to an embodiment of the present invention;

[0012] Figure 5 This is a circuit diagram of a clock phase control circuit according to another embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures

[0014] 100, 300, 500: Clock phase control circuit;

[0015] 101: Interrupt signal;

[0016] 103, 303, 5031, 5032: Selection signals;

[0017] 104, 304, 5041, 5042: Frequency division signals;

[0018] 110, 310, 510: Controller;

[0019] 120, 320: Frequency dividers;

[0020] 130, 330, 530, 540, 551-554: Multiplexers;

[0021] 301, 501: First overcurrent alarm signal;

[0022] 302, 502: Second overcurrent alarm signal;

[0023] 305, 505: Frequency modulation data;

[0024] 306, 506: Control signals;

[0025] 307, 308, 507, 508: Status signals;

[0026] 309, 509: Power information;

[0027] 311, 511: Register circuits;

[0028] 312, 512: State machine circuits;

[0029] 521: First frequency divider;

[0030] 522: Second frequency divider;

[0031] CK1, CK2_1~CK2_N, CK3~CK7, CKR: Clock signals;

[0032] S210~S240: Steps;

[0033] V1, V2: Voltage;

[0034] f0~f3: Clock frequency;

[0035] t0~t6: Time. Detailed Implementation

[0036] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0037] Figure 1 This is a circuit diagram of a clock phase control circuit according to an embodiment of the present invention. (See reference) Figure 1The Clock Step Control (CSC) circuit 100 includes a controller 110, a clock divider 120, and a multiplexer 130. The controller 110 is coupled to the clock divider 120 and the multiplexer 130. The clock divider 120 is coupled to the multiplexer 130. In this embodiment, the Clock Step Control circuit 100 may be located in a System-on-a-Chip (SoC) and provides a clock signal to the SoC's processing core. The SoC may be, for example, a High Performance Computing (HPC) chip or an AI accelerator chip, and the processing core may be, for example, a Microprocessor Unit (MPU), but this invention is not limited thereto. In this embodiment, the multiplexer 130 may be a glitch-free clock multiplexer.

[0038] In this embodiment, the frequency divider 120 can, for example, receive a clock signal output from a phase-locked loop (PLL) circuit or a first clock signal CK1 provided by a voltage-controlled oscillator (VCO) within the PLL circuit, and generate multiple second clock signals CK2_1 to CK2_N with different clock frequencies based on the first clock signal CK1, where N is a positive integer. In this embodiment, the frequency divider 120 can provide the second clock signals CK2_1 to CK2_N to the multiplexer 130, and the controller 110 can select one of the second clock signals CK2_1 to CK2_N as the core clock signal CK3 by controlling the multiplexer 130, and output it to the processing core of the system chip. Therefore, the clock phase control circuit 100 of this embodiment can effectively control the clock frequency of the core clock signal CK3 of the system chip, and can appropriately adjust the performance of the processing core.

[0039] Figure 2 This is a flowchart of a clock phase control method according to an embodiment of the present invention. (See reference) Figure 1 as well as Figure 2In this embodiment, the clock stage control circuit 100 can execute the following steps S210 to S240 to realize the stage control function of the clock signal. In step S210, the clock stage control circuit 100 can receive the first clock signal CK1 through the frequency divider 120 and output multiple second clock signals CK2_1 to CK2_N. In this embodiment, the second clock signals CK2_1 to CK2_N have different clock frequencies. For example, the second clock signal CK2_1 has the highest clock frequency, and the second clock signal CK2_N has the lowest clock frequency. In step S220, the clock stage control circuit 100 can receive multiple second clock signals CK2_1 to CK2_N through the multiplexer 130 and output one of the multiple second clock signals CK2_1 to CK2_N. In this regard, under normal operation, the controller 110 can, for example, pre-control the multiplexer 130 to output a second clock signal with a higher clock frequency as the core clock signal CK3 provided to the processing core.

[0040] In step S230, when the controller 110 receives the interrupt signal 101, the clock phase control circuit 100 can output a selection signal 103 to the multiplexer 130 based on the interrupt signal 101. In this embodiment, the interrupt signal 101 may be generated by, for example, the voltage regulator (VR) of the system chip based on whether an abnormality has occurred in the current current (power) supplied to the system or core, or by the firmware of the system chip monitoring the current current (power), and the present invention is not limited thereto.

[0041] In step S240, the clock phase control circuit 100 can output one of the multiple second clock signals CK2_1 to CK2_N through the multiplexer 130 according to the selection signal 103. In response, when an abnormal condition such as an overcurrent event occurs in the system or processing core, the controller 110 can receive a corresponding interrupt signal 101. The controller 110 can generate and output a corresponding selection signal 103 to the multiplexer 130 based on the interrupt signal 101, controlling the multiplexer 130 to output another second clock signal with a lower clock frequency as the core clock signal CK3 provided to the processing core. This allows for automatic and immediate reduction of the processing core's performance to prevent system shutdown, abnormal processing core operation, or even chip damage. Furthermore, when the abnormal current condition is resolved, the controller 110 can also automatically control the multiplexer 130 to resume outputting a clock signal with a normal clock frequency through the selection signal 103, thereby restoring the processing core's performance.

[0042] Furthermore, in this embodiment, the controller 110 can also output a frequency division signal 104 to the frequency divider 120, so that the frequency divider 120 can generate second clock signals CK2_1 to CK2_N according to the frequency division signal 104. The controller 110 can generate the frequency division signal 104 according to different frequency division requirements. In other words, the number of clock signals with different clock frequencies output by the frequency divider 120 can be determined according to different clock frequency adjustment requirements.

[0043] Figure 3 This is a circuit diagram of a clock phase control circuit according to another embodiment of the present invention. (See reference) Figure 3 The clock phase control circuit 300 includes a controller 310, a frequency divider 320, and a multiplexer 330. The controller 310 includes a register circuit 311 and a state machine (SM) circuit 312. The register circuit 311 is coupled to the state machine circuit 312. The state machine circuit 312 is coupled to the frequency divider 320 and the multiplexer 330. In this embodiment, when the register circuit 311 receives an interrupt signal, it can output a control signal 306 to the state machine circuit 312. The state machine circuit 312 can output a selection signal 303 to the multiplexer 330 according to the control signal 306, and output a frequency division signal 304 to the frequency divider 320, so that the frequency divider 320 can output multiple second clock signals CK2_1 to CK2_N to the multiplexer 330 according to the frequency division signal 304, and the multiplexer 330 can change its output according to the selection signal 303.

[0044] In this embodiment, the register circuit 311 can obtain frequency modulation data 305 through the bus to pre-store frequency modulation setting parameters based on the frequency modulation data 305. Therefore, when the register circuit 311 receives an interrupt signal, it can generate a corresponding control signal 306 based on the interrupt signal and the frequency modulation setting parameters. In this embodiment, the state machine circuit 312 can also receive a reference clock signal CKR and power information 309. The state machine circuit 312 can generate a corresponding selection signal 303 and a frequency divider signal 304 based on the control signal 306 and the power information 309, and the state machine circuit 312 can output the selection signal 303 and the frequency divider signal 304. The state machine circuit 312 can effectively synchronize and control the frequency divider 320 and the multiplexer 330 based on the reference clock signal CKR.

[0045] In this embodiment, when the register circuit 311 receives an interrupt signal, the multiplexer 330 can sequentially output at least a portion of multiple second clock signals CK2_1 to CK2_N in a multi-stage switching manner from high clock frequency to low clock frequency to achieve multi-stage frequency reduction. In this embodiment, the interrupt signal may include at least one of a first overcurrent alarm signal 301 and a second overcurrent alarm signal 302. The first overcurrent alarm signal 301 may respond to the average current of the system chip being higher than a first current threshold. The second overcurrent alarm signal 302 may respond to the instantaneous current of the system chip being higher than a second current threshold. The second current threshold may be higher than the first current threshold. In this way, the clock stage control circuit 300 of this embodiment can adjust the clock frequency of the corresponding core clock signal based on the two overcurrent conditions.

[0046] In this embodiment, when the controller 310 receives the first overcurrent alarm signal 301, the multiplexer 330 can sequentially output at least a portion of multiple second clock signals CK2_1 to CK2_N as the core clock signal CK3 during the first response period, in a multi-stage switching manner from high clock frequency to low clock frequency. Furthermore, when the controller 310 receives the second overcurrent alarm signal 302, the multiplexer 330 can sequentially output at least a portion of multiple second clock signals CK2_1 to CK2_N as the core clock signal CK3 during the second response period, in a multi-stage switching manner from high clock frequency to low clock frequency. In this embodiment, the duration of the first response period can be longer than the duration of the second response period. In other words, when the average operating current of the system single chip during a period is higher than a first current threshold, the clock stage control circuit 300 can gradually and progressively reduce the clock frequency of the core clock signal CK3 provided to the processing core. Furthermore, when the operating current of a single chip in the system momentarily exceeds the second current threshold, the clock phase control circuit 300 can quickly and progressively reduce the clock frequency of the core clock signal CK3 provided to the processing core.

[0047] It is worth noting that if the controller 310 receives the first overcurrent alarm signal 301 and is performing a gradual frequency reduction operation (before the frequency reduction is completed), and then receives the second overcurrent alarm signal 302, the controller 310 can control the multiplexer 330 to quickly reduce the clock frequency of the core clock signal CK3 provided to the processing core. In other words, the switching priority of the second overcurrent alarm signal is higher than that of the first overcurrent alarm signal. Furthermore, in this embodiment, when the controller 310 completes the frequency reduction operation of the core clock signal CK3, and the multiplexer 330 outputs a core clock signal CK3 with a low clock frequency, the state machine circuit 312 can output a state signal 307 to the register circuit 311 based on the switching result of the core clock signal CK3, to, for example, clear the clock frequency reduction trigger record recorded in the register circuit 311. Additionally, the state machine circuit 312 can also output a state signal 308 to the processing core of the system chip to notify the processing core that its frequency reduction operation has been completed.

[0048] In this embodiment, when the interrupt signal is de-asserted, the multiplexer 330 can output at least a portion of a plurality of second clock signals CK2_1 to CK2_N sequentially in a multi-stage switching manner from low clock frequency to high clock frequency during the recovery period. In other words, when there is no overcurrent in the system single chip, the clock stage control circuit 300 can gradually increase the clock frequency of the core clock signal CK3 provided to the processing core. In this embodiment, the duration of the recovery period can be equal to the duration of the first response period or the second response period, but the present invention is not limited thereto.

[0049] Figure 4 This is a schematic diagram illustrating the switching of a clock signal according to an embodiment of the present invention. (Reference) Figure 3 and Figure 4 The first overcurrent alarm signal 301 may, for example, have the following characteristics: Figure 4 The voltage signal showing the voltage change, and the second overcurrent alarm signal 302 may also have the same or similar characteristics, for example. Figure 4 The voltage signal represents the voltage change shown. It should be noted that in this embodiment, the first clock signal CK1 may, for example, have a clock frequency CLK. The second clock signals CK2_1 to CK2_N may, for example, have clock frequencies of (CLK / n) to (CLK / n+N-1), respectively, where n is a positive integer, and (n+N-1) is, for example, less than 64. In other words, when the multiplexer 130 sequentially outputs clock signals in a multi-stage switching manner from high clock frequency to low clock frequency, the down-frequency ratio of the first stage may be n / (n+1), the down-frequency ratio of the second stage may be (n+1) / (n+2), and so on. It is worth noting that the down-frequency ratio of each stage may be between 15% and 20%.

[0050] In this embodiment, the period from time t0 to time t3 can be the response phase of overcurrent protection, and the period from time t3 to time t6 can be the recovery phase of overcurrent protection. At time t0, when the register circuit 311 receives the first overcurrent alarm signal 301 changing from voltage V1 (low voltage level) to voltage V2 (high voltage level), it indicates that the average value of the operating current of the system single chip during a period is higher than the first current threshold. In this embodiment, the register circuit 311 can output a control signal 306 to the state machine circuit 312, so that the state machine circuit 312 can control the multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., the second clock signal CK2_1) with a clock frequency f0 (e.g., CLK / n) to outputting a core clock signal CK3 (e.g., the second clock signal CK2_2) with a clock frequency f1 (e.g., CLK / (n+1)).

[0051] Next, after a down-frequency waiting period of several reference clock cycles for the reference clock signal CKR, at time t1, the state machine circuit 312 can control the multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., a second clock signal CK2_2) with a clock frequency f1 (e.g., CLK / (n+1)) to outputting a core clock signal CK3 (e.g., a second clock signal CK2_3) with a clock frequency f2 (e.g., CLK / (n+2)).

[0052] Next, after a down-frequency waiting period of several reference clock cycles for the reference clock signal CKR, at time t2, state machine circuit 312 can control multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., a second clock signal CK2_3) with a clock frequency f2 (e.g., CLK / (n+2)) to outputting a core clock signal CK3 (e.g., a second clock signal CK2_4) with a clock frequency f3 (e.g., CLK / (n+3)). In this way, clock phase control circuit 300 can complete the down-frequency operation of core clock signal CK3 at time t2.

[0053] However, it is worth noting that between time t0 and time t2, when the register circuit 311 receives the second overcurrent alarm signal 302 changing from voltage V1 to voltage V2, it indicates that the operating current of the system single chip momentarily exceeds the second current threshold. In this embodiment, the register circuit 311 can output a control signal 306 to the state machine circuit 312, so that the state machine circuit 312 can control the multiplexer 330 to shorten the switching time length of the core clock signal CK3 from clock frequency f0 to clock frequency f3, so as to quickly switch to output a core clock signal CK3 (e.g., the second clock signal CK2_4) with clock frequency f3 (e.g., CLK / (n+3)). For example, between time t0 and time t1, when the register circuit 311 receives the second overcurrent alarm signal 302 changing from voltage V1 to voltage V2, the state machine circuit 312 can control the multiplexer 330 to quickly and in stages lower the clock frequency of the core clock signal CK3 from clock frequency f1, clock frequency f2 to clock frequency f3 before time t2. In this way, the clock phase control circuit 300 can effectively maintain the operation of the processing core during an overcurrent event in the system chip, thus avoiding system shutdown and interruption of the processing core's processing operations.

[0054] However, it is worth noting that in some other embodiments of the present invention, when the register circuit 311 receives the second overcurrent alarm signal 302 changing from voltage V1 to voltage V2, the multiplexer 330 may also use a method with fewer switching levels (higher frequency reduction ratio) to reduce the clock frequency of the core clock signal CK3. For example, the multiplexer 330 sequentially switches the clock frequency of the core clock signal CK3 from clock frequency f0, clock frequency f2 to clock frequency f3.

[0055] Next, at time t3, when the register circuit 311 receives the first overcurrent alarm signal 301 changing from voltage V2 (high voltage level) to voltage V1 (low voltage level), it indicates that the first overcurrent alarm signal 301 is released. In this embodiment, at time t4, the register circuit 311 can output a control signal 306 to the state machine circuit 312, so that the state machine circuit 312 can control the multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., the second clock signal CK2_4) with a clock frequency f3 (e.g., CLK / (n+3)) to outputting a core clock signal CK3 (e.g., the second clock signal CK2_3) with a clock frequency f2 (e.g., CLK / (n+2)).

[0056] Next, after a frequency upsampling wait period of several reference clock cycles for the reference clock signal CKR, at time t5, the state machine circuit 312 can control the multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., a second clock signal CK2_3) with a clock frequency f3 (e.g., CLK / (n+2)) to outputting a core clock signal CK3 (e.g., a second clock signal CK2_2) with a clock frequency f1 (e.g., CLK / (n+1)).

[0057] Next, after a frequency upsampling wait period of several reference clock cycles for the reference clock signal CKR, at time t6, the state machine circuit 312 can control the multiplexer 330 to switch, for example, from outputting a core clock signal CK3 (e.g., a second clock signal CK2_2) with a clock frequency f1 (e.g., CLK / (n+1)) to outputting a core clock signal CK3 (e.g., a second clock signal CK2_1) with a clock frequency f0 (e.g., CLK / (n)).

[0058] In this way, the clock phase control circuit 300 can restore the clock frequency of the core clock signal CK3 at time t6. Therefore, the clock phase control circuit 300 of this embodiment can automatically reduce the core clock frequency of the processing core of the system chip in response to the overcurrent event of the system chip, so as to realize the effective overcurrent protection function of the processing core. And when the overcurrent event ends, it can automatically increase the core clock frequency of the processing core of the system chip to restore the performance of the processing core.

[0059] Additionally, it is worth noting that the frequency modulation data 305 in this embodiment may include relevant frequency modulation setting parameters such as the time length of each response period of the clock frequency down operation and the clock frequency up operation, the frequency up / down ratio, the number of frequency up / down operations, and the waiting time length between each frequency up / down stage, so that the register circuit 311 can output corresponding control signals according to different overcurrent alarm signals after being set, so as to control the multiplexer 330 to realize the aforementioned clock frequency down operation and clock frequency up operation.

[0060] Figure 5 This is a circuit diagram of a clock phase control circuit according to another embodiment of the present invention. (See reference) Figure 5The clock phase control circuit 500 includes a controller 510, a first frequency divider 521, a second frequency divider 522, and multiplexers 530, 540, and 551-554. The controller 510 includes a register circuit 512 and a state machine circuit 511. The register circuit 512 is coupled to the state machine circuit 511. The state machine circuit 511 is coupled to the frequency dividers 521 and 522 and the multiplexers 530, 540, and 551-554. One input terminal of the second frequency divider 522 is coupled to the output terminal of the first frequency divider 521 to receive the clock signal output by the first frequency divider 521. In this embodiment, the register circuit 512 can receive a first overcurrent alarm signal 501, a second overcurrent alarm signal 502, and frequency modulation data 505. The register circuit 512 can receive a status signal 507 from the state machine circuit 511 and output a control signal 506 to the state machine circuit 511. State machine circuit 511 can output selection signals 5031-5036 to multiplexers 530, 540, and 551-554 respectively to control multiplexers 530, 540, and 551-554 respectively. State machine circuit 512 can output frequency division signals 5041 and 5042 to the first frequency divider 521 and the second frequency divider 522 respectively. State machine circuit 511 can output status signal 508, and state machine circuit 511 can also receive reference clock signal CKR and power information 509.

[0061] It is worth noting that this embodiment is the one described above. Figure 3 This is a specific implementation example. Therefore, the relevant circuit features, signal content, and implementation methods of the clock stage control circuit 500 in this embodiment can be referred to the above. Figure 3 The examples provided provide sufficient teaching, suggestions and implementation instructions, and will not be elaborated further here.

[0062] Compared to Figure 3 In this embodiment, the clock phase control circuit 500 may be equipped with two frequency dividers and multiple multiplexers. In this embodiment, the first frequency divider 521 may, for example, divide a first clock signal having a frequency of 4 gigahertz (GHz) to generate second clock signals CK2_1 to CK2_4. The second frequency divider 522 may, for example, divide a first clock signal having a frequency of 7.9 gigahertz to generate second clock signals CK2_5 to CK2_8. In other words, the first frequency divider 521 and the second frequency divider 522 may respectively correspond to different phase-locked loop circuits providing different first clock signals.

[0063] In this embodiment, the first frequency divider 521 is coupled to multiplexers 530, 551-554. The first frequency divider 521 provides second clock signals CK2_1 and CK2_2 to multiplexer 530. The first frequency divider 521 provides second clock signal CK2_2 to multiplexer 551. The first frequency divider 521 provides second clock signal CK2_3 to multiplexers 552 and 553. The first frequency divider 521 provides second clock signal CK2_4 to multiplexer 554. The second frequency divider 522 is coupled to multiplexers 540, 551-554. The second frequency divider 522 provides second clock signal CK2_5 to multiplexer 551. The second frequency divider 522 provides second clock signal CK2_6 to multiplexers 540 and 552. The second frequency divider 522 provides second clock signal CK2_7 to multiplexer 553. The second frequency divider 522 provides the second clock signal CK2_8 to the multiplexer 554.

[0064] In this embodiment, the clock phase control circuit 500 may, for example, be located in the chip performing image processing functions. Multiplexer 540 may, for example, output one of the second clock signals CK2_1, CK2_2, and CK2_6 according to selection signal 5032, as the core clock signal CK3. Multiplexer 551 may, for example, output the second clock signals CK2_2 and CK2_5 according to selection signal 5033, as the clock signal CK4. Clock signal CK4 may, for example, be provided in the data transceiver circuit of the system-on-a-chip. Multiplexer 552 may, for example, output the second clock signals CK2_3 and CK2_6 according to selection signal 5034, as the clock signal CK5. Clock signal CK5 may, for example, be provided in the relevant system circuitry of the system-on-a-chip. Multiplexer 553 may, for example, output the second clock signals CK2_3 and CK2_7 according to selection signal 5035, as the clock signal CK6. Clock signal CK6 may, for example, be provided in the image decoding circuit of the system-on-a-chip. The multiplexer 554 can, for example, output second clock signals CK2_4 and CK2_8 as clock signal C7 based on the selection signal 5036. The clock signal CK7 can, for example, be provided in the image encoding circuit in the system chip.

[0065] In this embodiment, when the register circuit 512 receives at least one of the interrupt signals, a first overcurrent alarm signal 501 and a second overcurrent alarm signal 502, the register circuit 512 can output a control signal 506 to the state machine circuit 511. The state machine circuit 511 can output selection signals 5031 and 5032 to multiplexers 530 and 540 according to the control signal 506, and output frequency division signals 5041 and 5042 to a first frequency divider 521 and a second frequency divider 522, so that the first frequency divider 521 can output second clock signals CK2_1 and CK2_2 to multiplexer 530 according to the frequency division signal 5041, and the second frequency divider 522 can output a second clock signal CK2_6 to multiplexer 540 according to the frequency division signal 5042. In this embodiment, the second clock signals CK2_1, CK2_2, and CK2_6 have different clock frequencies. For example, the second clock signal CK2_1 has the highest clock frequency, the second clock signal CK2_6 has the lowest clock frequency, and the clock frequency of the second clock signal CK2_2 is between that of the second clock signals CK2_1 and CK2_6. In this regard, the state machine circuit 512 can control multiplexers 530 and 540 to sequentially switch the output of the second clock signals CK2_1, CK2_2, and CK2_6 as the core clock signal CK3, thereby gradually reducing the clock frequency of the core clock signal CK3. Alternatively, the state machine circuit 511 can control multiplexers 530 and 540 to directly switch from outputting the second clock signal CK2_1 to outputting the second clock signal CK2_6 as the core clock signal CK3, thereby immediately reducing the clock frequency of the core clock signal CK3.

[0066] Similarly, when register circuit 512 receives at least one of the interrupt signals, first overcurrent alarm signal 501 and second overcurrent alarm signal 502, state machine circuit 511 can control multiplexers 551-554 respectively, so that multiplexers 551-554 can switch their output clock signals respectively. Therefore, the clock stage control circuit 500 of this embodiment can automatically adjust the clock frequency of the processing core and other related circuits of the system chip in response to the overcurrent event of the system chip, so as to achieve effective overcurrent protection for the overall circuit of the system chip.

[0067] Furthermore, in this embodiment, when the clock phase control circuit 500 is not operating under overcurrent protection, it can also be used when the phase-locked loop circuit corresponding to the first frequency divider 521 needs to be reprogrammed. In this case, the controller 510 can control multiplexers 530, 540, and 551-554 respectively, so that multiplexers 530, 540, and 551-554 respectively output multiple second clock signals provided by the second frequency divider 522. Moreover, after the phase-locked loop circuit of the first frequency divider 521 is restarted and re-locks the voltage-controlled oscillator frequency to a stable state, the controller 510 can again control multiplexers 530, 540, and 551-554 respectively to restore the output of multiple second clock signals provided by the first frequency divider 521.

[0068] In summary, the clock phase control circuit and clock phase control method of the present invention can adjust the clock frequency of the core clock signal provided to the processing core of the system chip according to the interrupt signal provided by the system chip, so as to effectively avoid system shutdown, abnormal operation of the processing core, or even chip damage caused by overcurrent events. Furthermore, the clock phase control circuit and clock phase control method of the present invention can provide an overcurrent protection mechanism with two frequency reduction methods, so as to effectively reduce the performance of the processing core under different overcurrent events.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock phase control circuit, characterized by, The clock phase control circuit is disposed in a system on chip, the system on chip includes an artificial intelligence accelerator chip, The clock phase control circuit includes: a frequency divider receiving a first clock signal and outputting a plurality of second clock signals; a multiplexer receiving the plurality of second clock signals and outputting one of the plurality of second clock signals; and a controller coupled to the frequency divider and the multiplexer, wherein when the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal, and the multiplexer outputs another one of the plurality of second clock signals according to the selection signal, the interrupt signal indicating that the current or power provided to the system or core is abnormal because it is greater than a preset threshold; The controller outputs a frequency division signal to the frequency divider, so that the frequency divider outputs the plurality of second clock signals according to the frequency division signal, and the plurality of second clock signals have different clock frequencies; wherein the multiplexer, when outputting another one of the plurality of second clock signals according to the selection signal, includes sequentially outputting at least a part of the plurality of second clock signals in the form of high clock frequency to low clock frequency and multi-stage switching, during which the system on chip maintains computing capability; The interrupt signal includes at least one of a first overcurrent alarm signal and a second overcurrent alarm signal, wherein the first overcurrent alarm signal is in response to the average current of the system on chip being higher than a first current threshold, wherein the second overcurrent alarm signal is in response to the instantaneous current of the system on chip being higher than a second current threshold; When the interrupt signal is the second overcurrent alarm signal, the multiplexer adopts a way of less switching stage and higher frequency reduction ratio to reduce the clock frequency of the core clock signal provided to the system on chip.

2. The clock phase control circuit of claim 1, wherein when the controller receives the first overcurrent alarm signal, the multiplexer sequentially outputs at least a part of the plurality of second clock signals in the form of high clock frequency to low clock frequency and multi-stage switching during a first response period, when the controller receives the second overcurrent alarm signal, the multiplexer sequentially outputs at least a part of the plurality of second clock signals in the form of high clock frequency to low clock frequency and multi-stage switching during a second response period, wherein the length of the first response period is greater than the length of the second response period.

3. The clock phase control circuit of claim 2, wherein, The switching priority of the second overcurrent alarm signal is higher than that of the first overcurrent alarm signal.

4. The clock phase control circuit of claim 1, wherein, When the interrupt signal is removed, the multiplexer sequentially outputs the at least a part of the plurality of second clock signals in the form of low clock frequency to high clock frequency and multi-stage switching during a recovery period.

5. The clock phase control circuit of claim 1, wherein, The controller includes: a state machine circuit coupled to the frequency divider and the multiplexer; and a register circuit coupled to the state machine circuit, wherein when the register circuit receives the interrupt signal, the register circuit outputs a control signal to the state machine circuit, the state machine circuit outputs the selection signal to the multiplexer according to the control signal, and outputs the frequency division signal to the frequency divider, so that the frequency divider outputs the plurality of second clock signals according to the frequency division signal, and the multiplexer changes the output according to the selection signal.

6. The clock phase control circuit of claim 5, wherein, The register circuit pre-writes frequency modulation setting parameters, and the register circuit generates the control signal according to the interrupt signal and the frequency modulation setting parameters.

7. The clock phase control circuit of claim 5, wherein, The state machine circuit outputs a state signal to the register circuit according to the switching state of the current clock signal.

8. The clock phase control circuit of claim 1, wherein, Further comprising: Another frequency divider coupled to the controller and outputting another second clock signal; Another multiplexer coupled to the controller, the output of the multiplexer, and the other frequency divider, and receiving the other second clock signal, wherein the controller further outputs another selection signal to the other multiplexer, so that the other multiplexer decides to output one of the plurality of second clock signals and the other second clock signal according to the other selection signal.

9. A clock phase control method, characterized by, Comprising: Receiving a first clock signal by a frequency divider, and outputting a plurality of second clock signals; Receiving the plurality of second clock signals by a multiplexer, and outputting one of the plurality of second clock signals; When a controller receives an interrupt signal, outputting a selection signal to the multiplexer by the controller according to the interrupt signal, the interrupt signal indicating that the current current or power provided to the system or core is greater than a preset threshold value and an abnormality occurs; Outputting another one of the plurality of second clock signals by the multiplexer according to the selection signal; And Outputting a frequency division signal to the frequency divider by the controller, so that the frequency divider outputs the plurality of second clock signals according to the frequency division signal, wherein the plurality of second clock signals have different clock frequencies; wherein the frequency divider, the multiplexer and the controller are arranged in a system on chip, the system on chip comprising an artificial intelligence accelerator chip, wherein the step of outputting another one of the plurality of second clock signals by the multiplexer according to the selection signal comprises sequentially outputting at least part of the plurality of second clock signals in the form of high clock frequency to low clock frequency and multi-stage switching by the multiplexer, in which process the system on chip maintains computing power; The interrupt signal comprises at least one of a first overcurrent alarm signal and a second overcurrent alarm signal, wherein the first overcurrent alarm signal is in response to the average current of the system on chip being higher than a first current threshold value, wherein the second overcurrent alarm signal is in response to the instantaneous current of the system on chip being higher than a second current threshold value; When the interrupt signal is the second overcurrent alarm signal, the multiplexer adopts a way of fewer switching stages and higher frequency reduction ratio to reduce the clock frequency of the core clock signal provided to the system on chip.

10. The clock phase control method of claim 9, wherein, The step of sequentially outputting at least a portion of the plurality of second clock signals in a form of a multi-stage switching from the high clock frequency to the low clock frequency by the multiplexer comprises: sequentially outputting at least a portion of the plurality of second clock signals in a form of a multi-stage switching from the high clock frequency to the low clock frequency by the multiplexer during a first response period when the controller receives the first overcurrent alarm signal; and sequentially outputting at least a portion of the plurality of second clock signals in a form of a multi-stage switching from the high clock frequency to the low clock frequency by the multiplexer during a second response period when the controller receives the second overcurrent alarm signal, wherein a time length of the first response period is greater than a time length of the second response period.

11. The clock phase control method of claim 10, wherein, The switching priority of the second overcurrent alarm signal is higher than that of the first overcurrent alarm signal.

12. The clock phase control method of claim 9, wherein, Further comprising: sequentially outputting the at least a portion of the plurality of second clock signals in a form of a multi-stage switching from the low clock frequency to the high clock frequency by the multiplexer during a recovery period when the interrupt signal is released.

13. The clock phase control method of claim 9, wherein, The controller comprises a state machine circuit and a register circuit, and when the register circuit receives the interrupt signal, the register circuit outputs a control signal to the state machine circuit, the state machine circuit outputs the selection signal to the multiplexer and the frequency division signal to the frequency divider according to the control signal, so that the frequency divider outputs the plurality of second clock signals according to the frequency division signal, and the multiplexer changes the output according to the selection signal.

14. The clock phase control method of claim 13, wherein, The register circuit is pre-written with a frequency modulation setting parameter, and the register circuit generates the control signal according to the interrupt signal and the frequency modulation setting parameter.

15. The clock phase control method of claim 13, wherein, The state machine circuit outputs a state signal to the register circuit according to the switching state of the current clock signal.

16. The clock phase control method of claim 9, wherein, Further comprising: outputting another second clock signal by another frequency divider; coupling an output terminal of the multiplexer to another multiplexer and receiving the another second clock signal by the another multiplexer; and outputting another selection signal to the another multiplexer by the controller, so that the another multiplexer decides to output one of the plurality of second clock signals and the another second clock signal according to the another selection signal.

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