Semiconductor structure and method for forming the same

Abstract

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to expose the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited extending into the opening. The isolation layer has a vertical portion and a first horizontal portion located in the opening and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, wherein the vertical portion of the isolation layer remains in the opening. Embodiments of the present invention also relate to semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] In the formation of integrated circuits, integrated circuit devices such as transistors and memory cells are formed on a semiconductor substrate. Metal pads are usually formed to be electrically connected to the integrated circuit, so that solder balls, metal bumps, wire bonding pillars, etc. can be formed on the metal pads to electrically couple external devices to the integrated circuit. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: depositing a first dielectric layer covering an electrical connector; depositing a second dielectric layer above the first dielectric layer; performing a first etching process to etch through the second dielectric layer and the first dielectric layer, wherein an opening is formed in the first dielectric layer and the second dielectric layer to expose the electrical connector; performing a second etching process to laterally etch the first dielectric layer and the second dielectric layer; depositing a first isolation layer extending into the opening, wherein the first isolation layer includes a first vertical portion and a first horizontal portion located in the opening and a second horizontal portion overlapping the second dielectric layer; and performing a first anisotropic etching process on the first isolation layer, wherein the first vertical portion of the first isolation layer remains in the opening.

[0004] Another embodiment of the present invention provides a semiconductor structure, comprising: an electrical connector; a plurality of dielectric layers covering at least one edge portion of the electrical connector, wherein the plurality of dielectric layers include: a first dielectric layer; a second dielectric layer located above or below the first dielectric layer; and a first isolation layer located above the first dielectric layer and the second dielectric layer; and a second isolation layer overlapping the electrical connector, wherein the second isolation layer includes side walls contacting the side walls of the first dielectric layer, the second dielectric layer, and the first isolation layer, and wherein the second isolation layer includes: a first portion overlapping the first isolation layer, wherein the first portion has a first width; and a second portion overlapping the first isolation layer, wherein the second portion has a second width different from the first width.

[0005] Another embodiment of the present invention provides a semiconductor structure, comprising: a metal pad; a plurality of oxide layers covering at least one edge portion of the metal pad; a first nitride layer overlapping the plurality of oxide layers, wherein edges of the plurality of oxide layers are laterally recessed from corresponding edges of the first nitride layer in a lateral direction toward an edge of the metal pad; and a second nitride layer located in an opening in the plurality of oxide layers and the first nitride layer, wherein the second nitride layer is in physical contact with the metal pad and the first nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view of a package assembly according to some embodiments is shown.

[0008] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B A cross-sectional view is shown of an intermediate stage in the formation of an isolation structure in accordance with some embodiments.

[0009] Figures 10 to 13 A cross-sectional view of an isolation structure in a package assembly according to some embodiments is shown.

[0010] Fig.14 A process flow for forming an isolation structure in a package assembly according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] A package assembly including a metal pad and an isolation structure and a method for forming the same are provided. According to some embodiments of the present invention, a metal pad is formed above an interconnect structure of a package assembly. Multiple dielectric layers are deposited and then patterned to expose the metal pad. An isotropic etching process may be performed to recess a material that is lighter (less dense) than a dense material in a plurality of dielectric layers. An isolation layer having good moisture isolation capability is deposited. A protective layer is then deposited on the isolation layer. The isolation layer and the protective layer are patterned to leave portions on the sidewalls of the plurality of dielectric layers. The protective layer prevents the isolation layer from being thinned during patterning and subsequent cleaning processes. In addition, the isolation layer can have a greater thickness on the sidewalls of the lighter dielectric layer and thus provide better isolation for the lighter dielectric layer. The embodiments discussed herein will provide examples to enable the subject matter of the present invention to be made or used, and those of ordinary skill in the art will readily understand modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A, Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B 1 shows a cross-sectional view of an intermediate stage in the formation of a package assembly and an isolation structure on a conductive pad in the package assembly according to some embodiments of the present invention. The corresponding process is also schematically reflected in FIG. Fig.14 In the process flow 200 shown.

[0015] refer to Figure 1 , forming a package assembly 10. According to some embodiments, the package assembly 10 is a device wafer, which includes an integrated circuit (having active devices, such as transistors, memory devices, etc.). The device wafer also includes a plurality of identical device dies 10'. According to optional embodiments, the package assembly 10 includes an interposer wafer, a reconstructed package including a plurality of device dies, and the like. In the subsequent discussion, the device die / wafer is used as an example of the package assembly 10, and the package assembly 10 may also be other types of package assemblies.

[0016] According to some embodiments of the present invention, the package assembly 10 includes a semiconductor substrate 24 and components formed at the surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include the following materials: crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or III-V compound semiconductors (such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. Shallow trench isolation (STI) regions 25 may be formed in the semiconductor substrate 24 to isolate different regions and devices in the semiconductor substrate 24. Although not shown, vias may (or may not) be formed to extend into the semiconductor substrate 24, wherein the vias are used to electrically interconnect components on opposite sides of the wafer 10.

[0017] According to some embodiments of the present invention, wafer 10 includes integrated circuit devices 26 formed at a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown here. According to alternative embodiments, wafer 10 is used to form an interposer (without active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0018] According to some embodiments, the integrated circuit device 26 may include memory cells 26A and 26B and a transistor (not shown). The memory cells 26A and 26B may be symmetrical to each other with respect to the center line of the drain region 28B. Therefore, the structure of the memory cell 26A is discussed below, and the memory cell 26B having the same structure as the memory cell 26A is not discussed. The memory cell 26A includes a source region 28A and a drain region 28B. The drain region 28B is a common drain region shared by the memory cells 26A and 26B. The gate dielectric 30 is formed above the substrate 24. According to some embodiments, the gate dielectric 30 includes silicon oxide, a high-k dielectric material (such as HfO2, La2O3, etc.) or a composite layer thereof. The select gate 32 is formed above the gate dielectric 30. The select gate 32 may be formed of polysilicon, a metal, a metal alloy, etc. A dielectric layer 33 and a dielectric mask 34 are formed above the select gate 32.

[0019] The control gate 36 is formed above the semiconductor substrate 24 and is separated from the semiconductor substrate 24 and the gate stack 30 / 32 / 33 / 34 by the stacking stack 38. The control gate 36 is formed of a conductive material such as a metal or metal alloy, polysilicon, etc. The stacking stack 38 includes a dielectric layer 38A, a charge trapping layer 38B, and a dielectric layer 38C. According to some embodiments, the dielectric layers 38A and 38C are formed of silicon oxide, which is used to electrically isolate the charge trapping layer 38B from the substrate 24 and the selection gate 32. The charge trapping layer 38B can be formed of silicon nitride, which can hold charges. The charge trapping layer 38B can also be formed of a conductive material such as polysilicon. Gate spacers 40 are formed on the sidewalls of the control gate 36 and the selection gate 32. The source contact plug 42A and the drain contact plug 42B are connected to the source region 28A and the drain region 28B, respectively. A contact etch stop layer (CESL) 45 and an interlayer dielectric 46 are also shown.

[0020] Contact etch stop layer (CESL) 45 and interlayer dielectric layer (ILD) 46 fill the space between the gate stacks of transistors and memory cells in integrated circuit device 26. According to some embodiments, CESL 45 is formed of silicon oxide, silicon nitride, etc. ILD 46 may be formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), low-k dielectric, etc. ILD 46 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present invention, ILD 46 is formed using a deposition process such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0021] Contact plugs 42A and 42B are formed in ILD 46 and are used to electrically connect source region 28A and drain region 28B to the metal lines and vias above, respectively. According to some embodiments of the present invention, contact plugs 42A and 42B are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plugs 42A and 42B may include forming contact openings in ILD 46, filling the contact openings with a conductive material, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surfaces of contact plugs 42A and 42B flush with the top surface of ILD 46.

[0022] The interconnect structure 48 is located above the ILD 46 and the contact plugs 42A and 42B. The interconnect structure 48 includes metal lines 50 and vias 52, which are formed in a dielectric layer 54 (also referred to as an intermetallic dielectric layer (IMD)). The metal lines 50 at the same level are collectively referred to as metal layers below. According to some embodiments of the present invention, the interconnect structure 48 includes a plurality of metal layers, which include metal lines 50 interconnected by vias 52. The metal lines 50 and vias 52 may be formed of copper, copper alloys, Ti, TiN, Ta, TaN, and composite layers thereof. According to some embodiments of the present invention, the dielectric layer 54 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be less than about 3.0. The dielectric layer 54 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0023] The formation of metal lines 50 and vias 52 in dielectric layer 54 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 54, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, trenches and via openings are formed in the dielectric layer, and the via openings are located below the trenches and connected to the trenches. Conductive materials are then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0024] Passivation layer 56 (sometimes referred to as passivation 1 or pass-1) may be formed over interconnect structure 48. According to some embodiments, passivation layer 56 is formed of a non-low-k dielectric material having a dielectric constant greater than that of silicon oxide. Passivation layer 56 may be formed of or include an inorganic dielectric material, which may include a material selected from, but not limited to, silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), oxycarbide (SiOC), silicon carbide (SiC), and the like, combinations thereof, and multilayers thereof.

[0025] In subsequent processes, through-holes 58 and electrical connectors 60 are formed. According to some embodiments, electrical connectors 60 are formed of or include a homogeneous material such as aluminum, aluminum copper (AlCu), copper, etc. Electrical connectors 60 may also have a composite structure including a conductive pad 60A ( Figure 2A ) and a glue layer 60B located above the conductive pad 60A. The conductive pad 60A may be formed of or include copper, aluminum, aluminum copper, nickel, palladium, gold, etc., their alloys and their multilayers. The glue layer 60B may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0026] According to some embodiments, the formation of the through hole 58 and the electrical connector 60 includes forming a through hole in the passivation layer 68 using a single damascene process. Next, a conductive layer is deposited, and then an etching process is performed to pattern the conductive layer and form the electrical connector 60. According to an optional embodiment, the formation of the through hole 58 and the electrical connector 60 includes etching the passivation layer 56 to form a through hole opening, depositing a blanket metal seed layer extending into the through hole opening, forming a patterned plating mask (such as a photoresist) to expose the through hole opening, and then performing a plating process to plate the through hole 58 and the electrical connector 60. The blanket metal seed layer may include a copper layer, or a titanium layer and a copper layer located above the titanium layer. The plating process may include an electrochemical plating process. The plating mask is then removed, and then an etching process is performed to remove the portion of the metal seed layer previously covered by the plating mask.

[0027] After forming electrical connector 60, multiple dielectric layers are deposited, with portions of the dielectric layers forming portions of isolation structures 66. Each isolation structure 66 is used to isolate one of electrical connectors 60. Isolation structures 66 are used to isolate harmful substances, such as hydrogen, moisture, etc., from penetrating into underlying components such as memory cell 26 and low-k dielectric layers. For example, memory cell 26 is sensitive to damage caused by hydrogen and moisture. Low-k dielectric layer 54 in interconnect structure 48 also forms a good penetration path for hydrogen and moisture, so that components such as metal line 50, via 52, and device 26 within or below the interconnect structure may be damaged. Therefore, isolation structure 66 is formed to have improved resistance to penetration of harmful substances. Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B An example formation process of the isolation structure 66 is shown in Figure 1 The parts shown in the dashed boxes are shown, while other parts are not copied in these figures.

[0028] Figure 2A and Figure 2B The cross-sectional view and top view respectively show the formation of multiple dielectric layers and the formation of an etch mask. Figure 2A , forming an electrical connection member 60 including a conductive pad 60A and an adhesive layer 60B. The corresponding process is shown as follows Fig.14 Process 202 in process flow 200 is shown. The formation process may include a deposition and patterning process or a plating process as described above. According to some embodiments, glue layer 60B is located above and in contact with conductive pad 60A, and the edge of glue layer 60B is flush with the corresponding edge of conductive pad 60A. Glue layer 60B is also called a barrier layer or an etch stop layer.

[0029] Then, a plurality of dielectric layers 68, 70, 72 and 74 are deposited. The corresponding process is shown as follows. Fig.14 Process 204 in process flow 200 is shown. A passivation layer 68 (sometimes referred to as "passivation 2" or "pass-2") is deposited on the electrical connector 60 and may extend over the top surface and sidewalls of the electrical connector 60. The passivation layer 68 is formed as a blanket layer. According to some embodiments, the passivation layer 68 is formed of or includes an inorganic dielectric material, which may include, but is not limited to, silicon oxide, silicon oxycarbide, silicon carbide, and the like. For example, the passivation layer 68 may be formed of silicon oxide using tetraethyl orthosilicate (TEOS) as a precursor. The material of the passivation layer 68 may be the same as or different from the material of the passivation layer 56. The deposition process may be performed by a conformal deposition process such as atomic layer deposition (ALD), CVD, and the like. Thus, the vertical portion and the horizontal portion of the passivation layer 68 have the same thickness or substantially the same thickness, for example, with a variation of less than about 20% or less than about 10%. The bottom surface of the passivation layer 68 may be the same as the bottom surface of the passivation layer 56. Figure 1 The top surface of passivation layer 56 is shown in physical contact. According to some embodiments, passivation layer 68 has a thickness T1 in a range between about 0.18 μm and about 0.22 μm.

[0030] Next, a dielectric layer 70 is deposited. According to some embodiments, the dielectric layer 70 is deposited using a non-conformal deposition process, which may include high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD), and the like. The deposited material may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, and the like. According to some embodiments in which the dielectric layer 70 is formed of or includes silicon oxide, silicon-containing precursors such as silane, disilane, dichlorosilane, and the like may be used. Due to the non-conformal deposition process, the top surface of the dielectric layer 70 has a smaller topology (smoother, less undulating) than the top surface of the dielectric layer 68. According to some embodiments, the thickness T2 of the dielectric layer 70 is in a range between about 0.81 μm and about 0.99 μm.

[0031] Dielectric layer 72 is formed over dielectric layer 70. According to some embodiments, dielectric layer 72 is deposited using a non-conformal deposition process or a conformal deposition process, which may include ALD, CVD, sub-atmospheric pressure chemical vapor deposition (SACVD), PECVD, etc. The deposited material may include undoped silicate glass (USG), silicon oxide, silicon oxycarbide, silicon carbide, etc. According to some embodiments, a thickness T3 of dielectric layer 72 is in a range between about 0.72 μm and about 0.88 μm.

[0032] A dielectric layer 74 is further deposited on top of the dielectric layer 72. According to some embodiments, the dielectric layer 74 is deposited using a non-conformal deposition process or a conformal deposition process, which may include ALD, CVD, low pressure chemical vapor deposition (LPCVD), PECVD, etc. The deposited material has good isolation capabilities to prevent harmful substances (such as hydrogen and moisture) from penetrating through. Therefore, the dielectric layer 74 is also referred to as an isolation layer. The dielectric layer 74 may include silicon nitride, silicon oxynitride, etc. According to some embodiments, the thickness T4 of the dielectric layer 74 is in a range between about 0.54 μm and about 0.66 μm. Throughout the specification, multiple dielectric layers 68, 70, 72, and 74 are collectively referred to as dielectric stacks 62.

[0033] It should be understood that the above-described dielectric layers 68, 70, 72, and 74 and methods of forming the same in dielectric stack 62 are examples, and that the present invention contemplates different materials and different methods of forming. Moreover, dielectric stack 62 may include more or fewer layers, and / or may have layers formed in a different order than that discussed.

[0034] According to some embodiments, the dielectric layers in dielectric stack 62 may be formed of the same material or different materials from each other, and may have the same density or different densities from each other. For example, assuming that dielectric layer 70 is formed of silicon oxide using HDPCVD, and dielectric layers 68 and 72 are formed of silicon oxide (using TEOS) and USG using CVD, respectively, dielectric layer 70 may have a higher density than dielectric layers 68 and 72. According to other embodiments, the relative density and materials of the dielectric layers in dielectric stack 62 may have any other combination. For example, according to some embodiments, the density of dielectric layer 68 may be greater than or less than the density of dielectric layers 70 and 72. Moreover, the materials of some dielectric layers in dielectric stack 62 (such as layers 68, 70, and 72) may be the same as or different from each other. For example, these layers may be formed of the same material, silicon oxide (although different methods may be used to form them), or may be formed of similar materials such as silicon oxide and USG.

[0035] An etch mask 76 is formed over the dielectric stack 62 and an opening 64 is formed directly over the electrical connector 60. The corresponding process is shown as follows. Fig.14 Process 206 of process flow 200 is shown. According to some embodiments, etch mask 76 is formed of or includes photoresist. A hard mask may or may not be formed under the photoresist. Figure 2B A top view of the electrical connector 60 and the opening 64 is shown. The electrical connector 60 extends laterally beyond the edge of the opening 64.

[0036] refer to Figure 3A and Figure 3B , an etching process 80 is performed to etch through the dielectric stack 62 so that the opening 64 extends into the dielectric stack 62. The corresponding process is shown as Fig.14 Process 208 in process flow 200 is shown. Figure 3A and Figure 3B A cross-sectional view and a top view are shown, respectively. According to some embodiments, etching process 80 is performed by a plurality of reactive ion etching (RIE) processes using different etching gases. The etching gas is selected depending on the material of the dielectric layers (such as layers 74, 72, 70, and 68) in dielectric stack 62. For example, when dielectric layer 74 is formed of or includes silicon nitride, a fluorine-containing gas (such as CF4, a mixture of O2 and N2, a mixture of NF3 and O2, SF6, a mixture of SF6 and O2, etc., or a combination thereof, may be used to etch dielectric layer 74. When dielectric layers 72, 70, and 68 are formed of or include silicon oxide, a gas including, for example, SiCONI (a mixture of NF3 and NH3), Certas (a mixture of HF and NH3), etc., or a combination thereof, may be used to etch dielectric layers 72, 70, and 68.

[0037] The etching process 80 is anisotropic, so that the exposed sidewalls of the dielectric layers 74, 72, 70 and 68 are vertical or substantially vertical, for example, the tilt angle α is in the range between about 75 degrees and about 100 degrees. The exposed sidewalls of the dielectric layers 74, 72, 70 and 68 may also be straight (vertical or tilted). The etching process 80 may be performed using the glue layer 60B as an etch stop layer. Therefore, the top surface of the glue layer 60B is exposed after the etching process 80. According to some embodiments, the anisotropic effect is achieved by applying a relatively high bias power (e.g., greater than about 1000 watts). The bias power may also be in the range between about 800 watts and about 1200 watts.

[0038] Figure 4A and Figure 4B The cross-sectional view and the top view of the isotropic etching process 82 are shown respectively. The corresponding process is shown as follows Fig.14 Process 210 in process flow 200 is shown. Etching process 82 may also use glue layer 60B as an etch stop layer. Etching process 82 is performed using an etching chemistry that corrodes layers in dielectric stack 62 that are easily permeated by harmful substances, but does not corrode anti-permeation layers (such as layer 74) in dielectric stack 62. For example, silicon nitride is more resistant to permeation than silicon oxide. Therefore, the etching gas is selected to have a higher etching rate for materials that are more easily permeated (such as silicon oxide and USG) than for materials that are more resistant to permeation (such as silicon nitride). Depending on the materials and etching gases used in etching process 82, dielectric layer 74 is not recessed laterally, or is substantially not recessed laterally, for example, the lateral recess distance is less than about 0.1 μm. According to an optional embodiment, dielectric layer 74 is also recessed laterally, but the recess distance is less than the recess distance of dielectric layers 68, 70 and 72.

[0039] According to some embodiments, the etching process 82 is performed by a wet etching process. For example, a diluted HF solution may be used. According to an alternative embodiment, the etching process 82 is implemented by a dry etching process, and there is no bias power or a low bias power. According to some embodiments, the etching gas may be selected from a mixture of NF3 and NH3, a mixture of HF and NH3, etc., or a combination thereof.

[0040] The etching is self-adjusted for dielectric layers that are easily penetrated, such as dielectric layers 68, 70, and 72. In the subsequent discussion, it is assumed that dielectric layers 68, 70, and 72 are formed of TEOS oxide (silicon oxide), HDPCVD oxide (silicon oxide), and USG, respectively, but each of these layers can be formed of different materials. Since TEOS oxide layer 68 and USG layer 72 are lighter (less dense) than HDPCVD oxide 70, the etching rate of TEOS oxide layer 68 and USG layer 72 is greater than the etching rate of HDPCVD oxide 70. This causes TEOS oxide layer 68 and USG layer 72 to be more laterally recessed than HDPCVD oxide 70. Materials with lower density are easier to penetrate than materials with higher density. For example, TEOS oxide and USG are easier to penetrate by harmful substances than HDPCVD oxide because their density is lower than HDPCVD oxide. As discussed in subsequent paragraphs, it is advantageous to laterally recess lighter dielectric materials more than denser dielectric materials in forming effective isolation structures.

[0041] According to some embodiments, the etch selectivity value, i.e., the ratio of the etch rate of relatively light dielectric layers 68 and 72 to the etch rate of relatively dense dielectric layer 70, is greater than about 2, and may be in a range between about 2 and about 10. For example, when dilute HF is used, and when dielectric layers 68, 72, and 70 are formed of TEOS oxide, USG, and HDPCVD oxide, respectively, the etch selectivity value may be about 4.

[0042] As a result of etching process 82, dielectric layers 72, 70, and 68 are laterally recessed from the edge of dielectric layer 74 by distances D1, D2, and D3, respectively. According to some embodiments, recess distance D2 is equal to or less than recess distance D1, and may be equal to or less than recess distance D3. Furthermore, depending on the material, distance D1 may be greater than, equal to, or less than distance D3. For example, when dielectric layers 72 and 68 are formed of USG and TEOS oxide, respectively, distance D1 may be greater than distance D3. According to some embodiments, recess distance D1 is in a range between about 50 nm and about 500 nm, recess distance D2 is in a range between about 50 nm and about 400 nm, and recess distance D3 is in a range between about 50 nm and about 500 nm.

[0043] Next, the glue layer 60B is etched through in an etching process 84. The corresponding process is shown as follows. Fig.14 Process 212 of process flow 200 is shown. Etch mask 76 is then removed. Figure 5A and Figure 5BA cross-sectional view and a top view of the resulting structure are shown, respectively. Etching process 84 may be a wet etching process or a dry etching process, and may be an anisotropic etching process or an isotropic etching process, or an etching process having an anisotropic etching effect and an isotropic etching effect. Conductive pad 60A is thus exposed. Since glue layer 60B is thin and its material is significantly different from the material of dielectric layers 68, 70, 72, and 74, dielectric layers 68, 70, 72, and 74 are not recessed. According to some embodiments, the edge of glue layer 60B is laterally recessed from the corresponding edge of dielectric layer 74 by a distance D4, and distance D4 is in a range between about 5 nm and about 300 nm.

[0044] refer to Fig. 6A and Figure 6B , Fig. 6A and Figure 6B The cross-sectional view and top view of the deposited isolation layer 86 are shown respectively. The corresponding process is shown as follows Fig.14 Process 214 in the process flow 200 shown. Isolation layer 86 can be formed of a material that resists penetration. For example, isolation layer 86 can be formed of silicon nitride, silicon oxynitride, etc., or a combination thereof. The materials of isolation layers 86 and 74 can be the same as or different from each other. According to some embodiments, isolation layer 86 is deposited using a selected deposition method so that portions of isolation layer 86 at locations where dielectric layers such as 68 and 72 are more recessed are thicker. Isolation layer 86 also has a substantially (but not completely) conformal profile so that the bottom of isolation layer 86 at the bottom of opening 64 is not significantly thicker than other portions. For example, thicknesses T9 and T10 can be substantially equal to each other, for example, with a variation of less than about 20%. According to some embodiments, isolation layer 86 is formed using PECVD or the like.

[0045] According to some embodiments, portions of isolation layer 86 located on the sidewalls of dielectric layers 74, 72, 70, and 68 have thicknesses T5, T6, T7, and T8, respectively, which may be in a range between about 0.5 μm and about 0.7 μm. According to some embodiments, thickness T7 is less than thicknesses T6 and T8, and may be equal to or greater than thickness T5. Thickness T6 may be greater than, equal to, or less than thickness T8. Thicknesses T6, T7, and T8 may be greater than thickness T5.

[0046] A protective layer 88 is deposited on the isolation layer 86. The corresponding process is shown as follows Fig.14Process 216 in process flow 200 is shown. According to some embodiments, a conformal deposition process such as ALD or CVD is used to deposit protective layer 88. The material of protective layer 88 is different from the material of isolation layer 86, and may be formed of or include silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, etc. The thickness T11 of protective layer 88 may be in a range between about 800 nm and about 1000 nm.

[0047] Fig. 7A and Figure 7B 1 and 2 show a cross-sectional view and a top view of the structure formed after an anisotropic etching process 90 is performed to etch the protective layer 88. The corresponding process is shown as Fig.14 Process 218 in process flow 200 is shown. The etching gas is selected so as to etch the protective layer 88 without etching the isolation layer 86. According to some embodiments, the etching gas includes SiCONi or Certas. The horizontal portion of the protective layer 88 is removed, while the vertical portion is retained to form an etching mask. Figure 7B As shown, the remaining protective layer 88 forms a ring surrounding the remainder of the opening 64 .

[0048] Next, refer to Fig. 8A and Figure 8B , a further anisotropic etching process 91 is performed to remove the exposed horizontal portion of the isolation layer 86, so that the conductive pad 60A is exposed. The corresponding process is shown as follows Fig.14 Process 220 in process flow 200 is shown. Protective layer 88 is used as an etching mask so that at the bottom of opening 64, isolation layer 86 remains with a horizontal portion, and the edge of isolation layer 86 is flush with the corresponding edge of protective layer 88. Using protective layer 88 as an etching mask can protect the vertical portion of isolation layer 86 from being thinned. According to some embodiments, the etching gas includes a fluorine-containing gas, such as CF4, a mixture of O2 and N2, a mixture of NF3 and O2, SF6, a mixture of SF6 and O2, etc. According to some embodiments, the lateral dimension W1 of opening 64 is greater than about 50 μm.

[0049] In a subsequent process, conductive feature 92 may be formed to extend into opening 64, such as Fig. 9A and Fig. 9B The corresponding process is shown as Fig.14Process 222 in process flow 200 shown. According to some embodiments, conductive feature 92 includes wire bonding column 92A formed by wire bonding, and bonding wire 92B attached to wire bonding column 92A. According to an alternative embodiment, conductive feature 92 includes metal bumps, such as copper bumps. According to another alternative embodiment, conductive feature 92 includes solder balls. Wafer 10 can also be separated in a die sawing process so that wafer 10 ( Figure 1 The formation of the conductive member 92 may be performed before or after the singulation process.

[0050] like Fig. 9A As shown, dielectric layers 72, 70 and 68 are respectively recessed from the corresponding edges of dielectric layer 74 by the recess distances D1, D2 and D3 discussed in the previous paragraphs. Distances D1, D2 and D3 are also the widths of the portions of dielectric layers 72, 70 and 68 that overlap dielectric layer 74. Thicknesses T6 and T8 are also advantageously greater than thickness T7 and thickness T5'. Since 72 of dielectric layers 68 are lighter and are susceptible to penetration by harmful substances, the penetration path is shown by arrow 94, making the portion of isolation layer 86 located on the sidewall of the dielectric layer susceptible to penetration thicker can effectively reduce the penetration of harmful substances. In addition, protective layer 88 also helps to reduce penetration, and in conventional structures, since protective layer 88 is not formed, this partial protection is not provided.

[0051] Fig.10 An embodiment is shown where package component 10' is joined to package component 96. According to some embodiments, conductive features 92 are solder areas (or metal bumps) that connect to electrical connectors 97 in package component 96. Underfill 98 is dispensed into the gap between package components 10' and 96.

[0052] Figures 11 to 13 Some embodiments of the present invention are shown Fig. 9A and Fig.10 Some details of the isolation structure 66 in FIG. Fig. 9A and Fig.10 The conductive components 92, packaging components 96, bottom fill 98, etc. are not shown. Figures 11 to 13 , but these components may also be present. Fig.11 , in the etching process 90( Fig. 7A ), the conductive pad 60A is also recessed by an over-etching process, so that a groove 101 extending into the conductive pad 60A is formed. The groove 101 has a depth D5, which may be greater than about 0.01 μm and may be in a range between about 0.005 μm and about 0.02 μm. The groove 101 may or may not be formed in Fig. 9A and Figures 11 to 13In the structure shown in , and therefore shown in these figures using dashed lines 102 to represent the bottom and side walls of the groove 101.

[0053] Fig.12 The corners of dielectric layer 74 in region 104 are shown to be rounded, which may be caused by etching process 90 ( Fig. 7A ) and the similarity of the materials of the dielectric layer 74 and the isolation layer 86. Fig.13 An embodiment is shown in which the portion of the isolation layer 86 located on top of the dielectric layer 74 remains in the final structure. Thus, the isolation layer 86 and the dielectric layer 74 are connected to each other. Fig.12 and Fig.13 In each of , the groove 101 may or may not be formed.

[0054] Embodiments of the present invention have several advantageous features. In conventional isolation structures, a single layer is formed on the sidewalls of a dielectric layer. In embodiments of the present invention, a double layer isolation structure is formed to improve isolation capability. The lateral recessing of the less dense dielectric layer provides a self-adjusting capability to automatically provide greater isolation capability for the less dense dielectric layer. Since the penetration path in the less dense dielectric layer is connected to the underlying components (such as memory cells) that are susceptible to damage by harmful substances, the reliability of the resulting product is improved.

[0055] According to some embodiments of the present invention, a method includes depositing a first dielectric layer covering an electrical connector; depositing a second dielectric layer over the first dielectric layer; performing a first etching process to etch through the second dielectric layer and the first dielectric layer, wherein an opening is formed in the first dielectric layer and the second dielectric layer to expose the electrical connector; performing a second etching process to laterally etch the first dielectric layer and the second dielectric layer; depositing a first isolation layer extending into the opening, wherein the first isolation layer includes a first vertical portion and a first horizontal portion located in the opening and a second horizontal portion overlapping the second dielectric layer; and performing a first anisotropic etching process on the first isolation layer, wherein the first vertical portion of the first isolation layer remains in the opening. In an embodiment, the method also includes depositing a protective layer over the first isolation layer, wherein the protective layer extends into the opening; and performing a second anisotropic etching process on the protective layer, wherein a second vertical portion of the protective layer remains in the opening, and the first anisotropic etching process is performed using the second vertical portion as a portion of an etching mask. In an embodiment, the method also includes forming a conductive feature extending into the opening and contacting the electrical connector, wherein the conductive feature contacts the second vertical portion of the protective layer. In an embodiment, the first etching process includes an anisotropic etching process, and the second etching process includes an isotropic etching process. In an embodiment, the method further includes depositing a second isolation layer over the second dielectric layer before the first etching process, wherein the second isolation layer is further etched in the first etching process to form an opening. In an embodiment, in the second etching process, the second isolation layer is not etched. In an embodiment, in the second etching process, the first of the first dielectric layer and the second dielectric layer has a first etching rate, and the second of the first dielectric layer and the second dielectric layer has a second etching rate different from the first etching rate, and the ratio of the first etching rate to the second etching rate is greater than about 2. In an embodiment, the first of the first dielectric layer and the second dielectric layer includes silicon oxide deposited using TEOS as a precursor, and the second of the first dielectric layer and the second dielectric layer includes silicon oxide deposited using high-density plasma chemical vapor deposition. In an embodiment, after the first anisotropic etching process, the top edge of the first vertical portion of the first isolation layer is flush with or lower than the top of the opening. In an embodiment, after the first anisotropic etching process, the first isolation layer includes a portion located outside the opening, and wherein the portion overlaps the second dielectric layer.

[0056] According to some embodiments of the present invention, a structure includes: an electrical connector; a plurality of dielectric layers covering at least one edge portion of the electrical connector, wherein the plurality of dielectric layers include a first dielectric layer; a second dielectric layer located above or below the first dielectric layer; and a first isolation layer located above the first dielectric layer and the second dielectric layer; and a second isolation layer overlapping the electrical connector, wherein the second isolation layer includes a sidewall that contacts the sidewalls of the first dielectric layer, the second dielectric layer, and the first isolation layer, and wherein the second isolation layer includes: a first portion overlapping the first isolation layer, wherein the first portion has a first width; and a second portion overlapping the first isolation layer, wherein the second portion has a second width different from the first width. In an embodiment, the first dielectric layer has a first density, and the second dielectric layer has a second density greater than the first density. In an embodiment, the first dielectric layer and the second dielectric layer include the same elements. In an embodiment, the second isolation layer has a vertical foot and a horizontal foot connected to the bottom end of the vertical foot, and wherein the structure also includes a protective layer overlapping the vertical foot. In an embodiment, the structure further comprises a conductive member located above and in contact with the electrical connector, wherein the conductive member further contacts the protection layer and the leveling foot. In an embodiment, the second isolation layer comprises a portion overlapping the second dielectric layer.

[0057] According to some embodiments of the present invention, a structure includes: a metal pad; a plurality of oxide layers covering edge portions of the metal pad; a first nitride layer overlapping the plurality of oxide layers, wherein edges of the plurality of oxide layers are laterally recessed from respective edges of the first nitride layer toward edges of the metal pad in a lateral direction; and a second nitride layer located in an opening in the plurality of oxide layers and the first nitride layer, wherein the second nitride layer is in physical contact with the metal pad and the first nitride layer. In an embodiment, the second nitride layer has a top, and wherein a lower portion of the top is increasingly wider than a corresponding upper portion of the top. In an embodiment, edges of the plurality of oxide layers are laterally recessed from respective edges of the first nitride layer by different distances. In an embodiment, the plurality of oxide layers include a first oxide layer and a second oxide layer that is denser than the first oxide layer, and wherein a first edge of the first oxide layer is laterally recessed by a greater distance from respective edges of the first nitride layer than the second oxide layer.

[0058] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: depositing a first dielectric layer covering the electrical connector; depositing a second dielectric layer over the first dielectric layer; performing a first etching process to etch through the second dielectric layer and the first dielectric layer, wherein openings are formed in the first dielectric layer and the second dielectric layer to expose the electrical connector; performing a second etching process to laterally etch the first dielectric layer and the second dielectric layer; depositing a first isolation layer extending into the opening, wherein the first isolation layer includes a first vertical portion and a first horizontal portion located in the opening and a second horizontal portion overlapping the second dielectric layer; and performing a first anisotropic etching process on the first isolation layer, wherein portions of the first vertical portion and the first horizontal portion of the first isolation layer remain in the opening, Wherein, the portion of the horizontal portion covers a portion of the top surface of the electrical connector.

2. The method according to claim 1, further comprising: depositing a protection layer over the first isolation layer, wherein the protection layer extends into the opening; and A second anisotropic etching process is performed on the protection layer, wherein a second vertical portion of the protection layer remains in the opening, and the first anisotropic etching process is performed using the second vertical portion as part of an etching mask.

3. The method of claim 2, further comprising forming a conductive member extending into the opening and contacting the electrical connector, wherein The conductive member is in contact with the second vertical portion of the protection layer.

4. The method according to claim 1, wherein: The first etching process includes an anisotropic etching process, and the second etching process includes an isotropic etching process.

5. The method according to claim 1, further comprising depositing a second isolation layer over the second dielectric layer before the first etching process, wherein The second isolation layer is also etched in the first etching process to form the opening.

6. The method according to claim 5, wherein: In the second etching process, the second isolation layer is not etched.

7. The method according to claim 1, wherein: In the second etching process, the first one of the first dielectric layer and the second dielectric layer has a first etching rate, and the second one of the first dielectric layer and the second dielectric layer has a second etching rate different from the first etching rate, and a ratio of the first etching rate to the second etching rate is greater than 2.

8. The method according to claim 1, wherein: A first one of the first dielectric layer and the second dielectric layer includes silicon oxide deposited using tetraethyl orthosilicate (TEOS) as a precursor, and a second one of the first dielectric layer and the second dielectric layer includes silicon oxide deposited using high density plasma chemical vapor deposition.

9. The method according to claim 1, wherein: After the first anisotropic etching process, a top edge of the first vertical portion of the first isolation layer is flush with or lower than a top end of the opening.

10. The method according to claim 1, wherein: After the first anisotropic etching process, the first isolation layer includes a portion located outside the opening, and wherein the portion overlaps the second dielectric layer.

11. A semiconductor structure comprising: Electrical connectors; a plurality of dielectric layers covering at least one edge portion of the electrical connector, wherein the plurality of dielectric layers comprises: a first dielectric layer; a second dielectric layer located above or below the first dielectric layer; and a first isolation layer located above the first dielectric layer and the second dielectric layer; and a second isolation layer overlapping the electrical connector, wherein the second isolation layer includes a sidewall contacting the sidewalls of the first dielectric layer, the second dielectric layer, and the first isolation layer, and wherein the second isolation layer includes: a first portion overlapping the first isolation layer, wherein the first portion has a first width; and a second portion overlapping the first dielectric layer, wherein the second portion has a second width different from the first width, The second isolation layer has a vertical leg and a horizontal leg connected to a bottom end of the vertical leg, and the horizontal leg physically contacts a portion of a top surface of the electrical connector.

12. The semiconductor structure according to claim 11, wherein: The first dielectric layer has a first density, and the second dielectric layer has a second density greater than the first density.

13. The semiconductor structure according to claim 12, wherein: The first dielectric layer and the second dielectric layer include the same element.

14. The semiconductor structure according to claim 11, wherein: The semiconductor structure also includes a protection layer overlapping the vertical foot.

15. The semiconductor structure of claim 14, further comprising a conductive member located above and in contact with the electrical connection, wherein: The conductive member is also in contact with the protection layer and the leveling foot.

16. The semiconductor structure according to claim 11, wherein: The second isolation layer includes a portion overlapping the second dielectric layer.

17. A semiconductor structure comprising: Metal pads; a plurality of oxide layers covering at least one edge portion of the metal pad; a first nitride layer overlapping the plurality of oxide layers, wherein edges of the plurality of oxide layers are laterally recessed from respective edges of the first nitride layer in a lateral direction toward an edge of the metal pad; and A second nitride layer is located in the openings in the plurality of oxide layers and the first nitride layer, wherein the second nitride layer is in physical contact with the metal pad and the first nitride layer.

18. The semiconductor structure according to claim 17, wherein: The second nitride layer has a top portion, and wherein a lower portion of the top portion is increasingly wider than a corresponding upper portion of the top portion.

19. The semiconductor structure according to claim 17, wherein: Edges of the plurality of oxide layers are laterally recessed by different distances from corresponding edges of the first nitride layer.

20. The semiconductor structure of claim 17, wherein: The plurality of oxide layers include a first oxide layer and a second oxide layer that is denser than the first oxide layer, and wherein a first edge of the first oxide layer is laterally recessed a greater distance from a corresponding edge of the first nitride layer than the second oxide layer.

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