Semiconductor structure and method for forming the same

Abstract

The present invention describes a method for forming n-type and p-type epitaxial source / drain structures having substantially coplanar top surfaces and different depths across input / output (I / O) and non-I / O regions of a substrate. In some embodiments, the method includes forming a fin structure and a planar portion on a substrate. The method also includes forming a first gate structure on the fin structure and forming a second gate structure on the planar portion. The method also includes etching the fin structure between the first gate structure to form a first opening, and etching the planar portion between the second gate structure to form a second opening. In addition, the method includes forming a first epitaxial structure in the first opening and forming a second epitaxial structure in the second opening, wherein the top surface of the first epitaxial structure is substantially coplanar with the top surface of the second epitaxial structure, and the bottom surface of the first epitaxial structure is not coplanar with the bottom surface of the second epitaxial structure. Embodiments of the present invention also disclose semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a first region on a substrate, the first region comprising a fin structure; forming a second region on the substrate, the second region comprising a planar portion having a first height; forming an isolation structure on the substrate, the isolation structure covering a bottom portion of the fin structure and a bottom portion of the planar portion; forming a first gate structure on the fin structure, the first gate structures being spaced apart by a first spacing; forming a second gate structure on the planar portion, the second gate structures being spaced apart by a second spacing greater than the first spacing; etching fin structures between the first gate structures until a top surface of the etched fin structure is coplanar with a top surface of the isolation structure; reducing a first height of the planar portion between the second gate structures to a second height; forming a first epitaxial structure on the etched fin structure; and forming a second epitaxial structure on the etched planar portion, the top surface of the second epitaxial structure being substantially coplanar with a top surface of the first epitaxial structure.

[0004] According to another aspect of an embodiment of the present invention, a semiconductor structure is provided, including: a first region having a first transistor, wherein a source / drain (S / D) epitaxial layer of the first transistor has a first height; and a second region having a second transistor and a third transistor, wherein the S / D epitaxial layer of the second transistor has a second height shorter than the first height; and the S / D epitaxial layer of the third transistor has a third height higher than the first height, wherein top surfaces of the S / D epitaxial layers of the first transistor, the second transistor, and the third transistor are substantially coplanar.

[0005] According to another aspect of an embodiment of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a first region on a substrate, the first region comprising a fin structure; forming a second region on the substrate, the second region comprising a planar portion; forming a first gate structure on the fin structure; forming a second gate structure on the planar portion; etching the fin structure between the first gate structures to form a first opening; etching the planar portion between the second gate structures to form a second opening, wherein the second opening is larger than the first opening; forming a first epitaxial structure in the first opening; and forming a second epitaxial structure in the second opening, wherein a top surface of the first epitaxial structure is substantially coplanar with a top surface of the second epitaxial structure, and a bottom surface of the first epitaxial structure is not coplanar with a bottom surface of the second epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, according to the convention in the industry, various components are not drawn to scale. In fact, the size of various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of transistors in non-input / output (non-I / O) and I / O regions, wherein source / drain (S / D) epitaxial structures are formed at substantially similar depths, according to some embodiments.

[0008] Figure 2 is an isometric view of a non-I / O area and an I / O area according to some embodiments.

[0009] Figure 3 is a cross-sectional view of transistors in non-I / O and I / O regions according to some embodiments, wherein S / D epitaxial structures are formed at different depths.

[0010] Figure 4A and Figure 4B is a cross-sectional view of S / D openings formed using different etching processes according to some embodiments.

[0011] Figure 5 is a flow chart describing a method for forming S / D epitaxial structures at substantially similar depths in non-I / O and I / O regions according to some embodiments.

[0012] Figures 6 to 9 is a cross-sectional view of an intermediate structure during formation of non-I / O and I / O regions according to some embodiments.

[0013] Fig.10 and Fig.11 is an isometric view of non-I / O and I / O areas according to some embodiments.

[0014] Fig.12is an isometric view of a non-I / O region and an I / O region after forming a sacrificial gate structure in accordance with some embodiments.

[0015] Fig.13 and Fig.14 is a cross-sectional view of an intermediate structure during formation of S / D epitaxial structures having substantially similar depths in non-I / O and I / O regions, according to some embodiments.

[0016] Fig.15 is an isometric view of non-I / O areas and I / O areas after an etching operation according to some embodiments.

[0017] Fig.16 and Fig.17 is a cross-sectional view of an intermediate structure during formation of S / D epitaxial structures having substantially similar depths in non-I / O and I / O regions, according to some embodiments.

[0018] Fig.18 is a cross-sectional view of an S / D epitaxial structure formed at substantially similar depths in non-I / O and I / O regions according to some embodiments.

[0019] Fig.19A and Fig.19B is a flow chart describing a method for forming an S / D epitaxial structure having a coplanar top surface topography across non-I / O and I / O regions in accordance with some embodiments.

[0020] Figure 20 to Figure 22 is a cross-sectional view of an intermediate structure during formation of an S / D epitaxial structure having a coplanar top surface topography across non-I / O and I / O regions in accordance with some embodiments.

[0021] Fig.23 is an isometric view of non-I / O areas and I / O areas after an etching operation according to some embodiments.

[0022] Figure 24 to Figure 27 is a cross-sectional view of an intermediate structure during formation of an S / D epitaxial structure having a coplanar top surface topography across non-I / O and I / O regions in accordance with some embodiments.

[0023] Fig.28 is a cross-sectional view of a non-I / O region and an I / O region having an S / D epitaxial structure with coplanar top surfaces according to some embodiments.

[0024] Fig.29A and Fig.29B ] are etch profiles obtained by isotropic and anisotropic etching processes according to some embodiments.

[0025] Fig.29C and Fig.29Dis a cross-sectional view of S / D openings formed using different etching processes according to some embodiments. DETAILED DESCRIPTION

[0026] The following disclosure provides different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component on a second component may include an embodiment in which the first component is in direct contact with the second component, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component is not in direct contact with the second component.

[0027] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be similarly interpreted accordingly.

[0028] In some embodiments, the terms "about" and "substantially" may refer to a value having a given number that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one of skill in the relevant art based on the teachings herein.

[0029] As used herein, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0030] An integrated circuit (IC) may include a combination of semiconductor structures, such as a combination of input / output (I / O) field effect transistors (FETs) and non-I / O FETs. An I / O FET may be a portion of a circuit formed in a peripheral region of the IC (referred to as an "I / O region" or "high voltage region"), while a non-I / O device may be a portion of a "core" circuit referred to as a logic circuit and / or a memory circuit formed in the "core" region of the IC. An I / O device may be configured to withstand higher voltages or currents than a non-I / O device. For example, an I / O device may be configured to handle an input voltage from an external power source (such as a lithium-ion battery) that outputs approximately 5V. In addition, an I / O device may be a portion of a transformer circuit that outputs a distribution voltage of approximately 1V, which may then be distributed to a non-I / O FET. On the other hand, a non-I / O device is not configured to directly handle an I / O voltage / current. A non-I / O device may include a FET that forms a logic gate, such as a NAND, a NOR, an inverter, and combinations thereof. Additionally, non-I / O devices may include memory devices, such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, other types of memory devices, and combinations thereof.

[0031] To improve manufacturing efficiency, it is desirable to form I / O and non-I / O FETs simultaneously on the same substrate. In the manufacture of gate stacks for non-I / O FETs, metal gate materials and high dielectric constant (high-k) dielectric materials (e.g., k values ​​greater than 3.9) have been implemented to improve device characteristics and facilitate device scaling. To simplify, coordinate and streamline the manufacturing process between I / O and non-I / O FETs, metal gates and high-k dielectric materials are also implemented for gate stacks for I / O FETs.

[0032] Because the I / O and non-I / O FETs are configured to operate at different voltages (e.g., about 5V and about 1V, respectively), their structures may vary greatly in physical dimensions (e.g., length, width, and height). For example, the gate stack of the I / O FET may have a larger surface area (e.g., greater than about 1 μm) than the gate stack of the smaller non-I / O FET. 2and include a thicker gate oxide. Other structural differences between I / O and non-I / O FETs include the height of their corresponding source / drain (S / D) epitaxial structures. For example, due to the larger size of I / O FETs, the S / D openings formed in the substrate to facilitate the formation of their S / D epitaxial structures are larger than the openings formed for the S / D epitaxial structures of non-I / O FETs. Therefore, and based on the growth characteristics of the S / D epitaxial structures, the resulting S / D epitaxial structures for I / O FETs may be larger or smaller than the S / D epitaxial structures for non-I / O FETs. As an example, a p-type S / D epitaxial structure for an I / O FET may be taller than a p-type S / D epitaxial structure for a non-I / O FET. At the same time, an n-type S / D epitaxial structure for an I / O FET may be shorter than an n-type S / D epitaxial structure for a non-I / O FET. The aforementioned size difference is related to the height and resistance of the S / D contacts formed on the S / D epitaxial structure and may cause a significant variation in resistance value between S / D contacts formed in I / O and non-I / O regions of the IC.

[0033] In addition, because I / O FETs operate at higher input voltages than non-I / O FETs (e.g., between about 3.3V and about 5V), I / O FETs are susceptible to hot carrier injection (HCI). HCI occurs when carriers from the channel region are accelerated toward the substrate (e.g., in the form of leakage current) or surrounding dielectric materials due to the presence of a high electric field near the drain terminal. If the "hot carriers" damage the atomic structure of the dielectric, the side effects of HCI include leakage current and damage to the surrounding dielectric materials (including the gate dielectric).

[0034] Embodiments of the present invention are directed to methods for forming an I / O FET that is not susceptible to HCI. In some embodiments, HCI mitigation is achieved by changing the sidewall profile of the S / D opening in the I / O FET to increase the spacing between the S / D epitaxial structure and the channel region. In some embodiments, the I / O FET formed by the methods described herein is characterized by having n-type and p-type S / D epitaxial structures with coplanar top surfaces. In some embodiments, the n-type and p-type S / D epitaxial structures formed in the I / O and non-I / O regions of the substrate have coplanar top surfaces. In some embodiments, the aforementioned coplanarity is achieved by adjusting the position of the S / D epitaxial structures for the n-type and p-type I / O FETs.

[0035] According to some embodiments, Figure 1 is a cross-sectional view of a non-I / O region A and an I / O region B of an IC. In some embodiments, the non-I / O region A and the I / O region B are not adjacent to each other (e.g., Figure 1 ), but separated by other areas of the IC. For example, I / O region B may be part of the periphery of the IC. Figure 1As shown, non-I / O region A may include n-type transistor 100 (also referred to as "transistor 100") and p-type transistor 105 (also referred to as "transistor 105"). I / O region B may include n-type transistor 110 (also referred to as "transistor 110") and p-type transistor 115 (also referred to as "transistor 115"). Additional transistors in both non-I / O region A and I / O region B are possible and within the spirit and scope of the present invention. In non-I / O region A, n-type transistor 100 includes gate structure 100G, n-type S / D epitaxial structure 120 (also referred to as "S / D epitaxial structure 120"), and channel region C. Similarly, p-type transistor 105 includes gate structure 105G, p-type S / D epitaxial structure 125 (also referred to as "S / D epitaxial structure 125"), and channel region D. In I / O region B, n-type transistor 110 includes gate structure 110G, n-type S / D epitaxial structure 130 (also referred to as “S / D epitaxial structure 130 ”), and channel region E. Similarly, p-type transistor 115 includes gate structure 115G, p-type S / D epitaxial structure 135 (also referred to as “S / D epitaxial structure 135 ”), and channel region F. In some embodiments, transistors 100 and 105 in I / O region A are formed on a fin structure disposed on substrate 140 , while transistors 110 and 115 in I / O region B are formed on a planar portion of substrate 140 . For example, transistors 100 and 105 in I / O region A are fin-based transistors in which channel regions C and D are formed in a fin structure, while transistors 110 and 115 are planar transistors in which channel regions E and F are formed on a planar portion of substrate 140 . Figure 1 As shown, transistors 100 , 105 , 110 , and 115 are isolated via isolation structures 145 formed on substrate 140 .

[0036] In some embodiments, even if Figure 1 Not shown, transistors 100 and 105 in non-I / O region A also have a smaller footprint than transistors 110 and 115 in I / O region B. For example, gate structures 100G and 105G are narrower along the x-direction than gate structures 110G and 115G. In addition, S / D epitaxial structures 120 and 125 are narrower along the x- and y-directions than S / D epitaxial structures 130 and 135. In some embodiments, the gate pitch in non-I / O region A is less than the gate pitch in I / O region B. Therefore, non-I / O region A has more transistors per unit area than I / O region B.

[0037] By way of example and not limitation, Figure 2is an isometric view of non-I / O region A and I / O region B prior to forming transistors 100 , 105 , 110 , and 115 . Transistors 100 and 105 are formed on fin structure 200 , while transistors 110 and 115 are formed on planar portion 205 , as described above, in accordance with some embodiments.

[0038] The fin structure 200 may be formed by patterning by any suitable method. For example, the fin structure 200 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. The double patterning or multiple patterning process combines photolithography with a self-aligned process, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that which can otherwise be obtained using a single direct photolithography method. For example, in some embodiments, a sacrificial layer is formed over the substrate 140, and then the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure 200.

[0039] refer to Figure 1 As shown by dashed line L, S / D epitaxial structures 120, 125, 130, and 135 may be formed at substantially similar depths within substrate 140. However, forming the S / D epitaxial structures at different depths may result in a height difference H between S / D epitaxial structures 120 and 130 as shown by dashed line K. n and a height difference H between the S / D epitaxial structures 125 and 135 p . More specifically, the n-type S / D epitaxial structure 130 of the n-type transistor 110 is formed to be shorter than the n-type S / D epitaxial structure 120 of the n-type transistor 100, and the p-type S / D epitaxial structure 135 of the p-type transistor 115 is formed to be taller than the p-type S / D epitaxial structure 125 of the p-type transistor 105. Based on the above, the height of the S / D contact formed on the p-type S / D epitaxial structure 135 will be shorter than the height of the S / D contacts formed on the S / D epitaxial structures 120 and 125. Therefore, the height of the S / D contact formed on the n-type S / D epitaxial structure 130 will be taller than the height of the S / D contacts formed on the S / D epitaxial structures 120 and 125. The aforementioned height difference between the S / D contacts in the non-I / O region A and the I / O region B may pose a challenge to the etching process for forming the S / D contacts and may exacerbate contact resistance variations across the IC.

[0040] In some embodiments, the height difference H between the p-type S / D epitaxial structures 125 and 135 is p It can be about 10 nm. However, the height difference H p The height difference H between the n-type S / D epitaxial structures 120 and 130 may be in the range of 0 nm to about 30 nm. ncan be about 15 nm respectively. However, the height difference H n It may be in the range of about 0 nm to about 30 nm.

[0041] According to some embodiments, Figure 3 1 is a cross-sectional view of non-I / O region A and I / O region B, wherein S / D epitaxial structures 130 and 135 have been placed to achieve substantially similar S / D contact heights for n-type transistors and p-type transistors in the I / O and non-I / O regions of substrate 140. More specifically, n-type S / D epitaxial structure 130 has been formed at a depth D shorter than S / D epitaxial structure 120. n As shown by the dotted line M, the S / D epitaxial structures 135 are formed at a depth D greater than that of the S / D epitaxial structures 125. p As shown by the dotted line M, the top surfaces of the n-type S / D epitaxial structures 120 and 130 are substantially coplanar, as shown by the dotted line N. In addition, the top surfaces of the S / D epitaxial structures 125 and 135 are also substantially coplanar.

[0042] In some embodiments, similar to Figure 1 , n-type S / D epitaxial structure 130 is shorter than n-type S / D epitaxial structure 120, and p-type S / D epitaxial structure 135 is taller than p-type S / D epitaxial structure 125. In some embodiments, Figure 3 Depth D shown p offset Figure 1 The height difference H shown p .For example, Figure 3 The depth difference D shown p Basically equal to Figure 1 The height difference H shown p (e.g., about 10 nm). In some embodiments, Figure 3 The depth difference D shown n offset Figure 1 The height difference H shown n .For example, Figure 2 The depth difference D shown n Basically equal to Figure 1 The height difference H shown n (e.g. about 15 nm).

[0043] In some embodiments, Figure 3Positioning the S / D epitaxial structures 130 and 125 at different depths as shown requires the use of etching masks that allow independent control of the etching processes used between the non-I / O region A and the I / O region B and between the n-type and p-type transistors in the I / O region B. The benefit of decoupling the etching processes between the non-I / O and I / O regions is that the HCI effect can be independently addressed for the transistors 110 and 115 in the I / O region B. In some embodiments, the etching process used to form the S / D openings of the transistors 110 and 115 is adjusted to increase the distance between the S / D epitaxial structure and the channel region. For example, and with reference to Figure 4A and Figure 4B , the etching parameters can be modulated so that Figure 4B As shown, the S / D opening 405 with an increased spacing S2 is formed instead of forming Figure 4A 4. S / D opening 400 is shown with spacing S1. In some embodiments, each spacing S1 and S2 corresponds to the horizontal distance from the edge of each S / D opening to the edge of the channel region of the transistor. In some embodiments, the etching process used to form S / D opening 405 is more anisotropic than the etching process used to form S / D opening 400. Therefore, S / D opening 405 has a larger vertical sidewall profile than S / D opening 400. In some embodiments, the difference between S2 and S1 (e.g., "proximity gain") is greater for n-type S / D epitaxial structures (e.g., Figure 3 The S / D epitaxial structure 130 shown is about 2.8 nm, and for the p-type S / D epitaxial structure ( Figure 3 The S / D epitaxial structure 135 is shown to be approximately 6 nm.

[0044] According to some embodiments, Figure 5 is used to form S / D epitaxial structures (e.g. Figure 1 1 and 135). Other manufacturing operations may be performed between the various operations of method 500 and may be omitted for clarity only. Figures 6 to 18 Method 500 is described.

[0045] refer to Figure 5 , method 500 begins with operation 505 and the process of forming non-I / O and I / O regions on a substrate. In some embodiments, operation 505 forms Figure 2 The non-I / O area A and the I / O area B are shown. As an example and not a limitation, reference will be made to Figures 6 to 10 The formation of the non-I / O region A and the I / O region B is described.

[0046] As mentioned above, about Figure 2, the non-I / O region A includes a fin structure 200, and the I / O region B includes one or more planar portions 205. The fin structure 200 may be formed by patterning by any suitable method. For example, the fin structure 200 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that which can otherwise be obtained using a single direct photolithography method. For example, and with reference to Figure 6 A sacrificial layer may be formed over the substrate 140, and then the sacrificial layer may be patterned using a photolithography process to form a sacrificial patterned structure 600. By depositing and anisotropically etching the spacer layer 605, the Figure 7 The patterned sacrificial structure 600 shown forms a spacer 605s. As a result, the spacer 605s becomes self-aligned with the sidewalls of the sacrificial patterned structure 600. Subsequently, the sacrificial patterned structure 600 is removed, and the remaining spacer 605s can be used to pattern the fin structure 200, such as Figure 8 The above method can be used, for example, to form fin structures 200 for n-type and p-type transistors in non-I / O regions. In some embodiments, the spacing (e.g., along the y-direction) of the patterned sacrificial structure 600 and the width spacer 605s respectively defines the pitch and width (e.g., along the y-direction) of the resulting fin structure 200.

[0047] like Figure 7 and Figure 8 As shown, the formation of the planar portion 205 may occur simultaneously with the formation of the fin structure 200. For example, Figure 7 As shown, a hard mask layer may be deposited and patterned to form a patterned structure 700. The patterned structure 700 is then used as an etch mask to define Figure 8 Planar portion 205 is shown. In some embodiments, a plurality of patterned structures 700 may be formed on substrate 140 to define planar portions, such as planar portion 205. For example, planar portions for n-type and p-type transistors may be formed in an I / O region by the above-described method.

[0048] In some embodiments, after forming the fin structure 200 and the planar portion 205, the spacer 605s and the patterned structure 700 are removed, as shown in FIG. Fig. 9 According to some embodiments, Fig.10 yes Fig. 9 As described above, the non-I / O region A and the I / O region B may be formed in different regions of the substrate 140, for example, not adjacent to each other, such as Fig.10 In some embodiments, for ease of description, the non-I / O region A and the I / O region B are shown adjacent to each other. In addition, additional fin structures and planar portions may be formed on corresponding regions of the substrate 140.

[0049] In some embodiments, substrate 140, fin structure 200, and planar portion 205 may include silicon, a compound semiconductor, an alloy semiconductor, or a combination thereof. Examples of compound semiconductors include, but are not limited to, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb). Examples of alloy semiconductors include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0050] In some embodiments, the fin structure 200 and the planar portion 205 may include a different semiconductor material than the substrate 140. For example, a different semiconductor material or combination thereof (eg, SiGe, Ge, or a SiGe / Si stack) may be deposited on the substrate 140 and then subsequently deposited as described above with reference to Figures 6 to 9 It is patterned to form the fin structure 200 , the planar portion 205 , or both.

[0051] For example purposes, semiconductor substrate 140, fin structure 200, and planar portion 205 will be described in the context of silicon. Other semiconductor materials and combinations thereof may be used based on the disclosure herein. These semiconductor materials and combinations thereof are within the spirit and scope of the present invention.

[0052] According to some embodiments, after forming the fin structure 200 and the planar portion 205 , Figure 3 As an example and not limitation, the isolation structure 145 may include a stack of dielectric layers (such as a liner dielectric layer and a fill dielectric layer) that are disposed between the dielectric layers 144 and 145. Figure 3140 , the fin structure 200 and the planar portion 205 are shown together as an isolation structure 145. In some embodiments, the isolation material is deposited over the fin structure 200 and the planar portion 205 to fill the gap between the structures arranged on the substrate 140, such as the fin structure 200 and the planar portion 205. In some embodiments, the fin structure 200 and the planar portion 205 are embedded in the isolation material. As an example and not limitation, the isolation material is planarized so that the top surface of the isolation material and the top surfaces of the fin structure 200 and the planar portion 205 are substantially coplanar. In some embodiments, the isolation material is deposited using a flowable chemical vapor deposition process (e.g., FCVD) to ensure that the isolation material fills the space between the fin structure 200 and the planar portion 205 without forming a seam or void. In some embodiments, the isolation material is a silicon oxide-based dielectric layer including, for example, nitrogen and hydrogen. In order to improve its dielectric and structural properties, the isolation material may be wet steam annealed (e.g., exposed to 100% water molecules) at a temperature between about 800°C and 1200°C. During the wet steam annealing, the isolation material densifies and its oxygen content may increase. Subsequently, an etch-back process etches the isolation material below the top surface of the fin structure 200 and the planar portion 205 to form Fig.11 An isolation structure 145 is shown.

[0053] refer to Figure 5 , method 500 continues with operation 510 and forming a sacrificial gate structure on the non-I / O region A and the I / O region B. In some embodiments, the sacrificial gate structure formed in the non-I / O region A is narrower along the x-direction than the sacrificial gate structure formed in the I / O region B. In some embodiments, the sacrificial gate structure formed in the non-I / O region A has a different length than the sacrificial gate structure formed in the I / O region B. By way of example and not limitation, Fig.12 1 is an isometric view of non-I / O region A and I / O region B, wherein the shaded area 1200 on the fin structure 200 and the area 1205 on the shaded plane portion 205 represent the corresponding sacrificial gate structure, and for the sake of clarity and simplicity of description, the individual layers thereof are not shown. In some embodiments, the sacrificial gate structure includes a sacrificial gate dielectric (e.g., silicon oxide or silicon oxynitride) and a sacrificial gate electrode (e.g., polysilicon), both of which are sequentially deposited and patterned to form the sacrificial structure represented by the shaded areas 1200 and 1205. In some embodiments, Fig.12 The number and density of sacrificial gate structures shown are not limited, and fewer or additional sacrificial gate structures are possible within the spirit and scope of the present invention.

[0054] According to some embodiments, the S / D epitaxial structures in the non-I / O region A and the I / O region B are formed between the sacrificial gate structures represented by the shaded areas 1200 and 1205, respectively. In some embodiments, due to the size difference between the sacrificial gate structures formed in the non-I / O region A and I / O region B, the spacing or interval between adjacent sacrificial gate structures is different between the non-I / O region A and the I / O region B, as described above. For example, the spacing P between adjacent sacrificial gate structures in the non-I / O region A is A shorter than the spacing P in I / O area B B In some embodiments, the height difference between n-type S / D epitaxy 120 and 130 (eg, H n )and Figure 1 The height difference (eg, H) between the p-type S / D epitaxial structures 125 and 135 is shown. p ) is due to the spacing P A With spacing P B The size difference between .

[0055] refer to Figure 5 , the method 500 continues with operation 515 and the following process: recessing the fin structure 200 in the first area of ​​the non-I / O region A and recessing the planar portion in the first area of ​​the I / O region B. In some embodiments, the non-I / O region A and the first area of ​​the I / O region B are formed to form an n-type transistor (such as Figure 1 Alternatively, the first region of the non-I / O region A and the I / O region B may be a region where a p-type transistor (such as Figure 1 As an example and not limitation, the first region of non-I / O region A and the first region of I / O region B will be described in the context of regions having n-type transistors, such as Figure 1 The n-type transistors 100 and 110 are shown. In some embodiments, recessing the fin structure 200 in the first region of the non-I / O region A and recessing the planar portion 205 in the first region of the I / O region B is achieved by selectively masking the substrate 140 except for the first region of the non-I / O region A. As an example and not limitation, Fig.13 It is along Fig.12 A cross-sectional view of a cutting line OO' is shown, which shows a non-I / O region A and an I / O region B along a yz plane.

[0056] In with Fig.12 Compared to the additional planar portion 205 Fig.13 In the embodiment, the mask layer 1300 covers the substrate 140 except for the first region A1 of the non-I / O region A and the first region B1 of the I / O region B. In some embodiments, the mask layer 1300 masks each sacrificial gate structure in the first regions A1 and B1. Fig.13Therefore, the recessing process of operation 515 occurs between sacrificial gate structures, for example, Fig.12 The shaded area 1200 and 1205 are shown. A The first dimension of the groove is defined by the width of the fin structure 200 along the y direction, and the second dimension of the groove is defined by the pitch P A Similarly, since the planar portion 205 is defined by the spacing P between adjacent sacrificial gate structures in the first region A1 of the non-I / O region A, the planar portion 205 is defined by the spacing P. B The first dimension of the groove is defined by the width of the planar portion 205 along the y direction, and the second dimension of the groove is defined by the spacing P B defined (eg, defined by spaces between adjacent sacrificial gate structures in the first region B1 of the I / O region B).

[0057] In some embodiments, the mask layer 1300 includes a hard mask material (eg, silicon nitride) or a photoresist layer. The mask layer 1300 may be disposed on the substrate 140 and then patterned such that portions of the mask layer 1300 above the first regions A1 and B1 are selectively removed to expose the underlying fin structure 200 and the planar portion 205, as shown in FIG. Fig.13 shown.

[0058] Once the fin structure 200 in the first region A1 and the planar portion 205 in the first region B1 are exposed, the etching process recesses (e.g., etches) the exposed fin and planar portion to reduce their height. In some embodiments, the recessed fin structure 200 and planar portion 205 are etched until their top surfaces are substantially coplanar with the top surface of the isolation structure 145, such as Fig.14 As shown. In some embodiments, the etching process does not substantially etch the mask layer 1300, the material of the isolation structure 145, and the sacrificial gate structure. In some embodiments, the etching process is a dry etching process. As an example and not limitation, the dry etching process may include an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination thereof. Examples of oxygen-containing gases include, but are not limited to, oxygen (O2) and sulfur dioxide (SO2). Examples of fluorine-containing gases include, but are not limited to, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and hexafluoroethane (C2F6). Examples of chlorine-containing gases include, but are not limited to, chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), silicon tetrachloride (SiCl4), and boron trichloride (BCl3). Examples of bromine-containing gases include, but are not limited to, hydrogen bromide (HBr) and bromoform (CHBr3).

[0059] In some embodiments, Fig.15FIG. 5 is an isometric view of the first area A1 of the non-I / O area A and the first area B1 of the I / O area B after the above operation 515. Fig.15 As shown, operation 515 recesses the fin structure 200 and the planar portion 205 to the level of the isolation structure 145. As described below, S / D epitaxial structures 120 and 130 will be formed on the recessed portion of the fin structure 200 and the planar portion 205.

[0060] refer to Figure 5 , the method 500 continues with operation 520 and the following process: forming an S / D epitaxial structure on the recessed fin structure and the planar portion (e.g., on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1). In some embodiments, the S / D epitaxial structure formed in operation 520 corresponds to Figure 1 S / D epitaxial structures 120 and 130 are shown. As an example and not limitation, a single deposition operation is used to simultaneously form the S / D epitaxial structures 120 and 130 on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1, respectively.

[0061] As an example and not limitation, S / D epitaxial structures 120 and 130 may be formed as follows. In some embodiments, mask layer 1300 is not removed during operation 520. Fig.16 , a chemical vapor deposition (CVD) process is used to grow the S / D epitaxial structures 120 and 130 on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1 using, for example, a silane (SiH4) precursor. In some embodiments, the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1 serve as seed locations for the S / D epitaxial structures 120 and 130. In some embodiments, the S / D epitaxial structures 120 and 130 are not grown on dielectric surfaces, such as the isolation structures 145 and the substrates formed by the isolation structures 145. Fig.15 The shaded areas 1200 and 1205 are shown to represent sacrificial gate structures.

[0062] In some embodiments, the S / D epitaxial structures 120 and 130 include arsenic-doped silicon (Si:As) epitaxial layers, phosphorus-doped silicon (Si:P) epitaxial layers, carbon-doped silicon (Si:C) epitaxial layers, or combinations thereof. The aforementioned dopants may be introduced during epitaxial layer growth by adding suitable precursors such as phosphine, arsine, and hydrocarbons. As an example and not limitation, Si:P and Si:As epitaxial layers may be deposited at a temperature of about 680°C, while Si:C epitaxial layers may be deposited at a temperature between about 600°C and about 700°C. In some embodiments, the amount of phosphorus or arsenic doped into the epitaxial layer may be about 3×10 21 Atom / cm 3As an example and not limitation, the concentration of C in Si:C may be equal to or less than about 5 atomic % (at.%). The foregoing dopants and atomic concentrations are exemplary and not limiting. Therefore, different dopants and atomic concentrations may be used and are within the spirit and scope of the present invention.

[0063] In some embodiments, and because of the above P A With P B Due to the gate spacing difference between the two, the etched portion of the planar portion 205 in the first region B1 is wider in both the x-direction and the y-direction than the etched portion of the fin structure 200 in the first region A1. Therefore, and due to the growth kinetics of the epitaxial layer growth, the n-type S / D epitaxial structure 130 is formed shorter than the etched portion of the planar portion 205 in the first region B1 in both the x-direction and the y-direction. Figure 1 The height difference H shown n An n-type S / D epitaxial structure 120 is depicted.

[0064] In some embodiments, the process of operations 515 and 520 of method 500 is repeated for a second region of non-I / O region A and I / O region B, wherein p-type transistors 105 and 115 are formed as described below.

[0065] refer to Figure 5 , the method 500 continues with operation 525 and the following process: recessing the fin structure 200 in the second region A2 of the non-I / O region A and recessing the planar portion 205 in the second region B2 of the I / O region B. In some embodiments, the second regions A2 and B2 are formed to form a p-type transistor (e.g. Figure 1 In some embodiments, recessing the fin structure 200 in the second region A2 and recessing the planar portion 205 in the second region B2 of the I / O region B is achieved by selectively masking the substrate 140 except for the second regions A2 and B2 (e.g., the regions where the p-type transistors are formed). Fig.17 , a mask layer 1700 is disposed on the substrate 140. The mask layer 1700 is patterned to expose the second regions A2 and B2. At the same time, other regions of the non-I / O region A and the I / O region B are masked.

[0066] In some embodiments, the etching process of operation 525 is similar to the etching process of operation 515 discussed above. For example, the etching process of operation 525 can be a dry etching process, including an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination thereof. Examples of oxygen-containing gases include, but are not limited to, O2 and SO2. Examples of fluorine-containing gases include, but are not limited to, CF4, SF6, CH2F2, CHF3, and C2F6. Examples of chlorine-containing gases include, but are not limited to, Cl2, CHCl3, CCl4, SiCl4, and BCl3. Examples of bromine-containing gases include, but are not limited to, HBr and CHBr3.

[0067] In some embodiments, the recessed fin structure 200 and the planar portion 205 are etched until their top surfaces are substantially coplanar with the top surface of the isolation structure 145 , such as Fig.17 In some embodiments, the etching process does not substantially etch the mask layer 1700, the material of the isolation structure 145, and the sacrificial gate structure.

[0068] In some embodiments, similar to operation 515 described above, after operation 525, the fin structure 200 and the planar portion 205 are recessed in the second regions A2 and B2 between the sacrificial gate structures (eg, at a spacing P A and spacing P B For example, during the etching process of operation 525, the mask layer 1700 covers the sacrificial gate structures in the second regions A2 and B2.

[0069] refer to Figure 5 , the method 500 continues with operation 530 and the following process: forming an S / D epitaxial structure on the recessed fin structure and the recessed planar portion (e.g., on the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2). In some embodiments, the S / D epitaxial structure formed in operation 530 corresponds to Figure 1 P-type S / D epitaxial structures 125 and 135 are shown. As an example and not limitation, a single deposition operation is used to simultaneously form the p-type S / D epitaxial structures 125 and 135 on the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2.

[0070] As an example and not limitation, the p-type S / D epitaxial structures 125 and 135 may be formed as follows. The p-type S / D epitaxial structures 125 and 135 are grown using a CVD process using, for example, SiH4 and / or germane (GeH4) precursors. In some embodiments, the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2 serve as seed locations for the p-type S / D epitaxial structures 125 and 135. In some embodiments, the p-type S / D epitaxial structures 125 and 135 are not grown on insulating surfaces such as the isolation structure 145 and on sacrificial gate structures.

[0071] In some embodiments, the p-type S / D epitaxial structures 125 and 135 include a boron-doped (B-doped) silicon germanium (SiGe:B) epitaxial layer, a boron-doped germanium (Ge:B) epitaxial layer, a boron-doped germanium tin (GeSn:B) epitaxial layer, or a combination thereof. Boron dopants may be introduced during epitaxial layer growth with appropriate precursors such as diborane (B2H6). By way of example and not limitation, SiGe:B may be deposited at a temperature of about 620°C, GeSn:B epitaxial layers may be deposited at a temperature between about 300°C and about 400°C, and Ge:B epitaxial layers may be deposited at a temperature between about 500°C and about 600°C. By way of example and not limitation, the amount of boron incorporated into the aforementioned epitaxial layers may be about 1×10 21 Atom / cm 3 In some embodiments, the concentration of Ge in SiGe:B may be between about 20 at.% and about 40 at.%. In addition, the concentration of Sn in GeSn:B may be between about 5 at.% and about 10 at.%. The foregoing dopants and atomic concentrations are exemplary and non-limiting. Therefore, dopants and atomic concentrations different from those provided above may be used and are within the spirit and scope of the present invention.

[0072] In some embodiments, and because of the above P A With P B Due to the gate spacing difference between the two, the etched portion of the planar portion 205 in the second region B2 is wider in both the x-direction and the y-direction than the etched portion of the fin structure 200 in the second region A2. Therefore, and due to the growth kinetics of the epitaxial layer growth, the p-type S / D epitaxial structure 135 is formed to be higher than the gate spacing difference between the two regions. Figure 1 The height difference H shown p The p-type S / D epitaxial structure 125 is discussed.

[0073] According to some embodiments, Fig.19A and Fig.19B It is used to form S / D epitaxial structures (such as Figure 3 120, 125, 130, and 135) shown in FIG. 121. In some embodiments, the spacing between the S / D epitaxial structure and the channel region in the I / O region is enlarged to mitigate the HCI effect. In some embodiments, the S / D epitaxial structure of method 1900 is formed with an additional etch mask. Other manufacturing operations may be performed between the various operations of method 1900 and may be omitted for clarity only. Reference will be made to Figures 20 to 28 Describe method 1900.

[0074] In some embodiments, operations 1905 and 1910 of method 1900 are similar to those described above with respect to Figures 6 to 12 Operations 505 and 510 of the method 500 discussed are the same. Therefore, the description of the method 1900 will be based on operations 1915 and Fig. 20 start.

[0075] refer to Fig.19A , the method 1900 continues with operation 1915 and the process of recessing the fin structure 200 in the first area of ​​the non-I / O region A. In some embodiments, the first area of ​​the non-I / O region A is a region where an n-type transistor (e.g., Figure 3 Alternatively, the first region of the non-I / O region A may be a region where a p-type transistor (such as Figure 3 As an example and not limitation, in the region with n-type transistors (such as Figure 3 The first region of the non-I / O region A is described in the context of a region of the n-type transistor 100 shown in FIG. 1 . In some embodiments, recessing the fin structure 200 in the first region of the non-I / O region A is achieved by selectively masking the substrate 140 except for the first region of the non-I / O region A (e.g., the region in the non-I / O region A where the n-type transistor is formed). As an example and not limitation, Fig. 20 It is along Fig.12 A cross-sectional view of a cutting line OO' is shown, which shows a non-I / O region A and an I / O region B along a yz plane.

[0076] In with Fig.12 Compared to the additional planar portion 205 Fig. 20 In the embodiment, the mask layer 1300 covers the substrate 140 except for the first region A1 of the non-I / O region A. In some embodiments, the mask layer 2000 masks the first region A1 of the non-I / O region A and each sacrificial gate structure of the entire I / O region B. Therefore, the recessing process of operation 1915 occurs between the sacrificial gate structures, for example, Fig.12 The shaded area 1200 is shown. Since the fin structure 200 is spaced by the pitch P A The groove is recessed in the defined area, so the width of the groove is defined by the width of the fin structure 200 along the y direction, and the length of the groove is defined by the pitch P A defined (eg, defined by the spaces between adjacent sacrificial gate structures in the first area A1 of the non-I / O region A).

[0077] In some embodiments, the mask layer 2000 includes a hard mask material (eg, silicon nitride) or a photoresist layer, which may be disposed on the substrate 140 and then patterned so that a portion of the mask layer 2000 above the first region A1 is selectively removed to expose the first region A1. Fig. 20 An underlying fin structure 200 is shown.

[0078] Once the fin structures 200 in the first region A1 are exposed, the etching process recesses (e.g., etches) the exposed fins to reduce their height. In some embodiments, the recessed fin structures 200 are etched until their top surfaces are substantially coplanar with the top surfaces of the isolation structures 145, such as Fig.21 As shown. In some embodiments, the etching process does not substantially etch the mask layer 2000, the material of the isolation structure 145, and the sacrificial gate structure. In some embodiments, the etching process is a dry etching process, similar to the etching process described above with respect to operation 515 of method 500. As an example and not limitation, the dry etching process may include an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination thereof. Examples of oxygen-containing gases include, but are not limited to, O2 and SO2. Examples of fluorine-containing gases include, but are not limited to, CF4, SF6, CH2F2, CHF3, and C2F6. Examples of chlorine-containing gases include, but are not limited to, Cl2, CHCl3, CCl4, SiCl4, and BCl3. Examples of bromine-containing gases include, but are not limited to, HBr and CHBr3. Once the fin structure 200 in the first region A1 is recessed between the sacrificial gate structures, the mask layer 2000 is removed from both the non-I / O region A and the I / O region B.

[0079] refer to Fig.19A , method 1900 continues with operation 1920 and recessing planar portion 205 of substrate 140 in a first region of I / O region B. In some embodiments, the first region of I / O region B is a region where an n-type transistor (e.g., Figure 3 Alternatively, the first region of the I / O region B may be a region where a p-type transistor (such as Figure 3 As an example and not limitation, in the region where the n-type transistor (such as Figure 3 The first region of the I / O region B is described in the context of a region of an n-type transistor 110 shown.

[0080] In some embodiments, recessing the planar portion 205 in the first region of the I / O region B is achieved by selectively masking the substrate 140 except for the first region of the I / O region B. For example, and with reference to Fig. 22 , the mask layer 2200 may be arranged and patterned over the substrate 140 to expose the first region B1 of the I / O region B. In some embodiments, the mask layer 2200 masks the sacrificial gate structures of the first region B1 and exposes the regions between the sacrificial gate structures, such as those formed by Fig.12 The spacing P shown BSubsequently, an etching process similar to the etching process described above with respect to operation 1915 is used to reduce the height of the planar portion 205 in the first region B1 between the sacrificial gate structures. After the etching process, the recessed planar portion 205 has a height h above the top surface of the isolation structure 145 and the recessed fin 200 in the first region A1. In some embodiments, the height h corresponds to Figure 1 The height difference H between the n-type epitaxial structures 120 and 130 is shown. n In some embodiments, the height h corresponds to Figure 3 The depth difference D between the n-type epitaxial structures 120 and 130 is shown as n In some embodiments, the height h of the recessed planar portion 205 is adjusted to compensate for Figure 1 The height difference H shown n And achieve Figure 3 The depth difference D between the n-type epitaxial structures 120 and 130 is shown as n In some embodiments, the height h is implemented Figure 3 The top surface coplanarity shown. In some embodiments, the etching process is timed to achieve a desired height h of the recessed planar portion 205 in the first region B1. In some embodiments, the height h ranges between about 0 nm and about 30 nm (e.g., about 15 nm). In some embodiments, after the etching process of operation 1920, the mask layer 2200 is removed by a dry etching or wet etching process.

[0081] In some embodiments, Fig.23 1 is an isometric view of the first region A1 of the I / O region A and the first region B1 of the I / O region B after the above operations 1915 and 1920. Fig.23 As shown, operations 1915 and 1920 recess the fin structure 200 to the level of the isolation structure 145, while Fig. 22 As discussed, the planar portion 205 is recessed to a height h above both the isolation structure 145 and the recessed fin structure 200. As described below, the S / D epitaxial structures 120 and 130 will be formed on the recessed portion of the fin structure 200 and the planar portion 205.

[0082] refer to Fig.19A , method 1900 continues with operation 1925 and the following process: forming an S / D epitaxial structure on the recessed fin structure and the planar portion (e.g., on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1). In some embodiments, the S / D epitaxial structure formed in operation 1925 corresponds to Figure 3S / D epitaxial structures 120 and 130 are shown. As an example and not limitation, a single deposition operation is used to simultaneously form the S / D epitaxial structures 120 and 130 on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1, respectively.

[0083] In some embodiments, operation 1925 is similar to operation 530 of method 500 described above. For example, S / D epitaxial structures 120 and 130 may be formed as follows. Fig.24 , a mask layer 2400 is arranged on the substrate 140 and patterned to mask the substrate 140 except for the first regions A1 and B1. Subsequently, a CVD process is applied using, for example, a SiH4 precursor to grow the S / D epitaxial structures 120 and 130 on the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1. In some embodiments, the recessed fin structure 200 in the first region A1 and the recessed planar portion 205 in the first region B1 are used as seed locations for the S / D epitaxial structures 120 and 130. In some embodiments, the S / D epitaxial structures 120 and 130 are not grown on dielectric surfaces, such as the isolation structure 145 and the substrate 140 formed by the isolation structure 145. Fig.24 The shaded areas 1200 and 1205 are shown to represent sacrificial gate structures.

[0084] In some embodiments, the S / D epitaxial structures 120 and 130 include Si:As epitaxial layers, Si:P epitaxial layers, Si:C epitaxial layers, or combinations thereof. The aforementioned dopants may be introduced during epitaxial layer growth by adding suitable precursors such as phosphine, arsine, and hydrocarbons. As an example and not limitation, Si:P and Si:As epitaxial layers may be deposited at a temperature of about 680°C, while Si:C epitaxial layers may be deposited at a temperature between about 600°C and about 700°C. In some embodiments, the amount of phosphorus or arsenic incorporated into the epitaxial layer may be about 3×10 21 Atom / cm 3 As an example and not limitation, the concentration of C in Si:C may be equal to or less than about 5 atomic % (at.%). The foregoing dopants and atomic concentrations are exemplary and not limiting. Therefore, different dopants and atomic concentrations may be used and are within the spirit and scope of the present invention.

[0085] In some embodiments, and because of the above P A With P BDue to the gate spacing difference between the recessed fin structure 200 and the recessed planar portion 205, the etched portion of the planar portion 205 in the first region B1 is wider in both the x-direction and the y-direction than the etched portion of the fin structure 200 in the first region A1. Therefore, and due to the growth kinetics of the epitaxial layer growth, the n-type S / D epitaxial structure 130 is formed with a height shorter than the n-type S / D epitaxial structure 120 as discussed above. However, due to the height offset h between the recessed fin structure 200 and the recessed planar portion 205, the top surfaces of the n-type S / D epitaxial structures 120 and 130 grow to be similar to the height of the n-type S / D epitaxial structures 120 and 130. Fig.24 As described above, the height h compensates for the height difference between the n-type S / D epitaxial structures 130 and 120 to achieve Figure 3 and Fig. 27 Thus, as described above, the height h is substantially equal to Figure 1 The height difference H shown n and Figure 3 The depth difference D shown n .

[0086] In some embodiments, the process of operations 1915 and 1920 of method 1900 is repeated for a second region of non-I / O region A and I / O region B, wherein p-type transistors 105 and 115 are formed. However, in the second region, planar portion 205 is etched under isolation structure 145 as described below.

[0087] In some embodiments, after operation 1925, mask layer 2400 is removed. As an example and not limitation, mask layer 2400 can be removed by a wet etching process or a dry etching process that is selective to mask layer 2400.

[0088] refer to Fig.19B The method 1900 continues with operation 1930 and recessing the fin structure 200 in the second region A2 of the non-I / O region A. In some embodiments, the second region A2 is a region where a p-type transistor (eg, Figure 3 In some embodiments, the fin structure 200 is recessed in the second region A2 by selectively masking the substrate 140 except for the second region A2 (eg, the region where the p-type transistor is formed). Fig.25 , a mask layer 2500 is disposed on the substrate 140. The mask layer 2500 is patterned to expose the second area A2. At the same time, other areas of the non-I / O area A and the I / O area B are masked.

[0089] In some embodiments, the etching process for recessing the fin structure 200 in the second region A2 is similar to the etching process for recessing the fin structure 200 in the first region A1 discussed above. For example, the etching process is a dry etching process. As an example and not limitation, the dry etching process may include an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination thereof. Examples of oxygen-containing gases include, but are not limited to, O2 and SO2. Examples of fluorine-containing gases include, but are not limited to, CF4, SF6, CH2F2, CHF3, and C2F6. Examples of chlorine-containing gases include, but are not limited to, Cl2, CHCl3, CCl4, SiCl4, and BCl3. Examples of bromine-containing gases include, but are not limited to, HBr and CHBr3. Once the fin structure 200 in the second region A2 is recessed (e.g., between sacrificial gate structures), the mask layer 2500 is removed from both the non-I / O region A and the I / O region B. As an example and not limitation, the mask layer 2500 may be removed by a wet etching process or a dry etching process that is selective to the mask layer 2500.

[0090] In some embodiments, the recessed fin structures 200 are etched until their top surfaces are substantially coplanar with the top surfaces of the isolation structures 145 . Fig.25 In some embodiments, the etching process does not etch the mask layer 2500, the material of the isolation structure 145, and the layer of the sacrificial gate structure.

[0091] refer to Fig.19B , method 1900 continues with operation 1935 and the process of recessing the planar portion in the second area of ​​I / O region B. In some embodiments, operation 1935 is similar to operation 1920 described above, except that a different area of ​​I / O region B is etched (e.g., recessed), and the recessed planar portion is etched to a depth below isolation structure 145 instead of being etched to a height h above isolation structure 145. In addition, similar masking operations used in operation 1920 may be used in operation 1935. For example, and with reference to Fig.26 , a mask layer 2600 is disposed on the substrate 140. The mask layer 2600 is patterned to expose the second region B2 of the I / O region B. At the same time, other regions of the non-I / O region A and the I / O region B are masked.

[0092] In some embodiments, the etching process used to recess the planar portion 205 in the second region B2 is similar to the etching process discussed above for recessing the planar portion 205 in the first region B1. After the etching process, the recessed planar portion 205 has a depth d below the top surface of the isolation structure 145. In some embodiments, the depth d corresponds to Figure 1 The height difference H between the p-type epitaxial structures 125 and 135 is shown p In some embodiments, the depth d corresponds to Figure 3 The depth difference D between the p-type epitaxial structures 125 and 135 is shown p In some embodiments, the depth d of the recessed planar portion 205 is adjusted to compensate for Figure 1 The height difference H shown p And achieve Figure 3 The depth difference D between the p-type epitaxial structures shown p In some embodiments, the depth d is implemented Figure 3 In some embodiments, the etching process is performed at a time to achieve a desired depth d of the recessed planar portion 205 in the second region B2. In some embodiments, the depth ranges between about 0 nm and about 30 nm (e.g., about 10 nm). In some embodiments, after the etching process of operation 1935, the mask layer 2600 is removed.

[0093] In some embodiments, operations 1930 and 1935 recess the fin structure 200 and the planar portion 205 in the second regions A2 and B2 between the sacrificial gate structures (eg, at a pitch P A and spacing P B ), as discussed above with respect to operations 1915 and 1920. For example, during the etching process in operations 1930 and 1935, the mask layers 2500 and 2600 cover the sacrificial gate structures in the second regions A2 and B2.

[0094] refer to Fig.19B , method 1900 continues with operation 1940 and the following process: forming an S / D epitaxial structure on the recessed fin structure and the recessed planar portion (e.g., on the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2). In some embodiments, the S / D epitaxial structure formed in operation 1940 corresponds to Figure 3 P-type S / D epitaxial structures 125 and 135 are shown. As an example and not limitation, a single deposition operation is used to simultaneously form the p-type S / D epitaxial structures 125 and 135 on the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2.

[0095] By way of example and not limitation, p-type S / D epitaxial structures 125 and 135 may be formed as follows. Fig. 27, a mask layer 2700 is arranged on the substrate 140 and patterned to mask the substrate 140 except for the second regions A2 and B2. Subsequently, a CVD process using, for example, SiH4 and / or GeH4 precursors is used to grow p-type S / D epitaxial structures 125 and 135 on the recessed fin structure 200 in the second region A2 and on the recessed planar portion 205 in the second region B2. In some embodiments, the recessed fin structure 200 in the second region A2 and the recessed planar portion 205 in the second region B2 serve as seed locations for the p-type S / D epitaxial structures 125 and 135. In some embodiments, the p-type S / D epitaxial structures 125 and 135 are not grown on insulating surfaces such as the isolation structure 145 and on sacrificial gate structures.

[0096] In some embodiments, the p-type S / D epitaxial structures 125 and 135 include SiGe:B epitaxial layers, Ge:B epitaxial layers, GeSn:B, or combinations thereof. Boron dopants may be introduced during epitaxial layer growth with appropriate precursors such as B2H6. As an example and not limitation, SiGe:B may be deposited at a temperature of about 620°C, GeSn:B epitaxial layers may be deposited at a temperature between about 300°C and about 400°C, and Ge:B epitaxial layers may be deposited at a temperature between about 500°C and about 600°C. As an example and not limitation, the amount of boron incorporated into the aforementioned epitaxial layers may be about 1×10 21 Atom / cm 3 In some embodiments, the concentration of Ge in SiGe:B may be between about 20 at.% and about 40 at.%. In addition, the concentration of Sn in GeSn:B may be between about 5 at.% and about 10 at.%. The foregoing dopants and atomic concentrations are exemplary and non-limiting. Therefore, dopants and atomic concentrations different from those provided above may be used and are within the spirit and scope of the present invention.

[0097] In some embodiments, and because of the above P A With P B Due to the gate spacing difference between the two, the etched portion of the planar portion 205 in the second region B2 is wider in both the x-direction and the y-direction than the etched portion of the fin structure 200 in the second region A2. Therefore, and due to the growth kinetics of the epitaxial layer growth, the p-type S / D epitaxial structure 135 is formed with a height higher than the n-type S / D epitaxial structure 125 as discussed above. However, due to the depth offset d between the recessed fin structure 200 and the recessed planar portion 205, the top surfaces of the p-type S / D epitaxial structures 125 and 135 grow to be the same as the n-type S / D epitaxial structures 125 and 135. Fig.28 As described above, the depth d compensates for the height difference between the p-type S / D epitaxial structures 125 and 135 to achieve Figure 3 and Fig.28 The top surface is coplanar as shown. Therefore, the depth d is substantially equal to Figure 1 The height difference H shown p and Figure 3 The depth difference D shown p .

[0098] In some embodiments, the etching processes used in operations 1920 and 1935 may be tuned to increase the distances between n-type and p-type S / D epitaxial structures 125 and 135 and their respective transistor channel regions, as described with respect to FIG. Figure 4A and Figure 4B Discussion In some embodiments, the etching process used in operations 1920 and 1935 includes isotropic and anisotropic components that can be independently tuned or turned off during the etching process.

[0099] like Fig.29A Etching processes with anisotropic and isotropic components remove material in all directions, as shown by the directional arrows in FIG. Processes with anisotropic and isotropic components produce S / D openings with sidewall profiles such as Fig.29C The S / D opening 2900 is shown. In some embodiments, the S / D opening 2900 has a sidewall angle θ ranging from about 0° to about 90°. Due to its sidewall profile, the S / D opening 2900 is formed adjacent to a channel region, which is formed under the gate structure 2205 when the transistor is turned on. Fig.29C In the embodiment of the present invention, the proximity of the S / D structure to the channel region can be defined by the horizontal distance S1 measured between the sidewall edge of the S / D opening 2900 and the channel region (e.g., the edge of the gate structure 2905). In some embodiments, the HCI effect depends on the horizontal distance S1 and is stronger for small S1 values ​​and weaker for larger S1 values.

[0100] On the other hand, an etch process without an isotropic component or an etch process with a predominantly anisotropic component preferentially removes material along the vertical direction (e.g., the z-axis), such as Fig.29B Etching processes without an isotropic component or with a predominantly anisotropic component can produce S / D openings, such as Fig.29D2. The S / D opening 2910 is shown. According to some embodiments, the S / D opening 2910 has a substantially vertical sidewall profile with a sidewall angle θ of about 90°. Due to its vertical sidewall profile, the S / D opening 2910 is spaced apart from the channel region by a horizontal distance S2 that is greater than a horizontal distance S1 (e.g., S2>S1). In some embodiments, the adjacent grain (e.g., S2-S1) that can be achieved for the n-type S / D epitaxial structure 130 is about 2.8 nm. In some embodiments, the adjacent grain (e.g., S2-S1) that can be achieved for the p-type S / D epitaxial structure 135 is about 6 nm.

[0101] As described above, by adjusting the horizontal distance between each S / D opening (e.g., as formed by operations 1920 and 1935) and the channel region, the effect of HCI on the transistors in the I / O region B can be mitigated. According to some embodiments, the etching process described in method 1900 may be different between the non-I / O region and the I / O region, so that the spacing between the S / D epitaxial structure and the channel region of the transistor can be independently controlled. In addition, method 1900 enables the formation of an S / D epitaxial structure having a coplanar top surface, and enables the manufacture of S / D contacts having substantially similar heights in the non-I / O and I / O regions of the substrate.

[0102] In some embodiments, the order of operations in method 1900 may be different from the order described above. For example, operation 1925 may be performed after operation 1935 and before operation 1940. In addition, since the fin structures in the first area A1 and the second area A2 are etched by the same amount, operations 1915 and 1930 may be performed in a single operation using one photomask. Therefore, permutations and combinations of the operations in method 1900 are possible and are within the spirit and scope of the present invention.

[0103] In some embodiments, methods 500 and 1900 are performed on the same substrate. For example, method 500 may be used to form a first I / O region and a non-I / O region on a substrate, while method 1900 may be used to form a second I / O region and a non-I / O region on a substrate. In addition, the etching process used in operations 1920 and 1935 may be adjusted to mitigate the HCI effect of the selected transistor in the second I / O region of the substrate.

[0104] Embodiments of the present invention are directed to a method for forming n-type and p-type S / D epitaxial structures having substantially coplanar top surfaces and different depths across non-I / O and I / O regions of a substrate. Thus, the S / D contacts in the non-I / O and I / O regions have substantially similar heights. In some embodiments, the above benefits are achieved by using an additional etching mask that decouples the etching process between the I / O and non-I / O regions of the substrate. In addition, the etching process can be independently controlled for n-type and p-type S / D epitaxial structures within the I / O region of the substrate. In some embodiments, the mitigation of the HCI effect can also be achieved by modulating the sidewall profile of the S / D opening in the I / O FET to increase the spacing between the S / D epitaxial structure and the channel region.

[0105] In some embodiments, a method includes forming a first region having a fin structure and a second region having a planar portion having a first height on a substrate. The method also includes forming an isolation structure on the substrate, the isolation structure covering a bottom portion of the fin structure and a bottom portion of the planar portion. In addition, the method includes forming a first gate structure on the fin structure and forming a second gate structure on the planar portion, wherein the first gate structures are spaced apart by a first spacing and the second gate structures are spaced apart by a second spacing greater than the first spacing. The method also includes: etching the fin structure between the first gate structures until the top surface of the etched fin structure is coplanar with the top surface of the isolation structure; and reducing the first height of the planar portion between the second gate structures to a second height. Finally, the method includes forming a first epitaxial structure on the etched fin portion and forming a second epitaxial structure on the etched planar portion, wherein the top surface of the first epitaxial layer is substantially coplanar with the top surface of the second epitaxial layer.

[0106] In the above method, forming the first region includes etching the substrate to form a fin structure.

[0107] In the above method, forming the second region includes etching the substrate to form a planar portion.

[0108] In the above method, etching the fin structure includes reducing a height of the fin structure to be below a second height.

[0109] In the above method, etching the fin structure includes reducing a height of the fin structure to be higher than a second height.

[0110] In the above method, reducing the first height to the second height includes etching the planar portion so that a top surface of the planar portion is located above the isolation structure.

[0111] In the above method, reducing the first height to the second height includes etching the planar portion so that a top surface of the planar portion is located below the isolation structure.

[0112] In the above method, forming the first epitaxial structure and the second epitaxial structure includes forming the first epitaxial structure to be higher than the second epitaxial structure.

[0113] In the above method, forming the first epitaxial structure and the second epitaxial structure includes forming the first epitaxial structure to be shorter than the second epitaxial structure.

[0114] In some embodiments, a structure includes a first region having a first transistor and a second region having a second transistor and a third transistor, wherein the S / D epitaxial layer of the first transistor has a first height, and the S / D epitaxial layer of the second transistor has a second height shorter than the first height. In addition, the S / D epitaxial layer of the third transistor has a third height higher than the first height, wherein top surfaces of the S / D epitaxial layers of the first, second, and third transistors are substantially coplanar.

[0115] In the above semiconductor structure, bottom surfaces of the S / D epitaxial layers of the first transistor, the second transistor and the third transistor are not coplanar.

[0116] In the above semiconductor structure, the first region includes more transistors per unit area than the second region.

[0117] In the above semiconductor structure, the first transistor includes an n-type transistor and a p-type transistor.

[0118] In the above semiconductor structure, the second transistor includes an n-type transistor, and the third transistor includes a p-type transistor.

[0119] In the above semiconductor structure, the S / D epitaxial layer of the second transistor is of n-type, and the S / D epitaxial layer of the third transistor is of p-type.

[0120] In the above semiconductor structure, the first region is a non-input / output region, and the second region is an input / output region.

[0121] In some embodiments, a method includes forming a first region having a fin structure and a second region having a planar portion on a substrate. In addition, the method includes forming a first gate structure on the fin structure and forming a second gate structure on the planar portion. The method also includes etching the fin structure between the first gate structure to form a first opening, and etching the planar portion between the second gate structure to form a second opening, wherein the second opening is larger than the first opening. Finally, the method includes forming a first epitaxial structure in the first opening and forming a second epitaxial structure in the second opening, wherein a top surface of the first epitaxial structure is substantially coplanar with a top surface of the second epitaxial structure, and a bottom surface of the first epitaxial structure is not coplanar with a bottom surface of the second epitaxial structure.

[0122] In the above method, etching the planar portion includes forming the second opening using a substantially anisotropic etching process.

[0123] In the above method, etching the planar portion includes forming the second opening to have a sidewall angle of approximately 90°.

[0124] In the above method, etching the fin structure and the planar portion includes forming the second opening to have a height different from that of the first opening.

[0125] It should be understood that the "Detailed Description" section, rather than the "Abstract" section, is intended to be used to interpret the claims. As the inventors intend, the "Abstract" section may set forth one or more but not all possible embodiments of the invention, and is therefore not intended to limit the embodiments of the invention in any way.

[0126] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first region on a substrate, the first region comprising a fin structure; forming a second region on the substrate, the second region including a planar portion having a first height; forming an isolation structure on the substrate, the isolation structure covering a bottom portion of the fin structure and a bottom portion of the planar portion; forming a first gate structure on the fin structure, the first gate structures being spaced apart by a first pitch; forming a second gate structure on the planar portion, the second gate structures being spaced apart by a second pitch greater than the first pitch; Etching the fin structure between the first gate structures until a top surface of the etched fin structure is coplanar with a top surface of the isolation structure; reducing the first height of the planar portion between the second gate structures to a second height; forming a first epitaxial structure on the etched fin structure; as well as A second epitaxial structure is formed on the etched planar portion, wherein the height of the second epitaxial structure is different from the height of the first epitaxial structure, the top surface of the etched fin structure is not coplanar with the top surface of the etched planar portion, and the depth offset between the top surface of the etched fin structure and the top surface of the etched planar portion compensates for the height difference between the first epitaxial structure and the second epitaxial structure so that the top surface of the second epitaxial structure is substantially coplanar with the top surface of the first epitaxial structure.

2. The method according to claim 1, wherein: Forming the first region includes etching the substrate to form the fin structure.

3. The method according to claim 1, wherein: Forming the second region includes etching the substrate to form the planar portion.

4. The method according to claim 1, wherein: Etching the fin structure includes reducing a height of the fin structure to below the second height.

5. The method according to claim 1, wherein: Etching the fin structure includes reducing a height of the fin structure to be above the second height.

6. The method according to claim 1, wherein: Reducing the first height to the second height includes etching the planar portion such that a top surface of the planar portion is located above the isolation structure.

7. The method according to claim 1, wherein: Reducing the first height to the second height includes etching the planar portion such that a top surface of the planar portion is located below the isolation structure.

8. The method according to claim 1, wherein: Forming the first epitaxial structure and the second epitaxial structure includes forming the first epitaxial structure to be taller than the second epitaxial structure.

9. The method according to claim 1, wherein: Forming the first epitaxial structure and the second epitaxial structure includes forming the first epitaxial structure to be shorter than the second epitaxial structure.

10. A semiconductor structure comprising: A first region having a first transistor, wherein a source / drain epitaxial layer of the first transistor has a first height; and The second region has a second transistor and a third transistor, wherein: The source / drain epitaxial layer of the second transistor has a second height shorter than the first height; and The source / drain epitaxial layer of the third transistor has a third height higher than the first height, wherein the bottom surfaces of the source / drain epitaxial layers of the first transistor, the second transistor and the third transistor are not coplanar, and the depth offset between the bottom surfaces of the source / drain epitaxial layers of the first transistor, the second transistor and the third transistor compensates for the height difference between the first height, the second height and the third height so that the top surfaces of the source / drain epitaxial layers of the first transistor, the second transistor and the third transistor are basically coplanar.

11. The semiconductor structure according to claim 10, wherein: The bottom surface of the source / drain epitaxial layer of the second transistor is higher than the bottom surface of the source / drain epitaxial layer of the first transistor, and the bottom surface of the source / drain epitaxial layer of the third transistor is lower than the bottom surface of the source / drain epitaxial layer of the first transistor.

12. The semiconductor structure according to claim 10, wherein: The first region includes more transistors per unit area than the second region.

13. The semiconductor structure according to claim 10, wherein: The first transistor includes an n-type transistor and a p-type transistor.

14. The semiconductor structure according to claim 10, wherein: The second transistor comprises an n-type transistor, and the third transistor comprises a p-type transistor.

15. The semiconductor structure according to claim 10, wherein: The source / drain epitaxial layer of the second transistor is of n-type, and the source / drain epitaxial layer of the third transistor is of p-type.

16. The semiconductor structure according to claim 10, wherein: The first area is a non-input / output area, and the second area is an input / output area.

17. A method of forming a semiconductor structure, comprising: forming a first region on a substrate, the first region comprising a fin structure; forming a second region on the substrate, the second region comprising a planar portion; forming a first gate structure on the fin structure; forming a second gate structure on the planar portion; etching the fin structure between the first gate structures to form a first opening; etching the planar portion between the second gate structures to form a second opening, wherein the second opening is larger than the first opening; forming a first epitaxial structure in the first opening; and A second epitaxial structure is formed in the second opening, wherein a bottom surface of the first epitaxial structure is not coplanar with a bottom surface of the second epitaxial structure, a height of the second epitaxial structure is different from a height of the first epitaxial structure, and a depth offset between a bottom surface of the first epitaxial structure and a bottom surface of the second epitaxial structure compensates for a height difference between the first epitaxial structure and the second epitaxial structure so that a top surface of the first epitaxial structure is substantially coplanar with a top surface of the second epitaxial structure.

18. The method according to claim 17, wherein: Etching the planar portion includes forming the second opening using an anisotropic etching process.

19. The method according to claim 17, wherein: Etching the planar portion includes forming the second opening with a sidewall angle of 90°±5%.

20. The method according to claim 17, wherein: Etching the fin structure and the planar portion includes forming the second opening to have a height different from a height of the first opening.

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