Gap filling structure and method of manufacturing the same

Abstract

The present disclosure relates to a gap filling structure and a method of manufacturing the same. A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material to a level below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material includes forming a second seam between a first portion of the second insulating material on a first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

Description

Technical Field

[0001] The present disclosure generally relates to gap filling structures and methods of manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers of material, conductive layers, and semiconductor layers over a semiconductor substrate and patterning the respective material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: patterning a trench; depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process, wherein depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench; etching the first insulating material to a level below a top of the trench; and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process, wherein depositing the second insulating material includes forming a second seam between a first portion of the second insulating material on a first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: patterning a first trench and a second trench, wherein the first trench is wider than the second trench; depositing a first material in the first trench and the second trench; etching the first material in the first trench and the second trench; and depositing a second material over the first material in the first trench and the second trench, wherein depositing the second material forms a first seam in the first trench and a second seam in the second trench, and wherein the second seam extends lower than the first seam.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first fin; a second fin; a first insulating material located between the first fin and the second fin; and a second insulating material located between the first fin and the second fin and on top of the first insulating material, wherein the first insulating material has a lower k value than the second insulating material, and wherein the interface between the first insulating material and the second insulating material is concave. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、 Figure 7G 、 Figure 7H 、 Figure 7I 、 Figure 7J 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E 、 Figure 8F 、 Figure 8G 、 Figure 8H 、 Figure 8I 、 Figure 8J 、 Figure 9 、 Figure 10 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 19A and Figure 19B are cross-sectional views of intermediate stages of manufacturing FinFETs according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatial relative terms (e.g., "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0012] Various embodiments provide a method for filling trenches and the resulting structure. The trenches may be filled with any suitable material, e.g., a low-k dielectric material, a metal oxide, a metal nitride, a pure metal, combinations thereof, etc. Filling the trenches may include one or more deposition and etch-back deposition cycles. For example, a first material may be deposited in the trenches using a conformal deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.), and the first material may be etched to a desired height. The deposition and etch-back process may be repeated until a desired material configuration is obtained. Due to the conformal deposition process, the first material may have seams that form and eventually merge as regions of the first material are deposited on the sidewalls of the trenches. In some embodiments, the etch-back process removes portions of the first material that contain the seams. Various embodiments may provide seam-free deposition via an ALD process (e.g., thermal-based ALD, plasma-assisted ALD, etc.) without post-deposition annealing, plasma bombardment, or the use of inhibitors, thereby reducing manufacturing defects.

[0013] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fin 52 protrudes above the adjacent isolation regions 56 from between the adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only the semiconductor substrate or a semiconductor substrate including the isolation regions. Further, although the fin 52 is shown as a single material continuous with the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between the adjacent isolation regions 56.

[0014] A gate dielectric layer 92 is along the sidewalls of the fin 52 and over the top surface of the fin 52, and a gate electrode 94 is located over the gate dielectric layer 92. Source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 A reference cross-section used in the subsequent figures is further shown. Cross-section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52 and in the direction of current flow between the source / drain regions 82 of the FinFET, for example. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0015] Some embodiments discussed herein are in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs), nanostructures (e.g., nanosheets, nanowires, gate-all-around, etc.) nanoscale field-effect transistors (NSFETs), etc.

[0016] Figures 2 to 19B is a cross-sectional view of an intermediate stage of manufacturing a FinFET according to some embodiments. Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、Figure 7F , Figure 7G , Figure 7H , Figure 7I , Figure 7J , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 8G , Figure 8H , Figure 8I , Figure 8J , Figure 9 and Figure 10 show the Figure 1 reference cross-section A-A shown, except for multiple fins / FinFETs. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A are shown along the Figure 1 reference cross-section A-A shown, and Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 17C , Figure 18B and Figure 19B are shown along the Figure 1 similar cross-section B-B shown, except for multiple fins / FinFETs. Figure 13C and Figure 13D are shown along the Figure 1 reference cross-section C-C shown, except for multiple fins / FinFETs.

[0017] In Figure 2In [the figure], a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, for example, a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulator layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (usually a silicon substrate or a glass substrate). Other substrates can also be used, for example, a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium phosphoarsenide; or a combination thereof.

[0018] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, for example, NMOS transistors (e.g., n-type FinFETs). The p-type region 50P can be used to form p-type devices, for example, PMOS transistors (e.g., p-type FinFETs). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P.

[0019] In Figure 3 [the figure], fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. Forming the fins 52 can further define trenches 22 between adjacent fins 52 (e.g., in region 20).

[0020] The fins can be patterned by any suitable method. For example, one or more lithography processes (including double patterning processes or multi-patterning processes) can be used to pattern the fins 52. Generally, double patterning processes or multi-patterning processes combine lithography processes and self-alignment processes, allowing the creation of patterns with, for example, smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the fins. In some embodiments, a mask (or other layer) can be retained on the fins 52.

[0021] In Figures 4A to 7J this, an insulating material 54 is formed in a trench 22 between adjacent fins 52 and over a substrate 50. Figures 4A to 7G A detailed view of a region 20 between adjacent fins 52 is shown. Referring to Figure 4A , a first insulating material 54A is deposited in the trench 22. The first insulating material 54A can be deposited by a conformal deposition process (e.g., CVD, ALD, etc.). In some embodiments, the conformal deposition process can be thermally assisted (e.g., performed above room temperature) and / or plasma assisted (e.g., performed using one or more plasma precursors) to improve the step coverage of the deposition process. In some embodiments, the first insulating material 54A can be a dielectric film, e.g., Si x O y C z N w , where x, y, z, and w are numbers greater than or equal to zero, respectively. In other embodiments, the first insulating material 54A can include C, Si, Ge, metal alloys (e.g., Al 2 O 3 , TiN, TiAlN, etc.), combinations thereof, etc. The embodiments described herein are in the context of forming a STI region by depositing and etching an insulating material. However, other embodiments can be applied to other gap filling processes (e.g., gate filling processes, damascene processes, etc.). In such embodiments, the material deposited in the trench can be a semiconductor or a metal, e.g., Si, Ge, C.

[0022] Depositing the first insulating material 54A can include conformally depositing the first insulating material 54A on sidewalls and a bottom surface of the trench 22. The deposition can continue until portions of the first insulating material 54A located on the sidewalls of the trench 22 merge together and form a seam 55A, thereby filling the trench 22. In some embodiments, as Figure 4B shown, due to manufacturing variations in the deposition process, voids 57 may also be formed along the seam 55A. It has been observed that the first insulating material 54A may be more prone to etching along the seam 55A and the voids 57. In addition, a bottom region 54A' of the first insulating material 54A may not have a seam 55A. For example, the seam 55A does not extend into the bottom region 54A' of the first insulating material 54A.

[0023] Next, in Figure 5A this, an etch-back process can be performed to recess the first insulating material 54A below the top of the fins 52. The etch-back process can include a wet etching process, a dry etching process, etc. For example, in an embodiment where the insulating material 54A includes SiOCN, CHF 3 and O 2 ; CF4 and O 2 ; and NF 3 、CH 3 F and / or CHF 3 can be used as an etchant in a dry etching process. As another example, in embodiments where the insulating material 54A includes SiOCN, HF can be used as an etchant in a wet etching process. The etch-back process can be anisotropic. In some embodiments, as Figure 5A shown, the etch-back process recesses the first insulating material 54A such that the seam 55A and any voids 57 (see Figure 4A and Figure 4B ) are removed. For example, the etch-back process can etch into the bottom region 54A' of the first insulating material 54A. In other embodiments, as Figure 5B shown, the etch-back process can leave a portion of the seam 55A and / or any voids (not explicitly shown). The amount of the first insulating material 54A removed can be controlled, for example, by controlling the duration of the etch-back process. As a result of the etch-back process, the top surface of the first insulating material 54A can be concave.

[0024] Subsequently, in Figure 6 , a second insulating material 54B can be deposited over the first insulating material 54A in the trench 22. The second insulating material 54B can be deposited by a conformal deposition process such as CVD, ALD, etc. In some embodiments, the conformal deposition process can be thermally assisted (e.g., performed above room temperature) or plasma assisted (e.g., performed using one or more plasma precursors) to improve the step coverage of the deposition process. In some embodiments, the second insulating material 54B can be a dielectric film, e.g., Si x O y C z N w , where x, y, z, and w are all numbers greater than or equal to zero. In other embodiments, the second insulating material 54B can include C, Si, Ge, metal alloys (e.g., Al 2 O 3 , TiN, TiAlN, ZrO 2 , etc.), combinations thereof, etc.

[0025] In some embodiments, the second insulating material 54B can have a different material composition from the first insulating material 54A, and the bottom surface of the second insulating material 54B can form an interface with the top surface of the first insulating material 54A. In some embodiments, the interface between the second insulating material 54B and the first insulating material 54A can be concave.

[0026] For example, the first insulating material 54A can be a low-k material (e.g., having a k value less than or equal to that of silicon dioxide, such as SiCN, SiOCN, etc.), and the second insulating material 54B can be a metal oxide or metal nitride that is more resistant to etching than the first insulating material 54A (e.g., ZrO 2 , TiN, etc.). In such an embodiment, due to the lower k value, the first insulating material 54A can be slightly porous. Thus, the first insulating material 54A can be included to reduce parasitic capacitance due to its low k value, and the second insulating material 54B can be included to protect the first insulating material 54A in subsequent processing steps (e.g., subsequent etching steps). In other embodiments, the second insulating material 54B can have the same material composition as the first insulating material 54A.

[0027] Depositing the second insulating material 54B can include conformally depositing the second insulating material 54B over the first insulating material 54A, on the sidewalls and bottom surface of the trench 22. This deposition can continue until the portions of the second insulating material 54B located on the sidewalls of the trench 22 merge together and form a seam 55B, thereby filling the trench 22. In some embodiments, voids may be formed along the seam 55B due to manufacturing variations in the deposition process. Additionally, the bottom region 54B' of the second insulating material 54B may not have a seam 55B. For example, the seam 55B does not extend into the bottom region 54B' of the second insulating material 54B.

[0028] The steps shown above in Figure 4A , Figure 5A and Figure 6 can be repeated any number of times until the desired insulating material configuration is deposited to fill the trench 22. For example, Figures 7A to 7G shows an alternative configuration of the insulating material 54 (e.g., including insulating materials 54A, 54B, 54C, 54D, 54E, and / or 54F) after one or more deposition-etch cycles according to some embodiments. In each of Figures 7A to 7G , the planarization stop line 59 indicates the level at which a subsequent planarization step (e.g., CMP) can end. Thus, any material above the planarization stop line 59 can be removed in the planarization step (e.g., see Figures 8A to 8J ), while the material below the planarization stop line 59 remains after the planarization step.

[0029] Figure 7AAn embodiment is shown in which the second insulating material 54B is recessed, the third insulating material 54C is deposited over the second insulating material 54B, the third insulating material 54C is recessed (e.g., below the seam of the third insulating material 54C), and the fourth insulating material 54D is deposited over the third insulating material 54C. Recessing the first insulating material 54A may leave a portion of the seam 55A while removing the seams from the second insulating material 54B and the third insulating material 54C. The seam 55D of the fourth insulating material 54D may terminate above the planarization stop line 59.

[0030] The material composition of the fourth insulating material 54D and / or the third insulating material 54C may be the same as or different from the material composition of the second insulating material 54B and / or the first insulating material 54A. For example, the first insulating material 54A may be a material having a relatively low k value, such as, for example, silicon dioxide, SiCN, SiOCN, etc.; the second insulating material 54B and the third insulating material 54C may be metal oxides or metal nitrides, respectively, such as, for example, ZrO 2 , TiN, etc.; and the fourth insulating material 54D may be a dielectric film, such as, for example, silicon dioxide, SiN 2 , etc. In such an embodiment, the second insulating material 54B and the third insulating material 54C may protect the underlying first insulating material 54A from defects caused by etching. Additionally, when the second insulating material 54B has the same material composition as the third insulating material 54C, an interface may not be formed between the second insulating material 54B and the third insulating material 54C. When the second insulating material 54B has a different material composition from the third insulating material 54C, an interface may be formed between the second insulating material 54B and the third insulating material 54C. In other embodiments, each of the first insulating material 54A, the second insulating material 54B, the third insulating material 54C, and the fourth insulating material 54D may have the same material composition (e.g., a low-k dielectric film). In some embodiments, the thickness of the second insulating material 54B may be in the range of about 3 nm to about 6 nm, and the combined thickness of the second insulating material 54B and the third insulating material 54C may be in the range of about 7 nm to about 13 nm.

[0031] Figure 7B An alternative embodiment is shown in which the first insulating material 54A is recessed to remove the seam 55A and the seam of the fourth insulating material 54D extends below the planarization stop line 59. The materials of the first insulating material 54A, the second insulating material 54B, the third insulating material 54C, and the fourth insulating material 54D may be similar to those described above with respect to Figure 7A the materials described above.

[0032] Figure 7CShows alternative embodiments in which each of the insulating materials 54A, 54B, 54C, 54D, 54E, and 54F is recessed or deposited so as not to form seams or to remove seams. Thus, a seamless insulating material 54 can be formed in Figure 7C without deposition annealing, high plasma bombardment processes, or inhibitors by the deposition-etch process described above, and the risk of damage due to any of these processes is avoided. The materials of the first insulating material 54A, the second insulating material 54B, the third insulating material 54C, and the fourth insulating material 54D can be similar to those described above with respect to Figure 7A Furthermore, each of the fifth insulating material 54E and the sixth insulating material 54F can be formed by a process and materials similar to those described above with respect to the second insulating material 54B.

[0033] Figure 7D Shows an embodiment in which the deposition-etch process ends at the stage described with respect to Figure 6 Figure 7E Shows an embodiment in which three insulating materials 54A, 54B, and 54C are deposited in the trench 22. The seam 55A is removed from the first insulating material 54A. The seam 55B remains in the second insulating material 54B, and a seam 55C is formed in the third insulating material 54C. The seam 55C can extend below the planarization stop line 59. A seam-free region 54C' can be provided between the seam 55C of the third insulating material 54C and the seam 55B of the second insulating material 54B. The materials of the first insulating material 54A, the second insulating material 54B, and the third insulating material 54C can be similar to those described above with respect to Figure 7A

[0034] Figure 7F Shows an embodiment in which four insulating materials 54A, 54B, 54C, and 54D are deposited in the trench 22. The seams 55A and 55B are removed from the first insulating material 54A and the second insulating material 54B. The seams 55C and 55D remain in the third insulating material 54C and the fourth insulating material 54D, respectively. The seam 55D can extend below the planarization stop line 59. The materials of the first insulating material 54A, the second insulating material 54B, the third insulating material 54C, and the fourth insulating material 54D can be similar to those described above with respect to Figure 7A

[0035] Figure 7G ​​​An embodiment is shown in which three insulating materials 54A, 54B, and 54C are deposited in trench 22. Seams 55A and 55B are removed from the first insulating material 54A and the second insulating material 54B, and seam 55C is formed in the third insulating material 54C. Seam 55C may extend beneath the planarization stop line 59. The materials of the first insulating material 54A, the second insulating material 54B, and the third insulating material 54C may be similar to those described above with respect to Figure 7A the materials described.

[0036] In Figure 3 and Figures 7A to 7G only two fins 52 are shown. Figures 7H to 7J Fins 52A, 52B, and 52C are shown, which are spaced apart by different distances. For example, the spacing between fins 52A and 52B is closer than the spacing between fins 52B and 52C. A first trench 22A is provided between fins 52A and 52B, and a second trench 22B is provided between fins 52B and 52C. The first trench 22A may be narrower than the second trench 22B, and as shown, the seam in trench 22A extends deeper than the seam in trench 22B.

[0037] For example, Figure 7H An embodiment is shown in which a first insulating material 54A and a second insulating material 54B are deposited in trenches 22A and 22B. The materials of the first insulating material 54A and the second insulating material 54B may be similar to those described above with respect to Figure 7A the materials described, and the first material 54A and the second material 54B may be formed using a process similar to that described above. For example, the first insulating material 54A may be deposited in trenches 22A and 22B, then the first insulating material may be recessed in trenches 22A and 22B, and the second insulating material 54B may be deposited over the first insulating material 54A. Recessing the first insulating material 54A may or may not include removing any seams and / or voids formed in the first insulating material 54A.

[0038] The second insulating material 54B includes a first seam 55B-1 in trench 22A and a second seam 55B-2 in trench 22B. Due to the conformal deposition process used to form the second insulating material 54B, the first seam 55B-1 may extend deeper than the second seam 55B-2. For example, the second insulating material 54B is conformally deposited and may merge at a higher location in the relatively wide trench 22B than in the relatively narrow trench 22A. As a result, the first seam 55B-1 extends lower than the second seam 55B-2. Figure 7I and Figure 7JAn alternative embodiment having three insulating materials 54A, 54B, and 54C is shown. The third insulating material 54C includes a first seam 55C-1 in the trench 22A and a second seam 55C-2 in the trench 22B. The first seam 55C-1 in the relatively narrow trench 22A extends lower than the second seam 55C-2 in the relatively wide trench 22B. The materials of the first insulating material 54A, the second insulating material 54B, and the third insulating material 54C may be similar to those described above with respect to Figure 7A and may be formed using a process similar to that described above with respect to Figure 7A . Figure 7I An embodiment is shown in which the third insulating material 54C is the topmost layer deposited in the trench 22, and Figure 7J an embodiment is shown in which a fourth insulating material 54D is deposited on top of the third insulating material 54C. The material of the fourth insulating material 54D may be similar to those described above with respect to Figure 7A .

[0039] In Figures 8A to 8J , a removal process is applied to the insulating material 54 to remove the excess insulating material 54 (e.g., including the first insulating material 54A, the second insulating material 54B, the third insulating material 54C, the fourth insulating material 54D, the fifth insulating material 54E, and / or the sixth insulating material 54F) located on top of the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be employed. The planarization process exposes the fin 52 such that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In some embodiments, the planarization process may end at the level of the planarization stop line 59 of Figures 7A to 7J . In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask such that, after the planarization process is completed, the mask or the top surfaces of the fin 52 and the insulating material 54 are flush, respectively. Figure 8A corresponds to the embodiment of Figure 7A ; Figure 8B corresponds to the embodiment of Figure 7B ; Figure 8C corresponds to the embodiment of Figure 7C ; Figure 8D corresponds to the embodiment of Figure 7D ; Figure 8E corresponds to the embodiment of Figure 7E ; Figure 8F corresponds to the embodiment of Figure 7F ; Figure 8G corresponds to the embodiment of Figure 7G ; Figure 8H corresponds to the embodiment of Figure 7H ; Figure 8I corresponds toFigure 7I Examples of; and Figure 8J Corresponding to Figure 7J Examples of.

[0040] In Figure 9 The insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 can have any of the above configurations. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 56. In addition, the top surface of the STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. An acceptable etching process can be used to recess the STI region 56, e.g., an etching process selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52). For example, oxide removal using, e.g., dilute hydrofluoric (dHF) acid can be used.

[0041] Regarding Figures 2 to 9 The process described with respect to Figure 9 is only one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form fins. In addition, in some embodiments, a heteroepitaxial structure can be used for the fins 52. For example,

[0042] Further, it may be advantageous to epitaxially grow a different material in the n-type region 50N (e.g., NMOS region) than in the p-type region 50P (e.g., PMOS region). In various embodiments, the upper portions of the fins 52 can be made of silicon germanium (Si x Ge1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, etc. are formed. For example, the available materials for forming group III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0043] Further, in Figure 9 , appropriate wells (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well can be formed in the n-type region 50N, and an N well can be formed in the p-type region 50P. In some embodiments, a P well or an N well is formed in both the n-type region 50N and the p-type region 50P.

[0044] In embodiments with different well types, photoresist and / or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fin 52 and the STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable lithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc. implanted into this region, and their concentration is equal to or less than 10 18 cm -3 , for example, between about 10 16 cm -3 and about 10 18 cm -3 . After the implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0045] After the implantation in the p-type region 50P, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable lithography techniques. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc. implanted into this region, and their concentration is equal to or less than 10 18 cm -3 , for example, between about 1016 cm -3 and about 10 18 cm -3 Thereafter, the photoresist can be removed, for example, by an acceptable ashing process after implantation.

[0046] After implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0047] In Figure 10 , a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group including: amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials having a high etch selectivity with respect to etching of isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). For example, the mask layer 64 can include one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 62 is shown as only covering the fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 56, extends above the STI region, and between the dummy gate layer 62 and the STI region 56.

[0048] Figures 11A to 19B Various additional steps for manufacturing an exemplary device are shown. Figures 11A to 19B Features in either the n-type region 50N or the p-type region 50P are shown. For example, Figures 11A to 19B the structures shown can be applicable to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structures of the n-type region 50N and the p-type region 50P are described in the text of each figure.

[0049] In Figure 11A and Figure 11B , acceptable lithography and etching techniques can be used to pattern the mask layer 64 (see Figure 10 ) to form the mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by acceptable etching techniques to form the dummy gate 72. The dummy gate 72 covers the corresponding channel regions 58 of the fins 52. The pattern of the mask 74 can be used to separate each dummy gate 72 from adjacent dummy gate entities. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0050] Further in Figure 11A and Figure 11B , gate seal spacers 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fins 52. Thermal oxidation or deposition followed by anisotropic etching can form the gate seal spacers 80. The gate seal spacers 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0051] After forming the gate seal spacers 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments having different device types, similar to the implantations discussed above in Figure 9 , a mask (e.g., photoresist) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 52 in the p-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 52 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have an impurity concentration ranging from about 10 15 cm -3 to about 10 19 cm -3 . Annealing can be used to repair implantation damage and activate the implanted impurities.

[0052] In Figure 12A and Figure 12BIn [description], gate spacers 86 are formed on the gate seal spacers 80 along the sidewalls of the dummy gates 72 and the mask 74. The gate spacers 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.

[0053] Note that the above disclosure generally describes the processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be utilized, different step sequences can be employed (e.g., the gate seal spacers 80 may not be etched before forming the gate spacers 86, resulting in "L-shaped" gate seal spacers), spacers can be formed and removed, etc. Additionally, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region of the n-type device can be formed before forming the gate seal spacers 80, while the LDD region of the p-type device can be formed after forming the gate seal spacers 80.

[0054] In Figure 13A and Figure 13B In [description], epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is disposed between a corresponding adjacent pair of the epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 can extend into the fins 52 and can also penetrate through the fins 52. In some embodiments, the gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gates of the resulting FinFET. The material of the epitaxial source / drain regions 82 can be selected to apply stress in the corresponding channel regions 58, thereby improving performance.

[0055] The epitaxial source / drain regions 82 in the n-type region 50N can be formed as follows: Mask the p-type region 50P and etch the source / drain regions of the fins 52 in the n-type region 50N to form recesses in the fins 52. Then, the epitaxial source / drain regions 82 in the n-type region 50N are epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include any acceptable material, e.g., a material suitable for an n-type FinFET. For example, if the fins 52 are silicon, the epitaxial source / drain regions 82 in the n-type region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, etc. The epitaxial source / drain regions 82 in the n-type region 50N can have a surface that protrudes from the corresponding surface of the fins 52 and can have facets.

[0056] The epitaxial source / drain regions 82 in the p-type region 50P can be formed as follows: mask the n-type region 50N and etch the source / drain regions of the fins 52 in the p-type region 50P to form recesses in the fins 52. Then, epitaxially grow the epitaxial source / drain regions 82 in the p-type region 50P in the recesses. The epitaxial source / drain regions 82 can include any acceptable material, e.g., a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the p-type region 50P can include a material that applies compressive strain in the channel region 58, e.g., silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the p-type region 50P can have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0057] The epitaxial source / drain regions 82 and / or the fins 52 can be implanted with dopants to form the source / drain regions, similar to the process discussed previously for forming lightly doped source / drain regions, and then annealed. The source / drain regions can have an impurity concentration between about 10 19 cm -3 to about 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be in-situ doped during growth.

[0058] As a result of the epitaxial process for forming the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as Figure 13C shown. In other embodiments, the adjacent source / drain regions 82 remain separate after the epitaxial process is completed, as Figure 13D shown. In the embodiments shown in Figure 13C and Figure 13D , the gate spacers 86 are formed to cover a portion of the sidewalls of the fins 52 that extends above the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch for forming the gate spacers 86 can be adjusted to remove the spacer material to allow the region of epitaxial growth to extend to the surface of the STI region 56.

[0059] In Figure 14A and Figure 14B , a first interlayer dielectric (ILD) 88 is deposited on Figure 13A and Figure 13BOn top of the structure shown. The first ILD 88 can be formed of a dielectric material and deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, mask 74, and gate spacers 86. The CESL 87 can include a dielectric material having a lower etch rate than the material of the first ILD 88 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0060] In Figure 15A and Figure 15B it is possible to perform a planarization process (e.g., CMP) to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or mask 74. This planarization process can also remove the mask 74 on the dummy gate 72 and portions of the gate seal spacers 80 and gate spacers 86 along the sidewalls of the mask 74. After this planarization process, the top surfaces of the dummy gate 72, gate seal spacers 80, gate spacers 86, and the first ILD 88 are flush. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0061] In Figure 16A and Figure 16BIn (one or more) etching steps, dummy gate 72 and mask 74 (if present) are removed to form recess 90. The portion of dummy dielectric layer 60 located in recess 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by recess 90. In some embodiments, dummy dielectric layer 60 is removed from recess 90 in a first region of the die (e.g., the core logic region) and remains in recess 90 in a second region of the die (e.g., the input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etch dummy gate 72 and etch little or no first ILD 88 or gate spacer 86. Each recess 90 exposes and / or overlies channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, dummy dielectric layer 60 may be used as an etch stop layer when etching dummy gate 72. Dummy dielectric layer 60 may then optionally be removed after removing dummy gate 72.

[0062] In Figure 17A and Figure 17B therein, a gate dielectric layer 92 and a gate electrode 94 are formed for replacing the gate. Figure 17C shows Figure 17B a detailed view of region 89. Gate dielectric layer 92 may include one or more layers deposited in recess 90, e.g., on the top surface and sidewalls of fins 52, and on the sidewalls of gate seal spacers 80 / gate spacers 86. Gate dielectric layer 92 may also be formed on the top surface of first ILD 88. In some embodiments, gate dielectric layer 92 includes one or more dielectric layers, e.g., one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, gate dielectric layer 92 includes an interface layer of silicon oxide formed by thermal oxidation or chemical oxidation, and a high-k dielectric material thereon, e.g., a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. The method of forming gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of dummy dielectric layer 60 remains in recess 90, gate dielectric layer 92 includes the material of dummy dielectric layer 60 (e.g., SiO 2 )).

[0063] The gate electrode 94 is deposited separately over the gate dielectric layer 92 and fills the remainder of the recess 90. The gate electrode 94 may include a metal-containing material, e.g., titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single-layer gate electrode 94 is shown in Figure 17B the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and a fill material 94C, as shown in Figure 17C . After filling the recess 90, a planarization process such as CMP may be performed to remove the excess material of the gate electrode 94 and the gate dielectric layer 92 that extends above the top surface of the first ILD 88. The remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0064] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P may occur simultaneously such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 may occur simultaneously such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by different processes such that the gate dielectric layer 92 may be different materials, and / or the gate electrode 94 in each region may be formed by different processes such that the gate electrode 94 may be different materials. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0065] In Figure 18A and Figure 18B , a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask may be disposed between opposite portions of the gate spacer 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack such that a recess is formed directly above the gate stack and between the opposite portions of the gate spacer 86. The gate mask 96 includes one or more dielectric materials, e.g., silicon nitride, silicon oxynitride, etc., filled in the recess, and then a planarization process is performed to remove the excess dielectric material that extends above the first ILD 88.

[0066] Also as shown in Figure 18A and Figure 18BAs shown, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable process such as CVD and PECVD. The subsequently formed gate contact 110( Figure 19A and Figure 19B ) passes through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0067] In Figure 19A and Figure 19B , according to some embodiments, the gate contact 110 and the source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. Openings for the source / drain contact 112 are formed through the first ILD 88 and the second ILD 108, and openings for the gate contact 110 are formed through the second ILD 108 and the gate mask 96. These openings can be formed using acceptable lithography and etching techniques. Liners (not shown) such as diffusion barrier layers, adhesion layers, etc., and conductive materials are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 can be formed by different processes or can be formed by the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 can be formed in different cross-sections, which can avoid short-circuiting of the contacts.

[0068] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, etc.) field-effect transistors (NSFETs). In an NSFET embodiment, the fin is replaced by a nanostructure formed by patterning a stack of alternating layers of a channel layer and a sacrificial layer. The dummy gate stack and source / drain regions are formed in a manner similar to the above embodiments. After removing the dummy gate stack, the sacrificial layer can be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to the above embodiments, the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to the above embodiments. The nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0069] Various embodiments provide a method for filling trenches and the resulting structure. The trenches can be filled with any suitable material, e.g., a low-k dielectric material, a metal oxide, a metal nitride, a pure metal, combinations thereof, etc. Filling the trenches can include one or more deposition and etch-back deposition cycles. For example, a first material can be deposited in the trenches using a conformal deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.), and the first material can be etched to a desired height. The deposition and etch-back process can be repeated until a desired material configuration is obtained. Due to the conformal deposition process, the first material may have seams that form and eventually merge as regions of the first material are deposited on the sidewalls of the trenches. In some embodiments, the etch-back process removes portions of the first material that contain the seams. Various embodiments can provide seam-free deposition via an ALD process (e.g., thermal-based ALD, plasma-assisted ALD, etc.) without deposition annealing, plasma bombardment, or the use of inhibitors, thereby reducing manufacturing defects.

[0070] In some embodiments, a method includes: patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material includes forming a second seam between a first portion of the second insulating material on a first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench. Optionally, in some embodiments, etching the first insulating material includes removing the first seam. Optionally, in some embodiments, after etching the first insulating material, a portion of the first seam remains. Optionally, in some embodiments, depositing the first insulating material further includes defining a void along the first seam. Optionally, in some embodiments, the first insulating material has a lower k value than the second insulating material. Optionally, in some embodiments, the second insulating material includes a metal oxide or a metal nitride. Optionally, in some embodiments, the method further includes: etching the second insulating material below a top of the trench; and depositing a third insulating material over the second insulating material and in the trench using a conformal deposition process, wherein depositing the third insulating material includes forming a third seam between a first portion of the third insulating material on a first sidewall of the trench and a second portion of the third insulating material on a second sidewall of the trench. Optionally, in some embodiments, the method further includes: etching the third insulating material below a top of the trench; depositing a fourth insulating material over the third insulating material and in the trench; and planarizing the fourth insulating material. Optionally, in some embodiments, the third insulating material has the same material composition as the second insulating material.

[0071] In some embodiments, a method includes: patterning a first trench and a second trench, wherein the first trench is wider than the second trench; depositing a first material in the first trench and the second trench; etching the first material in the first trench and the second trench; and depositing a second material over the first material in the first trench and the second trench, wherein depositing the second material forms a first seam in the first trench and a second seam in the second trench, and wherein the second seam extends lower than the first seam. Optionally, in some embodiments, the first material is Si x O y C z N wan insulating material, wherein x, y, z, and w are each numbers greater than or equal to zero. Optionally, in some embodiments, the second material comprises a metal oxide or a metal nitride. Optionally, in some embodiments, etching the first material comprises removing seams of the first material. Optionally, in some embodiments, the method further comprises: etching the second material in the first trench and the second trench; and depositing a third material over the second material in the first trench and the second trench, wherein depositing the third material forms a third seam in the first trench and a fourth seam in the second trench, and wherein the fourth seam extends lower than the third seam. Optionally, in some embodiments, etching the second material removes the first seam and the second seam.

[0072] In some embodiments, a device comprises: a first fin; a second fin; a first insulating material located between the first fin and the second fin; and a second insulating material located between the first fin and the second fin and over the first insulating material, wherein the first insulating material has a lower k value than the second insulating material, and wherein the interface between the first insulating material and the second insulating material is concave. Optionally, in some embodiments, the first insulating material does not have any seams. Optionally, in some embodiments, the first insulating material comprises seams. Optionally, in some embodiments, the device further comprises a third fin on a side of the first fin opposite the second fin, wherein the first insulating material and the second insulating material are also disposed between the third fin and the first fin, and wherein the second insulating material further comprises: a third seam located between the first fin and the second fin; and a fourth seam located between the first fin and the third fin, wherein the fourth seam extends lower than the third seam. Optionally, in some embodiments, the distance between the first fin and the second fin is greater than the distance between the first fin and the third fin.

[0073] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0074] Example 1 is a method for forming a semiconductor device, including: patterning a trench; depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process, wherein depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench; etching the first insulating material to a level lower than a top of the trench; and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process, wherein depositing the second insulating material includes forming a second seam between a first portion of the second insulating material on a first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

[0075] Example 2 is the method of Example 1, wherein etching the first insulating material includes removing the first seam.

[0076] Example 3 is the method of Example 1, wherein after etching the first insulating material, a portion of the first seam remains.

[0077] Example 4 is the method of Example 1, wherein depositing the first insulating material further includes defining a void along the first seam.

[0078] Example 5 is the method of Example 1, wherein the first insulating material has a lower k value than the second insulating material.

[0079] Example 6 is the method of Example 5, wherein the second insulating material includes a metal oxide or a metal nitride.

[0080] Example 7 is the method of Example 1, further including: etching the second insulating material to a level lower than a top of the trench; and depositing a third insulating material over the second insulating material and in the trench using a conformal deposition process, wherein depositing the third insulating material includes forming a third seam between a first portion of the third insulating material on a first sidewall of the trench and a second portion of the third insulating material on a second sidewall of the trench.

[0081] Example 8 is the method of Example 7, further including: etching the third insulating material to a level lower than a top of the trench; depositing a fourth insulating material over the third insulating material and in the trench; and planarizing the fourth insulating material.

[0082] Example 9 is the method of Example 8, wherein the third insulating material has the same material composition as the second insulating material.

[0083] Example 10 is a method for forming a semiconductor device, comprising: patterning a first trench and a second trench, wherein the first trench is wider than the second trench; depositing a first material in the first trench and the second trench; etching the first material in the first trench and the second trench; and depositing a second material over the first material in the first trench and the second trench, wherein depositing the second material forms a first seam in the first trench and a second seam in the second trench, and wherein the second seam extends lower than the first seam.

[0084] Example 11 is the method of Example 10, wherein the first material is an insulating material comprising Si x O y C z N w where x, y, z, and w are each numbers greater than or equal to zero.

[0085] Example 12 is the method of Example 10, wherein the second material comprises a metal oxide or a metal nitride.

[0086] Example 13 is the method of Example 10, wherein etching the first material comprises removing the seams of the first material.

[0087] Example 14 is the method of Example 10, further comprising: etching the second material in the first trench and the second trench; and depositing a third material over the second material in the first trench and the second trench, wherein depositing the third material forms a third seam in the first trench and a fourth seam in the second trench, and wherein the fourth seam extends lower than the third seam.

[0088] Example 15 is the method of Example 14, wherein etching the second material removes the first seam and the second seam.

[0089] Example 16 is a semiconductor device, comprising: a first fin; a second fin; a first insulating material located between the first fin and the second fin; and a second insulating material located between the first fin and the second fin and over the first insulating material, wherein the first insulating material has a lower k value than the second insulating material, and wherein the interface between the first insulating material and the second insulating material is concave.

[0090] Example 17 is the device of Example 16, wherein the first insulating material has no seams.

[0091] Example 18 is the device of Example 16, wherein the first insulating material comprises seams.

[0092] Example 19 is the device described in Example 16, further comprising a third fin, the third fin being located on a side of the first fin opposite to the second fin, wherein the first insulating material and the second insulating material are further disposed between the third fin and the first fin, and wherein the second insulating material further comprises: a third seam located between the first fin and the second fin; and a fourth seam located between the first fin and the third fin, wherein the fourth seam extends lower than the third seam.

[0093] Example 20 is the device described in Example 19, wherein the distance between the first fin and the second fin is greater than the distance between the first fin and the third fin.

Claims

1. A method for forming a semiconductor device, comprising: patterning a trench; depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process, wherein depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench; etching the first insulating material to a level below a top of the trench, wherein etching the first insulating material includes removing the first seam; depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process, wherein depositing the second insulating material includes forming a second seam between a first portion of the second insulating material on a first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench; and etching the second insulating material to a level below a top of the trench, wherein etching the second insulating material includes removing the second seam.

2. The method according to claim 1, wherein, depositing the first insulating material further includes defining a void along the first seam.

3. The method according to claim 1, wherein, the first insulating material has a lower k value than the second insulating material.

4. The method according to claim 3, wherein, the second insulating material includes a metal oxide or a metal nitride.

5. The method according to claim 1, further comprising: depositing a third insulating material over the second insulating material and in the trench using a conformal deposition process, wherein depositing the third insulating material includes forming a third seam between a first portion of the third insulating material on a first sidewall of the trench and a second portion of the third insulating material on a second sidewall of the trench.

6. The method according to claim 5, further comprising: etching the third insulating material to a level below a top of the trench; depositing a fourth insulating material over the third insulating material and in the trench; and planarizing the fourth insulating material.

7. The method according to claim 6, wherein, the third insulating material has the same material composition as the second insulating material.

8. A method for forming a semiconductor device, comprising: patterning a first trench and a second trench, wherein the first trench is wider than the second trench; Deposit a first material in the first trench and the second trench, wherein the first material is an insulating material including Si x O y C z N w , where x, y, z, and w are each numbers greater than or equal to zero; etching a first material in the first trench and the second trench; and depositing a second material over the first material in the first trench and the second trench, wherein depositing the second material forms a first seam in the first trench and a second seam in the second trench, and wherein the second seam extends lower than the first seam.

9. The method according to claim 8, wherein, the second material includes a metal oxide or a metal nitride.

10. The method according to claim 8, wherein, etching the first material includes removing a seam of the first material.

11. The method according to claim 8, further comprising: Etch the second material in the first trench and the second trench; and Deposit a third material over the second material in the first trench and the second trench, wherein depositing the third material forms a third seam in the first trench and a fourth seam in the second trench, and wherein the fourth seam extends lower than the third seam.

12. The method according to claim 11, wherein, Etching the second material removes the first seam and the second seam.

13. A semiconductor device, comprising: A first fin; A second fin; A first insulating material located between the first fin and the second fin; and A second insulating material located between the first fin and the second fin and over the first insulating material, wherein the first insulating material has a lower k value than the second insulating material, and wherein the interface between the first insulating material and the second insulating material is concave and the interface continuously extends from the sidewall of the first fin to the sidewall of the second fin.

14. The device according to claim 13, wherein, The first insulating material has no seams.

15. The device according to claim 13, wherein, The first insulating material includes seams.

16. The device according to claim 13, further comprising a third fin located on a side of the first fin opposite to the second fin, wherein, The first insulating material and the second insulating material are also disposed between the third fin and the first fin, and wherein the second insulating material further includes: A third seam located between the first fin and the second fin; and A fourth seam located between the first fin and the third fin, wherein the fourth seam extends lower than the third seam.

17. The device according to claim 16, wherein, The distance between the first fin and the second fin is greater than the distance between the first fin and the third fin.

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