Magnetic tunnel junction device and method

Abstract

The present disclosure relates to magnetic tunnel junction devices and methods. In an embodiment, a device includes a magnetoresistive random access memory cell, the magnetoresistive random access memory cell including: a bottom electrode; a reference layer located on the bottom electrode; a tunnel barrier layer located on the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer located on the tunnel barrier layer, the free layer having a smaller coercivity than the reference layer; a cap layer located on the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher oxygen atomic concentration and a smaller magnesium atomic concentration than the first composition of magnesium and oxygen; and a top electrode located on the cap layer.

Description

Technical Field

[0001] The present disclosure relates to magnetic tunnel junction devices and methods. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications such as radios, televisions, cell phones, and personal computing devices. One type of semiconductor memory is magnetoresistive random access memory (MRAM), which involves spintronic devices that combine semiconductor technology with magnetic materials and devices. The spin of electrons, through their magnetization, is used to represent bits of code. MRAM cells typically include a magnetic tunnel junction (MTJ) element, which includes two ferromagnets separated by a thin insulator. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate including an active device; a first intermetallic dielectric (IMD) layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode located above the first conductive feature; a magnetic tunnel junction element, comprising: a reference layer located above the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer comprising magnesium oxide; a free layer located above the tunnel barrier layer; and a cap layer located above the free layer, the cap layer comprising magnesium oxide, the magnesium oxide of the cap layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode located above the cap layer; a second IMD layer located above the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a magnetoresistive random access memory cell, comprising: a bottom electrode; a reference layer located above the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer located above the tunnel barrier layer, the free layer having a smaller coercive force than the reference layer; a cap layer located above the free layer, the cap layer comprising a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher oxygen atomic concentration and a smaller magnesium atomic concentration than the first composition of magnesium and oxygen; and a top electrode located above the cap layer.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a bottom electrode layer on a substrate; forming a ground layer on the bottom electrode layer; forming a seed layer on the ground layer; forming a reference layer on the seed layer; sputtering magnesium oxide by radio frequency (RF) sputtering to form a tunnel barrier layer on the reference layer; forming a free layer on the tunnel barrier layer; forming a cap layer on the free layer by repeatedly depositing and oxidizing magnesium; forming a top electrode layer on the cap layer; and patterning the top electrode layer, the cap layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of a semiconductor device according to some embodiments.

[0008] Figure 2 is a cross-sectional view of a semiconductor device according to some embodiments.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments.

[0010] Fig.19 is a flow chart of an example method for fabricating a semiconductor device according to some embodiments.

[0011] Fig. 20 is a block diagram of the processing tool.

[0012] Fig.21is a flowchart of an example method for fabricating a semiconductor device according to some other embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] According to some embodiments, a perpendicular magnetic tunnel junction (MTJ) element is formed by a cap layer of fully oxidized magnesium. Full oxidation of the cap layer is accomplished by forming the cap layer by repeated deposition and oxidation of multiple conductive sublayers. Deposition may be performed by direct current (DC) sputtering or atomic layer deposition (ALD), which results in the cap layer having a higher oxide concentration than radio frequency (RF) sputtering. Forming the MTJ element by a cap layer of fully oxidized magnesium allows the perpendicular magnetic anisotropy (PMA) of the MTJ element to be increased, thereby allowing the write error rate (WER) and read error rate (RER) of the resulting magnetoresistive random access memory (MRAM) cell to be improved.

[0016] Figure 15 is a block diagram of a semiconductor device 50 according to some embodiments. The semiconductor device 50 includes an MRAM array 52, a row decoder 54, and a column decoder 56. The MRAM array 52 includes MRAM cells 58 arranged in rows and columns. The row decoder 54 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc. During operation, the row decoder 54 selects the desired MRAM cell 58 in a row by activating the corresponding word line WL of the row of the MRAM array 52. ​​The column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc., and may include a write driver, a sense amplifier, a combination thereof, etc. During operation, the column decoder 56 selects the bit line BL of the desired MRAM cell from the column of the MRAM array 52 in the selected row, and reads data from the selected MRAM cell 58 or writes data to the selected MRAM cell 58 using the bit line BL.

[0017] Figure 2 is a cross-sectional view of a semiconductor device 50 according to some embodiments. Figure 2 5 is a simplified view, and some features of the semiconductor device 50 (discussed below) are omitted for clarity of illustration. The semiconductor device 50 includes a logic region 50L and a memory region 50M. Memory devices (e.g., MRAM) are formed in the memory region 50M, and logic devices (e.g., logic circuits) are formed in the logic region 50L. For example, the MRAM array 52 (see Figure 1 ) may be formed in the memory region 50M, and a row decoder 54 and a column decoder 56 (see Figure 1 ) may be formed in the logic region 50L. The logic region 50L may occupy most of the area of ​​the semiconductor device 50. For example, the logic region 50L may occupy 95% to 99% of the area of ​​the semiconductor device 50, and the memory region 50M occupies the remaining area of ​​the semiconductor device 50. The memory region 50M may be disposed at the edge of the logic region 50L, or the logic region 50L may surround the memory region 50M.

[0018] The logic region 50L and the memory region 50M are formed on the same substrate (e.g., semiconductor substrate 60). The semiconductor substrate 60 may be doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 60 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0019] Devices 62 are formed at the active surface of semiconductor substrate 60. Devices 62 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors, etc. formed by any suitable formation method. Devices 62 are interconnected to form memory devices and logic devices of semiconductor device 50. For example, some of devices 62 may be access transistors of MRAM cell 58.

[0020] One or more interlayer dielectric (ILD) layers 64 are formed on the semiconductor substrate 60, and conductive features (e.g., contact plugs 66) are formed to be physically and electrically coupled to the device 62. The ILD layer(s) 64 may be formed of any suitable dielectric material, such as: an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a nitride, such as silicon nitride; etc. The ILD layer(s) may be formed by any suitable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or a combination thereof. The conductive features in the ILD layer(s) may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), etc., or a combination thereof.

[0021] The interconnect structure 68 is formed on the semiconductor substrate 60, such as on the (one or more) ILD layers 64. The interconnect structure 68 interconnects the devices 62 to form an integrated circuit in each of the logic region 50L and the memory region 50M. The interconnect structure 68 includes a plurality of metallization layers M1-M6. Although six metallization layers are shown, it should be understood that more or fewer metallization layers may be included. Each of the metallization layers M1-M6 includes a metallization pattern in a dielectric layer. The metallization pattern is electrically coupled to the device 62 of the semiconductor substrate 60, and includes metal lines L1-L6 and vias V1-V6 formed in one or more intermetallic dielectric (IMD) layers, respectively. The interconnect structure 68 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. In some embodiments, the contact plug 66 is also part of the metallization pattern, such as part of the lowest layer of the metal via V1.

[0022] The MRAM cells 58 of the MRAM array 52 (see Figure 1) is formed in the interconnect structure 68. The MRAM cell 58 can be formed in any of the metallization layers M1-M6 and is shown as being formed in the middle metallization layer M5. Each MRAM cell 58 includes a conductive via 110, a bottom electrode 132 on the conductive via 110, an MTJ element 134 on the bottom electrode 132, and a top electrode 136 on the MTJ element 134. Another IMD layer 108 can be formed around the MRAM cell 58, wherein the conductive via 110 extends through the IMD layer 108. A spacer 140 can also be formed around the MRAM cell 58. The IMD layer 108 and / or the spacer 140 surround and protect the components of the MRAM cell 58. The resistance of the MTJ element 134 is programmable and can be switched between high resistance (R AP ) and low resistance (R P ) changes between AP Can represent codes such as "1", R P Thus, a code can be written to the MRAM cell 58 by programming the resistance of its MTJ element 134 with the corresponding access transistor of the MRAM cell 58, and a code can be read from the MRAM cell 58 by measuring the resistance of its MTJ element 134 with the corresponding access transistor of the MRAM cell 58.

[0023] The MRAM cell 58 is electrically coupled to the device 62. The conductive via 110 is physically and electrically coupled to the underlying metallization pattern, such as coupled to the metal line L4 in the example shown. The top electrode 136 is physically and electrically coupled to the overlying metallization pattern, such as coupled to the metal via V6 in the example shown. The MRAM cell 58 is arranged in an MRAM array having rows and columns of memory. The metallization pattern includes access lines (e.g., word lines and bit lines) of the MRAM array. For example, the underlying metallization pattern (e.g., M1-M4) may include word lines arranged along the rows of the MRAM array, and the overlying metallization pattern (e.g., M6) may include bit lines arranged along the columns of the MRAM array. Some of the devices 62 (e.g., access transistors) (e.g., devices of the row decoder 54) are electrically coupled to the word lines of the MRAM array. The top electrode 136 is electrically coupled to other devices, such as devices of the column decoder 56, through the bit lines of the MRAM array.

[0024] Figures 3 to 18 5 is a diagram showing various views of intermediate stages of manufacturing a semiconductor device 50 according to some embodiments. In particular, an interconnect structure 68 (see FIG. 5 ) for the semiconductor device 50 is shown. Figure 2 As described above, the interconnect structure 68 includes the MRAM cells 58 of the MRAM array 52 (see Figure 1 ).

[0025] exist Figure 3 In the example, a metallization layer (e.g., M4, see Figure 2 ). The metallization layer includes an IMD layer 102 and a conductive feature 104 (which may correspond to a metal line L4, see Figure 2 ). The IMD layer 102 is formed on the (one or more) ILD layers 64. The IMD layer 102 can be formed of any suitable dielectric material, for example: an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a nitride, such as silicon nitride; and the like. The IMD layer 102 can be formed by any suitable deposition process, such as spin coating, PVD, chemical vapor deposition (CVD), etc. or a combination thereof. The IMD layer 102 can be a layer formed of a low-k dielectric material having a k value less than about 3.0. The IMD layer 102 can be a layer formed of an ultra-low-k (ELK) dielectric material having a k value less than 2.5.

[0026] Conductive features 104 are formed in the IMD layer 102 and are electrically coupled to the device 62. According to some embodiments, the conductive features 104 include a diffusion barrier layer and a conductive material on the diffusion barrier layer. An opening is formed in the IMD layer 102 using, for example, an etching process. The opening exposes underlying conductive features, such as underlying metal vias. The diffusion barrier layer may be formed of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, etc., and may be formed in the opening by a deposition process such as atomic layer deposition (ALD), etc. The conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, etc., and may be formed on the diffusion barrier layer in the opening by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In an embodiment, the conductive material is copper, and the diffusion barrier layer is a thin barrier layer that prevents copper from diffusing into the IMD layer 102. After the diffusion barrier layer and the conductive material are formed, the excess portions of the diffusion barrier layer and the conductive material may be removed by, for example, a planarization process (e.g., a chemical mechanical polishing (CMP) process). In some embodiments, conductive feature 104 is a metal line (which may correspond to metal line L4, see Figure 2 ).

[0027] An etch stop layer 106 is formed on the conductive features 104 and the IMD layer 102. The etch stop layer 106 can be formed of a dielectric material such as aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. The etch stop layer 106 can be formed by chemical vapor deposition (CVD), PVD, ALD, a spin-on dielectric process, or the like, or a combination thereof. The etch stop layer 106 can also be a composite layer formed by a plurality of different dielectric sublayers. For example, the etch stop layer 106 can include a silicon carbide sublayer and an aluminum oxide sublayer formed on the silicon carbide sublayer. The silicon carbide sublayer can be used as a bonding layer to improve the adhesion between the aluminum oxide sublayer and the IMD layer 102.

[0028] An IMD layer 108 is formed on the etch stop layer 106. In some embodiments, the IMD layer 108 is formed of tetraethyl orthosilicate (TEOS) oxide (e.g., silicon oxide deposited using, for example, a chemical vapor deposition (CVD) process with TEOS as a precursor). In some embodiments, the IMD layer 108 may be formed using PSG, BSG, BPSG, undoped silicate glass (USG), fluorosilicate glass (FSG), SiOCH, flowable oxide, porous oxide, etc., or a combination thereof. For example, the IMD layer 108 may also be formed of a low-k dielectric material having a k value of less than about 3.0. The IMD layer 108 may be formed to a thickness in the range of about 50 nm to about 150 nm.

[0029] The conductive via 110 is formed to extend through the IMD layer 108 and the etch stop layer 106. The conductive via 110 may also be referred to as a bottom via. In some embodiments, the conductive via 110 includes a conductive region 112 and a conductive barrier layer 114, which is lined with the sidewalls and bottom surface of the conductive region 112. The conductive barrier layer 114 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and combinations thereof. The conductive region 112 may be formed of a metal such as copper, aluminum, tungsten, cobalt, and alloys thereof. The formation of the conductive via 110 may include etching the IMD layer 108 and the etch stop layer 106 to form a via opening, forming a conductive barrier layer extending into the via opening, depositing a metal material on the conductive barrier layer, and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the conductive barrier layer and the metal material.

[0030] exist Figures 4 to 10 In the embodiment, multiple layers are deposited on the conductive via 110 and the IMD layer 108. Specifically, the bottom electrode layer 116, the MTJ stack 118, and the top electrode layer 120 are deposited (see Fig.10). The MTJ stack 118 is a multilayer including a ground layer 118A, a seed layer 118B, one or more reference layers 118C, a tunnel barrier layer 118D, one or more free layers 118E, a cap layer 118F, and one or more capping layers 118G. The bottom electrode layer 116, the MTJ stack 118, and the top electrode layer 120 will be patterned in subsequent processing to form the bottom electrode 132, the MTJ element 134, and the top electrode 136 of the corresponding MRAM cell 58, respectively (see Figure 2 ). Figures 4 to 10 Combination Fig.19 Describe together.

[0031] Fig.19 is a flow chart of an example method 200 for fabricating a semiconductor device 50 according to some embodiments. The method 200 may be performed by, for example, a processing tool. Fig. 20 3 is a block diagram of a processing tool 300 that can perform the method 200. The processing tool 300 includes a plurality of modules 304, 306, 308, 310, 312, 314, 316, 318, and each of the steps 202, 204, 206, 208, 210, 212, 218 of the method 200 can be performed on a wafer by some or all of the modules of the processing tool 300. The modules can be, for example, different areas or functions of the processing tool 300, and can be located in the same chamber or different chambers of the processing tool 300. Wafer processing can be in-situ, for example, between each of the steps 202, 204, 206, 208, 210, 212, 218 of the method 200, the wafer can be processed without breaking the vacuum in the processing tool 300. Each of steps 202, 204, 206, 208, 210, 212, 218 of method 200 may also be performed in situ, e.g., when the steps include depositing layers using a module, the layers may be deposited without breaking the vacuum in the module between each deposition. The vacuum may be set by a load lock 302 of a processing tool 300 that holds the wafers for processing. As discussed further below, the modules of the processing tool 300 include sputtering modules of different types (e.g., direct current (DC) and radio frequency (RF)) for performing PVD, which will be used to deposit the wafers with respect to the substrate. Figures 4 to 10 The layer.

[0032] exist Figure 4, a bottom electrode layer 116 is formed on the conductive via 110 and the IMD layer 108. The bottom electrode layer 116 is formed of a conductive material such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, etc. The bottom electrode layer 116 is conformally formed and can be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0033] The ground layer 118A is formed on the bottom electrode layer 116. The ground layer 118A is formed of a conductive material such as tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, etc. The ground layer 118A is conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0034] The seed layer 118B is formed on the ground layer 118A. The seed layer 118B is formed of a conductive material such as ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), nitrides thereof, combinations thereof, multilayers thereof, etc. The seed layer 118B is conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0035] As an example for forming the bottom electrode layer 116, the ground layer 118A, and the seed layer 118B, in step 202 of the method 200, these layers can be deposited by DC sputtering. Specifically, the DC sputtering module is used to deposit the titanium nitride layer to form the bottom electrode layer 116. The titanium nitride layer (e.g., the bottom electrode layer 116) may have a thickness in the range of about 8nm to about 12nm. Then the DC sputtering module is used to deposit the tantalum nitride layer to form the ground layer 118A. The tantalum nitride layer (e.g., the ground layer 118A) may have a thickness in the range of about 1nm to about 5nm. Then the DC sputtering module is used to deposit the ruthenium layer to form the seed layer 118B. The ruthenium layer (e.g., the seed layer 118B) may have a thickness in the range of about 2nm to about 7nm. In some embodiments, the same DC sputtering module is used to deposit each of the bottom electrode layer 116, the ground layer 118A, and the seed layer 118B. For example, each of these layers can be deposited using a DC sputtering module 304 of the processing tool 300. The DC sputtering module 304 can be a multiple-target module capable of sputtering material for each desired layer. During DC sputtering, a wafer is placed under a target and an inert gas is introduced into the DC sputtering module. DC power is applied to the target to activate the inert gas into a plasma state and bombard the target with ionized gas molecules so that atoms from the target are sputtered onto the wafer being processed. Compared to other sputtering techniques such as radio frequency (RF) sputtering, DC sputtering of conductive materials can be performed at a lower cost and a higher deposition rate.

[0036] exist Figure 5In the embodiment of the present invention, (one or more) reference layers 118C are formed on the seed layer 118B. (One or more) reference layers 118C are formed of ferromagnetic materials (e.g., cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, etc.). (One or more) reference layers 118C can be formed of multiple different ferromagnetic and non-magnetic sublayers, which can be referred to as (one or more) flux-closure layers. In some embodiments, (one or more) flux-closure layers include a hard-biasing layer, an antiparallel-coupling layer, and a reference layer. During operation, antiparallel coupling occurs on the antiparallel-coupling layer, thereby orienting the magnetization of the hard-biasing layer and the reference layer along an antiparallel direction and forming a flux closure with a small net magnetization. Therefore, the stray field emitted from the flux closure into the (one or more) free layers 118E (discussed further below) becomes sufficiently negligible so that the magnetization of the (one or more) free layers 118E can be freely switched. In other words, the free layer(s) 118E have a smaller coercivity than the flux closure layer(s).The reference layer(s) 118C are conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like.

[0037] As an example of forming (one or more) reference layers 118C, in step 204 of method 200, the layers can be deposited by DC sputtering. Specifically, a DC sputtering module is used to deposit cobalt and platinum laminates, such as [Co / Pt]×n / Co, where n represents the number of laminates, which can be in the range of about 2 to about 6, thereby forming a hard bias layer. The cobalt sublayers can each have a thickness in the range of about 0.1nm to about 0.4nm, and the platinum sublayers can each have a thickness in the range of about 0.1nm to about 0.4nm. The top cobalt sublayers of the laminates can each have a thickness in the range of about 0.4nm to about 1.2nm. A DC sputtering module is then used to deposit an iridium layer to form an antiparallel coupling layer. The iridium layer can have a thickness in the range of about 0.4nm to about 0.6nm. A DC sputtering module is then used to deposit a cobalt layer, a molybdenum layer on the cobalt layer, and an iron boron layer on the molybdenum layer to form a reference layer. The cobalt layer can have a thickness in the range of about 0.4 nm to about 0.8 nm, the molybdenum layer can have a thickness in the range of about 0.2 nm to about 0.4 nm, and the iron boron layer can have a thickness in the range of about 0.6 nm to about 1.6 nm. In some embodiments, the same DC sputtering module is used to deposit each of the (one or more) reference layers 118C, for example, each of the hard bias layer, the antiparallel coupling layer, and the reference layer. For example, each of these layers can be deposited using the DC sputtering module 306 of the processing tool 300. The DC sputtering module 306 can be a multi-target module capable of sputtering material for each desired layer. Compared to other sputtering techniques such as RF sputtering, DC sputtering of ferromagnetic materials can be performed at a lower cost and a higher deposition rate.

[0038] exist Figure 6 , a tunnel barrier layer 118D is formed on (one or more) reference layers 118C. The tunnel barrier layer 118D is formed of a dielectric material, such as magnesium oxide (MgO), aluminum nitride (AlN), aluminum oxide (AlO), combinations thereof, multilayers thereof, etc. The tunnel barrier layer 118D is conformally formed and can be formed using CVD, PVD, ALD, etc.

[0039] As an example for forming the tunnel barrier layer 118D, in step 206 of the method 200, a layer may be deposited by RF sputtering. Specifically, the RF sputtering module is used to deposit a magnesium oxide layer to form the tunnel barrier layer 118D. The magnesium oxide layer (e.g., the tunnel barrier layer 118D) may have a thickness T in the range of about 0.6 nm to about 1.2 nm. 1During RF sputtering, a wafer is placed under a target in an RF sputtering module. An inert gas flows into the RF sputtering module. RF power is applied to the target to activate the inert gas into a plasma state and bombard the target with ionized gas molecules, causing atoms from the target to be sputtered onto the wafer being processed. Each cycle of the applied RF power includes a bombardment period (in which the target material is bombarded with ions) and a cleaning period (in which electrons are attracted to the target material to clear it of ion accumulation).

[0040] In some embodiments, a bonding process is performed in an RF sputtering module before depositing the magnesium oxide layer. The bonding process can be, for example, a metal bonding process performed by sputtering a metal such as tantalum on the sidewalls of the chamber of the RF sputtering module. Sputtering metal on the surface of the chamber (e.g., on top of an undesirable dielectric material) helps reduce the negative effects that may be caused by the accumulation of undesirable dielectric materials on the inner surface of the chamber after repeated deposition steps. In addition, the sputtering metal on the surface of the chamber may induce a gettering effect, which helps to reduce the vapor pressure in the chamber, thereby improving the properties of the magnesium oxide layer. In some embodiments, the same RF sputtering module is used for both bonding the chamber and depositing the magnesium oxide layer. For example, the RF sputtering module 308 of the processing tool 300 can be used for bonding and sputtering. The RF sputtering module 308 can be a dual-target module capable of sputtering both magnesium oxide and bonding metal.

[0041] In some embodiments, magnesium oxide is deposited by bombarding a magnesium oxide target with ions. Argon gas may flow into the RF sputtering module 308 at a low flow rate (e.g., a flow rate in the range of about 20 sccm to about 35 sccm) and be activated to a plasma state. Argon gas flowing at a low flow rate may reduce the deposition rate by producing less plasma, thereby reducing the number of ions bombarding the target. The deposition rate of the RF sputtering module 308 may be lower than the deposition rate of the DC sputtering modules 304, 306, 314, 316, 318. Reducing the deposition rate and performing a cleaning cycle during RF sputtering avoids accumulation of ions on the target, which helps avoid deposition of undesirable pure magnesium byproducts. Reducing the amount of magnesium byproducts when depositing the tunnel barrier layer 118D helps produce a more efficient MTJ element 134 (see Figure 2 ) does not contain undesirable conductive materials, thereby maintaining its desired high resistance (R AP ) and low resistance (R P ) code. Therefore, the generated MTJ element 134 (see Figure 2 ) can be in the MRAM cell 58 of the MRAM array 52 (see Figure 1) is more consistent. However, when magnesium oxide is deposited by RF sputtering, the oxygen concentration of the deposited magnesium oxide layer is limited. Specifically, preferential sputtering of magnesium can occur, which results in the oxygen concentration of the tunnel barrier layer 118D being lower than the oxygen concentration of the magnesium oxide target. In some embodiments, the stoichiometric ratio of oxygen to magnesium of the magnesium oxide target is greater than the stoichiometric ratio of oxygen to magnesium of the deposited magnesium oxide layer. For example, the magnesium oxide target can have a stoichiometric ratio of oxygen to magnesium equal to about 1. Similarly, the deposited magnesium oxide layer can have a stoichiometric ratio of oxygen to magnesium less than or equal to about 1, for example in the range of about 0.95 to about 1.05. In some embodiments, the tunnel barrier layer 118D has substantially equal magnesium atomic concentrations and oxygen atomic concentrations. Insufficient oxygen during RF sputtering can result in undesirable retention of pure magnesium byproducts, which can lead to problems such as electrical shorts, PMA degradation, and the like.

[0042] Although depositing magnesium oxide by RF sputtering can reduce the amount of undesirable magnesium byproducts, the oxygen concentration of the deposited magnesium oxide layer is limited by the initial oxygen concentration of the magnesium oxide target. In some embodiments, the magnesium oxide target is oxygen-deficient, and therefore, the deposited magnesium oxide layer can have a low concentration (in atomic percentage) of oxygen and can be only partially magnesium oxide. For example, the deposited magnesium oxide layer can have a stoichiometric ratio of oxygen to magnesium less than or equal to about 1 (e.g., in the range of about 0.95 to about 1.05). In some embodiments, the tunnel barrier layer 118D has a greater concentration of magnesium atoms than oxygen atoms. In some embodiments, the tunnel barrier layer 118D has substantially equal concentrations of magnesium atoms and oxygen atoms.

[0043] Optionally, in step 208 of method 200, tunnel barrier layer 118D is annealed. Annealing may increase the thickness T of tunnel barrier layer 118D. 1 As an example of annealing, a heating module 310 of the processing tool 300 may be used to heat the wafer being processed, after which a cooling module 312 of the processing tool 300 may be used to cool the heated wafer and help speed up the process. In an embodiment, the annealing may be performed at a temperature in a range of about 350° C. to about 425° C. and for a duration in a range of about 30 minutes to about 200 minutes, which increases the thickness of the tunnel barrier layer 118D to a thickness T in a range of about 0.7 nm to about 1.0 nm. 1 When the tunnel barrier layer 118D is formed by RF sputtering, increasing its thickness can help increase the thickness of the resulting MTJ element 134 (see Figure 2 ) of high resistance (R AP ) and low resistance (R P ) states, which can improve the MRAM cell 58 (see Figure 1 )’s write error rate (WER) and read error rate (RER).

[0044] exist Figure 7 In the embodiment, (one or more) free layers 118E are formed on the tunnel barrier layer 118D. (One or more) free layers 118E are formed of a ferromagnetic material, such as cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, etc. (One or more) free layers 118E are conformally formed and can be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0045] As an example for forming (one or more) free layers 118E, in step 210 of method 200, layers can be deposited by DC sputtering. Specifically, a DC sputtering module is used to deposit a first cobalt iron boron layer, a molybdenum layer on the first cobalt iron boron layer, and a second cobalt iron boron layer on the molybdenum layer to form (one or more) free layers 118E. The first cobalt iron boron layer can have a thickness in the range of about 0.8nm to about 1.4nm, the molybdenum layer can have a thickness in the range of about 0.2nm to about 0.4nm, and the second cobalt iron boron layer can have a thickness in the range of about 0.8nm to about 1.4nm. In some embodiments, the first cobalt iron boron layer is doped with more boron than the second cobalt iron boron layer. In some embodiments, the same DC sputtering module is used to deposit each of the (one or more) free layers 118E. For example, each of these layers can be deposited using the DC sputtering module 314 of the processing tool 300. The DC sputtering module 314 can be a multi-target module capable of sputtering material for each desired layer. DC sputtering of ferromagnetic materials can be performed at lower costs and higher deposition rates than other sputtering techniques such as RF sputtering.

[0046] The magnetization of the free layer(s) 118E can be switched freely, so the resulting MTJ element 134 (see Figure 2 ) is programmable accordingly. Specifically, the resistance of the MTJ element 134 can be set to a high resistance (R AP ) and low resistance (R P When the magnetization of the free layer(s) 118E is parallel to the magnetization of the reference layer(s) 118C, the MTJ element has a low resistance (R P When the magnetization of the free layer(s) 118E is antiparallel to the magnetization of the reference layer(s) 118C, the MTJ element has a high resistance (R AP ). Therefore, the generated MTJ element 134 may also be referred to as a programmable resistance element. The MTJ element 134 is a vertical MTJ element, for example, the magnetization direction is vertical to the main surface of the semiconductor substrate 60.

[0047] exist Figure 8In the embodiment of the present invention, a cap layer 118F is formed on the free layer(s) 118E. The cap layer 118F is formed of a dielectric material, such as magnesium oxide (MgO), aluminum nitride (AlN), aluminum oxide (AlO), combinations thereof, multilayers thereof, etc. The cap layer 118F is conformally formed and can be formed using CVD, PVD, ALD, etc.

[0048] As an example for forming the cap layer 118F, in step 212 of method 200, a layer is formed by multiple DC sputtering and oxidation steps. Specifically, in step 214 of method 200, a pure magnesium sublayer is deposited using a DC sputtering module. Next, in step 216 of method 200, the deposited magnesium sublayer is oxidized in a DC sputtering module to form a magnesium oxide layer. Steps 214 and 216 are repeated for several cycles (e.g., four cycles) until the magnesium oxide layer reaches a desired thickness, thereby forming the cap layer 118F. Each step is performed in the same DC sputtering module, and, for example, between each sputtering and oxidation step, it is performed in situ without breaking the vacuum in the sputtering module. For example, a magnesium oxide layer can be deposited using a DC sputtering module 316 of a processing tool 300. The DC sputtering module 316 can be a single target module capable of sputtering magnesium oxide without contaminating other targets. Figures 9A to 9E is a cross-sectional view of an intermediate stage in the fabrication of the capping layer 118F according to some embodiments.

[0049] exist Fig.9A In the DC sputtering module, a first magnesium sublayer 118F is deposited. 1 The first magnesium sublayer 118F 1 It may be deposited to a thickness in the range of about 0.2 nm to about 0.4 nm. The first magnesium sublayer 118F is then oxidized 1 In some embodiments, the oxidation is performed by flowing oxygen into a DC sputtering module (e.g., in the first magnesium sublayer 118F) at a flow rate in the range of about 8 sccm to about 40 sccm. 1 The oxidation is carried out at a high flow rate and for a long duration to ensure that the first magnesium sublayer 118F 1 Fully oxidized, especially when the first magnesium sublayer 118F 1 When thicker.

[0050] exist Fig. 9B In the DC sputtering module, a second magnesium sublayer 118F is deposited. 2 The second magnesium sublayer 118F 2 It may be deposited to a thickness in the range of about 0.08 nm to about 0.24 nm. The second magnesium sublayer 118F is then oxidized 2In some embodiments, the oxidation is performed by flowing oxygen into a DC sputtering module (e.g., in the second magnesium sublayer 118F) at a flow rate in a range of about 1 sccm to about 20 sccm. 2 ), and lasts for a period of time ranging from about 10 seconds to about 40 seconds. It should be noted that the second magnesium sublayer 118F 2 is deposited to a depth of 118F than the first magnesium sublayer 1 Small thickness, and the second magnesium sublayer 118F 2 Compared with the first magnesium sublayer 118F 1 A smaller oxygen flow rate is used for oxidation. Because the second magnesium sublayer 118F 2 Thinner, so it is thinner than the first magnesium sublayer 118F 1 More susceptible to oxidation.

[0051] exist Fig. 9C In the DC sputtering module, a third magnesium sublayer 118F is deposited. 3 The third magnesium sublayer 118F 3 It may be deposited to a thickness in the range of about 0.08 nm to about 0.24 nm. The third magnesium sublayer 118F is then oxidized 3 In some embodiments, the oxidation is performed by flowing oxygen into a DC sputtering module (e.g., in the third magnesium sublayer 118F) at a flow rate in the range of about 1 sccm to about 20 sccm. 3 ), and lasts for a period of time ranging from about 10 seconds to about 40 seconds. It should be noted that the third magnesium sublayer 118F 3 is deposited to a depth of 118F than the first magnesium sublayer 1 Small thickness, and the third magnesium sublayer 118F 3 Compared with the first magnesium sublayer 118F 1 In some embodiments, the third magnesium sublayer 118F 3 is deposited onto the second magnesium sublayer 118F 2 The same thickness, and the third magnesium sublayer 118F 3 With the second magnesium sublayer 118F 2 The third magnesium sublayer 118F is oxidized in the same way. 3 Thinner, so it is thinner than the first magnesium sublayer 118F 1 More susceptible to oxidation.

[0052] exist Fig.9D In the DC sputtering module, a fourth magnesium sublayer 118F is deposited. 4 The fourth magnesium sublayer 118F 4 It may be deposited to a thickness in the range of about 0.08 nm to about 0.24 nm. The fourth magnesium sublayer 118F is then oxidized4 In some embodiments, the oxidation is performed by flowing oxygen into a DC sputtering module (e.g., in the fourth magnesium sublayer 118F) at a flow rate in a range of about 100 sccm to about 1000 sccm. 4 The fourth magnesium sublayer 118F is completed by lasting for a period of time ranging from about 10 seconds to about 40 seconds. 4 is deposited onto the second magnesium sublayer 118F 2 and the third magnesium sublayer 118F 3 The fourth magnesium sublayer 118F has the same thickness. 4 Compared with the first magnesium sublayer 118F 1 , the second magnesium sublayer 118F 2 and the third magnesium sublayer 118F 3 The fourth magnesium sublayer 118F is oxidized by a greater oxygen flow rate. 4 It can also be compared with the first magnesium sublayer 118F 1 , the second magnesium sublayer 118F 2 and the third magnesium sublayer 118F 3 Oxidation at a high flow rate and for a long duration helps ensure that the first magnesium sublayer 118F 1 , the second magnesium sublayer 118F 2 , the third magnesium sublayer 118F 3 and the fourth magnesium sublayer 118F 4 Fully oxidized.

[0053] exist Fig.9E In the DC sputtering module, a fifth magnesium sublayer 118F is deposited. 5 The fifth magnesium sublayer 118F 5 It may be deposited to a thickness in the range of about 0.08 nm to about 0.24 nm. Forming the fifth magnesium sublayer 118F 5 The lower layer can be protected in subsequent processing. Fifth magnesium sublayer 118F 5 Instead of being oxidized alone, it can be oxidized by the fourth magnesium sublayer 118F 4 Diffusion to oxidation.

[0054] Although the sub-layers of the capping layer 118F are discretely deposited and oxidized, the capping layer 118F is a single uniform dielectric material composition after formation. Figure 8, forming the cap layer 118F by repeated deposition and oxidation of magnesium allows fine control of the composition of the cap layer 118F, and allows the cap layer 118F to be formed using more oxygen than other deposition techniques (e.g., reactive sputtering). Specifically, the cap layer 118F can be formed of magnesium oxide having a large concentration of oxygen (in atomic percent), and can be fully magnesium oxide, or at least can be more oxidized than the tunnel barrier layer 118D. In other words, the tunnel barrier layer 118D is formed of a first composition of magnesium and oxygen, and the cap layer 118F is formed of a second composition of magnesium and oxygen, wherein the second composition has a higher oxygen atomic concentration and a smaller magnesium atomic concentration than the first composition. In an embodiment, the cap layer 118F is deposited to a thickness T in the range of about 0.4 nm to about 1.0 nm. 2 The thickness T of the cap layer 118F is 2 Less than the thickness T of the tunnel barrier layer 118D 1 . In an embodiment, the cap layer 118F has a stoichiometric ratio of oxygen to magnesium greater than about 1, for example in a range of about 1.0 to about 1.2. In other words, when the cap layer 118F is deposited using repeated deposition and oxidation, the magnesium oxide of the cap layer 118F has a greater oxygen atomic concentration than a magnesium atomic concentration. In some embodiments, the cap layer 118F has a higher oxygen atomic concentration and a lower magnesium atomic concentration than the tunnel barrier layer 118D. In other words, the cap layer 118F has a first stoichiometric ratio of oxygen to magnesium, and the tunnel barrier layer 118D has a second stoichiometric ratio of oxygen to magnesium, wherein the first stoichiometric ratio is greater than the second stoichiometric ratio. In addition, the cap layer 118F can have a uniform oxygen concentration throughout the process, or at least can have a more uniform oxygen concentration than the tunnel barrier layer 118D. Forming the cap layer 118F of full magnesium oxide allows the cap layer 118F to act as a protective layer to reduce damage to the free layer(s) 118E by etching in a subsequent process for patterning the MTJ stack 118. In addition, forming the cap layer 118F of full magnesium oxide allows the resulting MTJ element 134 (see Figure 2 ) of the MTJ element 134. Increasing the PMA of the MTJ element 134 helps to increase the high resistance (R AP ) and low resistance (R P ) states, which can improve the MRAM cell 58 (see Figure 1 )’s write error rate (WER) and read error rate (RER).

[0055] exist Fig.10In the embodiment, (one or more) capping layers 118G are formed on the capping layer 118F. (One or more) capping layers 118G are formed of a ferromagnetic material, such as cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, etc. (One or more) capping layers 118G are conformally formed and can be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0056] The top electrode layer 120 is formed on the capping layer(s) 118G. The top electrode layer 120 is formed of a conductive material, such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, etc. The top electrode layer 120 is conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, chemical plating, etc.

[0057] As an example for forming (one or more) capping layers 118G and the top electrode layer 120, in step 218 of method 200, the layers may be deposited by DC sputtering. Specifically, the DC sputtering module is used to deposit a cobalt iron boron layer, a tantalum layer on the cobalt iron boron layer, and a ruthenium layer on the tantalum layer, thereby forming (one or more) capping layers 118G. The cobalt iron boron layer may have a thickness in the range of about 0.2 nm to about 0.4 nm, the tantalum layer may have a thickness in the range of about 1.5 nm to about 4 nm, and the ruthenium layer may have a thickness in the range of about 3 nm to about 6 nm. The cobalt iron boron layer is formed between the cap layer 118F and the tantalum layer so that the resulting MTJ element 134 (see Figure 2 ) exhibits perpendicular magnetic anisotropy (PMA), thereby enhancing the polarization of conduction electrons and improving the tunnel magnetoresistance (TMR) effect.

[0058] A DC sputtering module is then used to deposit a titanium nitride layer, thereby forming a top electrode layer 120. The titanium nitride layer (e.g., top electrode layer 120) can have a thickness in the range of about 60 nm to about 100 nm. In some embodiments, the same DC sputtering module is used to deposit each of the (one or more) capping layers 118G and the top electrode layer 120. For example, a DC sputtering module 318 of the processing tool 300 can be used to deposit each of these layers. The DC sputtering module 318 can be a multi-target module capable of sputtering material for each desired layer. Compared to other sputtering techniques such as RF sputtering, DC sputtering of conductive materials and ferromagnetic materials can be performed at a lower cost and a higher deposition rate.

[0059] It should be understood that the materials and structures of the MTJ stack 118 can have many variations, which are also within the scope of the present disclosure. For example, the layers 118A, 118B, 118C, 118D, 118E, 118F, 118G can be formed in the reverse order of the above order. Thus, the (one or more) capping layers 118G can be located at the bottom of the MTJ stack 118, and the ground layer 118A can be located at the top of the MTJ stack 118.

[0060] exist Fig.11 In the embodiment of the present invention, one or more masks are formed above the top electrode layer 120. These masks will be used to pattern different layers simultaneously and form MRAM cells. In some embodiments, the one or more masks may include one or more hard masks, three-layer masks, combinations thereof, and the like. For example, a hard mask layer 122 may be formed above the top electrode layer 120, and a photosensitive mask 124 may be formed above the hard mask layer 122. In some embodiments, the hard mask layer 122 is formed of an oxide such as titanium oxide, silicon oxide, a combination thereof, and the like. The photosensitive mask 124 may be a photoresist, such as a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, and the like. The photosensitive mask 124 is formed in the memory region 50M, wherein the pattern of the photosensitive mask 124 corresponds to the pattern of the subsequently formed MRAM cell.

[0061] exist Fig.12 In the embodiment of the present invention, the photosensitive mask 124 is used as an etching mask to etch and pattern the hard mask layer 122 to form a patterned hard mask. The patterned hard mask is then used as an etching mask to etch and pattern the top electrode layer 120, the MTJ stack 118, and the bottom electrode layer 116. Patterning may include one or more etching processes, and a groove 130 may be formed in the IMD layer 108. The etching method may include a plasma etching method, such as ion beam etching (IBE). IBE has a high degree of precision (e.g., a high degree of anisotropy), which helps to control the profile of the resulting MRAM cell. Etching can be achieved using glow discharge plasma (GDP), capacitive coupled plasma (CCP), inductively coupled plasma (ICP), etc. The photosensitive mask 124 and the hard mask layer 122 may be consumed in the etching process, or may be removed after the etching process.

[0062] The etching process forms a bottom electrode 132, an MTJ element 134, and a top electrode 136, which together form an MRAM cell 58. Each MRAM cell 58 includes a bottom electrode 132, an MTJ element 134, and a top electrode 136, wherein the MTJ element 134 is disposed between the bottom electrode 132 and the top electrode 136. The bottom electrode 132 includes a remaining portion of the bottom electrode layer 116. The MTJ element 134 includes a remaining portion of the MTJ stack 118. The top electrode 136 includes a remaining portion of the top electrode layer 120. In some embodiments, the etching process partially etches the IMD layer 108 and the conductive via 110. In such an embodiment, the remaining portion of the IMD layer 108 has a sloped sidewall and has a trapezoidal shape in the cross section shown. After the etching process, the remaining portion of the IMD layer 108 in the logic region 50L may have a thickness in the range of about 3 nm to about 30 nm. The bottom electrode 132, the MTJ element 134, and the top electrode 136 may also have sloped sidewalls and have a trapezoidal shape in the cross-section shown.

[0063] exist Fig.13 , a spacer 140 is formed on the sidewalls of the MRAM cell 58. The spacer 140 surrounds and protects the components of the MRAM cell 58. Specifically, the spacer 140 is disposed around the bottom electrode 132 and the MTJ element 134, and may be disposed at least partially around the top electrode 136. The spacer 140 may be formed of an oxide (e.g., silicon oxide, aluminum oxide, etc.), a nitride (e.g., silicon nitride, aluminum nitride, etc.), a carbide (e.g., silicon carbide), a combination thereof (e.g., silicon oxynitride, silicon carbonitride, etc.), a multilayer thereof, etc.

[0064] In embodiments where the spacer 140 includes multiple layers, the spacer 140 includes a passivation layer 142, a passivation layer 144, and an oxide layer 146. As an example for forming the spacer 140, the passivation layer 142 may be conformally formed over the MRAM cell 58 and in the recess 130. In some embodiments, the passivation layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, and the like, and may be formed using CVD, plasma enhanced chemical vapor deposition (PECVD), ALD, plasma enhanced atomic layer deposition (PEALD), PVD, combinations thereof, and the like. In some embodiments, the passivation layer 142 may reduce or prevent moisture (e.g., H) from being deposited during subsequent processing. 2O) is diffused into the MRAM cell 58. The passivation layer 142 is then patterned to expose a portion of the top electrode 136. In some embodiments, the patterning is a dry etching process, such as an anisotropic etching process. The patterning removes the horizontal portion of the passivation layer 142. Subsequently, another passivation layer 144 is formed over the passivation layer 142. In some embodiments, the passivation layer 144 is formed of one of the candidate materials and methods for the passivation layer 142, but is formed of a different material than the passivation layer 142. For example, the passivation layer 142 may be formed of an oxide (e.g., silicon oxide), and the passivation layer 144 may be formed of a nitride (e.g., silicon nitride). An oxide layer 146 is then formed over the passivation layer 144. In some embodiments, the oxide layer 146 may include silicon oxide, etc., and may be formed using CVD, PECVD, ALD, PEALD, combinations thereof, etc. Subsequently, one or more dry etching processes are performed to etch the passivation layer 144 and the oxide layer 146 and expose a portion of the top electrode 136. In some embodiments, the one or more dry etching processes are anisotropic etching processes and remove horizontal portions of oxide layer 146. Remaining portions of passivation layer 142, passivation layer 144, and oxide layer 146 form spacers 140. IMD layer 108 in logic region 50L is exposed after patterning spacers 140.

[0065] exist Fig.14 In the embodiment of the present invention, an IMD layer 150 is formed on the spacer 140, the MRAM cell 58, and the IMD layer 108. The IMD layer 150 is disposed on and around the spacer 140, and is disposed on and around the top electrode 136. In some embodiments, the IMD layer 150 is formed using materials and methods similar to those of the IMD layer 108. An anti-reflective layer 152 is then formed on the IMD layer 150. The anti-reflective layer 152 may be a nitrogen-free anti-reflective layer (NFARL) and may be formed of a nitrogen-free dielectric material (e.g., silicon oxycarbide). The IMD layer 150 and the anti-reflective layer 152 will be used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0066] exist Fig.15 In the embodiment of the present invention, the anti-reflective layer 152, the IMD layer 150 and the IMD layer 108 are patterned to expose the etch stop layer 106 in the logic region 50L. In some embodiments, the patterning process may include a suitable photolithography and etching process. After the patterning process, the anti-reflective layer 152 and the IMD layer 150 are retained in the memory region 50M.

[0067] exist Fig.16In the embodiment, an IMD layer 160 is formed over the etch stop layer 106 and the remaining portions of the anti-reflective layer 152, the IMD layer 150, and the IMD layer 108. The IMD layer 160 is adjacent to the IMD layers 108, 150. In some embodiments, the IMD layer 160 is formed using materials and methods similar to those of the IMD layer 108. An anti-reflective layer 162 is then formed over the IMD layer 160. In some embodiments, the anti-reflective layer 162 is formed using materials and methods similar to those of the anti-reflective layer 152.

[0068] exist Fig.17 In the embodiment, the conductive feature 164 is formed in the IMD layer 160 and the etch stop layer 106. The conductive feature 164 may include a conductive line 164L and a conductive via 164V, and is formed in the logic region 50L. The memory region 50M may not have the conductive feature 164. The conductive feature 164 may be formed by a suitable method, such as a damascene process. Example damascene processes include a single damascene process, a dual damascene process, and the like. In some embodiments, the opening for the conductive feature 164 is formed by a via-first process. In other embodiments, the opening for the conductive feature 164 is formed by a trench-first process. Suitable photolithography and etching techniques may be used to form the opening. Subsequently, the opening is filled with a suitable conductive material (e.g., copper, aluminum, a combination thereof, etc.). Next, a planarization process (e.g., a CMP process) is performed to remove excess material above the memory region 50M and expose the top electrode 136. In some embodiments, the top surface of the top electrode 136 is coplanar with the top surface of the conductive feature 164 after planarization. In some embodiments, the planarization process completely removes the anti-reflective layer 162 (see Fig.16 Although each conductive via 164V and corresponding conductive line 164L are shown as separate elements, it should be understood that each conductive via 164V and corresponding conductive line 164L may be a continuous conductive feature in embodiments where, for example, they are formed by a dual damascene process.

[0069] exist Fig.18 In the embodiment, another metallization layer (e.g., M6, see Figure 2 ). The metallization layer includes an etch stop layer 170, an IMD layer 172, and a conductive feature 174. The conductive feature 174 includes a conductive via 174V (which may correspond to a metal via V6, see Figure 2 ) and conductive line 174L (which may correspond to metal line L6, see Figure 2). Conductive feature 174 is formed in both logic region 50L and memory region 50M. In some embodiments, etch stop layer 170 is formed using materials and methods similar to etch stop layer 106. In some embodiments, IMD layer 172 is formed using materials and methods similar to IMD layer 160. In some embodiments, conductive feature 174 is formed using materials and methods similar to conductive feature 164. Conductive feature 174 is electrically coupled to a memory device (e.g., MRAM) formed in memory region 50M and a logic device (e.g., logic circuit) formed in logic region 50L. Specifically, conductive feature 174 is physically and electrically coupled to conductive feature 164 and top electrode 136. In some embodiments, conductive feature 174 electrically couples the memory device to the logic device. For example, conductive feature 174 can be used to electrically couple some of conductive features 164 to some of top electrodes 136, such as in the metallization layer shown or in another metallization layer. Although each conductive via 174V and corresponding conductive line 174L are illustrated as separate elements, it is understood that each conductive via 174V and corresponding conductive line 174L may be a continuous conductive feature in embodiments where, for example, they are formed by a dual damascene process.

[0070] Fig.21 4 is a flow chart of an exemplary method 400 for manufacturing a semiconductor device 50 according to some other embodiments. The method 400 includes steps 402, 404, 406, 408, 410, 418, which are similar to steps 202, 204, 206, 208, 210, 218 of the method 200 (see Fig.19 In this embodiment, the cap layer 118F is also deposited in step 412 by multiple deposition and oxidation steps (see Figures 9A to 9E ), however, ALD is used instead of DC sputtering for deposition. Specifically, in step 414, a pure magnesium sublayer is deposited using an ALD module. Next, in step 416, the deposited magnesium sublayer is oxidized in the ALD module to form a magnesium oxide layer. Steps 414 and 416 may be repeated until the magnesium oxide layer reaches a desired thickness, thereby forming the cap layer 118F. Depositing the magnesium sublayer by ALD in step 414 may provide a final thickness T of the cap layer 118F. 2 (See Figure 8 ) for finer control.

[0071] Embodiments can achieve advantages. Forming the cap layer 118F by repeated deposition and oxidation allows the cap layer 118F to be formed of magnesium oxide having a high concentration of oxygen. In some embodiments, the cap layer 118F can be completely magnesium oxide. Forming the cap layer 118F of completely magnesium oxide allows increasing the perpendicular magnetic anisotropy (PMA) of the resulting MTJ element 134, thereby increasing the high resistance (R AP ) and low resistance (R P ) states. Therefore, the write error rate (WER) and read error rate (RER) of the MRAM cell 58 can be improved.

[0072] In an embodiment, a device includes: a substrate including an active device; a first intermetallic dielectric (IMD) layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode located above the first conductive feature; a magnetic tunnel junction element including: a reference layer located above the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer including magnesium oxide; a free layer located above the tunnel barrier layer; and a cap layer located above the free layer, the cap layer including magnesium oxide, the magnesium oxide of the cap layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode located above the cap layer; a second IMD layer located above the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

[0073] In some embodiments, the device further comprises: a spacer surrounding the bottom electrode and the magnetic tunnel junction element; and a third IMD layer surrounding the spacer and the top electrode; a fourth IMD layer adjacent to the first IMD layer and the third IMD layer; and a third conductive feature extending through the fourth IMD layer, the third conductive feature being electrically coupled to the active device. In some embodiments of the device, the tunnel barrier layer has an equal concentration of magnesium atoms and oxygen atoms. In some embodiments of the device, the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05, and the tunnel barrier layer has a thickness in the range of 0.6 nm to 1.2 nm. In some embodiments of the device, the cap layer has a higher concentration of oxygen atoms than the concentration of magnesium atoms. In some embodiments of the device, the ratio of oxygen to magnesium in the cap layer is in the range of 1.0 to 1.2, and the cap layer has a thickness in the range of 0.4 nm to 1.0 nm.

[0074] In an embodiment, a device includes: a magnetoresistive random access memory cell, including: a bottom electrode; a reference layer located on the bottom electrode; a tunnel barrier layer located on the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer located on the tunnel barrier layer, the free layer having a smaller coercivity than the reference layer; a cap layer located on the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher oxygen atomic concentration and a smaller magnesium atomic concentration than the first composition of magnesium and oxygen; and a top electrode located on the cap layer.

[0075] In some embodiments, the device further comprises: a row decoder; a word line electrically coupling the row decoder to the bottom electrode; a column decoder; and a bit line electrically coupling the column decoder to the top electrode. In some embodiments of the device, the first composition of magnesium and oxygen has an equal magnesium atomic concentration and an oxygen atomic concentration, wherein the second composition of magnesium and oxygen has an oxygen atomic concentration that is higher than the magnesium atomic concentration. In some embodiments of the device, the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05 and has a thickness in the range of 0.6 nm to 1.2 nm. In some embodiments of the device, the ratio of oxygen to magnesium in the cap layer is in the range of 1.0 to 1.2 and has a thickness in the range of 0.4 nm to 1.0 nm. In some embodiments of the device, the cap layer has a more uniform oxygen concentration than the tunnel barrier layer.

[0076] In an embodiment, a method includes: forming a bottom electrode layer over a substrate; forming a ground layer over the bottom electrode layer; forming a seed layer over the ground layer; forming a reference layer over the seed layer; sputtering magnesium oxide by radio frequency (RF) sputtering to form a tunnel barrier layer over the reference layer; forming a free layer over the tunnel barrier layer; forming a cap layer over the free layer by repeatedly depositing and oxidizing magnesium; forming a top electrode layer over the cap layer; and patterning the top electrode layer, the cap layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell.

[0077] In some embodiments of the method: a bottom electrode layer, a ground layer, and a seed layer are formed in a first multi-target DC sputtering module; a reference layer is formed in a second multi-target DC sputtering module; a tunnel barrier layer is formed in a dual-target RF sputtering module; a free layer is formed in a third multi-target DC sputtering module; a cap layer is formed in a single-target DC sputtering module; and a top electrode layer is formed in a fourth multi-target DC sputtering module. In some embodiments, the method further comprises: performing a metal bonding process in a dual-target RF sputtering module before forming the tunnel barrier layer. In some embodiments of the method, forming the cap layer includes: depositing a first magnesium sublayer on the free layer, the first magnesium sublayer having a first thickness, the first thickness being in a range of 0.2 nm to 0.4 nm; flowing oxygen over the first magnesium sublayer at a first flow rate for a first duration, the first flow rate being in a range of 8 sccm to 40 sccm, and the first duration being in a range of 10 seconds to 40 seconds; depositing a second magnesium sublayer on the first magnesium sublayer, the second magnesium sublayer having a second thickness, the second thickness being in a range of 0.08 nm to 0.24 nm; and flowing oxygen over the second magnesium sublayer at a second flow rate for a second duration, the second flow rate being in a range of 1 sccm to 20 sccm, and the second duration being in a range of 10 seconds to 40 seconds; Depositing a third magnesium sublayer on the second magnesium sublayer, the third magnesium sublayer having a third thickness, the third thickness being in a range of 0.08 nm to 0.24 nm; flowing oxygen over the third magnesium sublayer at a third flow rate for a third duration, the third flow rate being in a range of 1 sccm to 20 sccm, and the third duration being in a range of 10 seconds to 40 seconds; depositing a fourth magnesium sublayer on the third magnesium sublayer, the fourth magnesium sublayer having a fourth thickness, the fourth thickness being in a range of 0.08 nm to 0.24 nm; flowing oxygen over the fourth magnesium sublayer at a fourth flow rate for a fourth duration, the fourth flow rate being in a range of 100 sccm to about 1000 sccm, and the fourth duration being in a range of 10 seconds to 40 seconds; and depositing a fifth magnesium sublayer on the fourth magnesium sublayer. In some embodiments of the method, each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by direct current (DC) sputtering. In some embodiments of the method, each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by atomic layer deposition (ALD). In some embodiments of the method, each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited and oxidized in the same module without breaking the vacuum in the module between each deposition and flow step. In some embodiments of the method, the fourth flow rate is greater than each of the first flow rate, the second flow rate, and the third flow rate, wherein the fourth duration is greater than each of the first duration, the second duration, and the third duration.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0079] Example 1 is a semiconductor device comprising: a substrate including an active device; a first intermetallic dielectric (IMD) layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode located above the first conductive feature; a magnetic tunnel junction element comprising: a reference layer located above the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer comprising magnesium oxide; a free layer located above the tunnel barrier layer; and a cap layer located above the free layer, the cap layer comprising magnesium oxide, the magnesium oxide of the cap layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode located above the cap layer; a second IMD layer located above the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

[0080] Example 2 is the device described in Example 1, further comprising: a spacer surrounding the bottom electrode and the magnetic tunnel junction element; and a third IMD layer surrounding the spacer and the top electrode; a fourth IMD layer adjacent to the first IMD layer and the third IMD layer; and a third conductive feature extending through the fourth IMD layer, the third conductive feature being electrically coupled to the active device.

[0081] Example 3 is the device of Example 1, wherein the tunnel barrier layer has equal magnesium atomic concentration and oxygen atomic concentration.

[0082] Example 4 is the device of Example 1, wherein the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05, and the tunnel barrier layer has a thickness in the range of 0.6 nm to 1.2 nm.

[0083] Example 5 is the device of Example 1, wherein the cap layer has a higher concentration of oxygen atoms than magnesium atoms.

[0084] Example 6 is the device of Example 1, wherein the ratio of oxygen to magnesium in the cap layer is in the range of 1.0 to 1.2, and the cap layer has a thickness in the range of 0.4 nm to 1.0 nm.

[0085] Example 7 is a semiconductor device, comprising: a magnetoresistive random access memory cell, comprising: a bottom electrode; a reference layer located above the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer located above the tunnel barrier layer, the free layer having a smaller coercive force than the reference layer; a cap layer located above the free layer, the cap layer comprising a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher oxygen atomic concentration and a smaller magnesium atomic concentration than the first composition of magnesium and oxygen; and a top electrode located above the cap layer.

[0086] Example 8 is the device described in Example 7, further comprising: a row decoder; a word line electrically coupling the row decoder to the bottom electrode; a column decoder; and a bit line electrically coupling the column decoder to the top electrode.

[0087] Example 9 is the device of Example 7, wherein the first composition of magnesium and oxygen has an equal magnesium atomic concentration and oxygen atomic concentration, and wherein the second composition of magnesium and oxygen has an oxygen atomic concentration greater than the magnesium atomic concentration.

[0088] Example 10 is the device of Example 7, wherein the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05 and has a thickness in the range of 0.6 nm to 1.2 nm.

[0089] Example 11 is the device of Example 7, wherein the ratio of oxygen to magnesium in the cap layer is in the range of 1.0 to 1.2 and has a thickness in the range of 0.4 nm to 1.0 nm.

[0090] Example 12 is the device of Example 7, wherein the cap layer has a more uniform oxygen concentration than the tunnel barrier layer.

[0091] Example 13 is a method for forming a semiconductor device, comprising: forming a bottom electrode layer over a substrate; forming a ground layer over the bottom electrode layer; forming a seed layer over the ground layer; forming a reference layer over the seed layer; sputtering magnesium oxide by radio frequency (RF) sputtering to form a tunnel barrier layer over the reference layer; forming a free layer over the tunnel barrier layer; forming a cap layer over the free layer by repeatedly depositing and oxidizing magnesium; forming a top electrode layer over the cap layer; and patterning the top electrode layer, the cap layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell.

[0092] Example 14 is the method described in Example 13, wherein: the bottom electrode layer, the ground layer and the seed layer are formed in a first multi-target DC sputtering module; the reference layer is formed in a second multi-target DC sputtering module; the tunnel barrier layer is formed in a dual-target RF sputtering module; the free layer is formed in a third multi-target DC sputtering module; the cap layer is formed in a single-target DC sputtering module; and the top electrode layer is formed in a fourth multi-target DC sputtering module.

[0093] Example 15 is the method of Example 14, further comprising: performing a metal bonding process in the dual-target RF sputtering module before forming the tunnel barrier layer.

[0094] Example 16 is the method described in Example 15, wherein forming the cap layer includes: depositing a first magnesium sublayer on the free layer, the first magnesium sublayer having a first thickness, the first thickness being in a range of 0.2 nm to 0.4 nm; flowing oxygen over the first magnesium sublayer at a first flow rate for a first duration, the first flow rate being in a range of 8 sccm to 40 sccm, and the first duration being in a range of 10 seconds to 40 seconds; depositing a second magnesium sublayer on the first magnesium sublayer, the second magnesium sublayer having a second thickness, the second thickness being in a range of 0.08 nm to 0.24 nm; and flowing oxygen over the second magnesium sublayer at a second flow rate for a second duration, the second flow rate being in a range of 1 sccm to 20 sccm, and the second duration being in a range of 10 seconds to 40 seconds depositing a third magnesium sublayer on the second magnesium sublayer, the third magnesium sublayer having a third thickness, the third thickness being in a range of 0.08 nm to 0.24 nm; flowing oxygen over the third magnesium sublayer at a third flow rate for a third duration, the third flow rate being in a range of 1 sccm to 20 sccm, and the third duration being in a range of 10 seconds to 40 seconds; depositing a fourth magnesium sublayer on the third magnesium sublayer, the fourth magnesium sublayer having a fourth thickness, the fourth thickness being in a range of 0.08 nm to 0.24 nm; flowing oxygen over the fourth magnesium sublayer at a fourth flow rate for a fourth duration, the fourth flow rate being in a range of 100 sccm to about 1000 sccm, and the fourth duration being in a range of 10 seconds to 40 seconds; and depositing a fifth magnesium sublayer on the fourth magnesium sublayer.

[0095] Example 17 is the method of Example 16, wherein each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by direct current (DC) sputtering.

[0096] Example 18 is the method of Example 16, wherein each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by atomic layer deposition (ALD).

[0097] Example 19 is the method of Example 16, wherein each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited and oxidized in the same module without breaking the vacuum in the module between each deposition and flow step.

[0098] Example 20 is the method of Example 16, wherein the fourth flow rate is greater than each of the first flow rate, the second flow rate, and the third flow rate, and wherein the fourth duration is greater than each of the first duration, the second duration, and the third duration.

Claims

1. A semiconductor device, comprising: substrate, including active devices; a first intermetal dielectric IMD layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode disposed on the first conductive feature; Magnetic tunnel junction device, including: a reference layer located on the bottom electrode; a tunnel barrier layer, located on the reference layer, wherein the tunnel barrier layer comprises magnesium oxide; a free layer located on the tunnel barrier layer; and A cap layer, located on the free layer, the cap layer comprising magnesium oxide, the magnesium oxide of the cap layer being more oxidized than the magnesium oxide of the tunnel barrier layer; A top electrode, located on the cap layer; a second IMD layer located on the top electrode; and A second conductive feature extends through the second IMD layer, the second conductive feature contacting the top electrode.

2. The device according to claim 1, further comprising: a spacer surrounding the bottom electrode and the magnetic tunnel junction element; as well as a third IMD layer surrounding the spacer and the top electrode; a fourth IMD layer, adjacent to the first IMD layer and the third IMD layer; as well as A third conductive feature extends through the fourth IMD layer, the third conductive feature being electrically coupled to the active device.

3. The device according to claim 1, wherein The tunnel barrier layer has equal magnesium atomic concentration and oxygen atomic concentration.

4. The device according to claim 1, wherein A ratio of oxygen to magnesium in the tunnel barrier layer is in a range of 0.95 to 1.05, and the tunnel barrier layer has a thickness in a range of 0.6 nm to 1.2 nm.

5. The device according to claim 1, wherein The capping layer has a higher oxygen atomic concentration than a magnesium atomic concentration.

6. The device according to claim 1, wherein The ratio of oxygen to magnesium in the capping layer is in the range of 1.0 to 1.2, and the capping layer has a thickness in the range of 0.4 nm to 1.0 nm.

7. A semiconductor device comprising: A magnetoresistive random access memory cell comprising: Bottom electrode; a reference layer located on the bottom electrode; a tunnel barrier layer located above the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; A free layer, located on the tunnel barrier layer, wherein the free layer has a smaller coercivity than the reference layer; a capping layer overlying the free layer, the capping layer comprising a second composition of magnesium and oxygen having a higher oxygen atomic concentration and a lower magnesium atomic concentration than the first composition of magnesium and oxygen; and A top electrode is located on the cap layer.

8. The device according to claim 7, further comprising: Line decoder; a word line electrically coupling the row decoder to the bottom electrode; Column decoder; as well as A bit line electrically couples the column decoder to the top electrode.

9. The device according to claim 7, wherein The first composition of magnesium and oxygen has an equal magnesium atomic concentration and an oxygen atomic concentration, and wherein the second composition of magnesium and oxygen has a higher oxygen atomic concentration than a magnesium atomic concentration.

10. The device according to claim 7, wherein The tunnel barrier layer has an oxygen to magnesium ratio in a range of 0.95 to 1.05 and a thickness in a range of 0.6 nm to 1.2 nm.

11. The device according to claim 7, wherein The cap layer has an oxygen to magnesium ratio in a range of 1.0 to 1.2 and has a thickness in a range of 0.4 nm to 1.0 nm.

12. The device according to claim 7, wherein The capping layer has a more uniform oxygen concentration than the tunnel barrier layer.

13. A method for forming a semiconductor device, comprising: forming a bottom electrode layer over the substrate; forming a ground layer on the bottom electrode layer; forming a seed layer on the ground layer; forming a reference layer on the seed layer; sputtering magnesium oxide by radio frequency (RF) sputtering to form a tunnel barrier layer on the reference layer; forming a free layer on the tunnel barrier layer; forming a capping layer over the free layer by repeatedly depositing and oxidizing magnesium; forming a top electrode layer over the cap layer, the cap layer comprising magnesium oxide extending continuously between the top electrode layer and the free layer; as well as The top electrode layer, the cap layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer are patterned to form a magnetoresistive random access memory cell.

14. The method according to claim 13, wherein: The bottom electrode layer, the ground layer and the seed layer are formed in a first multi-target DC sputtering module; The reference layer is formed in a second multi-target DC sputtering module; The tunnel barrier layer is formed in a dual-target RF sputtering module; The free layer is formed in a third multi-target DC sputtering module; The cap layer is formed in a single target DC sputtering module; and The top electrode layer is formed in a fourth multi-target DC sputtering module.

15. The method according to claim 14, further comprising: Before forming the tunnel barrier layer, a metal bonding process is performed in the dual-target RF sputtering module.

16. The method according to claim 15, wherein: Forming the cap layer includes: depositing a first magnesium sublayer on the free layer, the first magnesium sublayer having a first thickness, the first thickness being in a range of 0.2 nm to 0.4 nm; flowing oxygen over the first magnesium sublayer at a first flow rate for a first duration, the first flow rate being in a range of 8 sccm to 40 sccm, the first duration being in a range of 10 seconds to 40 seconds; depositing a second magnesium sublayer on the first magnesium sublayer, the second magnesium sublayer having a second thickness, the second thickness being in a range of 0.08 nm to 0.24 nm; and flowing oxygen over the second magnesium sublayer at a second flow rate for a second duration, the second flow rate being in a range of 1 sccm to 20 sccm, the second duration being in a range of 10 seconds to 40 seconds; depositing a third magnesium sublayer on the second magnesium sublayer, the third magnesium sublayer having a third thickness, the third thickness being in a range of 0.08 nm to 0.24 nm; flowing oxygen over the third magnesium sublayer at a third flow rate for a third duration, the third flow rate being in a range of 1 sccm to 20 sccm, the third duration being in a range of 10 seconds to 40 seconds; depositing a fourth magnesium sublayer on the third magnesium sublayer, the fourth magnesium sublayer having a fourth thickness in a range of 0.08 nm to 0.24 nm; flowing oxygen over the fourth magnesium sublayer at a fourth flow rate for a fourth duration, the fourth flow rate being in a range of 100 seem to about 1000 seem, the fourth duration being in a range of 10 seconds to 40 seconds; and A fifth magnesium sub-layer is deposited on the fourth magnesium sub-layer.

17. The method according to claim 16, wherein: Each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by direct current (DC) sputtering.

18. The method according to claim 16, wherein: Each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer is deposited by atomic layer deposition (ALD).

19. The method according to claim 16, wherein: Each of the first magnesium sublayer, the second magnesium sublayer, the third magnesium sublayer, the fourth magnesium sublayer, and the fifth magnesium sublayer are deposited and oxidized in the same module without breaking the vacuum in the module between each deposition and flow step.

20. The method according to claim 16, wherein: The fourth flow rate is greater than each of the first flow rate, the second flow rate, and the third flow rate, and wherein the fourth duration is greater than each of the first duration, the second duration, and the third duration.

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