Receiver and method of operating a receiver

Abstract

A transceiver and a method for operating the transceiver are disclosed. The transceiver includes a first common T-coil circuit connected to a first input-output pin of the transceiver; a terminal impedance connected to the first common T-coil circuit and configured to match the impedance of a transmission line connected to the first common T-coil circuit; an amplifier configured to: receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal; and a first transmission buffer configured to: send an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

Description

[0001] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 008,265, filed on April 10, 2020 (“SERDES WITH TX AND RX PIN SHARING”), and U.S. Patent Application No. 15 / 930,917, filed on May 13, 2020, the entire contents of which are incorporated herein by reference.

[0002] This application is also related to U.S. Patent Application No. 63 / 008,283, filed on April 10, 2020, entitled “DC-COUPLED SERDES RECEIVER” (Attorney Docket No. 188047 (303927-00196)), filed on the same date as this application, which claims priority to and the benefit of U.S. Provisional Application No. 63 / 008,283, filed on April 10, 2020 (“DC-COUPLED SERDES RECEIVER WITH T-COIL AND AUTO-ZEROSWITCH”), the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate generally to data communication systems. Background Art

[0004] As cellular standards evolve, the data connection speeds between cellular transceivers and cellular modems are becoming higher and higher. Traditional parallel connections between transceivers and modems are limited in speed to approximately 2Gbps (gigabits per second) per cable. To support a 32Gbps connection between the transceiver and the modem, more than 16 cables may be required in one direction, which translates to more than 32 cables to establish bidirectional communication. This presents a major problem in board design because such a large number of high-speed cables are difficult to fan out and route to space-constrained boards. To reduce the number of cables, parallel interfaces can be replaced with high-speed serializers / deserializers (SERDES).

[0005] SERDES is a functional block commonly used to send high-speed data through a channel. SERDES blocks convert parallel data to serial data and vice versa, and are commonly used for the transmission of parallel data through a single line or differential pair to reduce the number of input / output (I / O) pins and connectors. In high-speed bidirectional communication, two cables are used in each direction to implement differential signaling, so a minimum of four cables are used.

[0006] The above information disclosed in this background section is only for enhancement of understanding of the present disclosure and therefore, the above information disclosed in this background section may contain information that does not form the prior art already known to one of ordinary skill in the art. Summary of the invention

[0007] Aspects of embodiments of the present disclosure are directed to a transceiver capable of sharing transmit and receive pins. In some embodiments, the transceiver is capable of calibrating a transceiver amplifier while maintaining proper input impedance, and has improved input matching and return loss.

[0008] According to some embodiments of the present disclosure, a transceiver is provided, comprising: a first common T-coil circuit connected to a first input-output pin of the transceiver; a terminal impedance connected to the first common T-coil circuit and configured to match the impedance of a transmission line connected to the first common T-coil circuit; an amplifier configured to: receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal; and a first transmission buffer configured to: send an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

[0009] In some embodiments, the first common T-coil circuit includes: a first inductor connected between the transmission line and the central node; a second inductor connected between the first node and the second node; and a third inductor connected between the first transmission buffer and the central node.

[0010] In some embodiments, the terminal impedance includes: a variable resistor connected to the first common T-coil circuit and configured to change resistance according to a reception enable signal or a transmission enable signal; and a common capacitor connected to the variable resistor.

[0011] In some embodiments, the variable resistor has a first branch connected in parallel with a second branch, wherein the first branch includes a first resistor connected in series with a first switch, the first switch is configured to be activated in response to sending a disable signal, wherein the second branch includes a second resistor connected in series with a second switch, the second switch is configured to be activated in response to sending an enable signal, and wherein the second resistor has a higher resistance than the first resistor.

[0012] In some embodiments, the transceiver further includes: a first receiving switch configured to selectively electrically connect or disconnect a center node of the first common T-coil circuit to the amplifier based on a receiving enable signal; a calibration switch connected to the amplifier and configured to selectively electrically connect or disconnect a first input to a second input of the amplifier in response to the calibration enable signal; and a controller configured to confirm an operating mode of the transceiver as a calibration mode, a transmitting mode, or a receiving mode.

[0013] In some embodiments, the controller is further configured to: generate a receive disable signal to electrically disconnect the amplifier from the first common T-coil circuit; generate a transmit disable signal to disable the first transmission buffer and set the variable resistor of the termination impedance to a first resistance value; and generate a calibration enable signal to activate the calibration switch.

[0014] In some embodiments, the controller is further configured to: generate a receive enable signal to electrically connect the amplifier to the first common T-coil circuit so as to enable the amplifier to receive an input signal from the first input-output pin; generate a transmit disable signal to disable the first transmission buffer and set the variable resistor of the termination impedance to a first resistance value; and generate a calibration disable signal to deactivate the calibration switch.

[0015] In some embodiments, the controller is further configured to: generate a receive disable signal to electrically disconnect the amplifier from the first common T-coil circuit; generate a transmit enable signal to enable the first transmit buffer to send an output signal to the first input-output pin and set the variable resistor of the termination impedance to a second resistance value; and generate a calibration disable signal to deactivate the calibration switch.

[0016] In some embodiments, the amplifier is selectively connected to the center node of the first common T-coil circuit, and the amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

[0017] In some embodiments, the amplifier is fixedly connected to the first common T-coil circuit and the terminal impedance, and the amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

[0018] In some embodiments, the first transmission buffer includes: a tri-state buffer configured to generate a high impedance output based on the transmit disable signal.

[0019] In some embodiments, a center node of the first common T-coil circuit is connected to an electrostatic discharge (ESD) protection diode.

[0020] In some embodiments, the transceiver further includes: a second common T-coil circuit connected to a second input-output pin of the transceiver; and a second transmission buffer connected to the second common T-coil circuit, wherein the first common T-coil circuit and the second common T-coil circuit are configured to: receive a differential input signal at the first input-output pin and the second input-output pin, wherein the first transmission buffer and the second transmission buffer are configured to output the differential signal to the first input-output pin and the second input-output pin based on a transmit enable signal.

[0021] In some embodiments, the transceiver further includes: a second receive switch configured to selectively electrically connect or disconnect a center node of the second common T-coil circuit from the amplifier based on a receive enable signal.

[0022] In some embodiments, the amplifier is configured to amplify a differential signal output from a center node of the first common T-coil circuit and the second common T-coil circuit.

[0023] According to some embodiments of the present disclosure, a transceiver is provided, comprising: a pair of common T-coil circuits connected to a pair of input-output pins of the transceiver; a terminal impedance connected to the common T-coil circuit and configured to match the impedance of a transmission line connected to the common T-coil circuit; an amplifier configured to: receive a differential input signal from the input-output pins through the common T-coil circuit based on a receive enable signal; and a pair of transmit buffers configured to: send the differential output signal to the input-output pins based on a transmit enable signal.

[0024] In some embodiments, each common T-coil circuit includes: a first inductor connected between the transmission line and the center node; a second capacitor connected between the terminal impedance and the center node; and a third inductor connected between the first transmission buffer and the center node, wherein the transmission buffer is electrically connected to the corresponding center node of the common T-coil circuit.

[0025] According to some embodiments of the present disclosure, a method for operating a transceiver is provided, comprising: confirming an operating mode of the transceiver as a calibration mode, a transmission mode, or a reception mode; and in response to confirming the mode as the transmission mode: enabling a transmission buffer to send an output signal to an input-output pin of the transceiver through a common T-coil circuit, the input-output pin being connected to a transmission line; electrically disconnecting an amplifier of the transceiver from the common T-coil circuit; and adjusting an impedance of a terminal impedance connected to the common T-coil circuit from a first impedance value to a second impedance value, the first impedance value matching the impedance of the transmission line.

[0026] In some embodiments, the method further includes: in response to confirming the mode as a receive mode: electrically connecting the amplifier to the common T-coil circuit so that the amplifier can receive an input signal from the input-output pin; disabling the first transmission buffer to set the state of the first transmission buffer to a high impedance state; and adjusting the impedance of the terminal impedance to a first impedance value.

[0027] In some embodiments, the method further includes: in response to confirming the mode as a calibration mode: electrically disconnecting the amplifier from the common T-coil circuit; disabling the first transmission buffer to set the state of the first transmission buffer to a high impedance state; and activating a calibration switch connected to the amplifier to electrically connect the differential inputs of the amplifier and enable measurement of an input offset voltage of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings, together with the specification, illustrate example embodiments of the present disclosure, and, together with the description, serve to explain the principles of the present disclosure.

[0029] Figure 1 is a schematic diagram illustrating a data transmission system utilizing a serializer and deserializer (SERDES) according to some embodiments of the present disclosure.

[0030] Figure 2A is a schematic diagram of a receiver according to some embodiments of the present disclosure.

[0031] Figure 2B is a schematic diagram of a receiver when in a calibration mode according to some embodiments of the present disclosure.

[0032] Figure 2C is a schematic diagram of a receiver when in a receiving mode according to some embodiments of the present disclosure.

[0033] Figure 3A is a schematic diagram of a half-duplex system with two communication modules utilizing transceivers for bidirectional communication according to some embodiments of the present disclosure.

[0034] Figure 3B Show Figure 1 Example of time division duplexing on a half-duplex communications link.

[0035] Figure 4 is a schematic diagram of a transceiver according to some embodiments of the present disclosure.

[0036] Figure 5 is a schematic diagram of a transceiver capable of calibration according to some embodiments of the present disclosure.

[0037] Fig. 6A A half circuit of a transceiver is shown when in calibration mode and receive mode according to some embodiments of the present disclosure.

[0038] Figure 6B A half circuit of a transceiver when in transmit mode is shown according to some embodiments of the present disclosure.

[0039] Figure 7 is a schematic diagram illustrating a variable resistor according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] The specific embodiments set forth below are intended to be descriptions of example embodiments of receivers and transceivers and methods for operating the same provided by the present disclosure, and are not intended to represent the only form in which the present disclosure can be constructed or utilized. This description sets forth the features of the present disclosure in conjunction with the embodiments shown. However, it will be understood that the same or equivalent functions and structures can be realized by different embodiments that are also intended to be included in the disclosed scope. As indicated elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0041] Aspects of the present disclosure are directed to a receiver capable of calibrating an amplifier offset voltage without affecting the input impedance of the receiver and without adversely affecting a transmitter connected to the receiver via a transmission line. According to some embodiments, the receiver utilizes a large-sized and low-on-resistance receive switch in the signal path, the on-resistance receive switch being connected to the center node of a T-coil circuit at the input of the receiver, and therefore, not affecting the input impedance of the receiver. The specific configuration of the receiver also improves input matching and reduces (e.g., minimizes) return loss.

[0042] Figure 1 is a schematic diagram illustrating a data transmission system using a serializer and deserializer (SERDES) 1 according to some embodiments of the present disclosure.

[0043] According to some embodiments, the SERDES 1 includes a parallel-input serial-output (PISO) block 20 (also referred to as a serializer or a parallel-to-serial converter) and a serial-input parallel-output (SIPO) block 10 (also referred to as a deserializer or a serial-to-parallel converter). The PISO block 20 receives parallel data (e.g., high-speed parallel data) from a source (e.g., an external circuit), converts the parallel data into serial data (e.g., via a multiplexer / shift register 22), and transmits the serial data via a front-end transmitter 200 (hereinafter referred to as a "transmitter") through a transmission line (e.g., a pair of conductors) 30. The transmission line 30 may be a lossy and noisy channel, and the transmitter may sufficiently amplify the serial data to ensure that the signal can be properly received at the other end of the transmission line. In some examples, the transmission line 30 may be a cable / trace in a printed circuit board.

[0044] The SIPO block 10 receives and amplifies the attenuated signal from the transmission line 30 via a front-end receiver 100 (hereinafter referred to as a "receiver"). The received signal can be sampled by a clean clock to reduce (e.g., remove) noise, and the phase of the sampled received signal can be aligned with a well-defined clock phase. The SIPO block 10 then converts the received signal into a parallel digital signal (e.g., via a demultiplexer 12) for further processing by another circuit.

[0045] Figure 2A is a schematic diagram of a receiver 100 according to some embodiments of the present disclosure.

[0046] According to some embodiments, a receiver (e.g., a SERDES receiver) 100 includes a first T-coil circuit 102 and a second T-coil circuit 104 at first and second inputs (INP and INN) of the receiver (e.g., at differential inputs), a termination impedance 106 connected to (e.g., fixedly connected to) the first T-coil circuit 102 and the second T-coil circuit 104, and an amplifier (e.g., a differential gain amplifier) ​​108. In some embodiments, the receiver 100 also includes a calibration switch 110 connected between the inputs of the amplifier 108, a first receive switch 112 and a second receive switch 114 (e.g., an auto-zero / isolation switch) for selectively connecting the amplifier 108 to the first T-coil circuit 102 and the second T-coil circuit 104, and a controller 120 for controlling activation and deactivation states of the calibration switch 110, the first receive switch 112, and the second receive switch 114 based on whether the receiver 100 is in a receive mode or a calibration mode.

[0047] The first T-coil circuit 102 has an input connected to a first central node CN P The first-1 inductor L between P1 and connected to the first central node CN P The second-1 inductor L between the output P2 The second T-coil circuit 104 has an input connected to a second central node CN N Between the first-2 inductors L N1 and connected to the second central node CN N The second-2 inductor L between the output N2 According to some examples, the first-1 inductor L P1 and the second-1 inductor L P2 can be a coupled inductor, and the first-2 inductor L N1 and the second-2 inductor L N2It may also be a coupled inductor. The inputs of the first T-coil circuit 102 and the second T-coil circuit 104 may represent differential inputs of the receiver 100, and receive input data via a transmission line (e.g., a differential transmission line) 30. In some embodiments, the outputs of the first T-coil circuit 102 and the second T-coil circuit 104 are connected to a terminal impedance 106 (e.g., there is no switching element between the outputs of the first T-coil circuit 102 and the second T-coil circuit 104 and the terminal impedance 106). The terminal impedance 106 is configured to match the impedance of the transmission line 30 connected to the first T-coil circuit 102 and the second T-coil circuit 104, and may include a first resistor R connected to the outputs of the first T-coil circuit 102 and the second T-coil circuit 104, respectively. P and the second resistor R N , and may also include a first resistor R P With the second resistor R N The common capacitor C at the connection point between COM The first T-coil circuit 102 and the second T-coil circuit 104 together with the terminal impedance 106 have the effect of presenting a 50 ohm impedance to the outside (e.g., to the transmitter 200), extending the signal bandwidth, and reducing (e.g., minimizing) signal loss. In some examples, the first center node CN of the first T-coil circuit 102 P and a second central node CN of the second T-coil circuit 104 N Connected to a pair of large ESD diodes for electrostatic discharge (ESD) protection. The ESD diodes present a large parasitic load to the input and are represented as the first parasitic capacitor C ESDP and the second parasitic capacitor C ESDN However, a desirable aspect of the first T-coil circuit 102 and the second T-coil circuit 104 is that the first center node CN of the first T-coil circuit 102 P and a second central node CN of the second T-coil circuit 104 N Insensitive to capacitive loading; therefore, ESD diodes do not meaningfully affect signal bandwidth.

[0048] In some examples, the first resistor R P and the second resistor R N can be about 50 ohms, the common capacitor C COM can be about 1 pF (picofarad) to about 10 μF (microfarad) (depending on, for example, whether the common capacitor is implemented on-chip or off-chip), the first -1 inductor L P1 , 1st-2nd inductor L N1 , Second-1 inductor L P2 and the second-2 inductor L N2It can be about 50 pH (picohenry) to about 10 nH (nanohenry) (depending on, for example, bandwidth and load conditions). In some examples, switches 110, 112, and 114 can be implemented using transistors (e.g., metal oxide field effect transistors (MOSFETs) such as PMOS or NMOS transistors). However, embodiments of the invention are not limited thereto, and switches 110, 112, and 114 can be implemented in any other suitable manner.

[0049] According to some examples, the amplifier 108 may be a differential continuous time linear equalizer (CTLE) and configured to amplify a differential signal at a first input and a second input of the amplifier 108. The differential nature of the amplifier 108 allows the amplifier 108 to reduce (e.g., minimize) common noise (such as noise from a power supply). Therefore, the positive branch and the negative branch of the receiver 100 may be symmetrical. For example, the first T-coil circuit 102 may be identical to the second T-coil circuit 104, and the first resistor R P The resistance and the second resistor R N The resistance can be the same.

[0050] Amplifier 108 may be the first gain block in a larger circuit at receiver 100. As such, it is desirable to reduce (eg, minimize) any input referred offset voltage V since the offset may be amplified by amplifier 108 and subsequent blocks and may cause system errors. OFFSET . Input reference offset voltage V OFFSET It can be caused by various mismatches (such as device characteristic mismatch due to layout parasitics, non-uniform doping, lithographic mismatch, etc.). Input reference offset voltage V OFFSET It can range from a few mV (millivolts) to tens of mV. In Figure 2, the input reference offset voltage V OFFSET Shown is a voltage source at one of the amplifier 108 inputs.

[0051] In some examples, the input-referred offset voltage V may be corrected by using auto-zeroing techniques or offset cancellation. OFFSET However, both of these methods involve electrically shorting the two inputs of amplifier 108. In some embodiments, when in calibration mode, receiver 100 calibrates the input reference offset voltage V of amplifier 108. OFFSET .

[0052] Figure 2B is a schematic diagram of the receiver 100 when in a calibration mode according to some embodiments of the present disclosure.

[0053] In some embodiments, when the controller 120 (e.g., via a calibration / receive signal C / R from an external source) identifies the mode of the receiver 100 as the calibration mode, the controller activates (e.g., closes) the calibration switch 110 to electrically short the inputs of the amplifier 108 (i.e., the voltages of the two inputs of the amplifier 108 will be at the same voltage). Since the differential input voltage of the amplifier 108 is effectively zero in this mode, the output voltage of the amplifier 108 is the input reference offset voltage V OFFSET Multiply by the amplifier gain A CTLE In some examples, this output voltage is digitized by an analog-to-digital converter (ADC) 130 or stored in a capacitor for digital or analog offset cancellation. CTLE is a known value, so during calibration, the input reference offset voltage V OFFSET can be easily determined based on the output voltage of amplifier 108 .

[0054] According to some embodiments, when in the calibration mode, the controller 120 deactivates (e.g., opens) the first receiving switch 112 and the second receiving switch 114 to electrically isolate the amplifier 108 from the first T-coil circuit 102 and the second T-coil circuit 104, and thus, the controller 120 electrically isolates (e.g., electrically disconnects) the amplifier 108 from the input of the receiver 100. In this way, a short circuit of the input of the amplifier 108 through the calibration switch 110 does not cause a short circuit of the first input INP and the second input INN of the receiver 100, which may cause the output of the transmitter 200 to be electrically shorted and cause catastrophic results. Since the termination impedance 106 is connected to the input of the receiver 100 regardless of the mode of the receiver 100, the transmitter 200 on the other side of the transmission line 30 still observes an input matching the correct receiver 100 (e.g., 50 ohm resistor) even when the receiver 100 is being calibrated.

[0055] In some examples, in order to prevent an accidental conflict between the output of transmitter 200 and the short-circuited inputs INN and INP of receiver 100, the controller deactivates first receive switch 112 and second receive switch 114 before activating calibration switch 110; however, embodiments of the present disclosure are not limited thereto, and controller 120 may affect the states of switches 110, 112, and 114 in any suitable order.

[0056] Assuming that the calibration switch 110 is not in a high-speed signal path or a high-current path when the receiver 100 is in the calibration mode, the size of the calibration switch 110 may be appropriately reduced (eg, minimized) to reduce parasitic loading on the input of the amplifier 108 .

[0057] According to some embodiments, the receiver 100 enters a calibration mode upon initial power-up and before commencing normal transmission operations. However, calibration may also be performed at regular intervals or in response to specific conditions (such as power interruption, etc.).

[0058] When the receiver 100 is not in the calibration mode, the receiver 100 operates in a receiving mode (eg, a mission or normal operating mode), and the controller 120 adjusts the states of the switches 110 , 112 , and 114 accordingly.

[0059] Figure 2C is a schematic diagram of a receiver 100 when in a receiving mode according to some embodiments of the present disclosure.

[0060] In some embodiments, when the controller 120 confirms the mode of the receiver 100 as the receive mode (e.g., via the calibration signal / receive signal C / R from an external source), the controller 120 deactivates (e.g., opens) the calibration switch 110 to disconnect the input of the amplifier 108, and activates the first receive switch 112 and the second receive switch 114 to electrically connect the input of the amplifier 108 to the first T-coil circuit 102 and the second T-coil circuit 104 and allow the input signal at the inputs INN and INP of the receiver 100 to reach the amplifier 108. Since the first receive switch 112 and the second receive switch 114 are in the signal path from the inputs INN and INP of the receiver 100 to the amplifier 108, it is desirable to reduce (e.g., minimize) the on-resistance of the signal path from the inputs INN and INP of the receiver 100 to the amplifier 108 in order to reduce signal attenuation and reduce any adverse effects on the input impedance of the receiver 100. Therefore, in some embodiments, the receiver 100 uses large (e.g., large size) switches for the first receive switch 112 and the second receive switch 114 to reduce (e.g., minimize) the on-resistance in the signal path and improve (e.g., increase) the bandwidth during the receive mode. As a result, the signal received by the inputs INN and INP of the amplifier 108 in the receive mode can be approximated as the input signal V IN , and the output signal of amplifier 108 can be approximated as the amplified input signal plus an offset voltage (i.e., approximately A CTLE × (V IN +V OFFSET )).

[0061] A side effect of using large switches as the first receiving switch 112 and the second receiving switch 114 is that the large switches can also generate large capacitive loads. However, since the first center node CN of the T-coil circuit P and the second central node CN NThe first and second T-coil circuits 102 and 104 are insensitive to capacitive loads, and therefore, the input impedance of the first and second T-coil circuits 102 and 104 remains virtually unchanged due to the closing of the first and second receiving switches 112 and 114, and the effective bandwidth of the input signal of the receiver may be largely unaffected by the activation / deactivation states of the first and second receiving switches 112 and 114.

[0062] As described herein, the receiver 100 according to some embodiments of the present disclosure allows the input-referred offset voltage V of the amplifier 108 to be reduced without affecting the input impedance of the receiver 100 and without adversely affecting the transmitter 200 connected to the receiver 100 via the transmission line 30. OFFSET According to some embodiments, the first receiving switch 112 and the second receiving switch 114 in the signal path during the receiving mode of the receiver 100 are large in size and have a low on-resistance. Because the first receiving switch 112 and the second receiving switch 114 are connected to the first parasitic capacitor C ESDP and the second parasitic capacitor C ESDN The capacitive load is insensitive to the center nodes of the first T-coil circuit 102 and the second T-coil circuit 104 at the inputs INP and INN of the receiver 100, so the relatively large parasitic capacitance of the first receive switch and the second receive switch (due to their large size) does not affect the signal bandwidth. Connecting the first receive switch and the second receive switch to the center nodes of the first T-coil circuit 102 and the second T-coil circuit 104 allows the receiver 100 to present an almost purely resistive input impedance (e.g., about 50 ohms), which improves input matching and reduces (e.g., minimizes) return loss.

[0063] Aspects of receiver 100 may be used to construct a transceiver (eg, a SERDES transceiver) that is capable of pin sharing to reduce (eg, minimize) pin count.

[0064] Figure 3A is a schematic diagram of a half-duplex system having two communication modules 40 and 50 utilizing a transceiver 300 for bidirectional communication according to some embodiments of the present disclosure. Figure 3B Show Figure 3A Example of time division duplexing on a half-duplex communications link.

[0065] In the prior art, a communication module participating in high-speed bidirectional communication uses at least four pins (ie, at least two pins for transmitting differential signals and at least two pins for receiving differential signals).

[0066] According to some embodiments, the transceiver (eg, a SERDES transceiver (or Serdes TX / RX)) 300 can facilitate high-speed bidirectional communication using two pins. Figure 3A In a half-duplex system of FIG. 1 , a first communication module (e.g., a cellular transceiver block) 40 and a second communication module (e.g., a cellular modem block) 50 utilizing a transceiver 300 can engage in bidirectional differential signaling using only two pins each. The two pins on each side send or receive differential signals to or from a pair of conductors 30 (e.g., cables, interconnects, traces, etc.) that carry a pair of signals or complementary signals (e.g., differential signals) that help reduce / minimize common mode noise. According to some embodiments, as Figure 3B As shown in , the transceiver 300 implements pin sharing by adopting a time division duplex method. Figure 3B In the example of , the first communication module 40 and the second communication module 50 have been coordinated so that the pair of transceivers 300 carry the differential signal from the first communication module 40 to the second communication module 50 during the first time slot and the second time slot, and carry the differential signal from the second communication module 50 to the first communication module 40 during the third time slot. However, embodiments of the present invention are not limited thereto. For example, the first communication module 40 and the second communication module 50 may have a predefined time slot pattern, or one of the first communication module 40 and the second communication module 50 may act as a master module and dynamically change the time share pattern according to use.

[0067] Figure 4 is a schematic diagram of a transceiver 300 according to some embodiments of the present disclosure.

[0068] Reference Figure 4In some embodiments, the transceiver 300 includes: a first common T-coil circuit 302 connected to a first input-output pin 303 (also referred to as a first shared / common input-output pin) of the transceiver 300, a second common T-coil circuit 304 connected to a second input-output pin 305 (also referred to as a second shared / common input-output pin) of the transceiver 300, a terminal impedance (e.g., a variable terminal impedance) 306 connected to the first common T-coil circuit 302 and the second common T-coil circuit 304, an amplifier 108 configured to receive an input signal (e.g., a differential input signal) from the first input-output pin 303 and the second input-output pin 305 through the first common T-coil circuit 302 and the second common T-coil circuit 304, and a first transmission buffer 202 and a second transmission buffer 204 configured to send an output signal (e.g., a differential output signal) to the first input-output pin 303 and the second input-output pin 305 through the first common T-coil circuit 302 and the second common T-coil circuit 304.

[0069] According to some embodiments, the first common T-coil circuit 302 includes a first common T-coil circuit 302 connected between the transmission line 30 and the first central node CN. P The first-1 inductor L between P1 , connected between the terminal impedance 306 and the first central node CN P The second-1 inductor L between P2 , and connected between the corresponding first transmission buffer 202 and the first central node CN P The third-1 inductor L between TP The second common T coil circuit 304 includes a circuit connected between the transmission line 30 and the second central node CN N Between the first-2 inductors L N1 , connected between the terminal impedance 306 and the second central node CN N The second-2 inductor L between N2 , and connected between the corresponding second transmission buffer 204 and the second central node CN N The third-2 inductor L between TN According to some examples, the first-1 inductor L P1 , Second-1 inductor L P2 and the third-1 inductor L TP can be a coupled inductor, and the first-2 inductor L N1 , the second-2 inductor L N2 and the third-2 inductor L TN In some examples, the first center node CN of the first common T-coil circuit 302 is P and a second central node CN of the second common T-coil circuit 304N Connect to a pair of large ESD diodes for electrostatic discharge (ESD) protection (e.g., the first ESD diode C ESDP and the second ESD diode C ESDPN ).

[0070] The terminal impedance 306 is configured to match or substantially match the impedance of the transmission line 30 connected to the first common T-coil circuit 302 and the second common T-coil circuit 304 when the transceiver operates in the receive mode. In some embodiments, the terminal impedance 306 includes a third variable resistor R connected to the first common T-coil circuit. VP and a fourth variable resistor R connected to the second common T coil circuit VN , and further comprising a third variable resistor R connected VP With the fourth variable resistor R VN The common capacitor C between COM The third variable resistor R VP and the fourth variable resistor R VN The third variable resistor R is configured to change the value of the third variable resistor R based on the operation mode of the transceiver 300. VP and the fourth variable resistor R VN resistance.

[0071] The first transmission buffer 202 and the second transmission buffer 204 may be tri-state buffers, which may send output signals (TX_DP and TX_DN) to the input-output pins 303 and 305 when the transceiver 300 is enabled during the transmit mode, and may be in high output impedance when the transceiver 300 is disabled during the receive mode, wherein the high output impedance indicates that the impedance at the output end of the tri-state buffer is higher than a predetermined threshold.

[0072] According to some embodiments, when the controller 320 confirms that the operation mode of the transceiver 300 is the receiving mode, the controller 320 may generate a transmit disable signal (e.g., EN_TX = logic low 'L') to disable the first transmission buffer 202 and the second transmission buffer 204 and put them in a high impedance state, wherein the high impedance state indicates a state where the impedance is higher than a predetermined threshold. This (e.g., impedance higher than the predetermined threshold) prevents any transmission signal from being fed back to the amplifier 108. In this mode, the controller 320 also sets the third variable resistor R VP and the fourth variable resistor R VN The value of is set to a value (eg, 50 ohms) that matches or substantially matches the impedance of the transmission line 30. Since no signal passes through the third inductor L when the controller 320 confirms the operation mode of the transceiver 300 as the receiving mode, TP and the third-2 inductor L TN, therefore, the first common T-coil circuit 302 and the second common T-coil circuit 304 effectively function as a two-inductor peaking circuit for the first T-coil circuit 102 and the second T-coil circuit 104, and together with the termination impedance 306 have the effect of presenting a 50 ohm impedance to the outside (e.g., to the transmitter 200), extending the signal bandwidth, and reducing (e.g., minimizing) signal loss. In this mode, the controller 320 also generates a receive enable signal (e.g., EN_RX = logic high 'H') to enable the amplifier 108 and allow the amplifier 108 to receive and amplify the input signal for further processing by downstream circuits.

[0073] According to some embodiments, when the controller 320 determines the operation mode of the transceiver 300 as the transmit mode, the controller 320 generates a transmit enable signal (e.g., EN_TX = logic high 'H') to enable the first transmit buffer 202 and the second transmit buffer 204 to transmit the output signals (TX_DP and TX_DN) to the first input-output pin 303 and the second input-output pin 305. The controller 320 also generates a receive disable signal (e.g., EN_RX = logic low 'L') to disable the amplifier 108, thereby preventing the amplifier 108 from amplifying any transmit signals. In this mode, the controller 320 also sets the third variable resistor R VP and the fourth variable resistor R VN is set to a high impedance value (e.g., about 10,000 ohms) to significantly reduce or eliminate the P2 and the second-2 inductor L N2 Thus, again, the first common T-coil circuit 302 and the second common T-coil circuit 304 effectively function as a dual inductor peaking circuit for the first T-coil circuit 102 and the second T-coil circuit 104 (with the first -1 inductor L P1 and the third-1 inductor L TP and the first-2 inductor L N1 and the third-2 inductor L TN conduction signals) and improve transmission bandwidth.

[0074] like Figure 4 As shown in , in some embodiments, the amplifier 108 is fixedly connected to the terminal impedance 306 and the first common T-coil circuit 302 and the second common T-coil circuit 304. However, embodiments of the present invention are not limited thereto. For example, as shown in Figure 5As shown in , when it is desired to calibrate the offset voltage of amplifier 108 (e.g., when communicating over a long transmission line 30 and the input signal is small (e.g., weak)), calibration switch 110 can be used to selectively short the input of amplifier 108 and auto-zero switch (e.g., Figure 5 The first receive switch 112 and the second receive switch 114 in the embodiment of the present invention may be located in a signal path of the receive signal and be deactivated in the calibration mode to electrically isolate the amplifier from the input-output pins 303 and 305 .

[0075] Figure 5 is a schematic diagram of a transceiver 300 - 1 capable of calibration according to some embodiments of the present disclosure.

[0076] Reference Figure 5 , except for the terminal impedance 306 having a variable resistor, the transmitting side of the transceiver 300-1 is Figure 4 The transmitting side of the transceiver 300 is substantially the same as that of the transceiver 300, while the receiving side of the transceiver 300-1 is substantially the same as that of the transceiver 300-2. Figure 1 The receiver 100 is substantially the same as the receiver 100 of FIG. 1 . In addition, the controller 320-1 generates a calibration enable / disable signal EN_CAL. Figure 4 The controller 320 is substantially the same as that of FIG. Figure 4 A description of the circuit elements of transceiver 300.

[0077] According to some embodiments, the controller 320 - 1 is configured to confirm the operation mode of the transceiver 300 - 1 as a calibration mode, a transmission mode, or a reception mode.

[0078] In some embodiments, in the calibration mode, the controller 320-1 generates a receive disable signal (e.g., EN_RX = logic low 'L') to electrically disconnect (e.g., electrically isolate) the amplifier 108 from the first common T-coil circuit 302 and the second common T-coil circuit 304. The controller 320-1 also generates a transmit disable signal (e.g., EN_TX = logic low 'L') to disable the first transmission buffer 202 and the second transmission buffer 204 and to set the third variable resistor R of the termination impedance 306. VP and the fourth variable resistor R VN is set to a first resistance value (e.g., approximately 50 ohms). In calibration mode, controller 320-1 generates a calibration enable signal (e.g., EN_CAL = logic high 'H') to activate calibration switch 110 and short-circuit the two inputs of amplifier 108. This allows other circuits to measure and calibrate the offset voltage V of amplifier 108. OFFSET (For example, as mentioned above FIG. 2A to FIG. 2C described above).

[0079] According to some embodiments, in the receive mode, the controller 320-1 generates a receive enable signal to electrically connect the amplifier 108 to the first center node CN of the first common T-coil circuit 302. P and a second central node CN of the second common T-coil circuit 304 N , so that the amplifier 108 can receive input signals from the first input-output pin 303 and the second input-output pin 305. The controller 320-1 also generates a transmission disable signal to disable the first transmission buffer 202 and the second transmission buffer 204 and to set the third variable resistor R of the terminal impedance 306 VP and the fourth variable resistor R VN The first resistance value is set to be approximately 50 ohms. In the receiving mode, the controller 320 - 1 also generates a calibration disable signal to deactivate the calibration switch 110 .

[0080] In some embodiments, in the transmit mode, the controller 320-1 generates a receive disable signal to electrically disconnect (e.g., electrically isolate) the amplifier 108 from the first common T-coil circuit 302 and the second common T-coil circuit 304. The controller 320-1 may also generate a calibration disable signal to deactivate the calibration switch 110. In the transmit mode, the controller 320-1 generates a transmit enable signal to enable the first transmission buffer 202 and the second transmission buffer 204 to transmit output signals (TX_DP and TX_DN) to the first input-output pin 303 and the second input-output pin 305 and to connect the third variable resistor R of the terminal impedance 306. VP and the fourth variable resistor R VN The second resistance value is set (eg, approximately 10,000 ohms).

[0081] Fig. 6A A half circuit showing an effective peaking structure of the transceiver 300 / 300-1 when in calibration mode and receive mode according to some embodiments of the present disclosure. In these modes, each disabled transmit buffer 202 / 204 enters a high impedance state and effectively behaves as connected to the corresponding central node CN P / CN N The parasitic capacitance C parasitic However, as mentioned above FIG. 2A to FIG. 2C As described above, since the central node CN of the common T-coil circuit 302 / 304 P / CN N It is not sensitive to capacitive loads, so when receiving input signals, this parasitic capacitance C parasitic The bandwidth of the transceiver 300 / 300-1 is not affected.

[0082] Figure 6BFIG. 1 shows a half circuit of an effective peaking structure of the transceiver 300 / 300 - 1 when in transmit mode according to some embodiments of the present disclosure. In this mode, the enabled transmit buffer 202 / 204 may have an effective output impedance Rout (eg, about 50 ohms) that matches the impedance of the transmission line 30 . In addition, when the fourth variable resistor R VN is set to a high resistance (e.g., 1000 ohms or 10,000 ohms), through the second-2 inductor L N2 The path does not conduct any meaningful amount of signal, and the second common T-coil circuit 304 effectively acts as a 2-inductor peaking T-coil circuit similar to the second T-coil circuit 104 (with the first -2 inductor L N1 and the third-2 inductor L TN ).

[0083] Figure 7 2 is a diagram showing a variable resistor R according to some embodiments of the present disclosure. VP / R VN Schematic diagram of .

[0084] Reference Figure 7 , the third variable resistor R VP and the fourth variable resistor R VN This can be achieved using switchable elements. In some embodiments, the third variable resistor R VP and the fourth variable resistor R VN A first branch (eg, a first switchable branch) connected in parallel with a second branch (eg, a second switchable branch), each branch having a different resistance. The first branch includes a first resistor R connected in series with a first switch 308. 1 , the first switch 308 is configured to be activated in response to a transmit disable signal (eg, EN_TX_B=logic high 'H'), and the second branch includes a second resistor R connected in series with the second switch 310 2 , the second switch 310 is configured to be activated in response to sending an enable signal (eg, EN_TX = logic high 'H'), so that at any given time, either the first branch is activated or the second branch is activated, but not both the first branch and the second branch are activated. In an example, the second resistor R 2 may have a value greater than the first resistor R 1 For example, the first resistor R 1 The resistance value can be 50 ohms, the second resistor R 2 The resistance value can be 1000 ohms.

[0085] Although the receiver 100 and the transceiver 300 / 300-1 have been described herein with reference to a SERDES block, embodiments of the present application are not limited thereto, and the receiver 100 and the transceiver 300 / 300-1 may be used for any suitable application (e.g., non-return to zero (NRZ) and pulse-amplitude modulation 4-level (PAM4) signaling methods). For example, in one example, half of the circuitry of a transceiver according to some embodiments of the present disclosure may correspond to, for example, Fig. 6A and Figure 6B The other half of the circuit can be connected with Fig. 6A and Figure 6B Furthermore, it should be understood that even if only half of the circuitry of the transceiver according to some embodiments of the present disclosure corresponds to or adopts Fig. 6A and Figure 6B The transceiver can also be implemented as shown in the half circuit Figures 1 to 7 The effect described.

[0086] As described herein, the transceiver 300 / 300-1 according to some embodiments of the present disclosure allows the transmit and receive front-end circuits to share input / output pins, thereby saving chip pin count and reducing the number of cables / traces to be routed. In addition, the transceiver 300 / 300-1 according to some embodiments of the present disclosure allows the transmit and receive front-end circuits to share a pair of T-coil circuits (rather than using two separate T-coil pairs), thereby saving area (e.g., printed circuit board area). In some embodiments, the transceiver 300 / 300-1 allows the receiver-end amplifier to be calibrated in calibration mode or transmit mode by isolating the amplifier from the rest of the circuit using a switch. This makes the transceiver 300 / 300-1 suitable for long-range and small input signal communications. The isolation switch is large and has a low on-resistance, and the parasitic load of the isolation switch is masked by being connected to the center node of the T-coil circuit. In this way, the presence of a large isolation switch does not affect the signal bandwidth. Furthermore, regardless of the mode of operation (eg, calibration, receive, or transmit), the input of the transceiver sees a 50 ohm termination (ie, is not limited by parasitic loading from the switch), which allows the transceiver 300 / 300 - 1 to provide improved input matching and return loss.

[0087] In order to simplify the description, in the above, it is assumed that various components of the receiver 100 and the transceivers 300 and 300-1 are activated (e.g., enabled / turned on or closed) by a logic high signal (e.g., binary '1'), and deactivated (e.g., disabled / turned off or disconnected) by a logic low signal (e.g., binary '0'). However, the embodiments of the present application are not limited thereto, and one or more components of the receiver 100 and the transceivers 300 and 300-1 may be activated (e.g., enabled / turned on or closed) by a logic low signal (e.g., binary '0'), and deactivated (e.g., disabled / turned off or disconnected) by a logic high signal (e.g., binary '1').

[0088] As will be understood by one of ordinary skill in the art, the operations performed by the controller 120 / 320 / 320-1 may be performed by a processor. A memory local to the processor may have instructions that, when executed, cause the processor to perform the operations of the controller.

[0089] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0090] The terms used herein are used for the purpose of describing a particular embodiment and are not intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that the terms "include" and / or "comprise" when used in this specification specify the features, wholes, steps, operations, elements and / or components of the description, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Statements such as "at least one of..." modify the entire list of elements rather than modifying the individual elements in the list when following a list of elements. In addition, when describing the embodiments of the inventive concept, the use of "may" represents "one or more embodiments of the inventive concept". In addition, the term "exemplary" is intended to represent an example or description.

[0091] As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilize" and variations thereof, respectively.

[0092] The receiver, transceiver and / or any other related device or component (such as a controller) according to the embodiments of the present disclosure described herein can be implemented by utilizing any suitable hardware, firmware (e.g., a dedicated integrated circuit), software, or any suitable combination of software, firmware and hardware. For example, the various components of the receiver and transceiver can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of the receiver and transceiver can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on the same substrate. In addition, the various components of the receiver and transceiver can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components for performing various functions described herein. The computer program instructions are stored in a memory, where the memory can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). The computer program instructions can also be stored in other non-temporary computer-readable media (such as, for example, a CD-ROM, a flash drive, etc.). Furthermore, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the exemplary embodiments of the present disclosure.

[0093] Although the present disclosure has been described in detail with specific reference to the illustrative embodiments of the present disclosure, the embodiments described herein are not intended to be exhaustive or to limit the scope of the disclosure to the precise forms disclosed. Those skilled in the art and technology to which the present disclosure belongs will appreciate that changes and variations in the described structures, as well as assembly and operating methods, may be practiced without meaningfully departing from the principles and scope of the present disclosure as set forth in the claims and their equivalents.

Claims

1. A receiver, comprising: a first common T-coil circuit connected to a first input pin of the receiver; a terminating impedance connected to the first common T-coil circuit and configured to match an impedance of a transmission line connected to the first common T-coil circuit; an amplifier configured to: receive an input signal from the first common T-coil circuit based on a reception enable signal; as well as a first receiving switch configured to selectively electrically connect or disconnect a center node of the first common T-coil circuit from the amplifier based on a receiving enable signal; wherein the first common T-coil circuit has a center node selectively connected to an input of the amplifier and comprises: a first inductor connected between the transmission line and the central node; and The second inductor is connected between the terminal impedance and the center node.

2. The receiver according to claim 1, wherein: The terminal impedance includes: a resistor connected to the first common T-coil circuit; and Common capacitor, connected to the resistor.

3. The receiver according to claim 1, further comprising: a calibration switch connected to the amplifier and configured to selectively electrically connect or disconnect the first input of the amplifier from the second input in response to a calibration enable signal; as well as The controller is configured to: confirm the operation mode of the receiver as a calibration mode or a receiving mode.

4. The receiver according to claim 3, wherein: The controller is also configured to: generating a receive disable signal to electrically disconnect the amplifier from the first common T-coil circuit; and Generates a calibration enable signal to activate the calibration switch.

5. The receiver according to claim 3, wherein: The controller is also configured to: generating a receive enable signal to electrically connect the amplifier to the first common T-coil circuit to enable the amplifier to receive an input signal from the first input pin; and A calibration disable signal is generated to deactivate the calibration switch.

6. The receiver according to claim 1, wherein: The amplifier is selectively connected to the center node of the first common T-coil circuit, and The amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

7. The receiver according to claim 1, wherein: The amplifier is fixedly connected to the first common T-coil circuit and the terminating impedance, and The amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

8. The receiver according to claim 1, wherein: The input of the amplifier is fixedly connected to the second inductor of the first common T-coil circuit.

9. The receiver according to claim 1, wherein: A center node of the first common T-coil circuit is connected to an electrostatic discharge protection diode.

10. The receiver of claim 1, further comprising: A second common T-coil circuit, connected to a second input pin of the receiver, The first common T-coil circuit and the second common T-coil circuit are configured to receive a differential input signal at a first input pin and a second input pin.

11. The receiver according to claim 10, further comprising: The second receiving switch is configured to selectively electrically connect or disconnect a center node of the second common T-coil circuit from the amplifier based on the receiving enable signal.

12. The receiver according to claim 10, wherein: The amplifier is configured to amplify a differential signal output from a central node of the first common T-coil circuit and the second common T-coil circuit.

13. A receiver, comprising: a pair of common T-coil circuits connected to a pair of input pins of the receiver; a terminating impedance connected to the common T-coil circuit and configured to match an impedance of a transmission line connected to the common T-coil circuit; an amplifier configured to: receive a differential input signal from the input pin through the common T-coil circuit based on a receive enable signal; as well as A first receiving switch is configured to selectively electrically connect or disconnect a central node of one of the common T-coil circuits with the amplifier based on a receiving enable signal, wherein each of the common T-coil circuits has a central node selectively connected to an input of an amplifier and comprises: a first inductor connected between the transmission line and the central node; and The second capacitor is connected between the terminal impedance and the center node.

14. The receiver of claim 13, further comprising: a calibration switch connected to the amplifier and configured to selectively electrically connect or disconnect the first input of the amplifier from the second input in response to a calibration enable signal; as well as The controller is configured to: confirm the operation mode of the receiver as a calibration mode or a receiving mode.

15. The receiver according to claim 14, wherein: The controller is also configured to: generating a receive disable signal to electrically disconnect the amplifier from the common T-coil circuit; and Generates a calibration enable signal to activate the calibration switch.

16. The receiver according to claim 13, wherein: The amplifier is selectively connected to the center node of the common T-coil circuit, and The amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

17. The receiver according to claim 13, wherein: The amplifier is fixedly connected to the common T-coil circuit and the terminating impedance, and The amplifier includes a first input and a second input, and is configured to amplify a differential signal at the first input and the second input.

18. A method of operating a receiver, comprising: confirming the operating mode of the receiver as a calibration mode or a receiving mode; as well as In response to confirming the operating mode as the receive mode: electrically connecting an amplifier to a center node of the common T-coil circuit via a first receive switch to enable the amplifier to receive an input signal from an input pin of the receiver, the input pin being connected to the transmission line; deactivating a calibration switch connected to the amplifier to selectively electrically disconnect the differential inputs of the amplifier, wherein a central node of the common T-coil circuit is selectively connected to an input of the amplifier, and the common T-coil circuit comprises: a first inductor connected between the transmission line and the central node; and The second inductor is connected between the terminal impedance and the center node.

19. The method according to claim 18, wherein: The steps for electrically connecting the amplifier to the common T-coil circuit include: Close a first receive switch in the signal path directly between the input pin and the amplifier.

20. The method of claim 18, further comprising: In response to confirming the operating mode as calibration mode: Electrically disconnect the amplifier from the common T-coil circuit; as well as A calibration switch connected to the amplifier is activated to electrically connect the differential inputs of the amplifier and enable measurement of the input offset voltage of the amplifier.

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